From efb2f7b2d49b62d7019ccc283523353e061dab8c Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 19 Aug 2022 08:18:59 +0200 Subject: [PATCH] seems to work now --- gbe_hub/trb3sc_gbe_hub.prj | 7 ++++--- gbe_hub/trb3sc_gbe_hub.vhd | 34 +++++++++++++++++++++++++++------- 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index 154d721..d94bb35 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -122,11 +122,11 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" #Media interface add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" @@ -185,6 +185,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_sci_reader.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/inserter.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/remover.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_inserter.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 4e13b27..25eaac6 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -196,6 +196,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal tick_us_int : std_logic; signal aux_reg : std_logic_vector(31 downto 0); + signal control_reg : std_logic_vector(31 downto 0); -- signal dlm_found_int : std_logic; signal dlm_inject_int : std_logic; @@ -211,7 +212,11 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal master_clk : std_logic; signal global_reset_i : std_logic; - + signal wap_psca : std_logic_vector(15 downto 0); + signal wap_pscb : std_logic_vector(15 downto 0); + signal wap_pscc : std_logic_vector(15 downto 0); + signal wap_pscd : std_logic_vector(15 downto 0); + begin -- SerDes usage: @@ -501,7 +506,14 @@ begin MY_ADDRESS_OUT => open -- BUG? ); - common_stat_reg <= (others => '0'); +-- common_stat_reg <= (others => '0'); + common_stat_reg(std_COMSTATREG*32-1 downto 128) <= (others => '0'); + common_stat_reg(127 downto 96) <= x"deadbeef"; + common_stat_reg(95 downto 80) <= wap_psca; + common_stat_reg(79 downto 64) <= wap_pscb; + common_stat_reg(63 downto 48) <= wap_pscc; + common_stat_reg(47 downto 32) <= wap_pscd; + common_stat_reg(31 downto 0) <= (others => '0'); -- used for temperature --------------------------------------------------------------------------- -- Bus Handler @@ -544,7 +556,7 @@ begin SCL_INOUT => open, --SI2C_SCL, -- Additional register ADDITIONAL_REG => additional_reg, - CTRL_REG => open, + CTRL_REG => control_reg, AUX_REG => aux_reg, -- Ethernet registers FWD_MAC_OUT => open, @@ -626,13 +638,15 @@ begin MASTER_CLK_OUT => open, TX_CLK_AVAIL_OUT => open, SYNC_TX_PLL_IN => '0', + WAP_REQUESTED_IN => control_reg(3 downto 0), -- DLM DLM_INJECT_IN(0) => dlm_inject_int, DLM_DATA_IN(7 downto 0) => dlm_tx_data_int, DLM_FOUND_OUT => open, DLM_DATA_OUT => open, DLM_CLK_OUT => open, - -- Debug + -- Debug + WAP_OUT => wap_psca, STATUS_OUT => status_raw(1 * 32 - 1 downto 0 * 32), DEBUG_OUT => open ); @@ -731,6 +745,7 @@ begin MASTER_CLK_OUT => open, TX_CLK_AVAIL_OUT => open, SYNC_TX_PLL_IN => '0', + WAP_REQUESTED_IN => control_reg(3 downto 0), -- DLM DLM_INJECT_IN(0) => dlm_inject_int, DLM_INJECT_IN(1) => dlm_inject_int, @@ -743,7 +758,8 @@ begin DLM_FOUND_OUT => open, DLM_DATA_OUT => open, DLM_CLK_OUT => open, - -- Debug + -- Debug + WAP_OUT => wap_pscb, STATUS_OUT => status_raw(2 * 32 - 1 downto 1 * 32), DEBUG_OUT => open ); @@ -842,6 +858,7 @@ begin MASTER_CLK_OUT => open, TX_CLK_AVAIL_OUT => open, SYNC_TX_PLL_IN => '0', + WAP_REQUESTED_IN => control_reg(3 downto 0), -- DLM DLM_INJECT_IN(0) => dlm_inject_int, DLM_INJECT_IN(1) => dlm_inject_int, @@ -854,7 +871,8 @@ begin DLM_FOUND_OUT => open, DLM_DATA_OUT => open, DLM_CLK_OUT => open, - -- Debug + -- Debug + WAP_OUT => wap_pscc, STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32), DEBUG_OUT => open ); @@ -928,13 +946,15 @@ begin MASTER_CLK_OUT => master_clk, TX_CLK_AVAIL_OUT => tx_clk_avail_i, SYNC_TX_PLL_IN => '0', + WAP_REQUESTED_IN => control_reg(3 downto 0), -- DLM DLM_INJECT_IN => (others => '0'), DLM_DATA_IN => (others => '0'), DLM_FOUND_OUT => open, DLM_DATA_OUT => open, DLM_CLK_OUT => open, - -- Debug + -- Debug + WAP_OUT => wap_pscd, STATUS_OUT => status_raw(4 * 32 - 1 downto 3 * 32), DEBUG_OUT => debug --open ); -- 2.43.0