From f038ed9d68c55321a2889c394ee37a85b2a74067 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 10 Nov 2022 08:14:06 +0100 Subject: [PATCH] some FIFOs changed from DC to SC --- gbe_trb/base/gbe_frame_receiver.vhd | 24 +- gbe_trb/ipcores/ecp3/fifo_4096x9_s.lpc | 48 + gbe_trb/ipcores/ecp3/fifo_4096x9_s.vhd | 888 ++++++++++++++++++ gbe_trb/ipcores/ecp3/fifo_512x72_s.lpc | 48 + gbe_trb/ipcores/ecp3/fifo_512x72_s.vhd | 692 ++++++++++++++ .../gbe_response_constructor_Forward.vhd | 6 +- 6 files changed, 1686 insertions(+), 20 deletions(-) create mode 100644 gbe_trb/ipcores/ecp3/fifo_4096x9_s.lpc create mode 100644 gbe_trb/ipcores/ecp3/fifo_4096x9_s.vhd create mode 100644 gbe_trb/ipcores/ecp3/fifo_512x72_s.lpc create mode 100644 gbe_trb/ipcores/ecp3/fifo_512x72_s.vhd diff --git a/gbe_trb/base/gbe_frame_receiver.vhd b/gbe_trb/base/gbe_frame_receiver.vhd index c96d1fe..ef131e0 100644 --- a/gbe_trb/base/gbe_frame_receiver.vhd +++ b/gbe_trb/base/gbe_frame_receiver.vhd @@ -422,16 +422,14 @@ begin -- BUG: should be replaced by ring buffer -- FIFO for payload storage - THE_RECEIVE_FIFO: entity work.fifo_4096x9 + THE_RECEIVE_FIFO: entity work.fifo_4096x9_s port map( Data(8) => mac_rx_eof_q, Data(7 downto 0) => mac_rxd_q, - WrClock => CLK, - RdClock => CLK, + Clock => CLK, WrEn => fifo_pl_wr, RdEn => FR_RD_EN_IN, Reset => RESET, - RPReset => RESET, Q => fr_q, Empty => open, -- BUG Full => open -- BUG @@ -442,17 +440,15 @@ begin -- Happens when main control tries to read a frame directly when it was written. -- FIFO for header information - THE_FIRST_FIFO: entity work.fifo_512x72 + THE_FIRST_FIFO: entity work.fifo_512x72_s port map( Data(47 downto 0) => stored_src_mac, Data(63 downto 48) => stored_src_port, Data(71 downto 64) => std_logic_vector(rx_bytes_ctr(7 downto 0)), - WrClock => CLK, - RdClock => CLK, + Clock => CLK, WrEn => fifo_hd_wr_q, RdEn => FR_GET_FRAME_IN, Reset => RESET, - RPReset => RESET, Q(47 downto 0) => fr_src_mac, Q(63 downto 48) => fr_src_udp, Q(71 downto 64) => fr_frame_size(7 downto 0), @@ -461,17 +457,15 @@ begin ); -- FIFO for header information - THE_SECOND_FIFO: entity work.fifo_512x72 + THE_SECOND_FIFO: entity work.fifo_512x72_s port map( Data(47 downto 0) => stored_dst_mac, Data(63 downto 48) => stored_dst_port, Data(71 downto 64) => protocol_select, - WrClock => CLK, - RdClock => CLK, + Clock => CLK, WrEn => fifo_hd_wr_q, RdEn => FR_GET_FRAME_IN, Reset => RESET, - RPReset => RESET, Q(47 downto 0) => fr_dest_mac, Q(63 downto 48) => fr_dest_udp, Q(71 downto 64) => fr_ps, @@ -480,17 +474,15 @@ begin ); -- FIFO for header information - THE_THIRD_FIFO: entity work.fifo_512x72 + THE_THIRD_FIFO: entity work.fifo_512x72_s port map( Data(31 downto 0) => stored_src_ip, Data(63 downto 32) => stored_dst_ip, Data(71 downto 64) => std_logic_vector(rx_bytes_ctr(15 downto 8)), - WrClock => CLK, - RdClock => CLK, + Clock => CLK, WrEn => fifo_hd_wr_q, RdEn => FR_GET_FRAME_IN, Reset => RESET, - RPReset => RESET, Q(31 downto 0) => fr_src_ip, Q(63 downto 32) => fr_dest_ip, Q(71 downto 64) => fr_frame_size(15 downto 8), diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9_s.lpc b/gbe_trb/ipcores/ecp3/fifo_4096x9_s.lpc new file mode 100644 index 0000000..eb6b220 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9_s.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN672C +SpeedGrade=6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_4096x9_s +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/09/2022 +Time=17:02:41 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_4096x9_s -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 12 -data_width 9 -num_words 4096 -no_enable -pe -1 -pf -1 diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9_s.vhd b/gbe_trb/ipcores/ecp3/fifo_4096x9_s.vhd new file mode 100644 index 0000000..701b154 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9_s.vhd @@ -0,0 +1,888 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n fifo_4096x9_s -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -no_enable -pe -1 -pf -1 + +-- Wed Nov 09 17:02:42 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4096x9_s is + port ( + Data: in std_logic_vector(8 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x9_s; + +architecture Structure of fifo_4096x9_s is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co4: std_logic; + signal ifcount_12: std_logic; + signal co6: std_logic; + signal cnt_con: std_logic; + signal co5: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal co5_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal wren_i: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; + signal co5_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_12: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal iwcount_12: std_logic; + signal co6_1: std_logic; + signal co5_3: std_logic; + signal wcount_12: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal ircount_12: std_logic; + signal co6_2: std_logic; + signal co5_4: std_logic; + signal rcount_12: std_logic; + signal scuba_vlo: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rcount_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9_s.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9_s.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0, + ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3, + ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6, + ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9, + ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wcount_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, + ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, + ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, + ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, + ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rcount_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0, + ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3, + ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6, + ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9, + ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wcount_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, + ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, + ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, + ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, + ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rcount_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_41: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_40: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_39: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_38: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_37: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_36: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_35: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_34: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_33: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_32: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_31: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_30: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_29: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_28: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_27: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_26: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_25: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_24: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_23: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_22: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_21: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_20: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_19: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_18: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_17: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_16: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_15: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_14: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_13: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_12: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_11: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_10: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_9: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_8: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_7: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_6: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_5: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_4: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_3: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_2: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_1: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_0: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rcount_11_ff); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11); + + bdcnt_bctr_6: CB2 + port map (CI=>co5, PC0=>fcount_12, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co6, NC0=>ifcount_12, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>co5_1); + + e_cmp_6: ALEB2 + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + CI=>co4_2, GE=>co5_2); + + g_cmp_6: AGEB2 + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co5_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_ctr_6: CU2 + port map (CI=>co5_3, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4, + NC0=>ircount_10, NC1=>ircount_11); + + r_ctr_6: CU2 + port map (CI=>co5_4, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_2, + NC0=>ircount_12, NC1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rcount_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rcount_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rcount_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rcount_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rcount_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rcount_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rcount_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rcount_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rcount_11_ff, + Z=>Q(8)); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4096x9_s is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_512x72_s.lpc b/gbe_trb/ipcores/ecp3/fifo_512x72_s.lpc new file mode 100644 index 0000000..3e1038d --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x72_s.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN672C +SpeedGrade=6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_512x72_s +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/10/2022 +Time=07:29:43 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=72 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_512x72_s -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 9 -data_width 72 -num_words 512 -no_enable -pe -1 -pf -1 diff --git a/gbe_trb/ipcores/ecp3/fifo_512x72_s.vhd b/gbe_trb/ipcores/ecp3/fifo_512x72_s.vhd new file mode 100644 index 0000000..4a0ddef --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x72_s.vhd @@ -0,0 +1,692 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n fifo_512x72_s -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -no_enable -pe -1 -pf -1 + +-- Thu Nov 10 07:29:43 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_512x72_s is + port ( + Data: in std_logic_vector(71 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_512x72_s; + +architecture Structure of fifo_512x72_s is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co4: std_logic; + signal cnt_con: std_logic; + signal co3: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4_1: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_2: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72_s.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72_s.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, + ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5, + ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, + ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, + ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7, + ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), + DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), + DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), + DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), + DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), ADW0=>wcount_0, ADW1=>wcount_1, + ADW2=>wcount_2, ADW3=>wcount_3, ADW4=>wcount_4, + ADW5=>wcount_5, ADW6=>wcount_6, ADW7=>wcount_7, + ADW8=>wcount_8, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rcount_0, + ADR6=>rcount_1, ADR7=>rcount_2, ADR8=>rcount_3, + ADR9=>rcount_4, ADR10=>rcount_5, ADR11=>rcount_6, + ADR12=>rcount_7, ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(54), DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), + DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), + DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), DO12=>Q(66), + DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), DO16=>Q(70), + DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), + DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), DO24=>Q(42), + DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), DO28=>Q(46), + DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), DO32=>Q(50), + DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); + + FF_31: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_30: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_29: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_28: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_27: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_26: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_25: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_24: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_23: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_22: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_21: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_20: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_19: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_18: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_17: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_16: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_15: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_14: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_13: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_12: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_11: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_10: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_9: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_8: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_7: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_6: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_5: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_4: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_3: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_2: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_1: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_0: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, + CI=>co3_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2, + NC0=>ircount_8, NC1=>ircount_9); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_512x72_s is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/protocols/gbe_response_constructor_Forward.vhd b/gbe_trb/protocols/gbe_response_constructor_Forward.vhd index fbc41fc..1110fb4 100644 --- a/gbe_trb/protocols/gbe_response_constructor_Forward.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_Forward.vhd @@ -154,16 +154,14 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F end if; end process PROC_FF_RD_LOCK; - THE_FRAME_FIFO: entity work.fifo_4096x9 + THE_FRAME_FIFO: entity work.fifo_4096x9_s port map( Data(7 downto 0) => FWD_DATA_IN, Data(8) => local_eop, - WrClock => CLK, - RdClock => CLK, + Clock => CLK, WrEn => ff_wr_en, RdEn => ff_rd_en, Reset => RESET, - RPReset => RESET, Q => ff_q, Empty => ff_empty, Full => ff_full -- 2.43.0