From f0959a4f643c38009cd4a76494ce79d6abfa5426 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Tue, 12 Apr 2022 09:55:14 +0200 Subject: [PATCH] add cores for trb5sc GBE project, mentioned in .prj file --- gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.sbx | 2432 ++++++ gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd | 179 + .../GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v | 19 + gbe/cores/GbePcsExtrefclk/extref/extref.cmd | 18 + gbe/cores/GbePcsExtrefclk/extref/extref.fdc | 2 + gbe/cores/GbePcsExtrefclk/extref/extref.lpc | 31 + gbe/cores/GbePcsExtrefclk/extref/extref.ngd | Bin 0 -> 2905 bytes gbe/cores/GbePcsExtrefclk/extref/extref.ngo | Bin 0 -> 1141 bytes gbe/cores/GbePcsExtrefclk/extref/extref.vhd | 40 + .../GbePcsExtrefclk/extref/extref_ngd.asd | 1 + .../extref/syn_results/.recordref | 0 .../extref/syn_results/_CMD_.CML | 1 + .../extref/syn_results/_cmd._cml | 1 + .../extref/syn_results/dm/layer0.xdm | 79 + .../extref/syn_results/extref.areasrr | 15 + .../extref/syn_results/extref.fse | 0 .../extref/syn_results/extref.htm | 9 + .../extref/syn_results/extref.prj | 46 + .../extref/syn_results/extref.srd | Bin 0 -> 3132 bytes .../extref/syn_results/extref.srf | 333 + .../extref/syn_results/extref.srm | Bin 0 -> 3159 bytes .../extref/syn_results/extref.srr | 333 + .../extref/syn_results/extref.srr.db | Bin 0 -> 8192 bytes .../extref/syn_results/extref.srs | Bin 0 -> 2126 bytes .../extref/syn_results/extref.vhm | 54 + .../extref/syn_results/extref.vm | 59 + .../extref/syn_results/extref_cck.rpt.db | Bin 0 -> 8192 bytes .../extref/syn_results/extref_scck.rpt.db | Bin 0 -> 8192 bytes .../extref/syn_results/extref_synplify.lpf | 20 + .../syn_results/extref_synplify_tmp2.lpf | 0 .../syn_results/extref_synplify_tmp4.lpf | 0 .../syn_results/extref_synplify_tmp8.lpf | 0 .../extref/syn_results/run_options.txt | 75 + .../extref/syn_results/scemi_cfg.txt | 3 + .../extref/syn_results/scratchproject.prs | 73 + .../syn_results/synlog/extref_compiler.srr | 46 + .../syn_results/synlog/extref_compiler.srr.db | Bin 0 -> 8192 bytes .../synlog/extref_compiler.srr.rptmap | 1 + .../syn_results/synlog/extref_fpga_mapper.srr | 201 + .../synlog/extref_fpga_mapper.srr.db | Bin 0 -> 8192 bytes .../syn_results/synlog/extref_fpga_mapper.szr | Bin 0 -> 5141 bytes .../synlog/extref_multi_srs_gen.srr | 11 + .../synlog/extref_multi_srs_gen.srr.db | Bin 0 -> 8192 bytes .../syn_results/synlog/extref_premap.srr | 62 + .../syn_results/synlog/extref_premap.srr.db | Bin 0 -> 8192 bytes .../syn_results/synlog/extref_premap.szr | Bin 0 -> 2533 bytes .../syn_results/synlog/layer0.tlg.rptmap | 1 + .../synlog/report/extref_compiler_notes.txt | 8 + .../report/extref_compiler_runstatus.xml | 41 + .../report/extref_fpga_mapper_area_report.xml | 26 + .../report/extref_fpga_mapper_errors.txt | 0 .../report/extref_fpga_mapper_notes.txt | 7 + .../report/extref_fpga_mapper_opt_report.xml | 14 + .../report/extref_fpga_mapper_runstatus.xml | 46 + .../extref_fpga_mapper_timing_report.xml | 23 + .../report/extref_fpga_mapper_warnings.txt | 1 + .../synlog/report/extref_premap_errors.txt | 0 .../synlog/report/extref_premap_notes.txt | 2 + .../synlog/report/extref_premap_runstatus.xml | 46 + .../synlog/report/extref_premap_warnings.txt | 0 .../syn_results/synlog/report/metrics.db | Bin 0 -> 20480 bytes .../synlog/syntax_constraint_check.rpt.rptmap | 1 + .../extref/syn_results/syntmp/closed.png | Bin 0 -> 3672 bytes .../extref/syn_results/syntmp/extref.plg | 8 + .../extref/syn_results/syntmp/extref_srr.htm | 357 + .../extref/syn_results/syntmp/extref_toc.htm | 38 + .../extref/syn_results/syntmp/open.png | Bin 0 -> 452 bytes .../extref/syn_results/syntmp/run_option.xml | 24 + .../syn_results/syntmp/statusReport.html | 112 + .../extref/syn_results/synwork/.cckTransfer | Bin 0 -> 457 bytes .../extref/syn_results/synwork/_mh_info | 1 + .../syn_results/synwork/extref_comp.fdep | 21 + .../syn_results/synwork/extref_comp.srs | Bin 0 -> 2470 bytes .../extref/syn_results/synwork/extref_m.srm | Bin 0 -> 3159 bytes .../synwork/extref_m_srm/fileinfo.srm | Bin 0 -> 320 bytes .../syn_results/synwork/extref_mult.srs | Bin 0 -> 2126 bytes .../synwork/extref_mult_srs/fileinfo.srs | Bin 0 -> 299 bytes .../synwork/extref_mult_srs/skeleton.srs | Bin 0 -> 514 bytes .../syn_results/synwork/extref_prem.fse | 0 .../syn_results/synwork/extref_prem.srd | Bin 0 -> 2465 bytes .../extref/syn_results/synwork/layer0.fdep | 28 + .../syn_results/synwork/layer0.fdeporig | 24 + .../extref/syn_results/synwork/layer0.srs | Bin 0 -> 2552 bytes .../extref/syn_results/synwork/layer0.tlg | 4 + .../extref/syn_results/synwork/layer0.tlg.db | Bin 0 -> 8192 bytes .../syn_results/synwork/modulechange.db | Bin 0 -> 28672 bytes .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cmd | 18 + .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cst | 3 + .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc | 3 + .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.lpc | 97 + .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngd | Bin 0 -> 393974 bytes .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngo | Bin 0 -> 203442 bytes .../GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd | 433 ++ .../sgmii_ecp5/sgmii_ecp5_ngd.asd | 1 + .../sgmii_ecp5/sgmii_ecp5_softlogic.v | 2003 +++++ .../sgmii_ecp5/syn_results/.recordref | 0 .../sgmii_ecp5/syn_results/_CMD_.CML | 1 + .../sgmii_ecp5/syn_results/_cmd._cml | 1 + .../sgmii_ecp5/syn_results/dm/layer0.xdm | 548 ++ .../sgmii_ecp5/syn_results/dm/layer1.xdm | 255 + .../sgmii_ecp5/syn_results/run_options.txt | 76 + .../sgmii_ecp5/syn_results/scemi_cfg.txt | 3 + .../sgmii_ecp5/syn_results/scratchproject.prs | 74 + .../sgmii_ecp5/syn_results/sgmii_ecp5.areasrr | 97 + .../sgmii_ecp5/syn_results/sgmii_ecp5.fse | 12 + .../sgmii_ecp5/syn_results/sgmii_ecp5.htm | 9 + .../sgmii_ecp5/syn_results/sgmii_ecp5.prj | 47 + .../sgmii_ecp5/syn_results/sgmii_ecp5.srd | Bin 0 -> 72944 bytes .../sgmii_ecp5/syn_results/sgmii_ecp5.srf | 1134 +++ .../sgmii_ecp5/syn_results/sgmii_ecp5.srm | Bin 0 -> 31486 bytes .../sgmii_ecp5/syn_results/sgmii_ecp5.srr | 1134 +++ .../sgmii_ecp5/syn_results/sgmii_ecp5.srr.db | Bin 0 -> 40960 bytes .../sgmii_ecp5/syn_results/sgmii_ecp5.srs | Bin 0 -> 27443 bytes .../sgmii_ecp5/syn_results/sgmii_ecp5.vhm | 6445 ++++++++++++++++ .../sgmii_ecp5/syn_results/sgmii_ecp5.vm | 6626 +++++++++++++++++ .../syn_results/sgmii_ecp5_cck.rpt.db | Bin 0 -> 8192 bytes .../syn_results/sgmii_ecp5_scck.rpt.db | Bin 0 -> 8192 bytes .../syn_results/sgmii_ecp5_synplify.lpf | 29 + .../syn_results/sgmii_ecp5_synplify_tmp2.lpf | 0 .../syn_results/sgmii_ecp5_synplify_tmp4.lpf | 0 .../syn_results/sgmii_ecp5_synplify_tmp8.lpf | 0 .../syn_results/synlog/layer0.tlg.rptmap | 1 + .../syn_results/synlog/layer1.tlg.rptmap | 1 + .../syn_results/synlog/linker.rpt.rptmap | 1 + .../syn_results/synlog/report/metrics.db | Bin 0 -> 20480 bytes .../report/sgmii_ecp5_compiler_notes.txt | 16 + .../report/sgmii_ecp5_compiler_runstatus.xml | 41 + .../report/sgmii_ecp5_compiler_warnings.txt | 77 + .../sgmii_ecp5_fpga_mapper_area_report.xml | 26 + .../report/sgmii_ecp5_fpga_mapper_errors.txt | 0 .../report/sgmii_ecp5_fpga_mapper_notes.txt | 22 + .../sgmii_ecp5_fpga_mapper_opt_report.xml | 14 + .../sgmii_ecp5_fpga_mapper_runstatus.xml | 46 + .../sgmii_ecp5_fpga_mapper_timing_report.xml | 41 + .../sgmii_ecp5_fpga_mapper_warnings.txt | 4 + .../report/sgmii_ecp5_premap_errors.txt | 0 .../synlog/report/sgmii_ecp5_premap_notes.txt | 9 + .../report/sgmii_ecp5_premap_runstatus.xml | 46 + .../report/sgmii_ecp5_premap_warnings.txt | 3 + .../synlog/sgmii_ecp5_compiler.srr | 351 + .../synlog/sgmii_ecp5_compiler.srr.db | Bin 0 -> 28672 bytes .../synlog/sgmii_ecp5_compiler.srr.rptmap | 1 + .../synlog/sgmii_ecp5_fpga_mapper.srr | 673 ++ .../synlog/sgmii_ecp5_fpga_mapper.srr.db | Bin 0 -> 16384 bytes .../synlog/sgmii_ecp5_fpga_mapper.szr | Bin 0 -> 12840 bytes .../synlog/sgmii_ecp5_fpga_mapper.xck | 3 + .../synlog/sgmii_ecp5_multi_srs_gen.srr | 11 + .../synlog/sgmii_ecp5_multi_srs_gen.srr.db | Bin 0 -> 8192 bytes .../syn_results/synlog/sgmii_ecp5_premap.srr | 86 + .../synlog/sgmii_ecp5_premap.srr.db | Bin 0 -> 8192 bytes .../syn_results/synlog/sgmii_ecp5_premap.szr | Bin 0 -> 3856 bytes .../synlog/syntax_constraint_check.rpt.rptmap | 1 + .../sgmii_ecp5/syn_results/syntmp/closed.png | Bin 0 -> 3672 bytes .../sgmii_ecp5/syn_results/syntmp/open.png | Bin 0 -> 452 bytes .../syn_results/syntmp/run_option.xml | 24 + .../syn_results/syntmp/sgmii_ecp5.plg | 28 + .../syn_results/syntmp/sgmii_ecp5_srr.htm | 1162 +++ .../syn_results/syntmp/sgmii_ecp5_toc.htm | 60 + .../syn_results/syntmp/statusReport.html | 115 + .../syn_results/synwork/.cckTransfer | Bin 0 -> 456 bytes .../sgmii_ecp5/syn_results/synwork/_mh_info | 2 + .../syn_results/synwork/_verilog_hintfile | 69 + .../syn_results/synwork/layer0.fdep | 33 + .../syn_results/synwork/layer0.fdeporig | 29 + .../sgmii_ecp5/syn_results/synwork/layer0.srs | Bin 0 -> 50556 bytes .../sgmii_ecp5/syn_results/synwork/layer0.tlg | 2 + .../syn_results/synwork/layer0.tlg.db | Bin 0 -> 8192 bytes .../syn_results/synwork/layer1.fdep | 22 + .../syn_results/synwork/layer1.fdepxmr | 1 + .../syn_results/synwork/layer1.info | 2 + .../sgmii_ecp5/syn_results/synwork/layer1.srs | Bin 0 -> 21473 bytes .../sgmii_ecp5/syn_results/synwork/layer1.tlg | 252 + .../syn_results/synwork/layer1.tlg.db | Bin 0 -> 28672 bytes .../syn_results/synwork/modulechange.db | Bin 0 -> 28672 bytes .../layer0/modulechange.db | Bin 0 -> 20480 bytes .../layer1/modulechange.db | Bin 0 -> 20480 bytes .../syn_results/synwork/sgmii_ecp5_comp.fdep | 37 + .../synwork/sgmii_ecp5_comp.linkerlog | 0 .../syn_results/synwork/sgmii_ecp5_comp.srs | Bin 0 -> 46539 bytes .../syn_results/synwork/sgmii_ecp5_m.srm | Bin 0 -> 31486 bytes .../synwork/sgmii_ecp5_m_srm/1.srm | Bin 0 -> 68660 bytes .../synwork/sgmii_ecp5_m_srm/fileinfo.srm | Bin 0 -> 425 bytes .../syn_results/synwork/sgmii_ecp5_mult.srs | Bin 0 -> 27443 bytes .../synwork/sgmii_ecp5_mult_srs/1.srs | Bin 0 -> 13852 bytes .../synwork/sgmii_ecp5_mult_srs/fileinfo.srs | Bin 0 -> 403 bytes .../synwork/sgmii_ecp5_mult_srs/skeleton.srs | Bin 0 -> 6095 bytes .../syn_results/synwork/sgmii_ecp5_prem.fse | 12 + .../syn_results/synwork/sgmii_ecp5_prem.srd | Bin 0 -> 55846 bytes .../pll_200_125_100/pll_200_125_100.cmd | 18 + .../pll_200_125_100/pll_200_125_100.cst | 3 + .../pll_200_125_100/pll_200_125_100.fdc | 2 + .../pll_200_125_100/pll_200_125_100.lpc | 93 + .../pll_200_125_100/pll_200_125_100.ngd | Bin 0 -> 6054 bytes .../pll_200_125_100/pll_200_125_100.ngo | Bin 0 -> 3406 bytes .../pll_200_125_100/pll_200_125_100.vhd | 82 + .../pll_200_125_100/pll_200_125_100_ngd.asd | 1 + .../pll_200_125_100/pll_240_100.lpc | 93 + .../pll_200_125_100/syn_results/.recordref | 0 .../pll_200_125_100/syn_results/_CMD_.CML | 1 + .../pll_200_125_100/syn_results/_cmd._cml | 1 + .../pll_200_125_100/syn_results/dm/layer0.xdm | 163 + .../syn_results/pll_200_125_100.areasrr | 15 + .../syn_results/pll_200_125_100.fse | 0 .../syn_results/pll_200_125_100.htm | 9 + .../syn_results/pll_200_125_100.prj | 46 + .../syn_results/pll_200_125_100.srd | Bin 0 -> 5505 bytes .../syn_results/pll_200_125_100.srf | 403 + .../syn_results/pll_200_125_100.srm | Bin 0 -> 5633 bytes .../syn_results/pll_200_125_100.srr | 403 + .../syn_results/pll_200_125_100.srr.db | Bin 0 -> 8192 bytes .../syn_results/pll_200_125_100.srs | Bin 0 -> 4742 bytes .../syn_results/pll_200_125_100.vhm | 108 + .../syn_results/pll_200_125_100.vm | 117 + .../syn_results/pll_200_125_100_cck.rpt.db | Bin 0 -> 8192 bytes .../syn_results/pll_200_125_100_scck.rpt.db | Bin 0 -> 8192 bytes .../syn_results/pll_200_125_100_synplify.lpf | 20 + .../pll_200_125_100_synplify_tmp2.lpf | 0 .../pll_200_125_100_synplify_tmp4.lpf | 0 .../pll_200_125_100_synplify_tmp8.lpf | 0 .../syn_results/run_options.txt | 75 + .../pll_200_125_100/syn_results/scemi_cfg.txt | 3 + .../syn_results/scratchproject.prs | 73 + .../syn_results/synlog/layer0.tlg.rptmap | 1 + .../synlog/pll_200_125_100_compiler.srr | 51 + .../synlog/pll_200_125_100_compiler.srr.db | Bin 0 -> 8192 bytes .../pll_200_125_100_compiler.srr.rptmap | 1 + .../synlog/pll_200_125_100_fpga_mapper.srr | 265 + .../synlog/pll_200_125_100_fpga_mapper.srr.db | Bin 0 -> 8192 bytes .../synlog/pll_200_125_100_fpga_mapper.szr | Bin 0 -> 6127 bytes .../synlog/pll_200_125_100_multi_srs_gen.srr | 11 + .../pll_200_125_100_multi_srs_gen.srr.db | Bin 0 -> 8192 bytes .../synlog/pll_200_125_100_premap.srr | 63 + .../synlog/pll_200_125_100_premap.srr.db | Bin 0 -> 8192 bytes .../synlog/pll_200_125_100_premap.szr | Bin 0 -> 2598 bytes .../syn_results/synlog/report/metrics.db | Bin 0 -> 20480 bytes .../report/pll_200_125_100_compiler_notes.txt | 10 + .../pll_200_125_100_compiler_runstatus.xml | 41 + .../pll_200_125_100_compiler_warnings.txt | 2 + ...ll_200_125_100_fpga_mapper_area_report.xml | 26 + .../pll_200_125_100_fpga_mapper_errors.txt | 0 .../pll_200_125_100_fpga_mapper_notes.txt | 8 + ...pll_200_125_100_fpga_mapper_opt_report.xml | 14 + .../pll_200_125_100_fpga_mapper_runstatus.xml | 46 + ..._200_125_100_fpga_mapper_timing_report.xml | 23 + .../pll_200_125_100_fpga_mapper_warnings.txt | 1 + .../report/pll_200_125_100_premap_errors.txt | 0 .../report/pll_200_125_100_premap_notes.txt | 2 + .../pll_200_125_100_premap_runstatus.xml | 46 + .../pll_200_125_100_premap_warnings.txt | 0 .../synlog/syntax_constraint_check.rpt.rptmap | 1 + .../syn_results/syntmp/closed.png | Bin 0 -> 3672 bytes .../syn_results/syntmp/open.png | Bin 0 -> 452 bytes .../syn_results/syntmp/pll_200_125_100.plg | 8 + .../syntmp/pll_200_125_100_srr.htm | 428 ++ .../syntmp/pll_200_125_100_toc.htm | 45 + .../syn_results/syntmp/run_option.xml | 24 + .../syn_results/syntmp/statusReport.html | 112 + .../syn_results/synwork/.cckTransfer | Bin 0 -> 456 bytes .../syn_results/synwork/_mh_info | 1 + .../syn_results/synwork/layer0.fdep | 28 + .../syn_results/synwork/layer0.fdeporig | 24 + .../syn_results/synwork/layer0.srs | Bin 0 -> 6188 bytes .../syn_results/synwork/layer0.tlg | 9 + .../syn_results/synwork/layer0.tlg.db | Bin 0 -> 8192 bytes .../syn_results/synwork/modulechange.db | Bin 0 -> 28672 bytes .../synwork/pll_200_125_100_comp.fdep | 21 + .../synwork/pll_200_125_100_comp.srs | Bin 0 -> 5092 bytes .../syn_results/synwork/pll_200_125_100_m.srm | Bin 0 -> 5633 bytes .../pll_200_125_100_m_srm/fileinfo.srm | Bin 0 -> 316 bytes .../synwork/pll_200_125_100_mult.srs | Bin 0 -> 4742 bytes .../pll_200_125_100_mult_srs/fileinfo.srs | Bin 0 -> 296 bytes .../pll_200_125_100_mult_srs/skeleton.srs | Bin 0 -> 578 bytes .../synwork/pll_200_125_100_prem.fse | 0 .../synwork/pll_200_125_100_prem.srd | Bin 0 -> 4854 bytes .../pll_200_200_125_100.sbx | 617 ++ .../pll_200_200_125_100.vhd | 39 + .../pll_200_200_125_100_tmpl.v | 4 + gbe/cores/sgmii/PCSD/PCSD.cmd | 18 + gbe/cores/sgmii/PCSD/PCSD.cst | 3 + gbe/cores/sgmii/PCSD/PCSD.fdc | 3 + gbe/cores/sgmii/PCSD/PCSD.lpc | 97 + gbe/cores/sgmii/PCSD/PCSD.ngd | Bin 0 -> 180770 bytes gbe/cores/sgmii/PCSD/PCSD.ngo | Bin 0 -> 99461 bytes gbe/cores/sgmii/PCSD/PCSD.vhd | 390 + gbe/cores/sgmii/PCSD/PCSD_ngd.asd | 1 + gbe/cores/sgmii/PCSD/PCSD_softlogic.v | 943 +++ gbe/cores/sgmii/PCSD/stdout.log.bak.1 | 75 + gbe/cores/sgmii/PCSD/syn_results/.recordref | 0 gbe/cores/sgmii/PCSD/syn_results/PCSD.areasrr | 40 + gbe/cores/sgmii/PCSD/syn_results/PCSD.fse | 0 gbe/cores/sgmii/PCSD/syn_results/PCSD.htm | 9 + gbe/cores/sgmii/PCSD/syn_results/PCSD.prj | 47 + gbe/cores/sgmii/PCSD/syn_results/PCSD.srd | Bin 0 -> 41535 bytes gbe/cores/sgmii/PCSD/syn_results/PCSD.srf | 829 +++ gbe/cores/sgmii/PCSD/syn_results/PCSD.srm | Bin 0 -> 27644 bytes gbe/cores/sgmii/PCSD/syn_results/PCSD.srr | 829 +++ gbe/cores/sgmii/PCSD/syn_results/PCSD.srr.db | Bin 0 -> 24576 bytes gbe/cores/sgmii/PCSD/syn_results/PCSD.srs | Bin 0 -> 24257 bytes gbe/cores/sgmii/PCSD/syn_results/PCSD.vhm | 2765 +++++++ gbe/cores/sgmii/PCSD/syn_results/PCSD.vm | 2907 ++++++++ .../sgmii/PCSD/syn_results/PCSD_cck.rpt.db | Bin 0 -> 8192 bytes .../sgmii/PCSD/syn_results/PCSD_scck.rpt.db | Bin 0 -> 8192 bytes .../sgmii/PCSD/syn_results/PCSD_synplify.lpf | 24 + .../PCSD/syn_results/PCSD_synplify_tmp2.lpf | 0 .../PCSD/syn_results/PCSD_synplify_tmp4.lpf | 0 .../PCSD/syn_results/PCSD_synplify_tmp8.lpf | 0 gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML | 1 + gbe/cores/sgmii/PCSD/syn_results/_cmd._cml | 1 + .../sgmii/PCSD/syn_results/backup/PCSD.srr | 1157 +++ .../sgmii/PCSD/syn_results/dm/layer0.xdm | 513 ++ .../sgmii/PCSD/syn_results/dm/layer1.xdm | 65 + .../sgmii/PCSD/syn_results/run_options.txt | 76 + .../sgmii/PCSD/syn_results/scemi_cfg.txt | 3 + .../sgmii/PCSD/syn_results/scratchproject.prs | 74 + .../PCSD/syn_results/synlog/PCSD_compiler.srr | 201 + .../syn_results/synlog/PCSD_compiler.srr.db | Bin 0 -> 20480 bytes .../synlog/PCSD_compiler.srr.rptmap | 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+ + + + + + + extref_refclkn + extref_refclkn + + in + + + + extref.refclkn + + + + + extref_refclkp + extref_refclkp + + in + + + + extref.refclkp + + + + + sgmii_ecp5_ctc_del_s + sgmii_ecp5_ctc_del_s + + out + + + + sgmii_ecp5.ctc_del_s + + + + + sgmii_ecp5_ctc_ins_s + sgmii_ecp5_ctc_ins_s + + out + + + + sgmii_ecp5.ctc_ins_s + + + + + sgmii_ecp5_ctc_orun_s + sgmii_ecp5_ctc_orun_s + + out + + + + sgmii_ecp5.ctc_orun_s + + + + + sgmii_ecp5_ctc_urun_s + sgmii_ecp5_ctc_urun_s + + out + + + + sgmii_ecp5.ctc_urun_s + + + + + sgmii_ecp5_cyawstn + sgmii_ecp5_cyawstn + + in + + + + sgmii_ecp5.cyawstn + + + + + sgmii_ecp5_hdinn + sgmii_ecp5_hdinn + + in + + + + sgmii_ecp5.hdinn + + + + + sgmii_ecp5_hdinp + sgmii_ecp5_hdinp + + in + + + + sgmii_ecp5.hdinp + + + + + sgmii_ecp5_hdoutn + sgmii_ecp5_hdoutn + + out + + + + sgmii_ecp5.hdoutn + + + + + sgmii_ecp5_hdoutp + sgmii_ecp5_hdoutp + + out + + + + sgmii_ecp5.hdoutp + + + + + sgmii_ecp5_lsm_status_s + sgmii_ecp5_lsm_status_s + + out + + + + sgmii_ecp5.lsm_status_s + + + + + sgmii_ecp5_pll_lol + sgmii_ecp5_pll_lol + + out + + + + sgmii_ecp5.pll_lol + + + + + sgmii_ecp5_rsl_disable + sgmii_ecp5_rsl_disable + + in + + + + sgmii_ecp5.rsl_disable + + + + + sgmii_ecp5_rsl_rst + sgmii_ecp5_rsl_rst + + in + + + + sgmii_ecp5.rsl_rst + + + + + sgmii_ecp5_rsl_rx_rdy + sgmii_ecp5_rsl_rx_rdy + + out + + + + sgmii_ecp5.rsl_rx_rdy + + + + + sgmii_ecp5_rsl_tx_rdy + sgmii_ecp5_rsl_tx_rdy + + out + + + + sgmii_ecp5.rsl_tx_rdy + + + + + sgmii_ecp5_rst_dual_c + sgmii_ecp5_rst_dual_c + + in + + + + sgmii_ecp5.rst_dual_c + + + + + sgmii_ecp5_rx_cdr_lol_s + sgmii_ecp5_rx_cdr_lol_s + + out + + + + sgmii_ecp5.rx_cdr_lol_s + + + + + sgmii_ecp5_rx_los_low_s + sgmii_ecp5_rx_los_low_s + + out + + + + sgmii_ecp5.rx_los_low_s + + + + + sgmii_ecp5_rx_pcs_rst_c + sgmii_ecp5_rx_pcs_rst_c + + in + + + + sgmii_ecp5.rx_pcs_rst_c + + + + + sgmii_ecp5_rx_pwrup_c + sgmii_ecp5_rx_pwrup_c + + in + + + + sgmii_ecp5.rx_pwrup_c + + + + + sgmii_ecp5_rx_serdes_rst_c + sgmii_ecp5_rx_serdes_rst_c + + in + + + + sgmii_ecp5.rx_serdes_rst_c + + + + + sgmii_ecp5_sci_en + sgmii_ecp5_sci_en + + in + + + + sgmii_ecp5.sci_en + + + + + sgmii_ecp5_sci_en_dual + sgmii_ecp5_sci_en_dual + + in + + + + sgmii_ecp5.sci_en_dual + + + + + sgmii_ecp5_sci_int + sgmii_ecp5_sci_int + + out + + + + sgmii_ecp5.sci_int + + + + + sgmii_ecp5_sci_rd + sgmii_ecp5_sci_rd + + in + + + + sgmii_ecp5.sci_rd + + + + + sgmii_ecp5_sci_sel + sgmii_ecp5_sci_sel + + in + + + + sgmii_ecp5.sci_sel + + + + + sgmii_ecp5_sci_sel_dual + sgmii_ecp5_sci_sel_dual + + in + + + + sgmii_ecp5.sci_sel_dual + + + + + sgmii_ecp5_sci_wrn + sgmii_ecp5_sci_wrn + + in + + + + sgmii_ecp5.sci_wrn + + + + + sgmii_ecp5_serdes_pdb + sgmii_ecp5_serdes_pdb + + in + + + + sgmii_ecp5.serdes_pdb + + + + + sgmii_ecp5_serdes_rst_dual_c + sgmii_ecp5_serdes_rst_dual_c + + in + + + + sgmii_ecp5.serdes_rst_dual_c + + + + + sgmii_ecp5_signal_detect_c + sgmii_ecp5_signal_detect_c + + in + + + + sgmii_ecp5.signal_detect_c + + + + + sgmii_ecp5_tx_pclk + sgmii_ecp5_tx_pclk + + out + + + + sgmii_ecp5.tx_pclk + + + + + sgmii_ecp5_tx_pcs_rst_c + sgmii_ecp5_tx_pcs_rst_c + + in + + + + sgmii_ecp5.tx_pcs_rst_c + + + + + sgmii_ecp5_tx_pwrup_c + sgmii_ecp5_tx_pwrup_c + + in + + + + sgmii_ecp5.tx_pwrup_c + + + + + sgmii_ecp5_tx_serdes_rst_c + sgmii_ecp5_tx_serdes_rst_c + + in + + + + sgmii_ecp5.tx_serdes_rst_c + + + + + sgmii_ecp5_txi_clk + sgmii_ecp5_txi_clk + + in + + + + sgmii_ecp5.txi_clk + + + + + sgmii_ecp5_rx_cv_err + sgmii_ecp5_rx_cv_err + + out + + 0 + 0 + + + + + sgmii_ecp5.rx_cv_err + + + + + sgmii_ecp5_rx_disp_err + sgmii_ecp5_rx_disp_err + + out + + 0 + 0 + + + + + sgmii_ecp5.rx_disp_err + + + + + sgmii_ecp5_rx_k + sgmii_ecp5_rx_k + + out + + 0 + 0 + + + + + sgmii_ecp5.rx_k + + + + + sgmii_ecp5_rxdata + sgmii_ecp5_rxdata + + out + + 7 + 0 + + + + + sgmii_ecp5.rxdata + + + + + sgmii_ecp5_sci_addr + sgmii_ecp5_sci_addr + + in + + 5 + 0 + + + + + sgmii_ecp5.sci_addr + + + + + sgmii_ecp5_sci_rddata + sgmii_ecp5_sci_rddata + + out + + 7 + 0 + + + + + sgmii_ecp5.sci_rddata + + + + + sgmii_ecp5_sci_wrdata + sgmii_ecp5_sci_wrdata + + in + + 7 + 0 + + + + + sgmii_ecp5.sci_wrdata + + + + + sgmii_ecp5_tx_disp_correct + sgmii_ecp5_tx_disp_correct + + in + + 0 + 0 + + + + + sgmii_ecp5.tx_disp_correct + + + + + sgmii_ecp5_tx_k + sgmii_ecp5_tx_k + + in + + 0 + 0 + + + + + sgmii_ecp5.tx_k + + + + + sgmii_ecp5_txdata + sgmii_ecp5_txdata + + in + + 7 + 0 + + + + + sgmii_ecp5.txdata + + + + + sgmii_ecp5_xmit + sgmii_ecp5_xmit + + in + + 0 + 0 + + + + + sgmii_ecp5.xmit + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-05-13.09:04:13 AM + 2019-05-13.10:35:48 AM + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + GbePcsExtrefclk + 1.0 + + + extref + + Lattice Semiconductor Corporation + LEGACY + EXTREF + 1.1 + + + Diamond_Simulation + simulation + + ./extref/extref.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./extref/extref.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + refclkn + refclkn + + in + + + + true + + + + + refclko + refclko + + out + + + + refclkp + refclkp + + in + + + + true + + + + + + + synplify + 2019-05-13.10:35:48 AM + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + EXTREF + EXTREF + + true + false + EXTREF + 4 + + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + EXTREF + + + CoreRevision + 1.1 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/13/2019 + + + ModuleName + extref + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 09:10:11 + + + VendorName + Lattice Semiconductor Corporation + + + + Destination + Synplicity + + + EDIF + 1 + + + EXTREFDCBIAS + Disabled + + + EXTREFTERMRES + 50 ohms + + + Expression + BusA(0 to 7) + + + IO + 0 + + + Order + Big Endian [MSB:LSB] + + + VHDL + 1 + + + Verilog + 0 + + + + + EXTREF + 1 + + true + false + EXTREF + + EXTREF + + + + + + + sgmii_ecp5 + + Lattice Semiconductor Corporation + LEGACY + PCS + 8.2 + + + Diamond_Simulation + simulation + + ./sgmii_ecp5/sgmii_ecp5_softlogic.v + verilogSource + + + ./sgmii_ecp5/sgmii_ecp5.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./sgmii_ecp5/sgmii_ecp5_softlogic.v + verilogSource + + + ./sgmii_ecp5/sgmii_ecp5.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + ctc_del_s + ctc_del_s + + out + + + + ctc_ins_s + ctc_ins_s + + out + + + + ctc_orun_s + ctc_orun_s + + out + + + + ctc_urun_s + ctc_urun_s + + out + + + + cyawstn + cyawstn + + in + + + + hdinn + hdinn + + in + + + + true + + + + + hdinp + hdinp + + in + + + + true + + + + + hdoutn + hdoutn + + out + + + + true + + + + + hdoutp + hdoutp + + out + + + + true + + + + + lsm_status_s + lsm_status_s + + out + + + + pll_lol + pll_lol + + out + + + + pll_refclki + pll_refclki + + in + + + + rsl_disable + rsl_disable + + in + + + + rsl_rst + rsl_rst + + in + + + + rsl_rx_rdy + rsl_rx_rdy + + out + + + + rsl_tx_rdy + rsl_tx_rdy + + out + + + + rst_dual_c + rst_dual_c + + in + + + + rx_cdr_lol_s + rx_cdr_lol_s + + out + + + + rx_los_low_s + rx_los_low_s + + out + + + + rx_pcs_rst_c + rx_pcs_rst_c + + in + + + + rx_pwrup_c + rx_pwrup_c + + in + + + + rx_serdes_rst_c + rx_serdes_rst_c + + in + + + + rxrefclk + rxrefclk + + in + + + + sci_en + sci_en + + in + + + + sci_en_dual + sci_en_dual + + in + + + + sci_int + sci_int + + out + + + + sci_rd + sci_rd + + in + + + + sci_sel + sci_sel + + in + + + + sci_sel_dual + sci_sel_dual + + in + + + + sci_wrn + sci_wrn + + in + + + + serdes_pdb + serdes_pdb + + in + + + + serdes_rst_dual_c + serdes_rst_dual_c + + in + + + + signal_detect_c + signal_detect_c + + in + + + + sli_rst + sli_rst + + in + + + + true + + + + + tx_pclk + tx_pclk + + out + + + + tx_pcs_rst_c + tx_pcs_rst_c + + in + + + + tx_pwrup_c + tx_pwrup_c + + in + + + + tx_serdes_rst_c + tx_serdes_rst_c + + in + + + + txi_clk + txi_clk + + in + + + + rx_cv_err + rx_cv_err + + out + + 0 + 0 + + + + + rx_disp_err + rx_disp_err + + out + + 0 + 0 + + + + + rx_k + rx_k + + out + + 0 + 0 + + + + + rxdata + rxdata + + out + + 7 + 0 + + + + + sci_addr + sci_addr + + in + + 5 + 0 + + + + + sci_rddata + sci_rddata + + out + + 7 + 0 + + + + + sci_wrdata + sci_wrdata + + in + + 7 + 0 + + + + + tx_disp_correct + tx_disp_correct + + in + + 0 + 0 + + + + + tx_k + tx_k + + in + + 0 + 0 + + + + + txdata + txdata + + in + + 7 + 0 + + + + + xmit + xmit + + in + + 0 + 0 + + + + + + + synplify + 2019-05-13.10:35:48 AM + + false + false + false + false + false + false + false + false + false + false + LPM + DCU1_EXTREF + DCU1_EXTREF + false + false + + + + Lane0 + DCUCHANNEL + + true + false + DCUCHANNEL + 9 + + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PCS + + + CoreRevision + 8.2 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/13/2019 + + + ModuleName + sgmii_ecp5 + + + ParameterFileVersion + 1.0 + + + SourceFormat + VHDL + + + Time + 09:09:01 + + + VendorName + Lattice Semiconductor Corporation + + + + ;ACHARA + 0 00H + + + ;ACHARB + 0 00H + + + ;ACHARM + 0 00H + + + ;RXMCAENABLE + Disabled + + + CDRLOLACTION + Full Recalibration + + + CDRLOLRANGE + 0 + + + CDR_MAX_RATE + 1.25 + + + CDR_MULT + 10X + + + CDR_REF_RATE + 125.0000 + + + CH_MODE + Rx and Tx + + + Destination + Synplicity + + + EDIF + 1 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + IO_TYPE + GbE + + + LEQ + 0 + + + LOOPBACK + Disabled + + + LOSPORT + Enabled + + + NUM_CHS + 1 + + + Order + Big Endian [MSB:LSB] + + + PPORT_RX_RDY + Enabled + + + PPORT_TX_RDY + Enabled + + + PROTOCOL + GbE + + + PWAIT_RX_RDY + 3000 + + + PWAIT_TX_RDY + 3000 + + + RCSRC + Disabled + + + REFCLK_RATE + 125.0000 + + + RSTSEQSEL + Enabled + + + RX8B10B + Enabled + + + RXCOMMAA + 1010000011 + + + RXCOMMAB + 0101111100 + + + RXCOMMAM + 1111111111 + + + RXCOUPLING + AC + + + RXCTC + Enabled + + + RXCTCBYTEN + 0 00H + + + RXCTCBYTEN1 + 0 00H + + + RXCTCBYTEN2 + 1 BCH + + + RXCTCBYTEN3 + 0 50H + + + RXCTCMATCHPATTERN + M2-S2 + + + RXDIFFTERM + 50 ohms + + + RXFIFO_ENABLE + Enabled + + + RXINVPOL + Non-invert + + + RXLDR + Off + + + RXLOSTHRESHOLD + 2 + + + RXLSM + Enabled + + + RXSC + K28P5 + + + RXWA + Barrel Shift + + + RX_DATA_WIDTH + 8/10-Bit + + + RX_FICLK_RATE + 125.0000 + + + RX_LINE_RATE + 1.2500 + + + RX_RATE_DIV + Full Rate + + + SCIPORT + Enabled + + + SOFTLOL + Enabled + + + TX8B10B + Enabled + + + TXAMPLITUDE + 1100 + + + TXDEPOST + Disabled + + + TXDEPRE + Disabled + + + TXDIFFTERM + 50 ohms + + + TXFIFO_ENABLE + Enabled + + + TXINVPOL + Non-invert + + + TXLDR + Off + + + TXPLLLOLTHRESHOLD + 0 + + + TXPLLMULT + 10X + + + TX_DATA_WIDTH + 8/10-Bit + + + TX_FICLK_RATE + 125.0000 + + + TX_LINE_RATE + 1.2500 + + + TX_MAX_RATE + 1.25 + + + TX_RATE_DIV + Full Rate + + + VHDL + 1 + + + Verilog + 0 + + + + sgmii_ecp5.pp + pp + + + sgmii_ecp5.sym + sym + + + sgmii_ecp5.tft + tft + + + sgmii_ecp5.txt + pcs_module + + + + + DCUCHANNEL + 1 + + true + false + DCUCHANNEL + + Lane0 + + + + + + + + + extref_refclkn + extref_refclkn + + + sys_yes + + + + + + + extref_refclko + extref_refclko + extref_refclko + + + sys_no + internal + + + + + + + + extref_refclkp + extref_refclkp + + + sys_yes + + + + + + + sgmii_ecp5_ctc_del_s + sgmii_ecp5_ctc_del_s + + + + + sgmii_ecp5_ctc_ins_s + sgmii_ecp5_ctc_ins_s + + + + + sgmii_ecp5_ctc_orun_s + sgmii_ecp5_ctc_orun_s + + + + + sgmii_ecp5_ctc_urun_s + sgmii_ecp5_ctc_urun_s + + + + + sgmii_ecp5_cyawstn + sgmii_ecp5_cyawstn + + + + + sgmii_ecp5_hdinn + sgmii_ecp5_hdinn + + + sys_yes + + + + + + + sgmii_ecp5_hdinp + sgmii_ecp5_hdinp + + + sys_yes + + + + + + + sgmii_ecp5_hdoutn + sgmii_ecp5_hdoutn + + + sys_yes + + + + + + + sgmii_ecp5_hdoutp + sgmii_ecp5_hdoutp + + + sys_yes + + + + + + + sgmii_ecp5_lsm_status_s + sgmii_ecp5_lsm_status_s + + + + + sgmii_ecp5_pll_lol + sgmii_ecp5_pll_lol + + + + + sgmii_ecp5_rsl_disable + sgmii_ecp5_rsl_disable + + + + + sgmii_ecp5_rsl_rst + sgmii_ecp5_rsl_rst + + + + + sgmii_ecp5_rsl_rx_rdy + sgmii_ecp5_rsl_rx_rdy + + + + + sgmii_ecp5_rsl_tx_rdy + sgmii_ecp5_rsl_tx_rdy + + + + + sgmii_ecp5_rst_dual_c + sgmii_ecp5_rst_dual_c + + + + + sgmii_ecp5_rx_cdr_lol_s + sgmii_ecp5_rx_cdr_lol_s + + + + + sgmii_ecp5_rx_los_low_s + sgmii_ecp5_rx_los_low_s + + + + + sgmii_ecp5_rx_pcs_rst_c + sgmii_ecp5_rx_pcs_rst_c + + + + + sgmii_ecp5_rx_pwrup_c + sgmii_ecp5_rx_pwrup_c + + + + + sgmii_ecp5_rx_serdes_rst_c + sgmii_ecp5_rx_serdes_rst_c + + + + + sgmii_ecp5_sci_en + sgmii_ecp5_sci_en + + + + + sgmii_ecp5_sci_en_dual + sgmii_ecp5_sci_en_dual + + + + + sgmii_ecp5_sci_int + sgmii_ecp5_sci_int + + + + + sgmii_ecp5_sci_rd + sgmii_ecp5_sci_rd + + + + + sgmii_ecp5_sci_sel + sgmii_ecp5_sci_sel + + + + + sgmii_ecp5_sci_sel_dual + sgmii_ecp5_sci_sel_dual + + + + + sgmii_ecp5_sci_wrn + sgmii_ecp5_sci_wrn + + + + + sgmii_ecp5_serdes_pdb + sgmii_ecp5_serdes_pdb + + + + + sgmii_ecp5_serdes_rst_dual_c + sgmii_ecp5_serdes_rst_dual_c + + + + + sgmii_ecp5_signal_detect_c + sgmii_ecp5_signal_detect_c + + + + + sgmii_ecp5_tx_pclk + sgmii_ecp5_tx_pclk + + + + + sgmii_ecp5_tx_pcs_rst_c + sgmii_ecp5_tx_pcs_rst_c + + + + + sgmii_ecp5_tx_pwrup_c + sgmii_ecp5_tx_pwrup_c + + + + + sgmii_ecp5_tx_serdes_rst_c + sgmii_ecp5_tx_serdes_rst_c + + + + + sgmii_ecp5_txi_clk + sgmii_ecp5_txi_clk + + + + + sgmii_ecp5_rx_cv_err + sgmii_ecp5_rx_cv_err + + + + + sgmii_ecp5_rx_cv_err[0] + sgmii_ecp5_rx_cv_err[0] + + + + + sgmii_ecp5_rx_disp_err + sgmii_ecp5_rx_disp_err + + + + + sgmii_ecp5_rx_disp_err[0] + sgmii_ecp5_rx_disp_err[0] + + + + + sgmii_ecp5_rx_k + sgmii_ecp5_rx_k + + + + + sgmii_ecp5_rx_k[0] + sgmii_ecp5_rx_k[0] + + + + + sgmii_ecp5_rxdata + sgmii_ecp5_rxdata + + + + + sgmii_ecp5_rxdata[0] + sgmii_ecp5_rxdata[0] + + + + + sgmii_ecp5_rxdata[1] + sgmii_ecp5_rxdata[1] + + + + + sgmii_ecp5_rxdata[2] + sgmii_ecp5_rxdata[2] + + + + + sgmii_ecp5_rxdata[3] + sgmii_ecp5_rxdata[3] + + + + + sgmii_ecp5_rxdata[4] + sgmii_ecp5_rxdata[4] + + + + + sgmii_ecp5_rxdata[5] + sgmii_ecp5_rxdata[5] + + + + + sgmii_ecp5_rxdata[6] + sgmii_ecp5_rxdata[6] + + + + + sgmii_ecp5_rxdata[7] + sgmii_ecp5_rxdata[7] + + + + + sgmii_ecp5_sci_addr + sgmii_ecp5_sci_addr + + + + + sgmii_ecp5_sci_addr[0] + sgmii_ecp5_sci_addr[0] + + + + + sgmii_ecp5_sci_addr[1] + sgmii_ecp5_sci_addr[1] + + + + + sgmii_ecp5_sci_addr[2] + sgmii_ecp5_sci_addr[2] + + + + + sgmii_ecp5_sci_addr[3] + sgmii_ecp5_sci_addr[3] + + + + + sgmii_ecp5_sci_addr[4] + sgmii_ecp5_sci_addr[4] + + + + + sgmii_ecp5_sci_addr[5] + sgmii_ecp5_sci_addr[5] + + + + + sgmii_ecp5_sci_rddata + sgmii_ecp5_sci_rddata + + + + + sgmii_ecp5_sci_rddata[0] + sgmii_ecp5_sci_rddata[0] + + + + + sgmii_ecp5_sci_rddata[1] + sgmii_ecp5_sci_rddata[1] + + + + + sgmii_ecp5_sci_rddata[2] + sgmii_ecp5_sci_rddata[2] + + + + + sgmii_ecp5_sci_rddata[3] + sgmii_ecp5_sci_rddata[3] + + + + + sgmii_ecp5_sci_rddata[4] + sgmii_ecp5_sci_rddata[4] + + + + + sgmii_ecp5_sci_rddata[5] + sgmii_ecp5_sci_rddata[5] + + + + + sgmii_ecp5_sci_rddata[6] + sgmii_ecp5_sci_rddata[6] + + + + + sgmii_ecp5_sci_rddata[7] + sgmii_ecp5_sci_rddata[7] + + + + + sgmii_ecp5_sci_wrdata + sgmii_ecp5_sci_wrdata + + + + + sgmii_ecp5_sci_wrdata[0] + sgmii_ecp5_sci_wrdata[0] + + + + + sgmii_ecp5_sci_wrdata[1] + sgmii_ecp5_sci_wrdata[1] + + + + + sgmii_ecp5_sci_wrdata[2] + sgmii_ecp5_sci_wrdata[2] + + + + + sgmii_ecp5_sci_wrdata[3] + sgmii_ecp5_sci_wrdata[3] + + + + + sgmii_ecp5_sci_wrdata[4] + sgmii_ecp5_sci_wrdata[4] + + + + + sgmii_ecp5_sci_wrdata[5] + sgmii_ecp5_sci_wrdata[5] + + + + + sgmii_ecp5_sci_wrdata[6] + sgmii_ecp5_sci_wrdata[6] + + + + + sgmii_ecp5_sci_wrdata[7] + sgmii_ecp5_sci_wrdata[7] + + + + + sgmii_ecp5_tx_disp_correct + sgmii_ecp5_tx_disp_correct + + + + + sgmii_ecp5_tx_disp_correct[0] + sgmii_ecp5_tx_disp_correct[0] + + + + + sgmii_ecp5_tx_k + sgmii_ecp5_tx_k + + + + + sgmii_ecp5_tx_k[0] + sgmii_ecp5_tx_k[0] + + + + + sgmii_ecp5_txdata + sgmii_ecp5_txdata + + + + + sgmii_ecp5_txdata[0] + sgmii_ecp5_txdata[0] + + + + + sgmii_ecp5_txdata[1] + sgmii_ecp5_txdata[1] + + + + + sgmii_ecp5_txdata[2] + sgmii_ecp5_txdata[2] + + + + + sgmii_ecp5_txdata[3] + sgmii_ecp5_txdata[3] + + + + + sgmii_ecp5_txdata[4] + sgmii_ecp5_txdata[4] + + + + + sgmii_ecp5_txdata[5] + sgmii_ecp5_txdata[5] + + + + + sgmii_ecp5_txdata[6] + sgmii_ecp5_txdata[6] + + + + + sgmii_ecp5_txdata[7] + sgmii_ecp5_txdata[7] + + + + + sgmii_ecp5_xmit + sgmii_ecp5_xmit + + + + + sgmii_ecp5_xmit[0] + sgmii_ecp5_xmit[0] + + + + + + diff --git a/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd new file mode 100644 index 0000000..a9521ee --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd @@ -0,0 +1,179 @@ + + + +-- +-- Verific VHDL Description of module GbePcsExtrefclk +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity GbePcsExtrefclk is + port (sgmii_ecp5_rx_cv_err: out std_logic_vector(0 downto 0); + sgmii_ecp5_rx_disp_err: out std_logic_vector(0 downto 0); + sgmii_ecp5_rx_k: out std_logic_vector(0 downto 0); + sgmii_ecp5_rxdata: out std_logic_vector(7 downto 0); + sgmii_ecp5_sci_addr: in std_logic_vector(5 downto 0); + sgmii_ecp5_sci_rddata: out std_logic_vector(7 downto 0); + sgmii_ecp5_sci_wrdata: in std_logic_vector(7 downto 0); + sgmii_ecp5_tx_disp_correct: in std_logic_vector(0 downto 0); + sgmii_ecp5_tx_k: in std_logic_vector(0 downto 0); + sgmii_ecp5_txdata: in std_logic_vector(7 downto 0); + sgmii_ecp5_xmit: in std_logic_vector(0 downto 0); + extref_refclkn: in std_logic; + extref_refclkp: in std_logic; + sgmii_ecp5_ctc_del_s: out std_logic; + sgmii_ecp5_ctc_ins_s: out std_logic; + sgmii_ecp5_ctc_orun_s: out std_logic; + sgmii_ecp5_ctc_urun_s: out std_logic; + sgmii_ecp5_cyawstn: in std_logic; + sgmii_ecp5_hdinn: in std_logic; + sgmii_ecp5_hdinp: in std_logic; + sgmii_ecp5_hdoutn: out std_logic; + sgmii_ecp5_hdoutp: out std_logic; + sgmii_ecp5_lsm_status_s: out std_logic; + sgmii_ecp5_pll_lol: out std_logic; + sgmii_ecp5_rsl_disable: in std_logic; + sgmii_ecp5_rsl_rst: in std_logic; + sgmii_ecp5_rsl_rx_rdy: out std_logic; + sgmii_ecp5_rsl_tx_rdy: out std_logic; + sgmii_ecp5_rst_dual_c: in std_logic; + sgmii_ecp5_rx_cdr_lol_s: out std_logic; + sgmii_ecp5_rx_los_low_s: out std_logic; + sgmii_ecp5_rx_pcs_rst_c: in std_logic; + sgmii_ecp5_rx_pwrup_c: in std_logic; + sgmii_ecp5_rx_serdes_rst_c: in std_logic; + sgmii_ecp5_sci_en: in std_logic; + sgmii_ecp5_sci_en_dual: in std_logic; + sgmii_ecp5_sci_int: out std_logic; + sgmii_ecp5_sci_rd: in std_logic; + sgmii_ecp5_sci_sel: in std_logic; + sgmii_ecp5_sci_sel_dual: in std_logic; + sgmii_ecp5_sci_wrn: in std_logic; + sgmii_ecp5_serdes_pdb: in std_logic; + sgmii_ecp5_serdes_rst_dual_c: in std_logic; + sgmii_ecp5_signal_detect_c: in std_logic; + sgmii_ecp5_tx_pclk: out std_logic; + sgmii_ecp5_tx_pcs_rst_c: in std_logic; + sgmii_ecp5_tx_pwrup_c: in std_logic; + sgmii_ecp5_tx_serdes_rst_c: in std_logic; + sgmii_ecp5_txi_clk: in std_logic + ); + +end entity GbePcsExtrefclk; -- sbp_module=true + +architecture GbePcsExtrefclk of GbePcsExtrefclk is + component extref is + port (refclkn: in std_logic; + refclko: out std_logic; + refclkp: in std_logic + ); + + end component extref; -- not_need_bbox=true + + + component sgmii_ecp5 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + xmit: in std_logic_vector(0 downto 0); + ctc_del_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_orun_s: out std_logic; + ctc_urun_s: out std_logic; + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + sli_rst: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic; + txi_clk: in std_logic + ); + + end component sgmii_ecp5; -- not_need_bbox=true + + + signal extref_refclko,sli_rst_wire0,gnd : std_logic; +begin + sli_rst_wire0 <= sgmii_ecp5_serdes_rst_dual_c OR sgmii_ecp5_tx_serdes_rst_c OR (NOT sgmii_ecp5_serdes_pdb) OR (NOT sgmii_ecp5_tx_pwrup_c); + extref_inst: component extref port map (refclkn=>extref_refclkn,refclko=>extref_refclko, + refclkp=>extref_refclkp); + sgmii_ecp5_inst: component sgmii_ecp5 port map (rx_cv_err(0)=>sgmii_ecp5_rx_cv_err(0), + rx_disp_err(0)=>sgmii_ecp5_rx_disp_err(0),rx_k(0)=>sgmii_ecp5_rx_k(0), + rxdata(7)=>sgmii_ecp5_rxdata(7),rxdata(6)=>sgmii_ecp5_rxdata(6), + rxdata(5)=>sgmii_ecp5_rxdata(5),rxdata(4)=>sgmii_ecp5_rxdata(4), + rxdata(3)=>sgmii_ecp5_rxdata(3),rxdata(2)=>sgmii_ecp5_rxdata(2), + rxdata(1)=>sgmii_ecp5_rxdata(1),rxdata(0)=>sgmii_ecp5_rxdata(0), + sci_addr(5)=>sgmii_ecp5_sci_addr(5),sci_addr(4)=>sgmii_ecp5_sci_addr(4), + sci_addr(3)=>sgmii_ecp5_sci_addr(3),sci_addr(2)=>sgmii_ecp5_sci_addr(2), + sci_addr(1)=>sgmii_ecp5_sci_addr(1),sci_addr(0)=>sgmii_ecp5_sci_addr(0), + sci_rddata(7)=>sgmii_ecp5_sci_rddata(7),sci_rddata(6)=>sgmii_ecp5_sci_rddata(6), + sci_rddata(5)=>sgmii_ecp5_sci_rddata(5),sci_rddata(4)=>sgmii_ecp5_sci_rddata(4), + sci_rddata(3)=>sgmii_ecp5_sci_rddata(3),sci_rddata(2)=>sgmii_ecp5_sci_rddata(2), + sci_rddata(1)=>sgmii_ecp5_sci_rddata(1),sci_rddata(0)=>sgmii_ecp5_sci_rddata(0), + sci_wrdata(7)=>sgmii_ecp5_sci_wrdata(7),sci_wrdata(6)=>sgmii_ecp5_sci_wrdata(6), + sci_wrdata(5)=>sgmii_ecp5_sci_wrdata(5),sci_wrdata(4)=>sgmii_ecp5_sci_wrdata(4), + sci_wrdata(3)=>sgmii_ecp5_sci_wrdata(3),sci_wrdata(2)=>sgmii_ecp5_sci_wrdata(2), + sci_wrdata(1)=>sgmii_ecp5_sci_wrdata(1),sci_wrdata(0)=>sgmii_ecp5_sci_wrdata(0), + tx_disp_correct(0)=>sgmii_ecp5_tx_disp_correct(0),tx_k(0)=>sgmii_ecp5_tx_k(0), + txdata(7)=>sgmii_ecp5_txdata(7),txdata(6)=>sgmii_ecp5_txdata(6), + txdata(5)=>sgmii_ecp5_txdata(5),txdata(4)=>sgmii_ecp5_txdata(4), + txdata(3)=>sgmii_ecp5_txdata(3),txdata(2)=>sgmii_ecp5_txdata(2), + txdata(1)=>sgmii_ecp5_txdata(1),txdata(0)=>sgmii_ecp5_txdata(0), + xmit(0)=>sgmii_ecp5_xmit(0),ctc_del_s=>sgmii_ecp5_ctc_del_s,ctc_ins_s=>sgmii_ecp5_ctc_ins_s, + ctc_orun_s=>sgmii_ecp5_ctc_orun_s,ctc_urun_s=>sgmii_ecp5_ctc_urun_s, + cyawstn=>sgmii_ecp5_cyawstn,hdinn=>sgmii_ecp5_hdinn,hdinp=>sgmii_ecp5_hdinp, + hdoutn=>sgmii_ecp5_hdoutn,hdoutp=>sgmii_ecp5_hdoutp,lsm_status_s=>sgmii_ecp5_lsm_status_s, + pll_lol=>sgmii_ecp5_pll_lol,pll_refclki=>extref_refclko,rsl_disable=>sgmii_ecp5_rsl_disable, + rsl_rst=>sgmii_ecp5_rsl_rst,rsl_rx_rdy=>sgmii_ecp5_rsl_rx_rdy, + rsl_tx_rdy=>sgmii_ecp5_rsl_tx_rdy,rst_dual_c=>sgmii_ecp5_rst_dual_c, + rx_cdr_lol_s=>sgmii_ecp5_rx_cdr_lol_s,rx_los_low_s=>sgmii_ecp5_rx_los_low_s, + rx_pcs_rst_c=>sgmii_ecp5_rx_pcs_rst_c,rx_pwrup_c=>sgmii_ecp5_rx_pwrup_c, + rx_serdes_rst_c=>sgmii_ecp5_rx_serdes_rst_c,rxrefclk=>extref_refclko, + sci_en=>sgmii_ecp5_sci_en,sci_en_dual=>sgmii_ecp5_sci_en_dual, + sci_int=>sgmii_ecp5_sci_int,sci_rd=>sgmii_ecp5_sci_rd,sci_sel=>sgmii_ecp5_sci_sel, + sci_sel_dual=>sgmii_ecp5_sci_sel_dual,sci_wrn=>sgmii_ecp5_sci_wrn, + serdes_pdb=>sgmii_ecp5_serdes_pdb,serdes_rst_dual_c=>sgmii_ecp5_serdes_rst_dual_c, + signal_detect_c=>sgmii_ecp5_signal_detect_c,sli_rst=>sli_rst_wire0, + tx_pclk=>sgmii_ecp5_tx_pclk,tx_pcs_rst_c=>sgmii_ecp5_tx_pcs_rst_c, + tx_pwrup_c=>sgmii_ecp5_tx_pwrup_c,tx_serdes_rst_c=>sgmii_ecp5_tx_serdes_rst_c, + txi_clk=>sgmii_ecp5_txi_clk); + gnd <= '0' ; + +end architecture GbePcsExtrefclk; -- sbp_module=true + diff --git a/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v new file mode 100644 index 0000000..0876ac6 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v @@ -0,0 +1,19 @@ +//Verilog instantiation template + +GbePcsExtrefclk _inst (.extref_refclkn(), .extref_refclkp(), .sgmii_ecp5_rx_cv_err(), + .sgmii_ecp5_rx_disp_err(), .sgmii_ecp5_rx_k(), .sgmii_ecp5_rxdata(), + .sgmii_ecp5_sci_addr(), .sgmii_ecp5_sci_rddata(), .sgmii_ecp5_sci_wrdata(), + .sgmii_ecp5_tx_disp_correct(), .sgmii_ecp5_tx_k(), .sgmii_ecp5_txdata(), + .sgmii_ecp5_xmit(), .sgmii_ecp5_ctc_del_s(), .sgmii_ecp5_ctc_ins_s(), + .sgmii_ecp5_ctc_orun_s(), .sgmii_ecp5_ctc_urun_s(), .sgmii_ecp5_cyawstn(), + .sgmii_ecp5_hdinn(), .sgmii_ecp5_hdinp(), .sgmii_ecp5_hdoutn(), + .sgmii_ecp5_hdoutp(), .sgmii_ecp5_lsm_status_s(), .sgmii_ecp5_pll_lol(), + .sgmii_ecp5_rsl_disable(), .sgmii_ecp5_rsl_rst(), .sgmii_ecp5_rsl_rx_rdy(), + .sgmii_ecp5_rsl_tx_rdy(), .sgmii_ecp5_rst_dual_c(), .sgmii_ecp5_rx_cdr_lol_s(), + .sgmii_ecp5_rx_los_low_s(), .sgmii_ecp5_rx_pcs_rst_c(), .sgmii_ecp5_rx_pwrup_c(), + .sgmii_ecp5_rx_serdes_rst_c(), .sgmii_ecp5_sci_en(), .sgmii_ecp5_sci_en_dual(), + .sgmii_ecp5_sci_int(), .sgmii_ecp5_sci_rd(), .sgmii_ecp5_sci_sel(), + .sgmii_ecp5_sci_sel_dual(), .sgmii_ecp5_sci_wrn(), .sgmii_ecp5_serdes_pdb(), + .sgmii_ecp5_serdes_rst_dual_c(), .sgmii_ecp5_signal_detect_c(), + .sgmii_ecp5_tx_pclk(), .sgmii_ecp5_tx_pcs_rst_c(), .sgmii_ecp5_tx_pwrup_c(), + .sgmii_ecp5_tx_serdes_rst_c(), .sgmii_ecp5_txi_clk()); \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.cmd b/gbe/cores/GbePcsExtrefclk/extref/extref.cmd new file mode 100644 index 0000000..6dfe979 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/extref.cmd @@ -0,0 +1,18 @@ +PROJECT: extref + working_path: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results" + module: extref + verilog_file_list: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" + vlog_std_v2001: true + constraint_file_name: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc" + suffix_name: edn + output_file_name: extref + write_prf: true + disable_io_insertion: true + force_gsr: false + frequency: 100 + fanout_limit: 50 + retiming: false + pipe: false + part: LFE5UM-85F + speed_grade: 8 + diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.fdc b/gbe/cores/GbePcsExtrefclk/extref/extref.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/extref.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.lpc b/gbe/cores/GbePcsExtrefclk/extref/extref.lpc new file mode 100644 index 0000000..0365a5c --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/extref.lpc @@ -0,0 +1,31 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=EXTREF +CoreRevision=1.1 +CoreStatus=Demo +CoreType=LPM +Date=05/13/2019 +ModuleName=extref +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=09:10:11 +VendorName=Lattice Semiconductor Corporation +[Parameters] +Destination=Synplicity +EDIF=1 +EXTREFDCBIAS=Disabled +EXTREFTERMRES=50 ohms +Expression=BusA(0 to 7) +IO=0 +Order=Big Endian [MSB:LSB] +VHDL=1 +Verilog=0 +[SYSTEMPNR] +EXTREF=DCU1 diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.ngd b/gbe/cores/GbePcsExtrefclk/extref/extref.ngd new file mode 100644 index 0000000000000000000000000000000000000000..0df76d6f76a9f361c05840a346004fa7d65de336 GIT binary patch literal 2905 zcma)8O>9(E6n^&&?X*;}iHRDG=Bv& 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Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module extref +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity extref is + port (refclkp: in std_logic; + refclkn: in std_logic; + refclko: out std_logic + ); + +end entity extref; + +architecture v1 of extref is + signal n2,n1,gnd,pwr : std_logic; + attribute LOC : string; + attribute LOC of EXTREF1_inst : label is "EXTREF1"; +begin + EXTREF1_inst: component EXTREFB generic map (REFCK_PWDNB=>"0b1",REFCK_RTERM=>"0b1", + REFCK_DCBIAS_EN=>"0b0") + port map (REFCLKP=>refclkp,REFCLKN=>refclkn,REFCLKO=>refclko); + n2 <= '1' ; + n1 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref_ngd.asd b/gbe/cores/GbePcsExtrefclk/extref/extref_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/extref_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/.recordref b/gbe/cores/GbePcsExtrefclk/extref/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/_CMD_.CML b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_CMD_.CML new file mode 100644 index 0000000..59e765e --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs -top extref -hdllog /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/_cmd._cml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_cmd._cml new file mode 100644 index 0000000..840870f --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top extref -osyn /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/dm/layer0.xdm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..6d7c478 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/dm/layer0.xdm @@ -0,0 +1,79 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> 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b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.areasrr new file mode 100644 index 0000000..7038b76 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.areasrr @@ -0,0 +1,15 @@ +---------------------------------------------------------------------- +Report for cell extref.v1 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + EXTREFB 1 100.0 + GSR 1 100.0 + PUR 1 100.0 + VHI 1 100.0 + VLO 1 100.0 + + TOTAL 5 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.fse b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.fse new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.htm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.htm new file mode 100644 index 0000000..80016ba --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.htm @@ -0,0 +1,9 @@ + + + syntmp/extref_srr.htm log file + + + + + + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.prj b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.prj new file mode 100644 index 0000000..c373cbc --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.prj @@ -0,0 +1,46 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.prj +#-- Written on Mon May 13 09:10:13 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) 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b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srf new file mode 100644 index 0000000..9224860 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srf @@ -0,0 +1,333 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Mon May 13 09:10:13 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box. +Post processing for ecp5um.extrefb.syn_black_box +Post processing for work.extref.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:15 2019 + +###########################################################] +Pre-mapping Report + +# Mon May 13 09:10:15 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist extref + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------- +========================================================================= + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Mon May 13 09:10:16 2019 + +###########################################################] +Map & Optimize Report + +# Mon May 13 09:10:16 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Mon May 13 09:10:18 2019 +# + + +Top view: extref +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: NA + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +--------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 NA NA system system_clkgroup +=============================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------- +======================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +EXTREFB: 1 +GSR: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box. +Post processing for ecp5um.extrefb.syn_black_box +Post processing for work.extref.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:15 2019 + +###########################################################] +Pre-mapping Report + +# Mon May 13 09:10:15 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist extref + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------- +========================================================================= + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Mon May 13 09:10:16 2019 + +###########################################################] +Map & Optimize Report + +# Mon May 13 09:10:16 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Mon May 13 09:10:18 2019 +# + + +Top view: extref +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: NA + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +--------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 NA NA system system_clkgroup +=============================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------- +======================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +--------------------------------------- +Resource Usage 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std_logic ; + signal VCC : std_logic ; +begin +GND_0: VLO port map ( + Z => GND); +VCC_0: VHI port map ( + Z => VCC); +PUR_INST: PUR port map ( + PUR => VCC); +GSR_INST: GSR port map ( + GSR => VCC); +EXTREF1_INST: EXTREFB + generic map( + REFCK_PWDNB => "0b1", + REFCK_RTERM => "0b1", + REFCK_DCBIAS_EN => "0b0" + ) + port map ( + REFCLKP => refclkp, + REFCLKN => refclkn, + REFCLKO => refclko); +end beh; + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vm new file mode 100644 index 0000000..aa10424 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vm @@ -0,0 +1,59 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Mon May 13 09:10:18 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 11 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc " + +`timescale 100 ps/100 ps +module extref ( + refclkp, + refclkn, + refclko +) +; +input refclkp ; +input refclkn ; +output refclko ; +wire refclkp ; +wire refclkn ; +wire refclko ; +wire GND ; +wire VCC ; + VLO GND_0 ( + .Z(GND) +); + VHI VCC_0 ( + .Z(VCC) +); + PUR PUR_INST ( + .PUR(VCC) +); + GSR GSR_INST ( + .GSR(VCC) +); +// @8:31 +(* LOC="EXTREF1" *) EXTREFB EXTREF1_inst ( + .REFCLKP(refclkp), + .REFCLKN(refclkn), + .REFCLKO(refclko) +); +defparam EXTREF1_inst.REFCK_PWDNB = "0b1"; +defparam EXTREF1_inst.REFCK_RTERM = "0b1"; +defparam EXTREF1_inst.REFCK_DCBIAS_EN = "0b0"; +endmodule /* extref */ + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify.lpf new file mode 100644 index 0000000..8e445e1 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify.lpf @@ -0,0 +1,20 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp2.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp4.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp8.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/run_options.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/run_options.txt new file mode 100644 index 0000000..1343a58 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/run_options.txt @@ -0,0 +1,75 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/run_options.txt +#-- Written on Mon May 13 09:10:13 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "extref" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./extref.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.srf" +impl -active "syn_results" diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/scemi_cfg.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/scratchproject.prs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scratchproject.prs new file mode 100644 index 0000000..6a93ebc --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scratchproject.prs @@ -0,0 +1,73 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "extref" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.srf" +impl -active "syn_results" diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr new file mode 100644 index 0000000..c36cce0 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr @@ -0,0 +1,46 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box. +Post processing for ecp5um.extrefb.syn_black_box +Post processing for work.extref.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:14 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db new file mode 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b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr @@ -0,0 +1,11 @@ +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:10:15 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr new file mode 100644 index 0000000..27b114b --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr @@ -0,0 +1,62 @@ +# Mon May 13 09:10:15 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist extref + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------- +========================================================================= + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Mon May 13 09:10:16 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..4dd9838c94d7e3005cdc2c470cfbe338a4b457d4 GIT binary patch literal 8192 zcmeI#F;Buk6bJBYV`L(@7$%YzCP;)tC5;J-NN~bIWMgPb`zR;$j0+3$}A zz43s?y_?~H_PY(4&^pTFd6b{gQmVzF+O-@u7E=9aUfDOLGEFy|`<02PyxRo<0SG_< z0uX=z1Rwwb2tWV=5P-m61z!A8wY-^}`ggZM5cHQiUQn#nn)5W}Ds}xqr!|#^GM#YyyYmanA8M`u literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr new file mode 100644 index 0000000000000000000000000000000000000000..e4da5e4149a0131bb9984e345a8d72e1b101e717 GIT binary patch literal 2533 zcmV3|-4G(Gra8XPQxH?46ATuYJp9Jo!F>{#m`1Zc_lBl4gRJLZ z7aD_-a=#NtiaAHCprXDMH641KoU{*R3@%;?Um|%f9YbzWW#uCNEnQ~JHgDy{RnvX| z00960#8_=_+%^*ay!sWnP(b3sGHFZM@-|IT?@(MiSd#V>RX^l|V6KZ85^v>#-gOi7 z$KObfgI;?DdKWh#U|6QL^FGf!vu9bRWtthDUe%x@Pfi-{?7)o>^R#Bdb5JojE+D)~ z8n_p?yEXU~dm@?yo~s$8l>pZ8JlPf$>xE}oG*Vd(_c9x%h2u(iVZdnLnM^*?m;AIr=Z*}n+gG^dL9?-HpG|J?u4H~ep zxlf@G7%=I=re2~+Jk}Z{cgY%ZVK96x(ws9d0z?H)a2?VcL2kh9diTV$6^PW#ydrm3 zi9^HMoFoBLC|Hq#6L)y?WIuo3-W|=+6~PZP2e-ICTK+J{R16L!6vY-}<5q5Nv0G!I zX4<1Jnq)obG%z$pvl4>?CB0^ThDC+VU{;VUI7!BMrDqjG{INJ#`Wj{j|FW)%NO9-^ z+VQQ}w#Gsu&G^|LMKW|ReNqm*Y)5^}wpvv=;(4J#C8J@$$+uXZk9RdnHRbKRDeEF4 zi+yxW$_*-bw3ui?yFK9!U??JR}~pe*xX~`!E6K~Y>Q;QaVIj9`aEz~&;a>HmM8MpK{ydhCAuF_maFl~{ zP5mA8;9_!*9S6Zj&iUDJ253;!Td~2~C6Mn}hIX$p-#f(Ws;k~Ey7{8Q>Zp5r zoMm~inqkgvgcAlmT-M;N)@s=0m?9L8?6No<{zOPc!M9Pl;7}Z%(qNR&v3h&BJwS8X ztDgn-IN+wkqpEw3Z?}u9MRqk`=G5%98N?D_oV=y?k2Xbz)$?PW+rU_UXz{{dmRO@< z4|h1u=5*%3qLT`pV(6IBew;(-rS2(X!Z@Lw#T0;|se^HpKtZLLIYWP8ONBqHNhGBHkO66-2TcQ&pOxu*#eT~IVbcmn;#-wM9=uw&xMDtTxW%U8)etz=N;u2H$VJp4|+Ss6^-4lH-(8*kfr?i&K9@ZU-eRXqIeqY`BWPOEDqL6 zz9?}SbsYQPDN&PFP+w8c7pum!BR6!CD6niFIAN>3@;GCad5U)Iqp|)*>^0b^6DTvt zzGl`87%ptT6rZQQjvnfZ%6kL{b76%tG)8}Mqc6*#iGu*O(Tf9jss2>Y5_j(}!4Ncq z3X*zx(cPQ)vSS$cpfTnBc%OWqs2Ax&Rfqf2FatL}AD!$^Gs4%gw+O-XRO?YpcspT4X80Ufyo-XMeMo->$;bK`hx$&qXcHt^VR<3 zF3ZOH(3avr`0{L=oeZcR8=*$L=N@Dga z44_;fUTaqObk&#%n`kD3_9ETopQa1=U`e8HxPmzE+vaFqQoNoyY-nwR#WhLok@=>c zYM%B(G@ksXIArS10Kpe2$A;sx|7pMDW<3Dd#EE;&8|aT>JKr|NU)F81J6jtPBvBhD ztr)2Dq8Y{>Kwytv>qk}fvDWAGJl6Ur`oA(p*{c<2+fWqbcS(8q9C4>TIuf1tUnIw( zDJkw>q^=9G{cE}}@@#o?i>{{qEFOSX=MLj>A9I%$eRdtwda~&Pm$%A0A_>5Vna1-4 z$nUSatcSQx4avK`SR!#_&uW5StC2Xhrfp-9ecz3{meWd|wIJ!UtS3`xj4jsVJfr=A zZC}k1kkKsDNP97kd$Fa;HbOCi(P>7FI72{B`Xv!1f`3L_jBF9T?`<-}-+*HGCJd2JD%Oo;IH!RtKT2YGJH7hm^hz6JU|3^O~Q#Ojpy|Nj0-d61#yWueNQr; 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(Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..1ad405d --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +0 / 0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..68def92 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +7 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt + + + +1 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_errors.txt + + + +0h:00m:02s + + +0h:00m:02s + + +146MB + + +1557731418 + + + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..52701c6 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml @@ -0,0 +1,23 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +System +100.0 MHz +NA +NA + + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt new file mode 100644 index 0000000..b99a088 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt @@ -0,0 +1 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt new file mode 100644 index 0000000..eed8756 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt @@ -0,0 +1,2 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml new file mode 100644 index 0000000..963604b --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +2 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +142MB + + +1557731416 + + + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db new file mode 100644 index 0000000000000000000000000000000000000000..145597c4adc4b482a47f9aed0f9a755098cda8f8 GIT binary patch literal 20480 zcmeI3%Wm676oyG#wkQ}q$DyhyiwgKoQNv+WDyC9=!mMK{-RlXhVw{RbjBmvep|ec`s;cSJ3p ztbH0cA4%VczNh^IPk$yNX>{O^#(gjB$inOsq(_ol6`zJ`vABfHng4Gh!# z-(iWxf9KEm=W~C|{WN!xJ*NpY5C8!X009sH0T2KI5C8!X0D=EX;77+{Tbxx7D}hRk zr+k?-RBZAM`9`+Z#uCl%hwqpZ`M5`W{R4XOJaiMGY#Y&2L)W`yhi#Db!!haM;#=qr zeHycs^xbsz$gXreimj1<4bY_!PM6EpMY=9pI_OI!nomULy4sOS>QqGJMn+4Sd`p@1 zD&640gnqVk`VG#|>XeFL=PQ2t;lsZRR>i8G-z4ju7W6$z*3+On6ZbhI=r_>(k}~_t zoGsq11b(NXrSSqq&q7`u7(E8x+`277&-e#25%kaqDjvjr*}6{oewDm$7v90)qpCd;(Drb0Z@N>S3U_um4>DFe8@ah9MB2_>;#8VUZOd)fsIc zf9rV-Oh#q9!tUe?xyv(gK{Z zpEfu4{@LB7t~Lg4z5IixZW6|w1c0nMwY)qQ3kJ*wUP_`~F&Ug`6TAta8N}Vu3V@}9 zNw*s=>MUq@X`W(G>+tzJgd6bXv9Vx^T;JCdX0H}U~+(Mw$+Ww1bsj*JCH zwPXBAzHpwhx1fx7pS&S>BvtoL<~e<;a$8mY{0qH~lp)=^mv-|W+vk6GSW21>rnIDR zK=H-O;6(FfPc%`Wc)i|k#(?a$FuYXy9MG76_k)S5p)2)`{NnyZ!H1*!gy{9V8?C3ES;Qd#s z$CM6$uEqw6ed_P#zM-d<%4pb~-ul47As3uCpur=s&wXN@++Weshm_Xeezr?;(fw_C z=LuT1Swu-i=EnOvWHr=Lw0pTM`A~xOG(?=musEEnY=9T`D77|i!~)b_MEuU)<*Roo z?@w9bA@{&(^$?yvb@C7l_e?`ihbS7vZn4UIlXpCnUD)47;oTr?D!HiK6!}`HMYy&WIXK6&MpqK+*iyS6`Kx__7 z{ASEA(A;eX;&aUGh8O494$$}Dtipy+pEE>5Ih`|Oi55%3T?_$f zYT^$N8Uz-ud?F~tIe6x`X(cB7(X&R=Cm8l>247frrv93&#*A!%)$KKAeZ=nYn@eUm4Q`q zq?U_)DX%w547#U>8CCw>r+H5** zf@8(&_N78R)ugO&8pfV|FN|u>)J-8_~-dOd)h1RU_wD1BQlW2=9NphyM*@U#D zFDn^D7A32aWeO~3r7mYxy=UCzdI&vYJOUr3GsE7Ry|qYCX*H}gsWkF1Tfs}a+S*N; zKWz7E_DWh~8~&9AwGCHLQ4mn5osN7V{36@-f^EoiN?Vi{P{``U$&H$#2(R#RW&+z3Y`X{CL=VWcGb& zu2_wvrb?lJN|M9%%T^+_gxi&`27TF(!v``=7LRjBM^tixp0B48R2z6(bek!miG~4T8=UQ~?svFlT zo;M?Ef(?C53Tij8#nsNu(Iyd2NtGTgZ|xOs>Ne~?SG5SMtRpFr3Hy%rFneqJihG2g z=${FN9Zp!MKBuD3Mj;88jIOv6oC&5e4o0v6>kHOZu+>so*X)V{EdJ(8>mXN)+e*%U z4Gwj)&pV1c@x-0l{1c^uHTt^ZXd5?7k!TIrhpEhOgFqHS42 zzjYi5xbJ@dHPlC4@S?QPB_VI&4#5neiL~hS-SkW8r6PWUrb0U!+t5=Vk2_f&lRgg@ z5$~oKG#6hj?1w?GKyw|_=T(B*@I6N?d#ZZ^Bl~#|a<|+m+q|w^3zrFPpcuutQ=;JI&YyKc*Yx?2VdhvSt z2yttAGe7j-(5i!A>MbhMK^0d$mt`_bGBM+4hCfl3XfEecCtX)%HC}R~_-JfvY)@57 z^_TM)UaDEV8P?1cpb=0JFca|X%gh(vFSoxSuPE!yMi%cGNBs@o-WC0AyXz70Pt?cA z+Yv2$+y6=)F;fv#y@Q#(b!sT}P3*VWo)hs#lJlF}6J+jV!f_b&Dkq8S7B9sUBC8I; z$x_TQzHnE#o4SmS?4cRu7w89O5<{)HRPmNnsy>X{zq|Qs> zGhJ-vusCcj7M~NK^rx{nr6WZ(P29DHpcpliGsE6s=TMfBnRe%0aSDw1m?)kaGro`1 zQvb2iyK-;U+flWV(1`Rm4b_b*^du^*TE1Ht${VtlnUmSH%C`zOYcwlf?nX7>)w1-m ze`bBpKFQ{miM!5b?Q1bq^RBjZZJ3f3LGb?2tvi1P^T5G!_e(U=}Lr0vlhk%QUmO`_9tlL{f{NHr4cFtn-XK=q~`E*+_&1%%@ z+t{)TR}WX7dER<%`p&_^R~sueHO07gIq&hDCwI?>M6pFBMVTtaDD~89)`vO}TC5uT zTvnZ@92#!*5JF=mq83T9#FM6w>mfrSJ6tI4FE9RJcYH|qusSKa`4JRz&s(00ooRtZ zMSO)%iu6TS#DuSi26uJN*W-^;Rx&5~yI^w~F`9oj(s!Kuf8G1XzbUY){k#Md@e#2! zR)Ts$c~G``MNUx8DUNhp(NQw#I?WKW7Cag%8=4Uc3q4o5uRlL^f8pzC)x@)8s~4s9 zx++oK`<%;`ZwjoDLE~d37FV@{^p}srtu4n-IKTn{|FRr#Iq&1ckFuyW95GfgNVNqQ z{g9#WABG#!8cIGXw}kB9-tVM&{kEf`*A0jv4ZmEp8v}#6RVDPGYwE$LwZA@EboK_g z^bl4KmQWj%lFW_FiOZXp?ZWJ~`?~TX0+&zUv2L)!xNF26^lYQ2DKEFj?^oqk)e)VE zeJ}|rKlJPE-bt4zu(kNTbG@lVane-?jGEj0stleZi#?FKp+SNq%IFJ&{2mQ7{K8M?r^xf zI~+v^<&Hr?%EKXOlsh^cg+qe~&p|je1e1b#odP0ZK(F&5Bs%4grF_T|UCY&%udXL*$JVq7utpfAW!Cq~)vfZav1e=9J4)LuwIo$SQ2?#O z>5TN-e>7d4wWND_fn=Z>!aC
+
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:10:13 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : extref.vhd(18) | Top entity is set to extref.
+VHDL syntax check successful!
+@N:CD630 : extref.vhd(18) | Synthesizing work.extref.v1.
+@N:CD630 : ecp5um.vhd(2147) | Synthesizing ecp5um.extrefb.syn_black_box.
+Post processing for ecp5um.extrefb.syn_black_box
+Post processing for work.extref.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+
+
 +
+
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:15 2019
+
+###########################################################]
+
+
 +
+
+Pre-mapping Report
+
+
+
 +
+
+# Mon May 13 09:10:15 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+Linked File: extref_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist extref
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock     Clock     Clock
+Level     Clock     Frequency     Period        Type      Group     Load 
+-------------------------------------------------------------------------
+=========================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:10:16 2019
+
+###########################################################]
+
+
 +
+
+Map & Optimize Report
+
+
+
 +
+
+# Mon May 13 09:10:16 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W:MT246 : extref.vhd(31) | Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:10:18 2019
+#
+
+
+Top view:               extref
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: NA
+
+                   Requested     Estimated     Requested     Estimated               Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
+---------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        NA            NA        system     system_clkgroup
+===============================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+--------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+--------------------------------------------------------------------------------------------------------
+========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EXTREFB:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Mon May 13 09:10:18 2019
+
+###########################################################]
+
+
 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm new file mode 100644 index 0000000..88bb149 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/open.png b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/open.png new file mode 100644 index 0000000000000000000000000000000000000000..a227005ed89f5c742cd4c025799ae89068e785a8 GIT binary patch literal 452 zcmV;#0XzPQP)Px#1ZP1_K>z@;j|==^1poj5AY({UO#lFTCIA3{ga82g0001h=l}q9FaQARU;qF* zm;eA5aGbhPJOBUzLPZp>)DD*xuJrLE&vMd$CAS~p-?-;7v0}#6W zK!*&q^nLraG8##gHcA0$>IMWyA3F6832+TiX>f2vout6F5+Ar6F)sEtHPYQAm=&QB zzRsNDFORoz&Rd@j_9k}3P_@Yj@S4LDdw+c%F*c^MW@FMmL^UFq*q*9=#Vw}!jD6ML zTLufTX7?w3b>Dtd?Gz(`Oz!9Ne%vt|je?%YYT1@aFN29GQVmgR!B8?Xp%fDaA%{f{ uQpjB7cbS-F*)`{!amLtrN{glG@TUKEuz}n1Y}Ahc0000 + + + + + + + + + + + + + + + + diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..0991010 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html @@ -0,0 +1,112 @@ + + + Project Status Summary Page + + + + + + +
+ + + + + + + + + + +
Project Settings
Project Name extref Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
Implementation Name syn_results Top Module extref
Pipelining 0 Retiming 0
Resource Sharing 1 Fanout Guide 50
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Run Status
Job NameStatusCPU TimeReal TimeMemoryDate/Time
(compiler)Complete700-00m:01s-5/13/19
9:10 AM
(premap)Complete2000m:00s0m:00s142MB5/13/19
9:10 AM
(fpga_mapper)Complete7100m:02s0m:02s146MB5/13/19
9:10 AM
Multi-srs GeneratorComplete5/13/19
9:10 AM
+
+ + + + + + + + + + + + + + + + +
Area Summary
Register bits 0I/O cells 0
Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
ORCA LUTs +(total_luts) 0

+ + + + + + + + +
Timing Summary
Clock NameReq FreqEst FreqSlack
System100.0 MHzNANA
+
+ + + + + + +
Optimizations Summary
Combined Clock Conversion 0 / 0

+
+
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+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 +0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work extref v1 0 +module work extref 0 + + +# Configuration files used diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig new file mode 100644 index 0000000..79d35eb --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig @@ -0,0 +1,24 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412 +0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work extref v1 0 +module work extref 0 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs new file mode 100644 index 0000000000000000000000000000000000000000..a94cc5b5f880a789a49d583a873e3fc76f206d0b GIT binary patch literal 2552 zcmZvcc{CIZ7sl;mUq+e8Ud$Mb>`J!GYex2_?1k69&uht=HAL33j9r98W+sNpL_%X~ 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Mon May 13 09:09:04 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Mon May 13 09:09:04 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Mon May 13 09:09:04 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Mon May 13 09:09:05 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:09:05 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:09:05 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:09:06 2019 + +###########################################################] +Pre-mapping Report + +# Mon May 13 09:09:07 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Mon May 13 09:09:07 2019 + +###########################################################] +Map & Optimize Report + +# Mon May 13 09:09:07 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 4.90ns 155 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Mon May 13 09:09:11 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.043 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.902 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.043 + + Number of logic level(s): 11 + Starting point: rsl_inst.genblk2\.rxs_rst / Q + Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - +rxs_rst Net - - - - 6 +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - +rsl_rx_serdes_rst_c Net - - - - 3 +rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - +rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - +dual_or_rserd_rst Net - - - - 9 +rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - +rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - +rx_any_rst Net - - - - 2 +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - +rxr_wt_cnt9 Net - - - - 14 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - +rxr_wt_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - +rxr_wt_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - +rxr_wt_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - +rxr_wt_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - +rxr_wt_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - +rxr_wt_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - +rxr_wt_cnt_s[11] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - +================================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 154 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Mon May 13 09:09:11 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..52f21b6ca506bcb9c259911bbd654d527002a3c4 GIT binary patch literal 40960 zcmeHQU2NRgbsqiy*rVCC>nfX#n_Fdnq}HAxIh@gG?A=7xO0Kik+G}a!U2AQIL*CI) z;*d1S(T`U_F_Q#H+t(s}T`c<277Mfp(wCw@AJU>Nus~lMASv1c?MqQ$9~v}hiuRn# z;rw_lOJ0#Qjc{P|jwBA}e&?Kf@A27yf+IYdCfB=if`iT?3ilO~Jq9l~5p|Kth3p0tp2Y3M3RrD3DMfp+G`` zgaQc#e#t4|4vbBoKR?jCf64r0{1@Y6 zV`oOskIW7WLzf3v25zSAJPC`M&e`$lrqaCs;^5MCfh*1AYG$40WYyMWBe$u!IoGZf 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z8vGM3Z68;p-MbdELuX&$b?k@y-5~Zb{}ek9^d1rZ4k&wgem4M($1Vgz`=b0EsEhRP z4Ogb;IG)ANNF!aBKdWhsmG{@^Ts6@OP()xZ-5YvM<-s+LCx7IB1+UY+BYut?<#cR_ zo!B1Qwhd0lF5kzqrW@t42>yooVjOnq{4ak#q|iOU5Gl>)CzE4kN2ca={=X~5=drlZ!#B;-)6F%LWi!VZcud#Uciaaiv$Db7hw!%Ub z(xzv~p5pG2CUYDm2pzjy+HkQPERwgaM>EF?=Bd;E>iEBO#KJ{Q<6W%0X+*Y;f><_%<%Nd*G>0o z=ggw#rNiRgWhdEd?+sW4uY+NF?fsD?#UE>xiG42i;#shPzwm!WpBY$rT%If6$W<%q$d{4u}CEChxnzm~F-3iIk zwAcE2Sbd+t;(DO{aeB8y3CC^W~?NCo&OI20RR8ua!}v`00030 O{{sNu28kWUYykijX#}PK literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vhm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vhm new file mode 100644 index 0000000..a488a9a --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vhm @@ -0,0 +1,6445 @@ +-- +-- Written by Synplicity +-- Product Version "M-2017.03L-SP1-1" +-- Program "Synplify Pro", Mapper "maplat, Build 1796R" +-- Mon May 13 09:09:11 2019 +-- + +-- +-- Written by Synplify Pro version Build 1796R +-- Mon May 13 09:09:11 2019 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_0 is +port( + ppul_sync : in std_logic; + pdiff_sync : out std_logic; + sli_rst : in std_logic; + pll_refclki : in std_logic); +end sync_0s_0; + +architecture beh of sync_0s_0 is + signal DATA_P1 : std_logic ; + signal DATA_P2_QN_1 : std_logic ; + signal VCC : std_logic ; + signal DATA_P1_QN_1 : std_logic ; + signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => pll_refclki, + CD => sli_rst, + Q => pdiff_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => ppul_sync, + CK => pll_refclki, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_6 is +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic); +end sync_0s_6; + +architecture beh of sync_0s_6 is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => tx_pclk, + CD => sli_rst, + Q => ppul_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => rtc_pul, + CK => tx_pclk, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s is +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic); +end sync_0s; + +architecture beh of sync_0s is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN_0 : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN_0 : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( +D => DATA_P1, +CK => pll_refclki, +CD => sli_rst, +Q => rhb_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( +D => phb, +CK => pll_refclki, +CD => sli_rst, +Q => DATA_P1); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5rsl_core_Z2_layer1 is +port( +rx_pcs_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +tx_serdes_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rsl_disable : in std_logic; +rx_serdes_rst_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rst_dual_c : in std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic); +end sgmii_ecp5rsl_core_Z2_layer1; + +architecture beh of sgmii_ecp5rsl_core_Z2_layer1 is +signal RXS_CNT : std_logic_vector(1 downto 0); +signal RXS_CNT_3 : std_logic_vector(1 downto 0); +signal RXPR_APPD_RNO : std_logic_vector(0 to 0); +signal PLOL0_CNT : std_logic_vector(2 downto 0); +signal PLOL0_CNT_3 : std_logic_vector(2 downto 0); +signal RXSR_APPD : std_logic_vector(0 to 0); +signal RXS_CNT_QN : std_logic_vector(1 downto 0); +signal RLOS_DB_CNT : std_logic_vector(3 downto 0); +signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOLS0_CNT_S : std_logic_vector(17 downto 0); +signal RLOLS0_CNT : std_logic_vector(17 downto 0); +signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0); +signal RLOL_DB_CNT : std_logic_vector(3 downto 0); +signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOL1_CNT_S : std_logic_vector(18 downto 0); +signal RLOL1_CNT : std_logic_vector(18 downto 0); +signal RLOL1_CNT_QN : std_logic_vector(18 downto 0); +signal RXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal RXR_WT_CNT : std_logic_vector(11 downto 0); +signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal RXSR_APPD_QN : std_logic_vector(0 to 0); +signal RXPR_APPD : std_logic_vector(0 to 0); +signal RXPR_APPD_QN : std_logic_vector(0 to 0); +signal TXS_CNT : std_logic_vector(1 downto 0); +signal TXS_CNT_QN : std_logic_vector(1 downto 0); +signal TXS_CNT_RNO : std_logic_vector(1 to 1); +signal TXP_CNT : std_logic_vector(1 downto 0); +signal TXP_CNT_QN : std_logic_vector(1 downto 0); +signal TXP_CNT_RNO : std_logic_vector(1 to 1); +signal PLOL_CNT_S : std_logic_vector(19 downto 0); +signal PLOL_CNT : std_logic_vector(19 downto 0); +signal PLOL_CNT_QN : std_logic_vector(19 downto 0); +signal PLOL0_CNT_QN : std_logic_vector(2 downto 0); +signal TXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal TXR_WT_CNT : std_logic_vector(11 downto 0); +signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal TXPR_APPD : std_logic_vector(0 to 0); +signal TXPR_APPD_QN : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17); +signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal PLOL_CNT_CRY : std_logic_vector(18 downto 0); +signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19); +signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19); +signal RXS_RST : std_logic ; +signal VCC : std_logic ; +signal DUAL_OR_RSERD_RST : std_logic ; +signal PLOL0_CNT9 : std_logic ; +signal WAITA_PLOL0 : std_logic ; +signal RLOS_DB_P1 : std_logic ; +signal RLOS_DB : std_logic ; +signal RXP_RST25 : std_logic ; +signal RLOL_DB : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ; +signal RX_ALL_WELL : std_logic ; +signal RSL_RX_PCS_RST_C_10 : std_logic ; +signal UN3_RX_ALL_WELL_2 : std_logic ; +signal UN17_RXR_WT_TC : std_logic ; +signal UN3_RX_ALL_WELL_1 : std_logic ; +signal RX_ANY_RST : std_logic ; +signal RXR_WT_CNT9 : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_I : std_logic ; +signal RLOL1_CNT_TC_1 : std_logic ; +signal \RLOL1_CNT_\ : std_logic ; +signal RXR_WT_EN : std_logic ; +signal RXR_WT_CNTE : std_logic ; +signal RLOLS0_CNT_TC_1 : std_logic ; +signal UN2_RLOS_REDGE_1_I : std_logic ; +signal UN18_TXR_WT_TC : std_logic ; +signal TX_ANY_RST : std_logic ; +signal PLL_LOL_P2 : std_logic ; +signal UN2_PLOL_FEDGE_5_I : std_logic ; +signal N_2124_0 : std_logic ; +signal WAITA_RLOLS06 : std_logic ; +signal UN1_RLOLS0_CNT_TC : std_logic ; +signal WAITA_RLOLS0 : std_logic ; +signal WAITA_RLOLS0_QN : std_logic ; +signal WAIT_CALIB_RNO : std_logic ; +signal UN1_RLOS_FEDGE_1 : std_logic ; +signal WAIT_CALIB : std_logic ; +signal WAIT_CALIB_QN : std_logic ; +signal RXS_RST6 : std_logic ; +signal UN1_RXS_CNT_TC : std_logic ; +signal RXS_RST_QN : std_logic ; +signal RXP_RST2 : std_logic ; +signal RXP_RST2_QN : std_logic ; +signal RLOS_P1 : std_logic ; +signal RLOS_P2 : std_logic ; +signal RLOS_P2_QN : std_logic ; +signal RLOS_P1_QN : std_logic ; +signal RLOS_DB_P1_QN : std_logic ; +signal RLOS_DB_CNT_AXB_0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOS_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOS_DB_CNT_MAX : std_logic ; +signal RLOS_DB_QN : std_logic ; +signal RLOLS0_CNTE : std_logic ; +signal RLOL_P1 : std_logic ; +signal RLOL_P2 : std_logic ; +signal RLOL_P2_QN : std_logic ; +signal RLOL_P1_QN : std_logic ; +signal RLOL_DB_P1 : std_logic ; +signal RLOL_DB_P1_QN : std_logic ; +signal RLOL_DB_CNT_AXB_0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOL_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOL_DB_CNT_MAX : std_logic ; +signal RLOL_DB_QN : std_logic ; +signal RLOL1_CNTE : std_logic ; +signal RXSDR_APPD_2 : std_logic ; +signal RXSDR_APPD : std_logic ; +signal RXSDR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ; +signal RXR_WT_EN_QN : std_logic ; +signal RXDPR_APPD : std_logic ; +signal RXDPR_APPD_QN : std_logic ; +signal RSL_RX_RDY_9 : std_logic ; +signal RUO_RX_RDYR_QN : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ; +signal PLOL_FEDGE : std_logic ; +signal UN1_PLOL0_CNT_TC_1_I : std_logic ; +signal WAITA_PLOL0_QN : std_logic ; +signal UN1_PLOL_CNT_TC : std_logic ; +signal UN2_PLOL_CNT_TC : std_logic ; +signal TXS_RST : std_logic ; +signal TXS_RST_QN : std_logic ; +signal N_10_I : std_logic ; +signal UN9_PLOL0_CNT_TC : std_logic ; +signal UN1_PLOL0_CNT_TC_1 : std_logic ; +signal TXP_RST : std_logic ; +signal TXP_RST_QN : std_logic ; +signal N_11_I : std_logic ; +signal PLL_LOL_P3 : std_logic ; +signal PLL_LOL_P3_QN : std_logic ; +signal PLL_LOL_P1 : std_logic ; +signal PLL_LOL_P2_QN : std_logic ; +signal PLL_LOL_P1_QN : std_logic ; +signal TXSR_APPD_2 : std_logic ; +signal TXSR_APPD : std_logic ; +signal TXSR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ; +signal TXR_WT_EN : std_logic ; +signal TXR_WT_EN_QN : std_logic ; +signal TXR_WT_CNTE : std_logic ; +signal UN2_PLOL_FEDGE_2 : std_logic ; +signal UN2_PLOL_FEDGE_3_I : std_logic ; +signal TXDPR_APPD : std_logic ; +signal TXDPR_APPD_QN : std_logic ; +signal UN2_PLOL_FEDGE_5_1 : std_logic ; +signal RSL_TX_RDY_8 : std_logic ; +signal RUO_TX_RDYR_QN : std_logic ; +signal UN2_PLOL_FEDGE_8_I : std_logic ; +signal RLOS_REDGE : std_logic ; +signal RLOLS0_CNT11_0 : std_logic ; +signal RSL_TX_SERDES_RST_C_7 : std_logic ; +signal \PLOL_CNT_\ : std_logic ; +signal \RLOLS0_CNT_\ : std_logic ; +signal UN8_RXS_CNT_TC : std_logic ; +signal UN1_TXSR_APPD : std_logic ; +signal RSL_SERDES_RST_DUAL_C_6 : std_logic ; +signal UN3_RX_ALL_WELL_2_1 : std_logic ; +signal UN1_RXSDR_OR_SR_APPD : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_1_1 : std_logic ; +signal RSL_RX_SERDES_RST_C_5 : std_logic ; +signal RLOLS0_CNT_TC_1_10 : std_logic ; +signal RLOLS0_CNT_TC_1_11 : std_logic ; +signal RLOLS0_CNT_TC_1_12 : std_logic ; +signal RLOLS0_CNT_TC_1_13 : std_logic ; +signal UN1_PLOL_CNT_TC_11 : std_logic ; +signal UN1_PLOL_CNT_TC_12 : std_logic ; +signal UN1_PLOL_CNT_TC_13 : std_logic ; +signal UN1_PLOL_CNT_TC_14 : std_logic ; +signal RLOL1_CNT_TC_1_11 : std_logic ; +signal RLOL1_CNT_TC_1_12 : std_logic ; +signal RLOL1_CNT_TC_1_13 : std_logic ; +signal RLOL1_CNT_TC_1_14 : std_logic ; +signal TXSR_APPD_4 : std_logic ; +signal RSL_TX_PCS_RST_C_4 : std_logic ; +signal CO0_2 : std_logic ; +signal UN18_TXR_WT_TC_6 : std_logic ; +signal UN18_TXR_WT_TC_7 : std_logic ; +signal UN18_TXR_WT_TC_8 : std_logic ; +signal UN17_RXR_WT_TC_6 : std_logic ; +signal UN17_RXR_WT_TC_7 : std_logic ; +signal UN17_RXR_WT_TC_8 : std_logic ; +signal RXSDR_APPD_4 : std_logic ; +signal RLOLS0_CNT_TC_1_9 : std_logic ; +signal UN1_PLOL_CNT_TC_10 : std_logic ; +signal RLOL1_CNT_TC_1_10 : std_logic ; +signal \TXR_WT_CNT_\ : std_logic ; +signal RLOS_DB_CNT_CRY_0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOS_DB_CNT_CRY_2 : std_logic ; +signal RLOS_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOS_DB_CNT_S_3_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_2 : std_logic ; +signal RLOL_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOL_DB_CNT_S_3_0_S1 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_6 : std_logic ; +signal N_7 : std_logic ; +begin +\GENBLK2.RXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"2626" +) +port map ( +A => RXS_RST, +B => RXS_CNT(0), +C => RXS_CNT(1), +D => VCC, +Z => RXS_CNT_3(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"0101" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => rx_los_low_s, +C => rx_cdr_lol_s, +D => VCC, +Z => RXPR_APPD_RNO(0)); +\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 +generic map( + init => X"1222" +) +port map ( +A => PLOL0_CNT(1), +B => PLOL0_CNT9, +C => WAITA_PLOL0, +D => PLOL0_CNT(0), +Z => PLOL0_CNT_3(1)); +\GENBLK2.RXP_RST2_RNO\: LUT4 +generic map( + init => X"BABA" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => RLOS_DB_P1, +C => RLOS_DB, +D => VCC, +Z => RXP_RST25); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 +generic map( + init => X"0101" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => RLOS_DB, +C => RLOL_DB, +D => VCC, +Z => UN1_RUI_RST_DUAL_C_1_1); +\GENBLK2.GENBLK3.RUO_RX_RDYR_RNO\: LUT4 +generic map( + init => X"0002" +) +port map ( +A => RX_ALL_WELL, +B => rst_dual_c, +C => RSL_RX_PCS_RST_C_10, +D => DUAL_OR_RSERD_RST, +Z => UN3_RX_ALL_WELL_2); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0404" +) +port map ( +A => UN17_RXR_WT_TC, +B => RX_ALL_WELL, +C => DUAL_OR_RSERD_RST, +D => VCC, +Z => UN3_RX_ALL_WELL_1); +RX_ANY_RST_RNIFD021: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RX_ANY_RST, +B => UN17_RXR_WT_TC, +C => RLOS_DB, +D => RLOL_DB, +Z => RXR_WT_CNT9); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO_0\: LUT4 +generic map( + init => X"FBFB" +) +port map ( +A => rst_dual_c, +B => RX_ALL_WELL, +C => DUAL_OR_RSERD_RST, +D => VCC, +Z => UN1_RUI_RST_DUAL_C_1_I); +\GENBLK2.RXS_RST_RNIS0OP\: LUT4 +generic map( + init => X"1011" +) +port map ( +A => RLOL1_CNT_TC_1, +B => RXS_RST, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => \RLOL1_CNT_\); +\GENBLK2.GENBLK3.RXR_WT_EN_RNIQF0H1\: LUT4 +generic map( + init => X"FFEF" +) +port map ( +A => RXR_WT_EN, +B => RX_ANY_RST, +C => RX_ALL_WELL, +D => UN17_RXR_WT_TC, +Z => RXR_WT_CNTE); +\GENBLK2.RXP_RST2_RNO_0\: LUT4 +generic map( + init => X"EFEE" +) +port map ( +A => RLOLS0_CNT_TC_1, +B => DUAL_OR_RSERD_RST, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => UN2_RLOS_REDGE_1_I); +\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => UN18_TXR_WT_TC, +B => TX_ANY_RST, +C => PLL_LOL_P2, +D => VCC, +Z => UN2_PLOL_FEDGE_5_I); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RXSR_APPD(0), +B => rx_serdes_rst_c, +C => RXS_RST, +D => rsl_disable, +Z => N_2124_0); +\GENBLK2.WAITA_RLOLS0_REG_Z618\: FD1P3DX port map ( +D => WAITA_RLOLS06, +SP => UN1_RLOLS0_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => WAITA_RLOLS0); +\GENBLK2.WAIT_CALIB_REG_Z620\: FD1P3BX port map ( +D => WAIT_CALIB_RNO, +SP => UN1_RLOS_FEDGE_1, +CK => rxrefclk, +PD => rsl_rst, +Q => WAIT_CALIB); +\GENBLK2.RXS_RST_REG_Z622\: FD1P3DX port map ( +D => RXS_RST6, +SP => UN1_RXS_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_RST); +\GENBLK2.RXS_CNT[0]_REG_Z624\: FD1S3DX port map ( +D => RXS_CNT_3(0), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(0)); +\GENBLK2.RXS_CNT[1]_REG_Z626\: FD1S3DX port map ( +D => RXS_CNT_3(1), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(1)); +\GENBLK2.RXP_RST2_REG_Z628\: FD1P3BX port map ( +D => RXP_RST25, +SP => UN2_RLOS_REDGE_1_I, +CK => rxrefclk, +PD => rsl_rst, +Q => RXP_RST2); +\GENBLK2.RLOS_P2_REG_Z630\: FD1S3DX port map ( +D => RLOS_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P2); +\GENBLK2.RLOS_P1_REG_Z632\: FD1S3DX port map ( +D => rx_los_low_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P1); +\GENBLK2.RLOS_DB_P1_REG_Z634\: FD1S3BX port map ( +D => RLOS_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_P1); +\GENBLK2.RLOS_DB_CNT[0]_REG_Z636\: FD1S3BX port map ( +D => RLOS_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(0)); +\GENBLK2.RLOS_DB_CNT[1]_REG_Z638\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(1)); +\GENBLK2.RLOS_DB_CNT[2]_REG_Z640\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(2)); +\GENBLK2.RLOS_DB_CNT[3]_REG_Z642\: FD1S3BX port map ( +D => RLOS_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(3)); +\GENBLK2.RLOS_DB_REG_Z644\: FD1P3BX port map ( +D => RLOS_DB_CNT(1), +SP => UN1_RLOS_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB); +\GENBLK2.RLOLS0_CNT[0]_REG_Z646\: FD1P3DX port map ( +D => RLOLS0_CNT_S(0), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(0)); +\GENBLK2.RLOLS0_CNT[1]_REG_Z648\: FD1P3DX port map ( +D => RLOLS0_CNT_S(1), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(1)); +\GENBLK2.RLOLS0_CNT[2]_REG_Z650\: FD1P3DX port map ( +D => RLOLS0_CNT_S(2), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(2)); +\GENBLK2.RLOLS0_CNT[3]_REG_Z652\: FD1P3DX port map ( +D => RLOLS0_CNT_S(3), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(3)); +\GENBLK2.RLOLS0_CNT[4]_REG_Z654\: FD1P3DX port map ( +D => RLOLS0_CNT_S(4), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(4)); +\GENBLK2.RLOLS0_CNT[5]_REG_Z656\: FD1P3DX port map ( +D => RLOLS0_CNT_S(5), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(5)); +\GENBLK2.RLOLS0_CNT[6]_REG_Z658\: FD1P3DX port map ( +D => RLOLS0_CNT_S(6), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(6)); +\GENBLK2.RLOLS0_CNT[7]_REG_Z660\: FD1P3DX port map ( +D => RLOLS0_CNT_S(7), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(7)); +\GENBLK2.RLOLS0_CNT[8]_REG_Z662\: FD1P3DX port map ( +D => RLOLS0_CNT_S(8), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(8)); +\GENBLK2.RLOLS0_CNT[9]_REG_Z664\: FD1P3DX port map ( +D => RLOLS0_CNT_S(9), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(9)); +\GENBLK2.RLOLS0_CNT[10]_REG_Z666\: FD1P3DX port map ( +D => RLOLS0_CNT_S(10), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(10)); +\GENBLK2.RLOLS0_CNT[11]_REG_Z668\: FD1P3DX port map ( +D => RLOLS0_CNT_S(11), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(11)); +\GENBLK2.RLOLS0_CNT[12]_REG_Z670\: FD1P3DX port map ( +D => RLOLS0_CNT_S(12), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(12)); +\GENBLK2.RLOLS0_CNT[13]_REG_Z672\: FD1P3DX port map ( +D => RLOLS0_CNT_S(13), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(13)); +\GENBLK2.RLOLS0_CNT[14]_REG_Z674\: FD1P3DX port map ( +D => RLOLS0_CNT_S(14), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(14)); +\GENBLK2.RLOLS0_CNT[15]_REG_Z676\: FD1P3DX port map ( +D => RLOLS0_CNT_S(15), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(15)); +\GENBLK2.RLOLS0_CNT[16]_REG_Z678\: FD1P3DX port map ( +D => RLOLS0_CNT_S(16), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(16)); +\GENBLK2.RLOLS0_CNT[17]_REG_Z680\: FD1P3DX port map ( +D => RLOLS0_CNT_S(17), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(17)); +\GENBLK2.RLOL_P2_REG_Z682\: FD1S3DX port map ( +D => RLOL_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P2); +\GENBLK2.RLOL_P1_REG_Z684\: FD1S3DX port map ( +D => rx_cdr_lol_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P1); +\GENBLK2.RLOL_DB_P1_REG_Z686\: FD1S3BX port map ( +D => RLOL_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_P1); +\GENBLK2.RLOL_DB_CNT[0]_REG_Z688\: FD1S3BX port map ( +D => RLOL_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(0)); +\GENBLK2.RLOL_DB_CNT[1]_REG_Z690\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(1)); +\GENBLK2.RLOL_DB_CNT[2]_REG_Z692\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(2)); +\GENBLK2.RLOL_DB_CNT[3]_REG_Z694\: FD1S3BX port map ( +D => RLOL_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(3)); +\GENBLK2.RLOL_DB_REG_Z696\: FD1P3BX port map ( +D => RLOL_DB_CNT(1), +SP => UN1_RLOL_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB); +\GENBLK2.RLOL1_CNT[0]_REG_Z698\: FD1P3DX port map ( +D => RLOL1_CNT_S(0), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(0)); +\GENBLK2.RLOL1_CNT[1]_REG_Z700\: FD1P3DX port map ( +D => RLOL1_CNT_S(1), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(1)); +\GENBLK2.RLOL1_CNT[2]_REG_Z702\: FD1P3DX port map ( +D => RLOL1_CNT_S(2), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(2)); +\GENBLK2.RLOL1_CNT[3]_REG_Z704\: FD1P3DX port map ( +D => RLOL1_CNT_S(3), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(3)); +\GENBLK2.RLOL1_CNT[4]_REG_Z706\: FD1P3DX port map ( +D => RLOL1_CNT_S(4), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(4)); +\GENBLK2.RLOL1_CNT[5]_REG_Z708\: FD1P3DX port map ( +D => RLOL1_CNT_S(5), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(5)); +\GENBLK2.RLOL1_CNT[6]_REG_Z710\: FD1P3DX port map ( +D => RLOL1_CNT_S(6), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(6)); +\GENBLK2.RLOL1_CNT[7]_REG_Z712\: FD1P3DX port map ( +D => RLOL1_CNT_S(7), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(7)); +\GENBLK2.RLOL1_CNT[8]_REG_Z714\: FD1P3DX port map ( +D => RLOL1_CNT_S(8), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(8)); +\GENBLK2.RLOL1_CNT[9]_REG_Z716\: FD1P3DX port map ( +D => RLOL1_CNT_S(9), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(9)); +\GENBLK2.RLOL1_CNT[10]_REG_Z718\: FD1P3DX port map ( +D => RLOL1_CNT_S(10), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(10)); +\GENBLK2.RLOL1_CNT[11]_REG_Z720\: FD1P3DX port map ( +D => RLOL1_CNT_S(11), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(11)); +\GENBLK2.RLOL1_CNT[12]_REG_Z722\: FD1P3DX port map ( +D => RLOL1_CNT_S(12), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(12)); +\GENBLK2.RLOL1_CNT[13]_REG_Z724\: FD1P3DX port map ( +D => RLOL1_CNT_S(13), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(13)); +\GENBLK2.RLOL1_CNT[14]_REG_Z726\: FD1P3DX port map ( +D => RLOL1_CNT_S(14), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(14)); +\GENBLK2.RLOL1_CNT[15]_REG_Z728\: FD1P3DX port map ( +D => RLOL1_CNT_S(15), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(15)); +\GENBLK2.RLOL1_CNT[16]_REG_Z730\: FD1P3DX port map ( +D => RLOL1_CNT_S(16), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(16)); +\GENBLK2.RLOL1_CNT[17]_REG_Z732\: FD1P3DX port map ( +D => RLOL1_CNT_S(17), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(17)); +\GENBLK2.RLOL1_CNT[18]_REG_Z734\: FD1P3DX port map ( +D => RLOL1_CNT_S(18), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(18)); +\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z736\: FD1S3BX port map ( +D => RXSDR_APPD_2, +CK => rxrefclk, +PD => rsl_rst, +Q => RXSDR_APPD); +\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z738\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_1, +SP => UN1_DUAL_OR_RSERD_RST_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_EN); +\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z740\: FD1P3DX port map ( +D => RXR_WT_CNT_S(0), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z742\: FD1P3DX port map ( +D => RXR_WT_CNT_S(1), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(1)); +\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z744\: FD1P3DX port map ( +D => RXR_WT_CNT_S(2), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z746\: FD1P3DX port map ( +D => RXR_WT_CNT_S(3), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(3)); +\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z748\: FD1P3DX port map ( +D => RXR_WT_CNT_S(4), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z750\: FD1P3DX port map ( +D => RXR_WT_CNT_S(5), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(5)); +\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z752\: FD1P3DX port map ( +D => RXR_WT_CNT_S(6), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z754\: FD1P3DX port map ( +D => RXR_WT_CNT_S(7), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(7)); +\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z756\: FD1P3DX port map ( +D => RXR_WT_CNT_S(8), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z758\: FD1P3DX port map ( +D => RXR_WT_CNT_S(9), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(9)); +\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z760\: FD1P3DX port map ( +D => RXR_WT_CNT_S(10), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z762\: FD1P3DX port map ( +D => RXR_WT_CNT_S(11), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(11)); +\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z764\: FD1P3DX port map ( +D => UN1_RUI_RST_DUAL_C_1_1, +SP => UN1_RUI_RST_DUAL_C_1_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXDPR_APPD); +\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z766\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_2, +SP => RXR_WT_CNT9, +CK => rxrefclk, +CD => rsl_rst, +Q => RSL_RX_RDY_9); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z768\: FD1S3DX port map ( +D => N_2124_0, +CK => rxrefclk, +CD => rsl_rst, +Q => RXSR_APPD(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z770\: FD1P3DX port map ( +D => RXPR_APPD_RNO(0), +SP => UN2_RDO_SERDES_RST_DUAL_C_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXPR_APPD(0)); +\GENBLK1.WAITA_PLOL0_REG_Z772\: FD1P3DX port map ( +D => PLOL_FEDGE, +SP => UN1_PLOL0_CNT_TC_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => WAITA_PLOL0); +\GENBLK1.TXS_RST_REG_Z774\: FD1P3DX port map ( +D => UN1_PLOL_CNT_TC, +SP => UN2_PLOL_CNT_TC, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_RST); +\GENBLK1.TXS_CNT[0]_REG_Z776\: FD1S3DX port map ( +D => N_10_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(0)); +\GENBLK1.TXS_CNT[1]_REG_Z778\: FD1S3DX port map ( +D => TXS_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(1)); +\GENBLK1.TXP_RST_REG_Z780\: FD1P3DX port map ( +D => UN9_PLOL0_CNT_TC, +SP => UN1_PLOL0_CNT_TC_1, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_RST); +\GENBLK1.TXP_CNT[0]_REG_Z782\: FD1S3DX port map ( +D => N_11_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(0)); +\GENBLK1.TXP_CNT[1]_REG_Z784\: FD1S3DX port map ( +D => TXP_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(1)); +\GENBLK1.PLOL_CNT[0]_REG_Z786\: FD1S3DX port map ( +D => PLOL_CNT_S(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(0)); +\GENBLK1.PLOL_CNT[1]_REG_Z788\: FD1S3DX port map ( +D => PLOL_CNT_S(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(1)); +\GENBLK1.PLOL_CNT[2]_REG_Z790\: FD1S3DX port map ( +D => PLOL_CNT_S(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(2)); +\GENBLK1.PLOL_CNT[3]_REG_Z792\: FD1S3DX port map ( +D => PLOL_CNT_S(3), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(3)); +\GENBLK1.PLOL_CNT[4]_REG_Z794\: FD1S3DX port map ( +D => PLOL_CNT_S(4), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(4)); +\GENBLK1.PLOL_CNT[5]_REG_Z796\: FD1S3DX port map ( +D => PLOL_CNT_S(5), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(5)); +\GENBLK1.PLOL_CNT[6]_REG_Z798\: FD1S3DX port map ( +D => PLOL_CNT_S(6), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(6)); +\GENBLK1.PLOL_CNT[7]_REG_Z800\: FD1S3DX port map ( +D => PLOL_CNT_S(7), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(7)); +\GENBLK1.PLOL_CNT[8]_REG_Z802\: FD1S3DX port map ( +D => PLOL_CNT_S(8), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(8)); +\GENBLK1.PLOL_CNT[9]_REG_Z804\: FD1S3DX port map ( +D => PLOL_CNT_S(9), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(9)); +\GENBLK1.PLOL_CNT[10]_REG_Z806\: FD1S3DX port map ( +D => PLOL_CNT_S(10), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(10)); +\GENBLK1.PLOL_CNT[11]_REG_Z808\: FD1S3DX port map ( +D => PLOL_CNT_S(11), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(11)); +\GENBLK1.PLOL_CNT[12]_REG_Z810\: FD1S3DX port map ( +D => PLOL_CNT_S(12), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(12)); +\GENBLK1.PLOL_CNT[13]_REG_Z812\: FD1S3DX port map ( +D => PLOL_CNT_S(13), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(13)); +\GENBLK1.PLOL_CNT[14]_REG_Z814\: FD1S3DX port map ( +D => PLOL_CNT_S(14), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(14)); +\GENBLK1.PLOL_CNT[15]_REG_Z816\: FD1S3DX port map ( +D => PLOL_CNT_S(15), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(15)); +\GENBLK1.PLOL_CNT[16]_REG_Z818\: FD1S3DX port map ( +D => PLOL_CNT_S(16), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(16)); +\GENBLK1.PLOL_CNT[17]_REG_Z820\: FD1S3DX port map ( +D => PLOL_CNT_S(17), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(17)); +\GENBLK1.PLOL_CNT[18]_REG_Z822\: FD1S3DX port map ( +D => PLOL_CNT_S(18), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(18)); +\GENBLK1.PLOL_CNT[19]_REG_Z824\: FD1S3DX port map ( +D => PLOL_CNT_S(19), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(19)); +\GENBLK1.PLOL0_CNT[0]_REG_Z826\: FD1S3DX port map ( +D => PLOL0_CNT_3(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(0)); +\GENBLK1.PLOL0_CNT[1]_REG_Z828\: FD1S3DX port map ( +D => PLOL0_CNT_3(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(1)); +\GENBLK1.PLOL0_CNT[2]_REG_Z830\: FD1S3DX port map ( +D => PLOL0_CNT_3(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(2)); +\GENBLK1.PLL_LOL_P3_REG_Z832\: FD1S3DX port map ( +D => PLL_LOL_P2, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P3); +\GENBLK1.PLL_LOL_P2_REG_Z834\: FD1S3DX port map ( +D => PLL_LOL_P1, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P2); +\GENBLK1.PLL_LOL_P1_REG_Z836\: FD1S3DX port map ( +D => pll_lock_i, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P1); +\GENBLK1.GENBLK2.TXSR_APPD_REG_Z838\: FD1S3BX port map ( +D => TXSR_APPD_2, +CK => pll_refclki, +PD => rsl_rst, +Q => TXSR_APPD); +\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z840\: FD1P3DX port map ( +D => UN1_DUAL_OR_SERD_RST_1_1, +SP => UN1_DUAL_OR_SERD_RST_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_EN); +\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z842\: FD1P3DX port map ( +D => TXR_WT_CNT_S(0), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z844\: FD1P3DX port map ( +D => TXR_WT_CNT_S(1), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(1)); +\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z846\: FD1P3DX port map ( +D => TXR_WT_CNT_S(2), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z848\: FD1P3DX port map ( +D => TXR_WT_CNT_S(3), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(3)); +\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z850\: FD1P3DX port map ( +D => TXR_WT_CNT_S(4), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z852\: FD1P3DX port map ( +D => TXR_WT_CNT_S(5), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(5)); +\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z854\: FD1P3DX port map ( +D => TXR_WT_CNT_S(6), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z856\: FD1P3DX port map ( +D => TXR_WT_CNT_S(7), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(7)); +\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z858\: FD1P3DX port map ( +D => TXR_WT_CNT_S(8), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z860\: FD1P3DX port map ( +D => TXR_WT_CNT_S(9), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(9)); +\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z862\: FD1P3DX port map ( +D => TXR_WT_CNT_S(10), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z864\: FD1P3DX port map ( +D => TXR_WT_CNT_S(11), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(11)); +\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z866\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_3_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXDPR_APPD); +\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z868\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_5_1, +SP => UN2_PLOL_FEDGE_5_I, +CK => pll_refclki, +CD => rsl_rst, +Q => RSL_TX_RDY_8); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z870\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_8_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXPR_APPD(0)); +\GENBLK1.TXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXS_CNT(0), +B => TXS_RST, +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => N_10_I); +\GENBLK1.TXS_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => TXS_RST, +D => UN1_PLOL_CNT_TC, +Z => TXS_CNT_RNO(1)); +\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0F2F" +) +port map ( +A => TXPR_APPD(0), +B => PLL_LOL_P2, +C => UN1_DUAL_OR_SERD_RST_1_1, +D => RSL_TX_RDY_8, +Z => UN1_DUAL_OR_SERD_RST_1_I); +\GENBLK2.RXS_RST6\: LUT4 +generic map( + init => X"2020" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => RXS_RST6); +\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RXS_RST, +B => WAIT_CALIB, +C => RLOL1_CNT_TC_1, +D => RLOS_REDGE, +Z => RLOL1_CNTE); +\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS0, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => RLOLS0_CNTE); +\GENBLK1.PLOL_CNT11_I\: LUT4 +generic map( + init => X"0202" +) +port map ( +A => PLL_LOL_P2, +B => UN1_PLOL_CNT_TC, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => \PLOL_CNT_\); +\GENBLK2.RLOLS0_CNT11_I\: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOLS0_CNT11_0, +B => RLOLS0_CNT_TC_1, +C => VCC, +D => VCC, +Z => \RLOLS0_CNT_\); +\GENBLK2.UN1_RXS_CNT_TC\: LUT4 +generic map( + init => X"FEFC" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => UN8_RXS_CNT_TC, +D => RLOL1_CNT_TC_1, +Z => UN1_RXS_CNT_TC); +\GENBLK2.WAIT_CALIB_RNO\: LUT4 +generic map( + init => X"A3A3" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => WAIT_CALIB_RNO); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => UN1_TXSR_APPD, +B => PLL_LOL_P2, +C => RSL_SERDES_RST_DUAL_C_6, +D => RSL_TX_SERDES_RST_C_7, +Z => UN2_PLOL_FEDGE_8_I); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 +generic map( + init => X"FEFF" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => UN3_RX_ALL_WELL_2_1, +C => UN17_RXR_WT_TC, +D => RX_ALL_WELL, +Z => UN1_DUAL_OR_RSERD_RST_2_I); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO_0[0]\: LUT4 +generic map( + init => X"FFFB" +) +port map ( +A => UN1_RXSDR_OR_SR_APPD, +B => UN2_RDO_SERDES_RST_DUAL_C_1_1, +C => RSL_RX_SERDES_RST_C_5, +D => RSL_SERDES_RST_DUAL_C_6, +Z => UN2_RDO_SERDES_RST_DUAL_C_2_I); +\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => UN2_PLOL_CNT_TC); +\GENBLK1.GENBLK2.TXR_WT_EN_RNICEBT\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => TXR_WT_EN, +B => UN18_TXR_WT_TC, +C => TX_ANY_RST, +D => VCC, +Z => TXR_WT_CNTE); +\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => UN1_RLOS_FEDGE_1); +\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS06, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => UN1_RLOLS0_CNT_TC); +\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => rst_dual_c, +Z => UN2_PLOL_FEDGE_3_I); +\GENBLK1.TXP_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXP_CNT(0), +B => TXP_RST, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => N_11_I); +UN2_PLOL_FEDGE_5_1_Z890: LUT4 +generic map( + init => X"1111" +) +port map ( +A => PLL_LOL_P2, +B => TX_ANY_RST, +C => VCC, +D => VCC, +Z => UN2_PLOL_FEDGE_5_1); +UN1_DUAL_OR_SERD_RST_1_1_Z891: LUT4 +generic map( + init => X"0101" +) +port map ( +A => UN18_TXR_WT_TC, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => UN1_DUAL_OR_SERD_RST_1_1); +\GENBLK1.TXP_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => TXP_RST, +D => UN9_PLOL0_CNT_TC, +Z => TXP_CNT_RNO(1)); +RLOLS0_CNT_TC_1_Z893: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOLS0_CNT_TC_1_10, +B => RLOLS0_CNT_TC_1_11, +C => RLOLS0_CNT_TC_1_12, +D => RLOLS0_CNT_TC_1_13, +Z => RLOLS0_CNT_TC_1); +\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => UN1_PLOL_CNT_TC_11, +B => UN1_PLOL_CNT_TC_12, +C => UN1_PLOL_CNT_TC_13, +D => UN1_PLOL_CNT_TC_14, +Z => UN1_PLOL_CNT_TC); +RLOL1_CNT_TC_1_Z895: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL1_CNT_TC_1_11, +B => RLOL1_CNT_TC_1_12, +C => RLOL1_CNT_TC_1_13, +D => RLOL1_CNT_TC_1_14, +Z => RLOL1_CNT_TC_1); +\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOL_DB_CNT(0), +B => UN1_RLOL_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOL_DB_CNT_AXB_0); +\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOS_DB_CNT(0), +B => UN1_RLOS_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOS_DB_CNT_AXB_0); +\GENBLK1.WAITA_PLOL0_RNO\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1_I); +\GENBLK1.GENBLK2.MFOR[0].UN1_TXSR_APPD\: LUT4 +generic map( + init => X"C8C8" +) +port map ( +A => TXDPR_APPD, +B => TXSR_APPD_4, +C => RSL_TX_PCS_RST_C_4, +D => VCC, +Z => UN1_TXSR_APPD); +\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => TXSR_APPD_4, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => TXSR_APPD_2); +\GENBLK1.PLOL0_CNT_3[0]\: LUT4 +generic map( + init => X"1414" +) +port map ( +A => PLOL0_CNT9, +B => PLOL0_CNT(0), +C => WAITA_PLOL0, +D => VCC, +Z => PLOL0_CNT_3(0)); +\GENBLK1.PLOL0_CNT_3[2]\: LUT4 +generic map( + init => X"1320" +) +port map ( +A => CO0_2, +B => PLOL0_CNT9, +C => PLOL0_CNT(1), +D => PLOL0_CNT(2), +Z => PLOL0_CNT_3(2)); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN18_TXR_WT_TC_6, +B => UN18_TXR_WT_TC_7, +C => UN18_TXR_WT_TC_8, +D => VCC, +Z => UN18_TXR_WT_TC); +UN2_PLOL_FEDGE_2_Z904: LUT4 +generic map( + init => X"0101" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => UN2_PLOL_FEDGE_2); +TX_ANY_RST_Z905: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_6, +B => RSL_TX_PCS_RST_C_4, +C => RSL_TX_SERDES_RST_C_7, +D => rst_dual_c, +Z => TX_ANY_RST); +RX_ANY_RST_Z906: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => RSL_RX_PCS_RST_C_10, +C => rst_dual_c, +D => VCC, +Z => RX_ANY_RST); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN17_RXR_WT_TC_6, +B => UN17_RXR_WT_TC_7, +C => UN17_RXR_WT_TC_8, +D => VCC, +Z => UN17_RXR_WT_TC); +\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z908\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_BM(0)); +\UN1_RLOL_DB_CNT_ZERO[0]_Z909\: PFUMX port map ( +ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0), +C0 => RLOL_P2, +Z => UN1_RLOL_DB_CNT_ZERO(0)); +\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z910\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_BM(0)); +\UN1_RLOS_DB_CNT_ZERO[0]_Z911\: PFUMX port map ( +ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0), +C0 => RLOS_P2, +Z => UN1_RLOS_DB_CNT_ZERO(0)); +\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_MAX); +\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_MAX); +\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1); +\GENBLK2.WAITA_RLOLS06\: LUT4 +generic map( + init => X"0504" +) +port map ( +A => RLOL_DB, +B => RLOL_DB_P1, +C => RLOS_DB, +D => RLOS_DB_P1, +Z => WAITA_RLOLS06); +\RXS_CNT_3[1]_Z916\: LUT4 +generic map( + init => X"6464" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => RXS_RST, +D => VCC, +Z => RXS_CNT_3(1)); +\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD\: LUT4 +generic map( + init => X"3200" +) +port map ( +A => RXSR_APPD(0), +B => RX_ALL_WELL, +C => RXSDR_APPD_4, +D => RSL_RX_PCS_RST_C_10, +Z => UN1_RXSDR_OR_SR_APPD); +RLOLS0_CNT_TC_1_13_Z918: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RLOLS0_CNT(16), +B => RLOLS0_CNT(17), +C => RLOLS0_CNT_TC_1_9, +D => VCC, +Z => RLOLS0_CNT_TC_1_13); +\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 +generic map( + init => X"0100" +) +port map ( +A => PLOL_CNT(4), +B => PLOL_CNT(5), +C => PLOL_CNT(18), +D => UN1_PLOL_CNT_TC_10, +Z => UN1_PLOL_CNT_TC_14); +RLOL1_CNT_TC_1_14_Z920: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(11), +B => RLOL1_CNT(12), +C => RLOL1_CNT(18), +D => RLOL1_CNT_TC_1_10, +Z => RLOL1_CNT_TC_1_14); +\GENBLK2.GENBLK3.UN3_RX_ALL_WELL_2_1\: LUT4 +generic map( + init => X"0E0E" +) +port map ( +A => RXPR_APPD(0), +B => RXDPR_APPD, +C => RSL_RX_RDY_9, +D => VCC, +Z => UN3_RX_ALL_WELL_2_1); +RDO_SERDES_RST_DUAL_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => rsl_rst, +C => serdes_rst_dual_c, +D => VCC, +Z => RSL_SERDES_RST_DUAL_C_6); +RDO_TX_SERDES_RST_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXS_RST, +C => tx_serdes_rst_c, +D => VCC, +Z => RSL_TX_SERDES_RST_C_7); +\RDO_TX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXP_RST, +C => tx_pcs_rst_c, +D => VCC, +Z => RSL_TX_PCS_RST_C_4); +\RDO_RX_SERDES_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXS_RST, +C => rx_serdes_rst_c, +D => VCC, +Z => RSL_RX_SERDES_RST_C_5); +\RDO_RX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXP_RST2, +C => rx_pcs_rst_c, +D => VCC, +Z => RSL_RX_PCS_RST_C_10); +\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 +generic map( + init => X"1010" +) +port map ( +A => PLOL0_CNT(0), +B => PLOL0_CNT(1), +C => PLOL0_CNT(2), +D => VCC, +Z => UN9_PLOL0_CNT_TC); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RXR_WT_CNT(0), +B => RXR_WT_CNT(8), +C => RXR_WT_CNT(9), +D => RXR_WT_CNT(11), +Z => UN17_RXR_WT_TC_6); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RXR_WT_CNT(3), +B => RXR_WT_CNT(4), +C => RXR_WT_CNT(5), +D => RXR_WT_CNT(7), +Z => UN17_RXR_WT_TC_7); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RXR_WT_CNT(1), +B => RXR_WT_CNT(2), +C => RXR_WT_CNT(6), +D => RXR_WT_CNT(10), +Z => UN17_RXR_WT_TC_8); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => TXR_WT_CNT(0), +B => TXR_WT_CNT(8), +C => TXR_WT_CNT(9), +D => TXR_WT_CNT(11), +Z => UN18_TXR_WT_TC_6); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => TXR_WT_CNT(3), +B => TXR_WT_CNT(4), +C => TXR_WT_CNT(5), +D => TXR_WT_CNT(7), +Z => UN18_TXR_WT_TC_7); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => TXR_WT_CNT(1), +B => TXR_WT_CNT(2), +C => TXR_WT_CNT(6), +D => TXR_WT_CNT(10), +Z => UN18_TXR_WT_TC_8); +RLOLS0_CNT_TC_1_9_Z934: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(1), +B => RLOLS0_CNT(2), +C => RLOLS0_CNT(3), +D => RLOLS0_CNT(4), +Z => RLOLS0_CNT_TC_1_9); +RLOLS0_CNT_TC_1_10_Z935: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RLOLS0_CNT(0), +B => RLOLS0_CNT(10), +C => RLOLS0_CNT(14), +D => RLOLS0_CNT(15), +Z => RLOLS0_CNT_TC_1_10); +RLOLS0_CNT_TC_1_11_Z936: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(9), +B => RLOLS0_CNT(11), +C => RLOLS0_CNT(12), +D => RLOLS0_CNT(13), +Z => RLOLS0_CNT_TC_1_11); +RLOLS0_CNT_TC_1_12_Z937: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(5), +B => RLOLS0_CNT(6), +C => RLOLS0_CNT(7), +D => RLOLS0_CNT(8), +Z => RLOLS0_CNT_TC_1_12); +\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 +generic map( + init => X"1000" +) +port map ( +A => PLOL_CNT(2), +B => PLOL_CNT(3), +C => PLOL_CNT(17), +D => PLOL_CNT(19), +Z => UN1_PLOL_CNT_TC_10); +\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(13), +B => PLOL_CNT(14), +C => PLOL_CNT(15), +D => PLOL_CNT(16), +Z => UN1_PLOL_CNT_TC_11); +\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(7), +B => PLOL_CNT(8), +C => PLOL_CNT(9), +D => PLOL_CNT(11), +Z => UN1_PLOL_CNT_TC_12); +\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 +generic map( + init => X"0008" +) +port map ( +A => PLOL_CNT(1), +B => PLOL_CNT(6), +C => PLOL_CNT(10), +D => PLOL_CNT(12), +Z => UN1_PLOL_CNT_TC_13); +RLOL1_CNT_TC_1_10_Z942: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(7), +B => RLOL1_CNT(8), +C => RLOL1_CNT(9), +D => RLOL1_CNT(10), +Z => RLOL1_CNT_TC_1_10); +RLOL1_CNT_TC_1_11_Z943: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(3), +B => RLOL1_CNT(4), +C => RLOL1_CNT(5), +D => RLOL1_CNT(6), +Z => RLOL1_CNT_TC_1_11); +RLOL1_CNT_TC_1_12_Z944: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(0), +B => RLOL1_CNT(1), +C => RLOL1_CNT(2), +D => RLOL1_CNT(17), +Z => RLOL1_CNT_TC_1_12); +RLOL1_CNT_TC_1_13_Z945: LUT4 +generic map( + init => X"0040" +) +port map ( +A => RLOL1_CNT(13), +B => RLOL1_CNT(14), +C => RLOL1_CNT(15), +D => RLOL1_CNT(16), +Z => RLOL1_CNT_TC_1_13); +\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RXSDR_APPD_4, +B => serdes_rst_dual_c, +C => VCC, +D => VCC, +Z => RXSDR_APPD_2); +RX_ALL_WELL_Z947: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => VCC, +D => VCC, +Z => RX_ALL_WELL); +\GENBLK2.UN8_RXS_CNT_TC\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => VCC, +D => VCC, +Z => UN8_RXS_CNT_TC); +PLOL_FEDGE_Z949: LUT4 +generic map( + init => X"4444" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => VCC, +D => VCC, +Z => PLOL_FEDGE); +RLOS_REDGE_Z950: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => VCC, +D => VCC, +Z => RLOS_REDGE); +\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PLOL0_CNT(0), +B => WAITA_PLOL0, +C => VCC, +D => VCC, +Z => CO0_2); +UN2_RDO_SERDES_RST_DUAL_C_1_1_Z952: LUT4 +generic map( + init => X"1111" +) +port map ( +A => rx_cdr_lol_s, +B => rx_los_low_s, +C => VCC, +D => VCC, +Z => UN2_RDO_SERDES_RST_DUAL_C_1_1); +\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z953\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_AM(0)); +\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z954\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_AM(0)); +DUAL_OR_RSERD_RST_Z955: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RSL_RX_SERDES_RST_C_5, +B => serdes_rst_dual_c, +C => rsl_rst, +D => rsl_disable, +Z => DUAL_OR_RSERD_RST); +\GENBLK1.PLOL0_CNT9\: LUT4 +generic map( + init => X"AAAE" +) +port map ( +A => PLL_LOL_P2, +B => PLOL0_CNT(2), +C => PLOL0_CNT(1), +D => PLOL0_CNT(0), +Z => PLOL0_CNT9); +\GENBLK2.RLOLS0_CNT11_0\: LUT4 +generic map( + init => X"4F44" +) +port map ( +A => RLOL_DB_P1, +B => RLOL_DB, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => RLOLS0_CNT11_0); +\GENBLK1.GENBLK2.TXR_WT_CNT9_I\: LUT4 +generic map( + init => X"1555" +) +port map ( +A => TX_ANY_RST, +B => UN18_TXR_WT_TC_8, +C => UN18_TXR_WT_TC_7, +D => UN18_TXR_WT_TC_6, +Z => \TXR_WT_CNT_\); +\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOL1_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_7, +COUT => RLOL1_CNT_CRY(0), +S0 => RLOL1_CNT_CRY_0_S0(0), +S1 => RLOL1_CNT_S(0)); +\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(0), +COUT => RLOL1_CNT_CRY(2), +S0 => RLOL1_CNT_S(1), +S1 => RLOL1_CNT_S(2)); +\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(2), +COUT => RLOL1_CNT_CRY(4), +S0 => RLOL1_CNT_S(3), +S1 => RLOL1_CNT_S(4)); +\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(4), +COUT => RLOL1_CNT_CRY(6), +S0 => RLOL1_CNT_S(5), +S1 => RLOL1_CNT_S(6)); +\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(6), +COUT => RLOL1_CNT_CRY(8), +S0 => RLOL1_CNT_S(7), +S1 => RLOL1_CNT_S(8)); +\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(8), +COUT => RLOL1_CNT_CRY(10), +S0 => RLOL1_CNT_S(9), +S1 => RLOL1_CNT_S(10)); +\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(10), +COUT => RLOL1_CNT_CRY(12), +S0 => RLOL1_CNT_S(11), +S1 => RLOL1_CNT_S(12)); +\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(12), +COUT => RLOL1_CNT_CRY(14), +S0 => RLOL1_CNT_S(13), +S1 => RLOL1_CNT_S(14)); +\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(14), +COUT => RLOL1_CNT_CRY(16), +S0 => RLOL1_CNT_S(15), +S1 => RLOL1_CNT_S(16)); +\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"800a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(16), +COUT => RLOL1_CNT_CRY_0_COUT(17), +S0 => RLOL1_CNT_S(17), +S1 => RLOL1_CNT_S(18)); +\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOLS0_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_6, +COUT => RLOLS0_CNT_CRY(0), +S0 => RLOLS0_CNT_CRY_0_S0(0), +S1 => RLOLS0_CNT_S(0)); +\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(0), +COUT => RLOLS0_CNT_CRY(2), +S0 => RLOLS0_CNT_S(1), +S1 => RLOLS0_CNT_S(2)); +\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(2), +COUT => RLOLS0_CNT_CRY(4), +S0 => RLOLS0_CNT_S(3), +S1 => RLOLS0_CNT_S(4)); +\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(4), +COUT => RLOLS0_CNT_CRY(6), +S0 => RLOLS0_CNT_S(5), +S1 => RLOLS0_CNT_S(6)); +\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(6), +COUT => RLOLS0_CNT_CRY(8), +S0 => RLOLS0_CNT_S(7), +S1 => RLOLS0_CNT_S(8)); +\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(8), +COUT => RLOLS0_CNT_CRY(10), +S0 => RLOLS0_CNT_S(9), +S1 => RLOLS0_CNT_S(10)); +\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(10), +COUT => RLOLS0_CNT_CRY(12), +S0 => RLOLS0_CNT_S(11), +S1 => RLOLS0_CNT_S(12)); +\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(12), +COUT => RLOLS0_CNT_CRY(14), +S0 => RLOLS0_CNT_S(13), +S1 => RLOLS0_CNT_S(14)); +\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(14), +COUT => RLOLS0_CNT_CRY(16), +S0 => RLOLS0_CNT_S(15), +S1 => RLOLS0_CNT_S(16)); +\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(16), +COUT => RLOLS0_CNT_S_0_COUT(17), +S0 => RLOLS0_CNT_S(17), +S1 => RLOLS0_CNT_S_0_S1(17)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \TXR_WT_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => TXR_WT_CNT_CRY(0), +S0 => TXR_WT_CNT_CRY_0_S0(0), +S1 => TXR_WT_CNT_S(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(0), +COUT => TXR_WT_CNT_CRY(2), +S0 => TXR_WT_CNT_S(1), +S1 => TXR_WT_CNT_S(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(2), +COUT => TXR_WT_CNT_CRY(4), +S0 => TXR_WT_CNT_S(3), +S1 => TXR_WT_CNT_S(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(4), +COUT => TXR_WT_CNT_CRY(6), +S0 => TXR_WT_CNT_S(5), +S1 => TXR_WT_CNT_S(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(6), +COUT => TXR_WT_CNT_CRY(8), +S0 => TXR_WT_CNT_S(7), +S1 => TXR_WT_CNT_S(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(8), +COUT => TXR_WT_CNT_CRY(10), +S0 => TXR_WT_CNT_S(9), +S1 => TXR_WT_CNT_S(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(10), +COUT => TXR_WT_CNT_S_0_COUT(11), +S0 => TXR_WT_CNT_S(11), +S1 => TXR_WT_CNT_S_0_S1(11)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => RXR_WT_CNT9, +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RXR_WT_CNT_CRY(0), +S0 => RXR_WT_CNT_CRY_0_S0(0), +S1 => RXR_WT_CNT_S(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(0), +COUT => RXR_WT_CNT_CRY(2), +S0 => RXR_WT_CNT_S(1), +S1 => RXR_WT_CNT_S(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(2), +COUT => RXR_WT_CNT_CRY(4), +S0 => RXR_WT_CNT_S(3), +S1 => RXR_WT_CNT_S(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(4), +COUT => RXR_WT_CNT_CRY(6), +S0 => RXR_WT_CNT_S(5), +S1 => RXR_WT_CNT_S(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(6), +COUT => RXR_WT_CNT_CRY(8), +S0 => RXR_WT_CNT_S(7), +S1 => RXR_WT_CNT_S(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(8), +COUT => RXR_WT_CNT_CRY(10), +S0 => RXR_WT_CNT_S(9), +S1 => RXR_WT_CNT_S(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(10), +COUT => RXR_WT_CNT_S_0_COUT(11), +S0 => RXR_WT_CNT_S(11), +S1 => RXR_WT_CNT_S_0_S1(11)); +\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \PLOL_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => PLOL_CNT_CRY(0), +S0 => PLOL_CNT_CRY_0_S0(0), +S1 => PLOL_CNT_S(0)); +\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(0), +COUT => PLOL_CNT_CRY(2), +S0 => PLOL_CNT_S(1), +S1 => PLOL_CNT_S(2)); +\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(2), +COUT => PLOL_CNT_CRY(4), +S0 => PLOL_CNT_S(3), +S1 => PLOL_CNT_S(4)); +\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(4), +COUT => PLOL_CNT_CRY(6), +S0 => PLOL_CNT_S(5), +S1 => PLOL_CNT_S(6)); +\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(6), +COUT => PLOL_CNT_CRY(8), +S0 => PLOL_CNT_S(7), +S1 => PLOL_CNT_S(8)); +\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(8), +COUT => PLOL_CNT_CRY(10), +S0 => PLOL_CNT_S(9), +S1 => PLOL_CNT_S(10)); +\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(10), +COUT => PLOL_CNT_CRY(12), +S0 => PLOL_CNT_S(11), +S1 => PLOL_CNT_S(12)); +\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(12), +COUT => PLOL_CNT_CRY(14), +S0 => PLOL_CNT_S(13), +S1 => PLOL_CNT_S(14)); +\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(14), +COUT => PLOL_CNT_CRY(16), +S0 => PLOL_CNT_S(15), +S1 => PLOL_CNT_S(16)); +\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(16), +COUT => PLOL_CNT_CRY(18), +S0 => PLOL_CNT_S(17), +S1 => PLOL_CNT_S(18)); +\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(19), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(18), +COUT => PLOL_CNT_S_0_COUT(19), +S0 => PLOL_CNT_S(19), +S1 => PLOL_CNT_S_0_S1(19)); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOS_DB_CNT(0), +B1 => UN1_RLOS_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => RLOS_DB_CNT_CRY_0, +S0 => RLOS_DB_CNT_CRY_0_0_S0, +S1 => RLOS_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOS_DB_CNT_ZERO(0), +B0 => RLOS_P2, +C0 => RLOS_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOS_DB_CNT_ZERO(0), +B1 => RLOS_P2, +C1 => RLOS_DB_CNT(2), +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_0, +COUT => RLOS_DB_CNT_CRY_2, +S0 => RLOS_DB_CNT_CRY_1_0_S0, +S1 => RLOS_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOS_DB_CNT(3), +B0 => RLOS_P2, +C0 => UN1_RLOS_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_2, +COUT => RLOS_DB_CNT_S_3_0_COUT, +S0 => RLOS_DB_CNT_S_3_0_S0, +S1 => RLOS_DB_CNT_S_3_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOL_DB_CNT(0), +B1 => UN1_RLOL_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => RLOL_DB_CNT_CRY_0, +S0 => RLOL_DB_CNT_CRY_0_0_S0, +S1 => RLOL_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOL_DB_CNT_ZERO(0), +B0 => RLOL_P2, +C0 => RLOL_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOL_DB_CNT_ZERO(0), +B1 => RLOL_P2, +C1 => RLOL_DB_CNT(2), +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_0, +COUT => RLOL_DB_CNT_CRY_2, +S0 => RLOL_DB_CNT_CRY_1_0_S0, +S1 => RLOL_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOL_DB_CNT(3), +B0 => RLOL_P2, +C0 => UN1_RLOL_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_2, +COUT => RLOL_DB_CNT_S_3_0_COUT, +S0 => RLOL_DB_CNT_S_3_0_S0, +S1 => RLOL_DB_CNT_S_3_0_S1); +RXSDR_APPD_4 <= RXSDR_APPD; +TXSR_APPD_4 <= TXSR_APPD; +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_4; +rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_5; +rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_6; +rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_7; +rsl_tx_rdy <= RSL_TX_RDY_8; +rsl_rx_rdy <= RSL_RX_RDY_9; +rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_10; +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5sll_core_Z1_layer1 is +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic); +end sgmii_ecp5sll_core_Z1_layer1; + +architecture beh of sgmii_ecp5sll_core_Z1_layer1 is +signal PHB_CNT : std_logic_vector(2 downto 0); +signal PHB_CNT_I : std_logic_vector(2 downto 0); +signal RCOUNT : std_logic_vector(15 downto 0); +signal PCOUNT : std_logic_vector(21 downto 0); +signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0); +signal SLL_STATE : std_logic_vector(1 downto 0); +signal SLL_STATE_QN : std_logic_vector(1 downto 0); +signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0); +signal RCOUNT_S : std_logic_vector(15 downto 0); +signal RCOUNT_QN : std_logic_vector(15 downto 0); +signal PHB_CNT_QN : std_logic_vector(2 downto 0); +signal PHB_CNT_RNO : std_logic_vector(2 downto 1); +signal PCOUNT_S : std_logic_vector(21 downto 0); +signal PCOUNT_QN : std_logic_vector(21 downto 0); +signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0); +signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2); +signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2); +signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0); +signal PCOUNT_CRY : std_logic_vector(20 downto 0); +signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21); +signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21); +signal RCOUNT_CRY : std_logic_vector(14 downto 0); +signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15); +signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15); +signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0); +signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7); +signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7); +signal PLL_LOCK : std_logic ; +signal RTC_CTRL4_0_A3_1 : std_logic ; +signal UN13_LOCK_20 : std_logic ; +signal PPUL_SYNC_P2 : std_logic ; +signal PPUL_SYNC_P1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ; +signal UN13_LOCK_19 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ; +signal UN13_LOCK_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ; +signal UN13_LOCK_17 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_RNO : std_logic ; +signal UN13_LOCK_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_16 : std_logic ; +signal UN13_LOCK_15 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ; +signal UN13_LOCK_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ; +signal UN13_LOCK_13 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ; +signal UN13_LOCK_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ; +signal UN13_LOCK_11 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ; +signal UN13_LOCK_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ; +signal UN13_LOCK_9 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ; +signal UN13_LOCK_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ; +signal UN13_LOCK_7 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ; +signal UN13_LOCK_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ; +signal UN13_LOCK_5 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ; +signal UN13_LOCK_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ; +signal UN13_LOCK_3 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ; +signal UN13_LOCK_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ; +signal UN13_LOCK_1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ; +signal UN13_LOCK_21 : std_logic ; +signal PPUL_SYNC_P3 : std_logic ; +signal N_7 : std_logic ; +signal UN13_LOCK_0 : std_logic ; +signal RTC_CTRL4 : std_logic ; +signal RTC_CTRL : std_logic ; +signal VCC : std_logic ; +signal N_2085_0 : std_logic ; +signal UNLOCK_5 : std_logic ; +signal UNLOCK_1_SQMUXA_I : std_logic ; +signal UNLOCK : std_logic ; +signal UNLOCK_QN : std_logic ; +signal N_95_I : std_logic ; +signal N_97_I : std_logic ; +signal RTC_PUL : std_logic ; +signal RTC_PUL_P1 : std_logic ; +signal RTC_PUL_P1_QN : std_logic ; +signal RTC_PUL5 : std_logic ; +signal RTC_PUL_QN : std_logic ; +signal RTC_CTRL_QN : std_logic ; +signal RSTAT_PCLK_2 : std_logic ; +signal RSTAT_PCLK : std_logic ; +signal RSTAT_PCLK_QN : std_logic ; +signal RHB_SYNC_P1 : std_logic ; +signal RHB_SYNC_P2 : std_logic ; +signal RHB_SYNC_P2_QN : std_logic ; +signal RHB_SYNC : std_logic ; +signal RHB_SYNC_P1_QN : std_logic ; +signal PPUL_SYNC_P3_QN : std_logic ; +signal PPUL_SYNC_P2_QN : std_logic ; +signal PPUL_SYNC : std_logic ; +signal PPUL_SYNC_P1_QN : std_logic ; +signal N_53_I : std_logic ; +signal PLL_LOCK_QN : std_logic ; +signal PHB : std_logic ; +signal PHB_QN : std_logic ; +signal PDIFF_SYNC : std_logic ; +signal PDIFF_SYNC_P1 : std_logic ; +signal PDIFF_SYNC_P1_QN : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ; +signal LOCK_5 : std_logic ; +signal LOCK_1_SQMUXA_I : std_logic ; +signal LOCK : std_logic ; +signal LOCK_QN : std_logic ; +signal N_98 : std_logic ; +signal RTC_PUL5_0_O3 : std_logic ; +signal RTC_PUL5_0_A3_6 : std_logic ; +signal RTC_PUL5_0_A3_7 : std_logic ; +signal UN1_RCOUNT_1_0_A3 : std_logic ; +signal RHB_WAIT_CNT12 : std_logic ; +signal UN1_RHB_WAIT_CNT_4 : std_logic ; +signal UN1_RHB_WAIT_CNT_5 : std_logic ; +signal N_99 : std_logic ; +signal RTC_CTRL4_0_A3_12_4 : std_logic ; +signal RTC_CTRL4_0_A3_12_5 : std_logic ; +signal RTC_CTRL4_10 : std_logic ; +signal UN1_RCOUNT_1_0_A3_1 : std_logic ; +signal N_6 : std_logic ; +signal RTC_PUL5_0_A3_5 : std_logic ; +signal N_8 : std_logic ; +signal UN13_UNLOCK_CRY_21 : std_logic ; +signal UN13_LOCK_CRY_21_I : std_logic ; +signal \RHB_WAIT_CNT_\ : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ; +signal UN13_LOCK_CRY_0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S1 : std_logic ; +signal UN13_LOCK_CRY_2 : std_logic ; +signal UN13_LOCK_CRY_1_0_S0 : std_logic ; +signal UN13_LOCK_CRY_1_0_S1 : std_logic ; +signal UN13_LOCK_CRY_4 : std_logic ; +signal UN13_LOCK_CRY_3_0_S0 : std_logic ; +signal UN13_LOCK_CRY_3_0_S1 : std_logic ; +signal UN13_LOCK_CRY_6 : std_logic ; +signal UN13_LOCK_CRY_5_0_S0 : std_logic ; +signal UN13_LOCK_CRY_5_0_S1 : std_logic ; +signal UN13_LOCK_CRY_8 : std_logic ; +signal UN13_LOCK_CRY_7_0_S0 : std_logic ; +signal UN13_LOCK_CRY_7_0_S1 : std_logic ; +signal UN13_LOCK_CRY_10 : std_logic ; +signal UN13_LOCK_CRY_9_0_S0 : std_logic ; +signal UN13_LOCK_CRY_9_0_S1 : std_logic ; +signal UN13_LOCK_CRY_12 : std_logic ; +signal UN13_LOCK_CRY_11_0_S0 : std_logic ; +signal UN13_LOCK_CRY_11_0_S1 : std_logic ; +signal UN13_LOCK_CRY_14 : std_logic ; +signal UN13_LOCK_CRY_13_0_S0 : std_logic ; +signal UN13_LOCK_CRY_13_0_S1 : std_logic ; +signal UN13_LOCK_CRY_16 : std_logic ; +signal UN13_LOCK_CRY_15_0_S0 : std_logic ; +signal UN13_LOCK_CRY_15_0_S1 : std_logic ; +signal UN13_LOCK_CRY_18 : std_logic ; +signal UN13_LOCK_CRY_17_0_S0 : std_logic ; +signal UN13_LOCK_CRY_17_0_S1 : std_logic ; +signal UN13_LOCK_CRY_20 : std_logic ; +signal UN13_LOCK_CRY_19_0_S0 : std_logic ; +signal UN13_LOCK_CRY_19_0_S1 : std_logic ; +signal UN13_LOCK_CRY_21_0_COUT : std_logic ; +signal UN13_LOCK_CRY_21_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_2 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_4 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_6 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_8 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_10 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_12 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_14 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_16 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_18 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_20 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ; +signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ; +signal N_21 : std_logic ; +signal N_20 : std_logic ; +signal N_19 : std_logic ; +signal N_18 : std_logic ; +signal N_14 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_9 : std_logic ; +component sync_0s +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +component sync_0s_6 +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic ); +end component; +component sync_0s_0 +port( +ppul_sync : in std_logic; +pdiff_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +begin +PHB_RNO: INV port map ( +A => PHB_CNT(2), +Z => PHB_CNT_I(2)); +\PHB_CNT_RNO[0]\: INV port map ( +A => PHB_CNT(0), +Z => PHB_CNT_I(0)); +PLL_LOCK_RNI6JK9: INV port map ( +A => PLL_LOCK, +Z => pll_lock_i); +RTC_CTRL4_0_A3_RNO: LUT4 +generic map( + init => X"2000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => RTC_CTRL4_0_A3_1); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_20, +B => PCOUNT(20), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_20); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_19, +B => PCOUNT(19), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_19); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_18, +B => PCOUNT(18), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_18); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_Z477: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_17, +B => PCOUNT(17), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_16, +B => PCOUNT(16), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_16); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_15, +B => PCOUNT(15), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_15); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_14, +B => PCOUNT(14), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_14); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_13, +B => PCOUNT(13), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_13); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_12, +B => PCOUNT(12), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_12); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_11, +B => PCOUNT(11), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_11); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_10, +B => PCOUNT(10), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_10); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_9, +B => PCOUNT(9), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_9); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_8, +B => PCOUNT(8), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_8); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_7, +B => PCOUNT(7), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_7); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_6, +B => PCOUNT(6), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_6); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_5, +B => PCOUNT(5), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_5); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_4, +B => PCOUNT(4), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_4); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_3, +B => PCOUNT(3), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_3); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_2, +B => PCOUNT(2), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_2); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_1, +B => PCOUNT(1), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_1); +PPUL_SYNC_P3_RNIU65C: LUT4 +generic map( + init => X"2F20" +) +port map ( +A => UN13_LOCK_21, +B => PPUL_SYNC_P3, +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => N_7); +\PCOUNT_DIFF_RNO[0]\: LUT4 +generic map( + init => X"FD20" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => PCOUNT(0), +D => UN13_LOCK_0, +Z => UN1_PCOUNT_DIFF_I(0)); +RTC_CTRL_0: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RTC_CTRL4, +B => RTC_CTRL, +C => VCC, +D => VCC, +Z => N_2085_0); +UNLOCK_REG_Z498: FD1P3DX port map ( +D => UNLOCK_5, +SP => UNLOCK_1_SQMUXA_I, +CK => pll_refclki, +CD => sli_rst, +Q => UNLOCK); +\SLL_STATE[0]_REG_Z500\: FD1S3DX port map ( +D => N_95_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(0)); +\SLL_STATE[1]_REG_Z502\: FD1S3DX port map ( +D => N_97_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(1)); +RTC_PUL_P1_REG_Z504: FD1S3DX port map ( +D => RTC_PUL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL_P1); +RTC_PUL_REG_Z506: FD1P3DX port map ( +D => RTC_PUL5, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL); +RTC_CTRL_REG_Z508: FD1S3DX port map ( +D => N_2085_0, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_CTRL); +RSTAT_PCLK_REG_Z510: FD1P3DX port map ( +D => RSTAT_PCLK_2, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RSTAT_PCLK); +\RHB_WAIT_CNT[0]_REG_Z512\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(0), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(0)); +\RHB_WAIT_CNT[1]_REG_Z514\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(1), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(1)); +\RHB_WAIT_CNT[2]_REG_Z516\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(2), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(2)); +\RHB_WAIT_CNT[3]_REG_Z518\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(3), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(3)); +\RHB_WAIT_CNT[4]_REG_Z520\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(4), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(4)); +\RHB_WAIT_CNT[5]_REG_Z522\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(5), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(5)); +\RHB_WAIT_CNT[6]_REG_Z524\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(6), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(6)); +\RHB_WAIT_CNT[7]_REG_Z526\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(7), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(7)); +RHB_SYNC_P2_REG_Z528: FD1S3DX port map ( +D => RHB_SYNC_P1, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P2); +RHB_SYNC_P1_REG_Z530: FD1S3DX port map ( +D => RHB_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P1); +\RCOUNT[0]_REG_Z532\: FD1S3DX port map ( +D => RCOUNT_S(0), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(0)); +\RCOUNT[1]_REG_Z534\: FD1S3DX port map ( +D => RCOUNT_S(1), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(1)); +\RCOUNT[2]_REG_Z536\: FD1S3DX port map ( +D => RCOUNT_S(2), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(2)); +\RCOUNT[3]_REG_Z538\: FD1S3DX port map ( +D => RCOUNT_S(3), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(3)); +\RCOUNT[4]_REG_Z540\: FD1S3DX port map ( +D => RCOUNT_S(4), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(4)); +\RCOUNT[5]_REG_Z542\: FD1S3DX port map ( +D => RCOUNT_S(5), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(5)); +\RCOUNT[6]_REG_Z544\: FD1S3DX port map ( +D => RCOUNT_S(6), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(6)); +\RCOUNT[7]_REG_Z546\: FD1S3DX port map ( +D => RCOUNT_S(7), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(7)); +\RCOUNT[8]_REG_Z548\: FD1S3DX port map ( +D => RCOUNT_S(8), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(8)); +\RCOUNT[9]_REG_Z550\: FD1S3DX port map ( +D => RCOUNT_S(9), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(9)); +\RCOUNT[10]_REG_Z552\: FD1S3DX port map ( +D => RCOUNT_S(10), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(10)); +\RCOUNT[11]_REG_Z554\: FD1S3DX port map ( +D => RCOUNT_S(11), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(11)); +\RCOUNT[12]_REG_Z556\: FD1S3DX port map ( +D => RCOUNT_S(12), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(12)); +\RCOUNT[13]_REG_Z558\: FD1S3DX port map ( +D => RCOUNT_S(13), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(13)); +\RCOUNT[14]_REG_Z560\: FD1S3DX port map ( +D => RCOUNT_S(14), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(14)); +\RCOUNT[15]_REG_Z562\: FD1S3DX port map ( +D => RCOUNT_S(15), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(15)); +PPUL_SYNC_P3_REG_Z564: FD1S3DX port map ( +D => PPUL_SYNC_P2, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P3); +PPUL_SYNC_P2_REG_Z566: FD1S3DX port map ( +D => PPUL_SYNC_P1, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P2); +PPUL_SYNC_P1_REG_Z568: FD1S3DX port map ( +D => PPUL_SYNC, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P1); +PLL_LOCK_REG_Z570: FD1S3DX port map ( +D => N_53_I, +CK => pll_refclki, +CD => sli_rst, +Q => PLL_LOCK); +\PHB_CNT[0]_REG_Z572\: FD1S3DX port map ( +D => PHB_CNT_I(0), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(0)); +\PHB_CNT[1]_REG_Z574\: FD1S3DX port map ( +D => PHB_CNT_RNO(1), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(1)); +\PHB_CNT[2]_REG_Z576\: FD1S3DX port map ( +D => PHB_CNT_RNO(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(2)); +PHB_REG_Z578: FD1S3DX port map ( +D => PHB_CNT_I(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB); +PDIFF_SYNC_P1_REG_Z580: FD1S3DX port map ( +D => PDIFF_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => PDIFF_SYNC_P1); +\PCOUNT[0]_REG_Z582\: FD1S3DX port map ( +D => PCOUNT_S(0), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(0)); +\PCOUNT_DIFF[0]_REG_Z584\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_I(0), +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_0); +\PCOUNT[1]_REG_Z586\: FD1S3DX port map ( +D => PCOUNT_S(1), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(1)); +\PCOUNT_DIFF[1]_REG_Z588\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_1); +\PCOUNT_DIFF[2]_REG_Z590\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_2); +\PCOUNT[2]_REG_Z592\: FD1S3DX port map ( +D => PCOUNT_S(2), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(2)); +\PCOUNT_DIFF[3]_REG_Z594\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_3); +\PCOUNT[3]_REG_Z596\: FD1S3DX port map ( +D => PCOUNT_S(3), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(3)); +\PCOUNT_DIFF[4]_REG_Z598\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_4); +\PCOUNT[4]_REG_Z600\: FD1S3DX port map ( +D => PCOUNT_S(4), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(4)); +\PCOUNT_DIFF[5]_REG_Z602\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_5); +\PCOUNT[5]_REG_Z604\: FD1S3DX port map ( +D => PCOUNT_S(5), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(5)); +\PCOUNT[6]_REG_Z606\: FD1S3DX port map ( +D => PCOUNT_S(6), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(6)); +\PCOUNT_DIFF[6]_REG_Z608\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_6); +\PCOUNT[7]_REG_Z610\: FD1S3DX port map ( +D => PCOUNT_S(7), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(7)); +\PCOUNT_DIFF[7]_REG_Z612\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_7); +\PCOUNT[8]_REG_Z614\: FD1S3DX port map ( +D => PCOUNT_S(8), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(8)); +\PCOUNT_DIFF[8]_REG_Z616\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_8); +\PCOUNT_DIFF[9]_REG_Z618\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_9); +\PCOUNT[9]_REG_Z620\: FD1S3DX port map ( +D => PCOUNT_S(9), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(9)); +\PCOUNT[10]_REG_Z622\: FD1S3DX port map ( +D => PCOUNT_S(10), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(10)); +\PCOUNT_DIFF[10]_REG_Z624\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_10); +\PCOUNT_DIFF[11]_REG_Z626\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_11); +\PCOUNT[11]_REG_Z628\: FD1S3DX port map ( +D => PCOUNT_S(11), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(11)); +\PCOUNT[12]_REG_Z630\: FD1S3DX port map ( +D => PCOUNT_S(12), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(12)); +\PCOUNT_DIFF[12]_REG_Z632\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_12); +\PCOUNT_DIFF[13]_REG_Z634\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_13); +\PCOUNT[13]_REG_Z636\: FD1S3DX port map ( +D => PCOUNT_S(13), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(13)); +\PCOUNT_DIFF[14]_REG_Z638\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_14); +\PCOUNT[14]_REG_Z640\: FD1S3DX port map ( +D => PCOUNT_S(14), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(14)); +\PCOUNT[15]_REG_Z642\: FD1S3DX port map ( +D => PCOUNT_S(15), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(15)); +\PCOUNT_DIFF[15]_REG_Z644\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_15); +\PCOUNT[16]_REG_Z646\: FD1S3DX port map ( +D => PCOUNT_S(16), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(16)); +\PCOUNT_DIFF[16]_REG_Z648\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_16); +\PCOUNT_DIFF[17]_REG_Z650\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_17); +\PCOUNT[17]_REG_Z652\: FD1S3DX port map ( +D => PCOUNT_S(17), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(17)); +\PCOUNT_DIFF[18]_REG_Z654\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_18); +\PCOUNT[18]_REG_Z656\: FD1S3DX port map ( +D => PCOUNT_S(18), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(18)); +\PCOUNT[19]_REG_Z658\: FD1S3DX port map ( +D => PCOUNT_S(19), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(19)); +\PCOUNT_DIFF[19]_REG_Z660\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_19); +\PCOUNT[20]_REG_Z662\: FD1S3DX port map ( +D => PCOUNT_S(20), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(20)); +\PCOUNT_DIFF[20]_REG_Z664\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_20); +\PCOUNT_DIFF[21]_REG_Z666\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_S_21_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_21); +\PCOUNT[21]_REG_Z668\: FD1S3DX port map ( +D => PCOUNT_S(21), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(21)); +LOCK_REG_Z670: FD1P3DX port map ( +D => LOCK_5, +SP => LOCK_1_SQMUXA_I, +CK => pll_refclki, +CD => sli_rst, +Q => LOCK); +\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z672\: FD1S3DX port map ( +D => VCC, +CK => pll_refclki, +CD => sli_rst, +Q => RDIFF_COMP_LOCK(2)); +\SLL_STATE_RNO[0]\: LUT4 +generic map( + init => X"E050" +) +port map ( +A => N_98, +B => LOCK, +C => RSTAT_PCLK, +D => SLL_STATE(0), +Z => N_95_I); +RTC_PUL5_0_0: LUT4 +generic map( + init => X"FF80" +) +port map ( +A => RTC_PUL5_0_O3, +B => RTC_PUL5_0_A3_6, +C => RTC_PUL5_0_A3_7, +D => UN1_RCOUNT_1_0_A3, +Z => RTC_PUL5); +RSTAT_PCLK_2_IV: LUT4 +generic map( + init => X"AEEE" +) +port map ( +A => RHB_WAIT_CNT12, +B => RSTAT_PCLK, +C => UN1_RHB_WAIT_CNT_4, +D => UN1_RHB_WAIT_CNT_5, +Z => RSTAT_PCLK_2); +\SLL_STATE_RNO[1]\: LUT4 +generic map( + init => X"8088" +) +port map ( +A => N_99, +B => RSTAT_PCLK, +C => SLL_STATE(1), +D => UNLOCK, +Z => N_97_I); +RTC_CTRL4_0_A3: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_1, +B => RTC_CTRL4_0_A3_12_4, +C => RTC_CTRL4_0_A3_12_5, +D => RTC_CTRL4_10, +Z => RTC_CTRL4); +UN1_RCOUNT_1_0_A3_Z678: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_12_4, +B => RTC_CTRL4_0_A3_12_5, +C => RTC_CTRL4_10, +D => UN1_RCOUNT_1_0_A3_1, +Z => UN1_RCOUNT_1_0_A3); +LOCK_1_SQMUXA_I_Z679: LUT4 +generic map( + init => X"7575" +) +port map ( +A => LOCK, +B => PDIFF_SYNC, +C => PDIFF_SYNC_P1, +D => VCC, +Z => LOCK_1_SQMUXA_I); +UNLOCK_1_SQMUXA_I_Z680: LUT4 +generic map( + init => X"4F4F" +) +port map ( +A => PDIFF_SYNC, +B => PDIFF_SYNC_P1, +C => UNLOCK, +D => VCC, +Z => UNLOCK_1_SQMUXA_I); +RTC_PUL5_0_O3_Z681: LUT4 +generic map( + init => X"AAAB" +) +port map ( +A => N_6, +B => RCOUNT(1), +C => RCOUNT(2), +D => RCOUNT(3), +Z => RTC_PUL5_0_O3); +RTC_PUL5_0_A3_7_Z682: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RTC_PUL5_0_A3_5, +D => VCC, +Z => RTC_PUL5_0_A3_7); +\SLL_STATE_NS_I_M4[1]\: LUT4 +generic map( + init => X"EF20" +) +port map ( +A => LOCK, +B => RTC_PUL, +C => RTC_PUL_P1, +D => SLL_STATE(1), +Z => N_99); +PLL_LOCK_RNO: LUT4 +generic map( + init => X"8888" +) +port map ( +A => SLL_STATE(0), +B => SLL_STATE(1), +C => VCC, +D => VCC, +Z => N_53_I); +\PHB_CNT_RNO[2]_Z685\: LUT4 +generic map( + init => X"7878" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => PHB_CNT(2), +D => VCC, +Z => PHB_CNT_RNO(2)); +\SLL_STATE_NS_I_O4[0]\: LUT4 +generic map( + init => X"BFBF" +) +port map ( +A => RTC_PUL, +B => RTC_PUL_P1, +C => SLL_STATE(1), +D => VCC, +Z => N_98); +RTC_CTRL4_0_A3_10: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(1), +B => RCOUNT(3), +C => RCOUNT(6), +D => RCOUNT(15), +Z => RTC_CTRL4_10); +UN1_RHB_WAIT_CNT_4_Z688: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(4), +B => RHB_WAIT_CNT(5), +C => RHB_WAIT_CNT(6), +D => RHB_WAIT_CNT(7), +Z => UN1_RHB_WAIT_CNT_4); +UN1_RHB_WAIT_CNT_5_Z689: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(0), +B => RHB_WAIT_CNT(1), +C => RHB_WAIT_CNT(2), +D => RHB_WAIT_CNT(3), +Z => UN1_RHB_WAIT_CNT_5); +RTC_CTRL4_0_A3_12_4_Z690: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(11), +B => RCOUNT(12), +C => RCOUNT(13), +D => RCOUNT(14), +Z => RTC_CTRL4_0_A3_12_4); +RTC_CTRL4_0_A3_12_5_Z691: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RCOUNT(9), +D => RCOUNT(10), +Z => RTC_CTRL4_0_A3_12_5); +RTC_PUL5_0_A3_5_Z692: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(6), +B => RCOUNT(13), +C => RCOUNT(14), +D => RCOUNT(15), +Z => RTC_PUL5_0_A3_5); +RTC_PUL5_0_A3_6_Z693: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(9), +B => RCOUNT(10), +C => RCOUNT(11), +D => RCOUNT(12), +Z => RTC_PUL5_0_A3_6); +PCOUNT10_0_O3: LUT4 +generic map( + init => X"DDDD" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => VCC, +D => VCC, +Z => N_8); +\PHB_CNT_RNO[1]_Z695\: LUT4 +generic map( + init => X"6666" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => VCC, +D => VCC, +Z => PHB_CNT_RNO(1)); +RTC_CTRL4_0_O3: LUT4 +generic map( + init => X"7777" +) +port map ( +A => RCOUNT(4), +B => RCOUNT(5), +C => VCC, +D => VCC, +Z => N_6); +UNLOCK_5_Z697: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_UNLOCK_CRY_21, +C => VCC, +D => VCC, +Z => UNLOCK_5); +LOCK_5_Z698: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_LOCK_CRY_21_I, +C => VCC, +D => VCC, +Z => LOCK_5); +RHB_WAIT_CNT12_Z699: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RHB_SYNC_P1, +B => RHB_SYNC_P2, +C => VCC, +D => VCC, +Z => RHB_WAIT_CNT12); +\UN1_PCOUNT_DIFF[0]_Z700\: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_0, +B => PCOUNT(0), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF(0)); +UN1_RCOUNT_1_0_A3_1_Z701: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => UN1_RCOUNT_1_0_A3_1); +RHB_SYNC_P2_RNIU9TG1: LUT4 +generic map( + init => X"7077" +) +port map ( +A => UN1_RHB_WAIT_CNT_5, +B => UN1_RHB_WAIT_CNT_4, +C => RHB_SYNC_P2, +D => RHB_SYNC_P1, +Z => \RHB_WAIT_CNT_\); +\PCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => N_8, +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_9, +COUT => PCOUNT_CRY(0), +S0 => PCOUNT_CRY_0_S0(0), +S1 => PCOUNT_S(0)); +\PCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(0), +COUT => PCOUNT_CRY(2), +S0 => PCOUNT_S(1), +S1 => PCOUNT_S(2)); +\PCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(2), +COUT => PCOUNT_CRY(4), +S0 => PCOUNT_S(3), +S1 => PCOUNT_S(4)); +\PCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(4), +COUT => PCOUNT_CRY(6), +S0 => PCOUNT_S(5), +S1 => PCOUNT_S(6)); +\PCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(6), +COUT => PCOUNT_CRY(8), +S0 => PCOUNT_S(7), +S1 => PCOUNT_S(8)); +\PCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(8), +COUT => PCOUNT_CRY(10), +S0 => PCOUNT_S(9), +S1 => PCOUNT_S(10)); +\PCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(10), +COUT => PCOUNT_CRY(12), +S0 => PCOUNT_S(11), +S1 => PCOUNT_S(12)); +\PCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(12), +COUT => PCOUNT_CRY(14), +S0 => PCOUNT_S(13), +S1 => PCOUNT_S(14)); +\PCOUNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(16), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(14), +COUT => PCOUNT_CRY(16), +S0 => PCOUNT_S(15), +S1 => PCOUNT_S(16)); +\PCOUNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(17), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(18), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(16), +COUT => PCOUNT_CRY(18), +S0 => PCOUNT_S(17), +S1 => PCOUNT_S(18)); +\PCOUNT_CRY_0[19]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(19), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(20), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(18), +COUT => PCOUNT_CRY(20), +S0 => PCOUNT_S(19), +S1 => PCOUNT_S(20)); +\PCOUNT_S_0[21]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(21), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(20), +COUT => PCOUNT_S_0_COUT(21), +S0 => PCOUNT_S(21), +S1 => PCOUNT_S_0_S1(21)); +\RCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => UN1_RCOUNT_1_0_A3, +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => RCOUNT_CRY(0), +S0 => RCOUNT_CRY_0_S0(0), +S1 => RCOUNT_S(0)); +\RCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(0), +COUT => RCOUNT_CRY(2), +S0 => RCOUNT_S(1), +S1 => RCOUNT_S(2)); +\RCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(2), +COUT => RCOUNT_CRY(4), +S0 => RCOUNT_S(3), +S1 => RCOUNT_S(4)); +\RCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(4), +COUT => RCOUNT_CRY(6), +S0 => RCOUNT_S(5), +S1 => RCOUNT_S(6)); +\RCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(6), +COUT => RCOUNT_CRY(8), +S0 => RCOUNT_S(7), +S1 => RCOUNT_S(8)); +\RCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(8), +COUT => RCOUNT_CRY(10), +S0 => RCOUNT_S(9), +S1 => RCOUNT_S(10)); +\RCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(10), +COUT => RCOUNT_CRY(12), +S0 => RCOUNT_S(11), +S1 => RCOUNT_S(12)); +\RCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(12), +COUT => RCOUNT_CRY(14), +S0 => RCOUNT_S(13), +S1 => RCOUNT_S(14)); +\RCOUNT_S_0[15]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(14), +COUT => RCOUNT_S_0_COUT(15), +S0 => RCOUNT_S(15), +S1 => RCOUNT_S_0_S1(15)); +\RHB_WAIT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RHB_WAIT_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RHB_WAIT_CNT_CRY(0), +S0 => RHB_WAIT_CNT_CRY_0_S0(0), +S1 => RHB_WAIT_CNT_S(0)); +\RHB_WAIT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(0), +COUT => RHB_WAIT_CNT_CRY(2), +S0 => RHB_WAIT_CNT_S(1), +S1 => RHB_WAIT_CNT_S(2)); +\RHB_WAIT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(2), +COUT => RHB_WAIT_CNT_CRY(4), +S0 => RHB_WAIT_CNT_S(3), +S1 => RHB_WAIT_CNT_S(4)); +\RHB_WAIT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(4), +COUT => RHB_WAIT_CNT_CRY(6), +S0 => RHB_WAIT_CNT_S(5), +S1 => RHB_WAIT_CNT_S(6)); +\RHB_WAIT_CNT_S_0[7]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(6), +COUT => RHB_WAIT_CNT_S_0_COUT(7), +S0 => RHB_WAIT_CNT_S(7), +S1 => RHB_WAIT_CNT_S_0_S1(7)); +UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500f", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF(0), +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => UN1_PCOUNT_DIFF_1_CRY_0, +S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1); +UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_1, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_2, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_0, +COUT => UN1_PCOUNT_DIFF_1_CRY_2, +S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1); +UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_2, +COUT => UN1_PCOUNT_DIFF_1_CRY_4, +S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1); +UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_4, +COUT => UN1_PCOUNT_DIFF_1_CRY_6, +S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1); +UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_6, +COUT => UN1_PCOUNT_DIFF_1_CRY_8, +S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1); +UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_8, +COUT => UN1_PCOUNT_DIFF_1_CRY_10, +S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1); +UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_10, +COUT => UN1_PCOUNT_DIFF_1_CRY_12, +S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1); +UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_12, +COUT => UN1_PCOUNT_DIFF_1_CRY_14, +S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1); +UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_14, +COUT => UN1_PCOUNT_DIFF_1_CRY_16, +S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1); +UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C +generic map( + INIT0 => X"b404", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => RDIFF_COMP_LOCK(2), +C0 => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_16, +COUT => UN1_PCOUNT_DIFF_1_CRY_18, +S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1); +UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_18, +COUT => UN1_PCOUNT_DIFF_1_CRY_20, +S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1); +UN1_PCOUNT_DIFF_1_S_21_0: CCU2C +generic map( + INIT0 => X"350a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => PCOUNT(21), +B0 => UN13_LOCK_21, +C0 => N_8, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_20, +COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT, +S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0, +S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1); +UN13_LOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => UN13_LOCK_CRY_0, +S0 => UN13_LOCK_CRY_0_0_S0, +S1 => UN13_LOCK_CRY_0_0_S1); +UN13_LOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_0, +COUT => UN13_LOCK_CRY_2, +S0 => UN13_LOCK_CRY_1_0_S0, +S1 => UN13_LOCK_CRY_1_0_S1); +UN13_LOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_2, +COUT => UN13_LOCK_CRY_4, +S0 => UN13_LOCK_CRY_3_0_S0, +S1 => UN13_LOCK_CRY_3_0_S1); +UN13_LOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_4, +COUT => UN13_LOCK_CRY_6, +S0 => UN13_LOCK_CRY_5_0_S0, +S1 => UN13_LOCK_CRY_5_0_S1); +UN13_LOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_6, +COUT => UN13_LOCK_CRY_8, +S0 => UN13_LOCK_CRY_7_0_S0, +S1 => UN13_LOCK_CRY_7_0_S1); +UN13_LOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_8, +COUT => UN13_LOCK_CRY_10, +S0 => UN13_LOCK_CRY_9_0_S0, +S1 => UN13_LOCK_CRY_9_0_S1); +UN13_LOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_10, +COUT => UN13_LOCK_CRY_12, +S0 => UN13_LOCK_CRY_11_0_S0, +S1 => UN13_LOCK_CRY_11_0_S1); +UN13_LOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_12, +COUT => UN13_LOCK_CRY_14, +S0 => UN13_LOCK_CRY_13_0_S0, +S1 => UN13_LOCK_CRY_13_0_S1); +UN13_LOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_14, +COUT => UN13_LOCK_CRY_16, +S0 => UN13_LOCK_CRY_15_0_S0, +S1 => UN13_LOCK_CRY_15_0_S1); +UN13_LOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_16, +COUT => UN13_LOCK_CRY_18, +S0 => UN13_LOCK_CRY_17_0_S0, +S1 => UN13_LOCK_CRY_17_0_S1); +UN13_LOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_18, +COUT => UN13_LOCK_CRY_20, +S0 => UN13_LOCK_CRY_19_0_S0, +S1 => UN13_LOCK_CRY_19_0_S1); +UN13_LOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_20, +COUT => UN13_LOCK_CRY_21_0_COUT, +S0 => UN13_LOCK_CRY_21_0_S0, +S1 => UN13_LOCK_CRY_21_I); +UN13_UNLOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => UN13_UNLOCK_CRY_0, +S0 => UN13_UNLOCK_CRY_0_0_S0, +S1 => UN13_UNLOCK_CRY_0_0_S1); +UN13_UNLOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_0, +COUT => UN13_UNLOCK_CRY_2, +S0 => UN13_UNLOCK_CRY_1_0_S0, +S1 => UN13_UNLOCK_CRY_1_0_S1); +UN13_UNLOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_2, +COUT => UN13_UNLOCK_CRY_4, +S0 => UN13_UNLOCK_CRY_3_0_S0, +S1 => UN13_UNLOCK_CRY_3_0_S1); +UN13_UNLOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_4, +COUT => UN13_UNLOCK_CRY_6, +S0 => UN13_UNLOCK_CRY_5_0_S0, +S1 => UN13_UNLOCK_CRY_5_0_S1); +UN13_UNLOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_6, +COUT => UN13_UNLOCK_CRY_8, +S0 => UN13_UNLOCK_CRY_7_0_S0, +S1 => UN13_UNLOCK_CRY_7_0_S1); +UN13_UNLOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_8, +COUT => UN13_UNLOCK_CRY_10, +S0 => UN13_UNLOCK_CRY_9_0_S0, +S1 => UN13_UNLOCK_CRY_9_0_S1); +UN13_UNLOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_10, +COUT => UN13_UNLOCK_CRY_12, +S0 => UN13_UNLOCK_CRY_11_0_S0, +S1 => UN13_UNLOCK_CRY_11_0_S1); +UN13_UNLOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_12, +COUT => UN13_UNLOCK_CRY_14, +S0 => UN13_UNLOCK_CRY_13_0_S0, +S1 => UN13_UNLOCK_CRY_13_0_S1); +UN13_UNLOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_14, +COUT => UN13_UNLOCK_CRY_16, +S0 => UN13_UNLOCK_CRY_15_0_S0, +S1 => UN13_UNLOCK_CRY_15_0_S1); +UN13_UNLOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_16, +COUT => UN13_UNLOCK_CRY_18, +S0 => UN13_UNLOCK_CRY_17_0_S0, +S1 => UN13_UNLOCK_CRY_17_0_S1); +UN13_UNLOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_18, +COUT => UN13_UNLOCK_CRY_20, +S0 => UN13_UNLOCK_CRY_19_0_S0, +S1 => UN13_UNLOCK_CRY_19_0_S1); +UN13_UNLOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_20, +COUT => UN13_UNLOCK_CRY_21_0_COUT, +S0 => UN13_UNLOCK_CRY_21_0_S0, +S1 => UN13_UNLOCK_CRY_21); +PHB_SYNC_INST: sync_0s port map ( +phb => PHB, +rhb_sync => RHB_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +RTC_SYNC_INST: sync_0s_6 port map ( +rtc_pul => RTC_PUL, +ppul_sync => PPUL_SYNC, +sli_rst => sli_rst, +tx_pclk => tx_pclk); +PDIFF_SYNC_INST: sync_0s_0 port map ( +ppul_sync => PPUL_SYNC, +pdiff_sync => PDIFF_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5 is +port( +hdoutp : out std_logic; +hdoutn : out std_logic; +hdinp : in std_logic; +hdinn : in std_logic; +rxrefclk : in std_logic; +tx_pclk : out std_logic; +txi_clk : in std_logic; +txdata : in std_logic_vector(7 downto 0); +tx_k : in std_logic_vector(0 downto 0); +xmit : in std_logic_vector(0 downto 0); +tx_disp_correct : in std_logic_vector(0 downto 0); +rxdata : out std_logic_vector(7 downto 0); +rx_k : out std_logic_vector(0 downto 0); +rx_disp_err : out std_logic_vector(0 downto 0); +rx_cv_err : out std_logic_vector(0 downto 0); +signal_detect_c : in std_logic; +rx_los_low_s : out std_logic; +lsm_status_s : out std_logic; +ctc_urun_s : out std_logic; +ctc_orun_s : out std_logic; +rx_cdr_lol_s : out std_logic; +ctc_ins_s : out std_logic; +ctc_del_s : out std_logic; +sli_rst : in std_logic; +tx_pwrup_c : in std_logic; +rx_pwrup_c : in std_logic; +sci_wrdata : in std_logic_vector(7 downto 0); +sci_addr : in std_logic_vector(5 downto 0); +sci_rddata : out std_logic_vector(7 downto 0); +sci_en_dual : in std_logic; +sci_sel_dual : in std_logic; +sci_en : in std_logic; +sci_sel : in std_logic; +sci_rd : in std_logic; +sci_wrn : in std_logic; +sci_int : out std_logic; +cyawstn : in std_logic; +serdes_pdb : in std_logic; +pll_refclki : in std_logic; +rsl_disable : in std_logic; +rsl_rst : in std_logic; +serdes_rst_dual_c : in std_logic; +rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +pll_lol : out std_logic; +rsl_tx_rdy : out std_logic; +rx_serdes_rst_c : in std_logic; +rx_pcs_rst_c : in std_logic; +rsl_rx_rdy : out std_logic); +end sgmii_ecp5; + +architecture beh of sgmii_ecp5 is +signal TX_PCLK_11 : std_logic ; +signal RX_LOS_LOW_S_12 : std_logic ; +signal RX_CDR_LOL_S_13 : std_logic ; +signal RSL_TX_PCS_RST_C : std_logic ; +signal RSL_RX_PCS_RST_C : std_logic ; +signal RSL_RX_SERDES_RST_C : std_logic ; +signal RSL_SERDES_RST_DUAL_C : std_logic ; +signal RSL_TX_SERDES_RST_C : std_logic ; +signal N47_1 : std_logic ; +signal N48_1 : std_logic ; +signal N1_1 : std_logic ; +signal N2_1 : std_logic ; +signal N3_1 : std_logic ; +signal N4_1 : std_logic ; +signal N5_1 : std_logic ; +signal N49_1 : std_logic ; +signal N6_1 : std_logic ; +signal N50_1 : std_logic ; +signal N7_1 : std_logic ; +signal N51_1 : std_logic ; +signal N8_1 : std_logic ; +signal N52_1 : std_logic ; +signal N9_1 : std_logic ; +signal N53_1 : std_logic ; +signal N54_1 : std_logic ; +signal N55_1 : std_logic ; +signal N56_1 : std_logic ; +signal N57_1 : std_logic ; +signal N58_1 : std_logic ; +signal N59_1 : std_logic ; +signal N60_1 : std_logic ; +signal N61_1 : std_logic ; +signal N62_1 : std_logic ; +signal N63_1 : std_logic ; +signal N64_1 : std_logic ; +signal N65_1 : std_logic ; +signal N10_1 : std_logic ; +signal N66_1 : std_logic ; +signal N67_1 : std_logic ; +signal N68_1 : std_logic ; +signal N69_1 : std_logic ; +signal N70_1 : std_logic ; +signal N71_1 : std_logic ; +signal N72_1 : std_logic ; +signal N73_1 : std_logic ; +signal N74_1 : std_logic ; +signal N75_1 : std_logic ; +signal N76_1 : std_logic ; +signal N77_1 : std_logic ; +signal N78_1 : std_logic ; +signal N79_1 : std_logic ; +signal N80_1 : std_logic ; +signal N81_1 : std_logic ; +signal N82_1 : std_logic ; +signal N83_1 : std_logic ; +signal N84_1 : std_logic ; +signal N85_1 : std_logic ; +signal N86_1 : std_logic ; +signal N87_1 : std_logic ; +signal N88_1 : std_logic ; +signal N11_1 : std_logic ; +signal N89_1 : std_logic ; +signal N12_1 : std_logic ; +signal N90_1 : std_logic ; +signal N13_1 : std_logic ; +signal N91_1 : std_logic ; +signal N92_1 : std_logic ; +signal N93_1 : std_logic ; +signal N94_1 : std_logic ; +signal N95_1 : std_logic ; +signal N14_1 : std_logic ; +signal N96_1 : std_logic ; +signal N15_1 : std_logic ; +signal N97_1 : std_logic ; +signal N98_1 : std_logic ; +signal N99_1 : std_logic ; +signal N100_1 : std_logic ; +signal N101_1 : std_logic ; +signal N112_1 : std_logic ; +signal N16_1 : std_logic ; +signal N17_1 : std_logic ; +signal N18_1 : std_logic ; +signal N19_1 : std_logic ; +signal N20_1 : std_logic ; +signal N21_1 : std_logic ; +signal N22_1 : std_logic ; +signal N23_1 : std_logic ; +signal N24_1 : std_logic ; +signal N25_1 : std_logic ; +signal N26_1 : std_logic ; +signal N27_1 : std_logic ; +signal N28_1 : std_logic ; +signal N29_1 : std_logic ; +signal N30_1 : std_logic ; +signal N31_1 : std_logic ; +signal N32_1 : std_logic ; +signal N33_1 : std_logic ; +signal N34_1 : std_logic ; +signal N35_1 : std_logic ; +signal N36_1 : std_logic ; +signal N37_1 : std_logic ; +signal N38_1 : std_logic ; +signal N39_1 : std_logic ; +signal N40_1 : std_logic ; +signal N41_1 : std_logic ; +signal N42_1 : std_logic ; +signal N43_1 : std_logic ; +signal N46_1 : std_logic ; +signal TX_PCLK_I : std_logic ; +signal GND : std_logic ; +signal VCC : std_logic ; +signal \SLL_INST.PLL_LOCK_I_14\ : std_logic ; +component sgmii_ecp5sll_core_Z1_layer1 +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic ); +end component; +component sgmii_ecp5rsl_core_Z2_layer1 +port( +rx_pcs_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +tx_serdes_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rsl_disable : in std_logic; +rx_serdes_rst_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rst_dual_c : in std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic ); +end component; +begin +VCC_0: VHI port map ( +Z => VCC); +GND_0: VLO port map ( +Z => GND); +PUR_INST: PUR port map ( +PUR => VCC); +GSR_INST: GSR port map ( +GSR => VCC); +TX_PCLK_11 <= TX_PCLK_I; +DCU0_INST: DCUA +generic map( + D_MACROPDB => "0b1", + D_IB_PWDNB => "0b1", + D_XGE_MODE => "0b0", + D_LOW_MARK => "0d4", + D_HIGH_MARK => "0d12", + D_BUS8BIT_SEL => "0b0", + D_CDR_LOL_SET => "0b00", + D_BITCLK_LOCAL_EN => "0b1", + D_BITCLK_ND_EN => "0b0", + D_BITCLK_FROM_ND_EN => "0b0", + D_SYNC_LOCAL_EN => "0b1", + D_SYNC_ND_EN => "0b0", + CH0_UC_MODE => "0b0", + CH0_PCIE_MODE => "0b0", + CH0_RIO_MODE => "0b0", + CH0_WA_MODE => "0b0", + CH0_INVERT_RX => "0b0", + CH0_INVERT_TX => "0b0", + CH0_PRBS_SELECTION => "0b0", + CH0_GE_AN_ENABLE => "0b0", + CH0_PRBS_LOCK => "0b0", + CH0_PRBS_ENABLE => "0b0", + CH0_ENABLE_CG_ALIGN => "0b1", + CH0_TX_GEAR_MODE => "0b0", + CH0_RX_GEAR_MODE => "0b0", + CH0_PCS_DET_TIME_SEL => "0b00", + CH0_PCIE_EI_EN => "0b0", + CH0_TX_GEAR_BYPASS => "0b0", + CH0_ENC_BYPASS => "0b0", + CH0_SB_BYPASS => "0b0", + CH0_RX_SB_BYPASS => "0b0", + CH0_WA_BYPASS => "0b0", + CH0_DEC_BYPASS => "0b0", + CH0_CTC_BYPASS => "0b0", + CH0_RX_GEAR_BYPASS => "0b0", + CH0_LSM_DISABLE => "0b0", + CH0_MATCH_2_ENABLE => "0b1", + CH0_MATCH_4_ENABLE => "0b0", + CH0_MIN_IPG_CNT => "0b11", + CH0_CC_MATCH_1 => "0x000", + CH0_CC_MATCH_2 => "0x000", + CH0_CC_MATCH_3 => "0x1BC", + CH0_CC_MATCH_4 => "0x050", + CH0_UDF_COMMA_MASK => "0x3ff", + CH0_UDF_COMMA_A => "0x283", + CH0_UDF_COMMA_B => "0x17C", + CH0_RX_DCO_CK_DIV => "0b010", + CH0_RCV_DCC_EN => "0b0", + CH0_REQ_LVL_SET => "0b00", + CH0_REQ_EN => "0b1", + CH0_RTERM_RX => "0d22", + CH0_PDEN_SEL => "0b1", + CH0_LDR_RX2CORE_SEL => "0b0", + CH0_LDR_CORE2TX_SEL => "0b0", + CH0_TPWDNB => "0b1", + CH0_RATE_MODE_TX => "0b0", + CH0_RTERM_TX => "0d19", + CH0_TX_CM_SEL => "0b00", + CH0_TDRV_PRE_EN => "0b0", + CH0_TDRV_SLICE0_SEL => "0b01", + CH0_TDRV_SLICE1_SEL => "0b00", + CH0_TDRV_SLICE2_SEL => "0b01", + CH0_TDRV_SLICE3_SEL => "0b01", + CH0_TDRV_SLICE4_SEL => "0b01", + CH0_TDRV_SLICE5_SEL => "0b01", + CH0_TDRV_SLICE0_CUR => "0b101", + CH0_TDRV_SLICE1_CUR => "0b000", + CH0_TDRV_SLICE2_CUR => "0b11", + CH0_TDRV_SLICE3_CUR => "0b11", + CH0_TDRV_SLICE4_CUR => "0b11", + CH0_TDRV_SLICE5_CUR => "0b00", + CH0_TDRV_DAT_SEL => "0b00", + CH0_TX_DIV11_SEL => "0b0", + CH0_RPWDNB => "0b1", + CH0_RATE_MODE_RX => "0b0", + CH0_RLOS_SEL => "0b1", + CH0_RX_LOS_LVL => "0b010", + CH0_RX_LOS_CEQ => "0b11", + CH0_RX_LOS_HYST_EN => "0b0", + CH0_RX_LOS_EN => "0b1", + CH0_RX_DIV11_SEL => "0b0", + CH0_SEL_SD_RX_CLK => "0b0", + CH0_FF_RX_H_CLK_EN => "0b0", + CH0_FF_RX_F_CLK_DIS => "0b0", + CH0_FF_TX_H_CLK_EN => "0b0", + CH0_FF_TX_F_CLK_DIS => "0b0", + CH0_RX_RATE_SEL => "0d8", + CH0_TDRV_POST_EN => "0b0", + CH0_TX_POST_SIGN => "0b0", + CH0_TX_PRE_SIGN => "0b0", + CH0_RXTERM_CM => "0b11", + CH0_RXIN_CM => "0b11", + CH0_LEQ_OFFSET_SEL => "0b0", + CH0_LEQ_OFFSET_TRIM => "0b000", + D_TX_MAX_RATE => "1.25", + CH0_CDR_MAX_RATE => "1.25", + CH0_TXAMPLITUDE => "0d1100", + CH0_TXDEPRE => "DISABLED", + CH0_TXDEPOST => "DISABLED", + CH0_PROTOCOL => "GBE", + D_ISETLOS => "0d0", + D_SETIRPOLY_AUX => "0b00", + D_SETICONST_AUX => "0b00", + D_SETIRPOLY_CH => "0b00", + D_SETICONST_CH => "0b00", + D_REQ_ISET => "0b000", + D_PD_ISET => "0b00", + D_DCO_CALIB_TIME_SEL => "0b00", + CH0_DCOCTLGI => "0b010", + CH0_DCOATDDLY => "0b00", + CH0_DCOATDCFG => "0b00", + CH0_DCOBYPSATD => "0b1", + CH0_DCOSCALEI => "0b00", + CH0_DCOITUNE4LSB => "0b111", + CH0_DCOIOSTUNE => "0b000", + CH0_DCODISBDAVOID => "0b0", + CH0_DCOCALDIV => "0b001", + CH0_DCONUOFLSB => "0b101", + CH0_DCOIUPDNX2 => "0b1", + CH0_DCOSTEP => "0b00", + CH0_DCOSTARTVAL => "0b000", + CH0_DCOFLTDAC => "0b01", + CH0_DCOITUNE => "0b00", + CH0_DCOFTNRG => "0b110", + CH0_CDR_CNT4SEL => "0b00", + CH0_CDR_CNT8SEL => "0b00", + CH0_BAND_THRESHOLD => "0d0", + CH0_AUTO_FACQ_EN => "0b1", + CH0_AUTO_CALIB_EN => "0b1", + CH0_CALIB_CK_MODE => "0b0", + CH0_REG_BAND_OFFSET => "0d0", + CH0_REG_BAND_SEL => "0d0", + CH0_REG_IDAC_SEL => "0d0", + CH0_REG_IDAC_EN => "0b0", + D_TXPLL_PWDNB => "0b1", + D_SETPLLRC => "0d1", + D_REFCK_MODE => "0b001", + D_TX_VCO_CK_DIV => "0b010", + D_PLL_LOL_SET => "0b00", + D_RG_EN => "0b0", + D_RG_SET => "0b00", + D_CMUSETISCL4VCO => "0b000", + D_CMUSETI4VCO => "0b00", + D_CMUSETINITVCT => "0b00", + D_CMUSETZGM => "0b000", + D_CMUSETP2AGM => "0b000", + D_CMUSETP1GM => "0b000", + D_CMUSETI4CPZ => "0d3", + D_CMUSETI4CPP => "0d3", + D_CMUSETICP4Z => "0b101", + D_CMUSETICP4P => "0b01", + D_CMUSETBIASI => "0b00" +) +port map ( +CH0_HDINP => hdinp, +CH1_HDINP => GND, +CH0_HDINN => hdinn, +CH1_HDINN => GND, +D_TXBIT_CLKP_FROM_ND => GND, +D_TXBIT_CLKN_FROM_ND => GND, +D_SYNC_ND => GND, +D_TXPLL_LOL_FROM_ND => GND, +CH0_RX_REFCLK => rxrefclk, +CH1_RX_REFCLK => GND, +CH0_FF_RXI_CLK => TX_PCLK_11, +CH1_FF_RXI_CLK => VCC, +CH0_FF_TXI_CLK => txi_clk, +CH1_FF_TXI_CLK => VCC, +CH0_FF_EBRD_CLK => TX_PCLK_11, +CH1_FF_EBRD_CLK => VCC, +CH0_FF_TX_D_0 => txdata(0), +CH1_FF_TX_D_0 => GND, +CH0_FF_TX_D_1 => txdata(1), +CH1_FF_TX_D_1 => GND, +CH0_FF_TX_D_2 => txdata(2), +CH1_FF_TX_D_2 => GND, +CH0_FF_TX_D_3 => txdata(3), +CH1_FF_TX_D_3 => GND, +CH0_FF_TX_D_4 => txdata(4), +CH1_FF_TX_D_4 => GND, +CH0_FF_TX_D_5 => txdata(5), +CH1_FF_TX_D_5 => GND, +CH0_FF_TX_D_6 => txdata(6), +CH1_FF_TX_D_6 => GND, +CH0_FF_TX_D_7 => txdata(7), +CH1_FF_TX_D_7 => GND, +CH0_FF_TX_D_8 => tx_k(0), +CH1_FF_TX_D_8 => GND, +CH0_FF_TX_D_9 => GND, +CH1_FF_TX_D_9 => GND, +CH0_FF_TX_D_10 => xmit(0), +CH1_FF_TX_D_10 => GND, +CH0_FF_TX_D_11 => tx_disp_correct(0), +CH1_FF_TX_D_11 => GND, +CH0_FF_TX_D_12 => GND, +CH1_FF_TX_D_12 => GND, +CH0_FF_TX_D_13 => GND, +CH1_FF_TX_D_13 => GND, +CH0_FF_TX_D_14 => GND, +CH1_FF_TX_D_14 => GND, +CH0_FF_TX_D_15 => GND, +CH1_FF_TX_D_15 => GND, +CH0_FF_TX_D_16 => GND, +CH1_FF_TX_D_16 => GND, +CH0_FF_TX_D_17 => GND, +CH1_FF_TX_D_17 => GND, +CH0_FF_TX_D_18 => GND, +CH1_FF_TX_D_18 => GND, +CH0_FF_TX_D_19 => GND, +CH1_FF_TX_D_19 => GND, +CH0_FF_TX_D_20 => GND, +CH1_FF_TX_D_20 => GND, +CH0_FF_TX_D_21 => GND, +CH1_FF_TX_D_21 => GND, +CH0_FF_TX_D_22 => GND, +CH1_FF_TX_D_22 => GND, +CH0_FF_TX_D_23 => GND, +CH1_FF_TX_D_23 => GND, +CH0_FFC_EI_EN => GND, +CH1_FFC_EI_EN => GND, +CH0_FFC_PCIE_DET_EN => GND, +CH1_FFC_PCIE_DET_EN => GND, +CH0_FFC_PCIE_CT => GND, +CH1_FFC_PCIE_CT => GND, +CH0_FFC_SB_INV_RX => GND, +CH1_FFC_SB_INV_RX => GND, +CH0_FFC_ENABLE_CGALIGN => GND, +CH1_FFC_ENABLE_CGALIGN => GND, +CH0_FFC_SIGNAL_DETECT => signal_detect_c, +CH1_FFC_SIGNAL_DETECT => GND, +CH0_FFC_FB_LOOPBACK => GND, +CH1_FFC_FB_LOOPBACK => GND, +CH0_FFC_SB_PFIFO_LP => GND, +CH1_FFC_SB_PFIFO_LP => GND, +CH0_FFC_PFIFO_CLR => GND, +CH1_FFC_PFIFO_CLR => GND, +CH0_FFC_RATE_MODE_RX => GND, +CH1_FFC_RATE_MODE_RX => GND, +CH0_FFC_RATE_MODE_TX => GND, +CH1_FFC_RATE_MODE_TX => GND, +CH0_FFC_DIV11_MODE_RX => GND, +CH1_FFC_DIV11_MODE_RX => GND, +CH0_FFC_RX_GEAR_MODE => GND, +CH1_FFC_RX_GEAR_MODE => GND, +CH0_FFC_TX_GEAR_MODE => GND, +CH1_FFC_TX_GEAR_MODE => GND, +CH0_FFC_DIV11_MODE_TX => GND, +CH1_FFC_DIV11_MODE_TX => GND, +CH0_FFC_LDR_CORE2TX_EN => GND, +CH1_FFC_LDR_CORE2TX_EN => GND, +CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C, +CH1_FFC_LANE_TX_RST => GND, +CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C, +CH1_FFC_LANE_RX_RST => GND, +CH0_FFC_RRST => RSL_RX_SERDES_RST_C, +CH1_FFC_RRST => GND, +CH0_FFC_TXPWDNB => tx_pwrup_c, +CH1_FFC_TXPWDNB => GND, +CH0_FFC_RXPWDNB => rx_pwrup_c, +CH1_FFC_RXPWDNB => GND, +CH0_LDR_CORE2TX => GND, +CH1_LDR_CORE2TX => GND, +D_SCIWDATA0 => sci_wrdata(0), +D_SCIWDATA1 => sci_wrdata(1), +D_SCIWDATA2 => sci_wrdata(2), +D_SCIWDATA3 => sci_wrdata(3), +D_SCIWDATA4 => sci_wrdata(4), +D_SCIWDATA5 => sci_wrdata(5), +D_SCIWDATA6 => sci_wrdata(6), +D_SCIWDATA7 => sci_wrdata(7), +D_SCIADDR0 => sci_addr(0), +D_SCIADDR1 => sci_addr(1), +D_SCIADDR2 => sci_addr(2), +D_SCIADDR3 => sci_addr(3), +D_SCIADDR4 => sci_addr(4), +D_SCIADDR5 => sci_addr(5), +D_SCIENAUX => sci_en_dual, +D_SCISELAUX => sci_sel_dual, +CH0_SCIEN => sci_en, +CH1_SCIEN => GND, +CH0_SCISEL => sci_sel, +CH1_SCISEL => GND, +D_SCIRD => sci_rd, +D_SCIWSTN => sci_wrn, +D_CYAWSTN => cyawstn, +D_FFC_SYNC_TOGGLE => GND, +D_FFC_DUAL_RST => rst_dual_c, +D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C, +D_FFC_MACROPDB => serdes_pdb, +D_FFC_TRST => RSL_TX_SERDES_RST_C, +CH0_FFC_CDR_EN_BITSLIP => GND, +CH1_FFC_CDR_EN_BITSLIP => GND, +D_SCAN_ENABLE => GND, +D_SCAN_IN_0 => GND, +D_SCAN_IN_1 => GND, +D_SCAN_IN_2 => GND, +D_SCAN_IN_3 => GND, +D_SCAN_IN_4 => GND, +D_SCAN_IN_5 => GND, +D_SCAN_IN_6 => GND, +D_SCAN_IN_7 => GND, +D_SCAN_MODE => GND, +D_SCAN_RESET => GND, +D_CIN0 => GND, +D_CIN1 => GND, +D_CIN2 => GND, +D_CIN3 => GND, +D_CIN4 => GND, +D_CIN5 => GND, +D_CIN6 => GND, +D_CIN7 => GND, +D_CIN8 => GND, +D_CIN9 => GND, +D_CIN10 => GND, +D_CIN11 => GND, +CH0_HDOUTP => hdoutp, +CH1_HDOUTP => N47_1, +CH0_HDOUTN => hdoutn, +CH1_HDOUTN => N48_1, +D_TXBIT_CLKP_TO_ND => N1_1, +D_TXBIT_CLKN_TO_ND => N2_1, +D_SYNC_PULSE2ND => N3_1, +D_TXPLL_LOL_TO_ND => N4_1, +CH0_FF_RX_F_CLK => N5_1, +CH1_FF_RX_F_CLK => N49_1, +CH0_FF_RX_H_CLK => N6_1, +CH1_FF_RX_H_CLK => N50_1, +CH0_FF_TX_F_CLK => N7_1, +CH1_FF_TX_F_CLK => N51_1, +CH0_FF_TX_H_CLK => N8_1, +CH1_FF_TX_H_CLK => N52_1, +CH0_FF_RX_PCLK => N9_1, +CH1_FF_RX_PCLK => N53_1, +CH0_FF_TX_PCLK => TX_PCLK_I, +CH1_FF_TX_PCLK => N54_1, +CH0_FF_RX_D_0 => rxdata(0), +CH1_FF_RX_D_0 => N55_1, +CH0_FF_RX_D_1 => rxdata(1), +CH1_FF_RX_D_1 => N56_1, +CH0_FF_RX_D_2 => rxdata(2), +CH1_FF_RX_D_2 => N57_1, +CH0_FF_RX_D_3 => rxdata(3), +CH1_FF_RX_D_3 => N58_1, +CH0_FF_RX_D_4 => rxdata(4), +CH1_FF_RX_D_4 => N59_1, +CH0_FF_RX_D_5 => rxdata(5), +CH1_FF_RX_D_5 => N60_1, +CH0_FF_RX_D_6 => rxdata(6), +CH1_FF_RX_D_6 => N61_1, +CH0_FF_RX_D_7 => rxdata(7), +CH1_FF_RX_D_7 => N62_1, +CH0_FF_RX_D_8 => rx_k(0), +CH1_FF_RX_D_8 => N63_1, +CH0_FF_RX_D_9 => rx_disp_err(0), +CH1_FF_RX_D_9 => N64_1, +CH0_FF_RX_D_10 => rx_cv_err(0), +CH1_FF_RX_D_10 => N65_1, +CH0_FF_RX_D_11 => N10_1, +CH1_FF_RX_D_11 => N66_1, +CH0_FF_RX_D_12 => N67_1, +CH1_FF_RX_D_12 => N68_1, +CH0_FF_RX_D_13 => N69_1, +CH1_FF_RX_D_13 => N70_1, +CH0_FF_RX_D_14 => N71_1, +CH1_FF_RX_D_14 => N72_1, +CH0_FF_RX_D_15 => N73_1, +CH1_FF_RX_D_15 => N74_1, +CH0_FF_RX_D_16 => N75_1, +CH1_FF_RX_D_16 => N76_1, +CH0_FF_RX_D_17 => N77_1, +CH1_FF_RX_D_17 => N78_1, +CH0_FF_RX_D_18 => N79_1, +CH1_FF_RX_D_18 => N80_1, +CH0_FF_RX_D_19 => N81_1, +CH1_FF_RX_D_19 => N82_1, +CH0_FF_RX_D_20 => N83_1, +CH1_FF_RX_D_20 => N84_1, +CH0_FF_RX_D_21 => N85_1, +CH1_FF_RX_D_21 => N86_1, +CH0_FF_RX_D_22 => N87_1, +CH1_FF_RX_D_22 => N88_1, +CH0_FF_RX_D_23 => N11_1, +CH1_FF_RX_D_23 => N89_1, +CH0_FFS_PCIE_DONE => N12_1, +CH1_FFS_PCIE_DONE => N90_1, +CH0_FFS_PCIE_CON => N13_1, +CH1_FFS_PCIE_CON => N91_1, +CH0_FFS_RLOS => RX_LOS_LOW_S_12, +CH1_FFS_RLOS => N92_1, +CH0_FFS_LS_SYNC_STATUS => lsm_status_s, +CH1_FFS_LS_SYNC_STATUS => N93_1, +CH0_FFS_CC_UNDERRUN => ctc_urun_s, +CH1_FFS_CC_UNDERRUN => N94_1, +CH0_FFS_CC_OVERRUN => ctc_orun_s, +CH1_FFS_CC_OVERRUN => N95_1, +CH0_FFS_RXFBFIFO_ERROR => N14_1, +CH1_FFS_RXFBFIFO_ERROR => N96_1, +CH0_FFS_TXFBFIFO_ERROR => N15_1, +CH1_FFS_TXFBFIFO_ERROR => N97_1, +CH0_FFS_RLOL => RX_CDR_LOL_S_13, +CH1_FFS_RLOL => N98_1, +CH0_FFS_SKP_ADDED => ctc_ins_s, +CH1_FFS_SKP_ADDED => N99_1, +CH0_FFS_SKP_DELETED => ctc_del_s, +CH1_FFS_SKP_DELETED => N100_1, +CH0_LDR_RX2CORE => N101_1, +CH1_LDR_RX2CORE => N112_1, +D_SCIRDATA0 => sci_rddata(0), +D_SCIRDATA1 => sci_rddata(1), +D_SCIRDATA2 => sci_rddata(2), +D_SCIRDATA3 => sci_rddata(3), +D_SCIRDATA4 => sci_rddata(4), +D_SCIRDATA5 => sci_rddata(5), +D_SCIRDATA6 => sci_rddata(6), +D_SCIRDATA7 => sci_rddata(7), +D_SCIINT => sci_int, +D_SCAN_OUT_0 => N16_1, +D_SCAN_OUT_1 => N17_1, +D_SCAN_OUT_2 => N18_1, +D_SCAN_OUT_3 => N19_1, +D_SCAN_OUT_4 => N20_1, +D_SCAN_OUT_5 => N21_1, +D_SCAN_OUT_6 => N22_1, +D_SCAN_OUT_7 => N23_1, +D_COUT0 => N24_1, +D_COUT1 => N25_1, +D_COUT2 => N26_1, +D_COUT3 => N27_1, +D_COUT4 => N28_1, +D_COUT5 => N29_1, +D_COUT6 => N30_1, +D_COUT7 => N31_1, +D_COUT8 => N32_1, +D_COUT9 => N33_1, +D_COUT10 => N34_1, +D_COUT11 => N35_1, +D_COUT12 => N36_1, +D_COUT13 => N37_1, +D_COUT14 => N38_1, +D_COUT15 => N39_1, +D_COUT16 => N40_1, +D_COUT17 => N41_1, +D_COUT18 => N42_1, +D_COUT19 => N43_1, +D_REFCLKI => pll_refclki, +D_FFS_PLOL => N46_1); +SLL_INST: sgmii_ecp5sll_core_Z1_layer1 port map ( +tx_pclk => TX_PCLK_11, +sli_rst => sli_rst, +pll_refclki => pll_refclki, +pll_lock_i => \SLL_INST.PLL_LOCK_I_14\); +RSL_INST: sgmii_ecp5rsl_core_Z2_layer1 port map ( +rx_pcs_rst_c => rx_pcs_rst_c, +tx_pcs_rst_c => tx_pcs_rst_c, +tx_serdes_rst_c => tx_serdes_rst_c, +serdes_rst_dual_c => serdes_rst_dual_c, +rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C, +rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C, +rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C, +rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C, +rsl_tx_rdy => rsl_tx_rdy, +pll_lock_i => \SLL_INST.PLL_LOCK_I_14\, +pll_refclki => pll_refclki, +rsl_rx_rdy => rsl_rx_rdy, +rsl_rst => rsl_rst, +rxrefclk => rxrefclk, +rsl_disable => rsl_disable, +rx_serdes_rst_c => rx_serdes_rst_c, +rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C, +rst_dual_c => rst_dual_c, +rx_cdr_lol_s => RX_CDR_LOL_S_13, +rx_los_low_s => RX_LOS_LOW_S_12); +tx_pclk <= TX_PCLK_11; +rx_los_low_s <= RX_LOS_LOW_S_12; +rx_cdr_lol_s <= RX_CDR_LOL_S_13; +pll_lol <= \SLL_INST.PLL_LOCK_I_14\; +end beh; + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vm new file mode 100644 index 0000000..eff3561 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vm @@ -0,0 +1,6626 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Mon May 13 09:09:10 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v " +// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v " +// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v " +// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v " +// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v " +// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh " +// file 16 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v " +// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 18 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc " + +`timescale 100 ps/100 ps +module sync_0s ( + phb, + rhb_sync, + sli_rst, + pll_refclki +) +; +input phb ; +output rhb_sync ; +input sli_rst ; +input pll_refclki ; +wire phb ; +wire rhb_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_0 ; +wire VCC ; +wire data_p1_QN_0 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(phb), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s */ + +module sync_0s_6 ( + rtc_pul, + ppul_sync, + sli_rst, + tx_pclk +) +; +input rtc_pul ; +output ppul_sync ; +input sli_rst ; +input tx_pclk ; +wire rtc_pul ; +wire ppul_sync ; +wire sli_rst ; +wire tx_pclk ; +wire data_p1 ; +wire data_p2_QN ; +wire VCC ; +wire data_p1_QN ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(rtc_pul), + .CK(tx_pclk), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_6 */ + +module sync_0s_0 ( + ppul_sync, + pdiff_sync, + sli_rst, + pll_refclki +) +; +input ppul_sync ; +output pdiff_sync ; +input sli_rst ; +input pll_refclki ; +wire ppul_sync ; +wire pdiff_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_1 ; +wire VCC ; +wire data_p1_QN_1 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(ppul_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_0 */ + +module sgmii_ecp5sll_core_Z1_layer1 ( + tx_pclk, + sli_rst, + pll_refclki, + pll_lock_i +) +; +input tx_pclk ; +input sli_rst ; +input pll_refclki ; +output pll_lock_i ; +wire tx_pclk ; +wire sli_rst ; +wire pll_refclki ; +wire pll_lock_i ; +wire [2:0] phb_cnt; +wire [2:0] phb_cnt_i; +wire [15:0] rcount; +wire [21:0] pcount; +wire [0:0] un1_pcount_diff_i; +wire [1:0] sll_state; +wire [1:0] sll_state_QN; +wire [7:0] rhb_wait_cnt_s; +wire [7:0] rhb_wait_cnt; +wire [7:0] rhb_wait_cnt_QN; +wire [15:0] rcount_s; +wire [15:0] rcount_QN; +wire [2:0] phb_cnt_QN; +wire [2:1] phb_cnt_RNO; +wire [21:0] pcount_s; +wire [21:0] pcount_QN; +wire [21:0] pcount_diff_QN; +wire [2:2] rdiff_comp_lock; +wire [2:2] rdiff_comp_lock_QN; +wire [0:0] un1_pcount_diff; +wire [20:0] pcount_cry; +wire [0:0] pcount_cry_0_S0; +wire [21:21] pcount_s_0_COUT; +wire [21:21] pcount_s_0_S1; +wire [14:0] rcount_cry; +wire [0:0] rcount_cry_0_S0; +wire [15:15] rcount_s_0_COUT; +wire [15:15] rcount_s_0_S1; +wire [6:0] rhb_wait_cnt_cry; +wire [0:0] rhb_wait_cnt_cry_0_S0; +wire [7:7] rhb_wait_cnt_s_0_COUT; +wire [7:7] rhb_wait_cnt_s_0_S1; +wire pll_lock ; +wire rtc_ctrl4_0_a3_1 ; +wire un13_lock_20 ; +wire ppul_sync_p2 ; +wire ppul_sync_p1 ; +wire un1_pcount_diff_1_axb_20 ; +wire un13_lock_19 ; +wire un1_pcount_diff_1_axb_19 ; +wire un13_lock_18 ; +wire un1_pcount_diff_1_axb_18 ; +wire un13_lock_17 ; +wire un1_pcount_diff_1_cry_17_0_RNO ; +wire un13_lock_16 ; +wire un1_pcount_diff_1_axb_16 ; +wire un13_lock_15 ; +wire un1_pcount_diff_1_axb_15 ; +wire un13_lock_14 ; +wire un1_pcount_diff_1_axb_14 ; +wire un13_lock_13 ; +wire un1_pcount_diff_1_axb_13 ; +wire un13_lock_12 ; +wire un1_pcount_diff_1_axb_12 ; +wire un13_lock_11 ; +wire un1_pcount_diff_1_axb_11 ; +wire un13_lock_10 ; +wire un1_pcount_diff_1_axb_10 ; +wire un13_lock_9 ; +wire un1_pcount_diff_1_axb_9 ; +wire un13_lock_8 ; +wire un1_pcount_diff_1_axb_8 ; +wire un13_lock_7 ; +wire un1_pcount_diff_1_axb_7 ; +wire un13_lock_6 ; +wire un1_pcount_diff_1_axb_6 ; +wire un13_lock_5 ; +wire un1_pcount_diff_1_axb_5 ; +wire un13_lock_4 ; +wire un1_pcount_diff_1_axb_4 ; +wire un13_lock_3 ; +wire un1_pcount_diff_1_axb_3 ; +wire un13_lock_2 ; +wire un1_pcount_diff_1_axb_2 ; +wire un13_lock_1 ; +wire un1_pcount_diff_1_axb_1 ; +wire un13_lock_21 ; +wire ppul_sync_p3 ; +wire N_7 ; +wire un13_lock_0 ; +wire rtc_ctrl4 ; +wire rtc_ctrl ; +wire VCC ; +wire N_2085_0 ; +wire unlock_5 ; +wire unlock_1_sqmuxa_i ; +wire unlock ; +wire unlock_QN ; +wire N_95_i ; +wire N_97_i ; +wire rtc_pul ; +wire rtc_pul_p1 ; +wire rtc_pul_p1_QN ; +wire rtc_pul5 ; +wire rtc_pul_QN ; +wire rtc_ctrl_QN ; +wire rstat_pclk_2 ; +wire rstat_pclk ; +wire rstat_pclk_QN ; +wire rhb_sync_p1 ; +wire rhb_sync_p2 ; +wire rhb_sync_p2_QN ; +wire rhb_sync ; +wire rhb_sync_p1_QN ; +wire ppul_sync_p3_QN ; +wire ppul_sync_p2_QN ; +wire ppul_sync ; +wire ppul_sync_p1_QN ; +wire N_53_i ; +wire pll_lock_QN ; +wire phb ; +wire phb_QN ; +wire pdiff_sync ; +wire pdiff_sync_p1 ; +wire pdiff_sync_p1_QN ; +wire un1_pcount_diff_1_cry_1_0_S0 ; +wire un1_pcount_diff_1_cry_1_0_S1 ; +wire un1_pcount_diff_1_cry_3_0_S0 ; +wire un1_pcount_diff_1_cry_3_0_S1 ; +wire un1_pcount_diff_1_cry_5_0_S0 ; +wire un1_pcount_diff_1_cry_5_0_S1 ; +wire un1_pcount_diff_1_cry_7_0_S0 ; +wire un1_pcount_diff_1_cry_7_0_S1 ; +wire un1_pcount_diff_1_cry_9_0_S0 ; +wire un1_pcount_diff_1_cry_9_0_S1 ; +wire un1_pcount_diff_1_cry_11_0_S0 ; +wire un1_pcount_diff_1_cry_11_0_S1 ; +wire un1_pcount_diff_1_cry_13_0_S0 ; +wire un1_pcount_diff_1_cry_13_0_S1 ; +wire un1_pcount_diff_1_cry_15_0_S0 ; +wire un1_pcount_diff_1_cry_15_0_S1 ; +wire un1_pcount_diff_1_cry_17_0_S0 ; +wire un1_pcount_diff_1_cry_17_0_S1 ; +wire un1_pcount_diff_1_cry_19_0_S0 ; +wire un1_pcount_diff_1_cry_19_0_S1 ; +wire un1_pcount_diff_1_s_21_0_S0 ; +wire lock_5 ; +wire lock_1_sqmuxa_i ; +wire lock ; +wire lock_QN ; +wire N_98 ; +wire rtc_pul5_0_o3 ; +wire rtc_pul5_0_a3_6 ; +wire rtc_pul5_0_a3_7 ; +wire un1_rcount_1_0_a3 ; +wire rhb_wait_cnt12 ; +wire un1_rhb_wait_cnt_4 ; +wire un1_rhb_wait_cnt_5 ; +wire N_99 ; +wire rtc_ctrl4_0_a3_12_4 ; +wire rtc_ctrl4_0_a3_12_5 ; +wire rtc_ctrl4_10 ; +wire un1_rcount_1_0_a3_1 ; +wire N_6 ; +wire rtc_pul5_0_a3_5 ; +wire N_8 ; +wire un13_unlock_cry_21 ; +wire un13_lock_cry_21_i ; +wire rhb_wait_cnt_scalar ; +wire un1_pcount_diff_1_cry_0 ; +wire un1_pcount_diff_1_cry_0_0_S0 ; +wire un1_pcount_diff_1_cry_0_0_S1 ; +wire un1_pcount_diff_1_cry_2 ; +wire un1_pcount_diff_1_cry_4 ; +wire un1_pcount_diff_1_cry_6 ; +wire un1_pcount_diff_1_cry_8 ; +wire un1_pcount_diff_1_cry_10 ; +wire un1_pcount_diff_1_cry_12 ; +wire un1_pcount_diff_1_cry_14 ; +wire un1_pcount_diff_1_cry_16 ; +wire un1_pcount_diff_1_cry_18 ; +wire un1_pcount_diff_1_cry_20 ; +wire un1_pcount_diff_1_s_21_0_COUT ; +wire un1_pcount_diff_1_s_21_0_S1 ; +wire un13_lock_cry_0 ; +wire un13_lock_cry_0_0_S0 ; +wire un13_lock_cry_0_0_S1 ; +wire un13_lock_cry_2 ; +wire un13_lock_cry_1_0_S0 ; +wire un13_lock_cry_1_0_S1 ; +wire un13_lock_cry_4 ; +wire un13_lock_cry_3_0_S0 ; +wire un13_lock_cry_3_0_S1 ; +wire un13_lock_cry_6 ; +wire un13_lock_cry_5_0_S0 ; +wire un13_lock_cry_5_0_S1 ; +wire un13_lock_cry_8 ; +wire un13_lock_cry_7_0_S0 ; +wire un13_lock_cry_7_0_S1 ; +wire un13_lock_cry_10 ; +wire un13_lock_cry_9_0_S0 ; +wire un13_lock_cry_9_0_S1 ; +wire un13_lock_cry_12 ; +wire un13_lock_cry_11_0_S0 ; +wire un13_lock_cry_11_0_S1 ; +wire un13_lock_cry_14 ; +wire un13_lock_cry_13_0_S0 ; +wire un13_lock_cry_13_0_S1 ; +wire un13_lock_cry_16 ; +wire un13_lock_cry_15_0_S0 ; +wire un13_lock_cry_15_0_S1 ; +wire un13_lock_cry_18 ; +wire un13_lock_cry_17_0_S0 ; +wire un13_lock_cry_17_0_S1 ; +wire un13_lock_cry_20 ; +wire un13_lock_cry_19_0_S0 ; +wire un13_lock_cry_19_0_S1 ; +wire un13_lock_cry_21_0_COUT ; +wire un13_lock_cry_21_0_S0 ; +wire un13_unlock_cry_0 ; +wire un13_unlock_cry_0_0_S0 ; +wire un13_unlock_cry_0_0_S1 ; +wire un13_unlock_cry_2 ; +wire un13_unlock_cry_1_0_S0 ; +wire un13_unlock_cry_1_0_S1 ; +wire un13_unlock_cry_4 ; +wire un13_unlock_cry_3_0_S0 ; +wire un13_unlock_cry_3_0_S1 ; +wire un13_unlock_cry_6 ; +wire un13_unlock_cry_5_0_S0 ; +wire un13_unlock_cry_5_0_S1 ; +wire un13_unlock_cry_8 ; +wire un13_unlock_cry_7_0_S0 ; +wire un13_unlock_cry_7_0_S1 ; +wire un13_unlock_cry_10 ; +wire un13_unlock_cry_9_0_S0 ; +wire un13_unlock_cry_9_0_S1 ; +wire un13_unlock_cry_12 ; +wire un13_unlock_cry_11_0_S0 ; +wire un13_unlock_cry_11_0_S1 ; +wire un13_unlock_cry_14 ; +wire un13_unlock_cry_13_0_S0 ; +wire un13_unlock_cry_13_0_S1 ; +wire un13_unlock_cry_16 ; +wire un13_unlock_cry_15_0_S0 ; +wire un13_unlock_cry_15_0_S1 ; +wire un13_unlock_cry_18 ; +wire un13_unlock_cry_17_0_S0 ; +wire un13_unlock_cry_17_0_S1 ; +wire un13_unlock_cry_20 ; +wire un13_unlock_cry_19_0_S0 ; +wire un13_unlock_cry_19_0_S1 ; +wire un13_unlock_cry_21_0_COUT ; +wire un13_unlock_cry_21_0_S0 ; +wire N_21 ; +wire N_20 ; +wire N_19 ; +wire N_18 ; +wire N_14 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_9 ; + INV phb_RNO ( + .A(phb_cnt[2]), + .Z(phb_cnt_i[2]) +); + INV \phb_cnt_RNO[0] ( + .A(phb_cnt[0]), + .Z(phb_cnt_i[0]) +); + INV pll_lock_RNI6JK9 ( + .A(pll_lock), + .Z(pll_lock_i) +); + LUT4 rtc_ctrl4_0_a3_RNO ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(rtc_ctrl4_0_a3_1) +); +defparam rtc_ctrl4_0_a3_RNO.init=16'h2000; + LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 ( + .A(un13_lock_20), + .B(pcount[20]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_20) +); +defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_19_0_RNO ( + .A(un13_lock_19), + .B(pcount[19]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_19) +); +defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 ( + .A(un13_lock_18), + .B(pcount[18]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_18) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_cZ ( + .A(un13_lock_17), + .B(pcount[17]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_cry_17_0_RNO) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_cZ.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO_0 ( + .A(un13_lock_16), + .B(pcount[16]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_16) +); +defparam un1_pcount_diff_1_cry_15_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO ( + .A(un13_lock_15), + .B(pcount[15]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_15) +); +defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 ( + .A(un13_lock_14), + .B(pcount[14]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_14) +); +defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO ( + .A(un13_lock_13), + .B(pcount[13]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_13) +); +defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 ( + .A(un13_lock_12), + .B(pcount[12]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_12) +); +defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO ( + .A(un13_lock_11), + .B(pcount[11]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_11) +); +defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 ( + .A(un13_lock_10), + .B(pcount[10]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_10) +); +defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO ( + .A(un13_lock_9), + .B(pcount[9]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_9) +); +defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 ( + .A(un13_lock_8), + .B(pcount[8]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_8) +); +defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO ( + .A(un13_lock_7), + .B(pcount[7]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_7) +); +defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 ( + .A(un13_lock_6), + .B(pcount[6]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_6) +); +defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO ( + .A(un13_lock_5), + .B(pcount[5]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_5) +); +defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 ( + .A(un13_lock_4), + .B(pcount[4]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_4) +); +defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO ( + .A(un13_lock_3), + .B(pcount[3]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_3) +); +defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 ( + .A(un13_lock_2), + .B(pcount[2]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_2) +); +defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO ( + .A(un13_lock_1), + .B(pcount[1]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_1) +); +defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355; + LUT4 ppul_sync_p3_RNIU65C ( + .A(un13_lock_21), + .B(ppul_sync_p3), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(N_7) +); +defparam ppul_sync_p3_RNIU65C.init=16'h2F20; + LUT4 \pcount_diff_RNO[0] ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(pcount[0]), + .D(un13_lock_0), + .Z(un1_pcount_diff_i[0]) +); +defparam \pcount_diff_RNO[0] .init=16'hFD20; +// @16:1304 + LUT4 rtc_ctrl_0 ( + .A(rtc_ctrl4), + .B(rtc_ctrl), + .C(VCC), + .D(VCC), + .Z(N_2085_0) +); +defparam rtc_ctrl_0.init=16'hEEEE; +// @16:1278 + FD1P3DX unlock_reg ( + .D(unlock_5), + .SP(unlock_1_sqmuxa_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(unlock) +); +// @16:1801 + FD1S3DX \sll_state_reg[0] ( + .D(N_95_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[0]) +); +// @16:1801 + FD1S3DX \sll_state_reg[1] ( + .D(N_97_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[1]) +); +// @16:1304 + FD1S3DX rtc_pul_p1_reg ( + .D(rtc_pul), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul_p1) +); +// @16:1304 + FD1P3DX rtc_pul_reg ( + .D(rtc_pul5), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul) +); +// @16:1304 + FD1S3DX rtc_ctrl_reg ( + .D(N_2085_0), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_ctrl) +); +// @16:1350 + FD1P3DX rstat_pclk_reg ( + .D(rstat_pclk_2), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rstat_pclk) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[0] ( + .D(rhb_wait_cnt_s[0]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[0]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[1] ( + .D(rhb_wait_cnt_s[1]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[1]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[2] ( + .D(rhb_wait_cnt_s[2]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[2]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[3] ( + .D(rhb_wait_cnt_s[3]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[3]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[4] ( + .D(rhb_wait_cnt_s[4]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[4]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[5] ( + .D(rhb_wait_cnt_s[5]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[5]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[6] ( + .D(rhb_wait_cnt_s[6]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[6]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[7] ( + .D(rhb_wait_cnt_s[7]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[7]) +); +// @16:1350 + FD1S3DX rhb_sync_p2_reg ( + .D(rhb_sync_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p2) +); +// @16:1350 + FD1S3DX rhb_sync_p1_reg ( + .D(rhb_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p1) +); +// @16:1304 + FD1S3DX \rcount_reg[0] ( + .D(rcount_s[0]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[0]) +); +// @16:1304 + FD1S3DX \rcount_reg[1] ( + .D(rcount_s[1]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[1]) +); +// @16:1304 + FD1S3DX \rcount_reg[2] ( + .D(rcount_s[2]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[2]) +); +// @16:1304 + FD1S3DX \rcount_reg[3] ( + .D(rcount_s[3]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[3]) +); +// @16:1304 + FD1S3DX \rcount_reg[4] ( + .D(rcount_s[4]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[4]) +); +// @16:1304 + FD1S3DX \rcount_reg[5] ( + .D(rcount_s[5]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[5]) +); +// @16:1304 + FD1S3DX \rcount_reg[6] ( + .D(rcount_s[6]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[6]) +); +// @16:1304 + FD1S3DX \rcount_reg[7] ( + .D(rcount_s[7]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[7]) +); +// @16:1304 + FD1S3DX \rcount_reg[8] ( + .D(rcount_s[8]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[8]) +); +// @16:1304 + FD1S3DX \rcount_reg[9] ( + .D(rcount_s[9]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[9]) +); +// @16:1304 + FD1S3DX \rcount_reg[10] ( + .D(rcount_s[10]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[10]) +); +// @16:1304 + FD1S3DX \rcount_reg[11] ( + .D(rcount_s[11]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[11]) +); +// @16:1304 + FD1S3DX \rcount_reg[12] ( + .D(rcount_s[12]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[12]) +); +// @16:1304 + FD1S3DX \rcount_reg[13] ( + .D(rcount_s[13]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[13]) +); +// @16:1304 + FD1S3DX \rcount_reg[14] ( + .D(rcount_s[14]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[14]) +); +// @16:1304 + FD1S3DX \rcount_reg[15] ( + .D(rcount_s[15]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[15]) +); +// @16:1408 + FD1S3DX ppul_sync_p3_reg ( + .D(ppul_sync_p2), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p3) +); +// @16:1408 + FD1S3DX ppul_sync_p2_reg ( + .D(ppul_sync_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p2) +); +// @16:1408 + FD1S3DX ppul_sync_p1_reg ( + .D(ppul_sync), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p1) +); +// @16:1879 + FD1S3DX pll_lock_reg ( + .D(N_53_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pll_lock) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[0] ( + .D(phb_cnt_i[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[0]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[1] ( + .D(phb_cnt_RNO[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[1]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[2] ( + .D(phb_cnt_RNO[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[2]) +); +// @16:1759 + FD1S3DX phb_reg ( + .D(phb_cnt_i[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb) +); +// @16:1278 + FD1S3DX pdiff_sync_p1_reg ( + .D(pdiff_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync_p1) +); +// @16:1759 + FD1S3DX \pcount_reg[0] ( + .D(pcount_s[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[0]) +); +// @16:1759 + FD1P3BX \pcount_diff[0] ( + .D(un1_pcount_diff_i[0]), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_0) +); +// @16:1759 + FD1S3DX \pcount_reg[1] ( + .D(pcount_s[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[1]) +); +// @16:1759 + FD1P3BX \pcount_diff[1] ( + .D(un1_pcount_diff_1_cry_1_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_1) +); +// @16:1759 + FD1P3BX \pcount_diff[2] ( + .D(un1_pcount_diff_1_cry_1_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_2) +); +// @16:1759 + FD1S3DX \pcount_reg[2] ( + .D(pcount_s[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[2]) +); +// @16:1759 + FD1P3BX \pcount_diff[3] ( + .D(un1_pcount_diff_1_cry_3_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_3) +); +// @16:1759 + FD1S3DX \pcount_reg[3] ( + .D(pcount_s[3]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[3]) +); +// @16:1759 + FD1P3BX \pcount_diff[4] ( + .D(un1_pcount_diff_1_cry_3_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_4) +); +// @16:1759 + FD1S3DX \pcount_reg[4] ( + .D(pcount_s[4]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[4]) +); +// @16:1759 + FD1P3BX \pcount_diff[5] ( + .D(un1_pcount_diff_1_cry_5_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_5) +); +// @16:1759 + FD1S3DX \pcount_reg[5] ( + .D(pcount_s[5]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[5]) +); +// @16:1759 + FD1S3DX \pcount_reg[6] ( + .D(pcount_s[6]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[6]) +); +// @16:1759 + FD1P3BX \pcount_diff[6] ( + .D(un1_pcount_diff_1_cry_5_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_6) +); +// @16:1759 + FD1S3DX \pcount_reg[7] ( + .D(pcount_s[7]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[7]) +); +// @16:1759 + FD1P3BX \pcount_diff[7] ( + .D(un1_pcount_diff_1_cry_7_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_7) +); +// @16:1759 + FD1S3DX \pcount_reg[8] ( + .D(pcount_s[8]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[8]) +); +// @16:1759 + FD1P3BX \pcount_diff[8] ( + .D(un1_pcount_diff_1_cry_7_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_8) +); +// @16:1759 + FD1P3BX \pcount_diff[9] ( + .D(un1_pcount_diff_1_cry_9_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_9) +); +// @16:1759 + FD1S3DX \pcount_reg[9] ( + .D(pcount_s[9]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[9]) +); +// @16:1759 + FD1S3DX \pcount_reg[10] ( + .D(pcount_s[10]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[10]) +); +// @16:1759 + FD1P3BX \pcount_diff[10] ( + .D(un1_pcount_diff_1_cry_9_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_10) +); +// @16:1759 + FD1P3BX \pcount_diff[11] ( + .D(un1_pcount_diff_1_cry_11_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_11) +); +// @16:1759 + FD1S3DX \pcount_reg[11] ( + .D(pcount_s[11]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[11]) +); +// @16:1759 + FD1S3DX \pcount_reg[12] ( + .D(pcount_s[12]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[12]) +); +// @16:1759 + FD1P3BX \pcount_diff[12] ( + .D(un1_pcount_diff_1_cry_11_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_12) +); +// @16:1759 + FD1P3BX \pcount_diff[13] ( + .D(un1_pcount_diff_1_cry_13_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_13) +); +// @16:1759 + FD1S3DX \pcount_reg[13] ( + .D(pcount_s[13]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[13]) +); +// @16:1759 + FD1P3BX \pcount_diff[14] ( + .D(un1_pcount_diff_1_cry_13_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_14) +); +// @16:1759 + FD1S3DX \pcount_reg[14] ( + .D(pcount_s[14]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[14]) +); +// @16:1759 + FD1S3DX \pcount_reg[15] ( + .D(pcount_s[15]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[15]) +); +// @16:1759 + FD1P3BX \pcount_diff[15] ( + .D(un1_pcount_diff_1_cry_15_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_15) +); +// @16:1759 + FD1S3DX \pcount_reg[16] ( + .D(pcount_s[16]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[16]) +); +// @16:1759 + FD1P3DX \pcount_diff[16] ( + .D(un1_pcount_diff_1_cry_15_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_16) +); +// @16:1759 + FD1P3DX \pcount_diff[17] ( + .D(un1_pcount_diff_1_cry_17_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_17) +); +// @16:1759 + FD1S3DX \pcount_reg[17] ( + .D(pcount_s[17]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[17]) +); +// @16:1759 + FD1P3DX \pcount_diff[18] ( + .D(un1_pcount_diff_1_cry_17_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_18) +); +// @16:1759 + FD1S3DX \pcount_reg[18] ( + .D(pcount_s[18]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[18]) +); +// @16:1759 + FD1S3DX \pcount_reg[19] ( + .D(pcount_s[19]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[19]) +); +// @16:1759 + FD1P3DX \pcount_diff[19] ( + .D(un1_pcount_diff_1_cry_19_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_19) +); +// @16:1759 + FD1S3DX \pcount_reg[20] ( + .D(pcount_s[20]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[20]) +); +// @16:1759 + FD1P3DX \pcount_diff[20] ( + .D(un1_pcount_diff_1_cry_19_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_20) +); +// @16:1759 + FD1P3DX \pcount_diff[21] ( + .D(un1_pcount_diff_1_s_21_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_21) +); +// @16:1759 + FD1S3DX \pcount_reg[21] ( + .D(pcount_s[21]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[21]) +); +// @16:1278 + FD1P3DX lock_reg ( + .D(lock_5), + .SP(lock_1_sqmuxa_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(lock) +); +// @16:1739 + FD1S3DX \genblk5.rdiff_comp_lock[2] ( + .D(VCC), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rdiff_comp_lock[2]) +); +// @16:1801 + LUT4 \sll_state_RNO[0] ( + .A(N_98), + .B(lock), + .C(rstat_pclk), + .D(sll_state[0]), + .Z(N_95_i) +); +defparam \sll_state_RNO[0] .init=16'hE050; +// @16:1334 + LUT4 rtc_pul5_0_0 ( + .A(rtc_pul5_0_o3), + .B(rtc_pul5_0_a3_6), + .C(rtc_pul5_0_a3_7), + .D(un1_rcount_1_0_a3), + .Z(rtc_pul5) +); +defparam rtc_pul5_0_0.init=16'hFF80; +// @16:1389 + LUT4 rstat_pclk_2_iv ( + .A(rhb_wait_cnt12), + .B(rstat_pclk), + .C(un1_rhb_wait_cnt_4), + .D(un1_rhb_wait_cnt_5), + .Z(rstat_pclk_2) +); +defparam rstat_pclk_2_iv.init=16'hAEEE; +// @16:1801 + LUT4 \sll_state_RNO[1] ( + .A(N_99), + .B(rstat_pclk), + .C(sll_state[1]), + .D(unlock), + .Z(N_97_i) +); +defparam \sll_state_RNO[1] .init=16'h8088; +// @16:1328 + LUT4 rtc_ctrl4_0_a3 ( + .A(rtc_ctrl4_0_a3_1), + .B(rtc_ctrl4_0_a3_12_4), + .C(rtc_ctrl4_0_a3_12_5), + .D(rtc_ctrl4_10), + .Z(rtc_ctrl4) +); +defparam rtc_ctrl4_0_a3.init=16'h8000; +// @16:1319 + LUT4 un1_rcount_1_0_a3_cZ ( + .A(rtc_ctrl4_0_a3_12_4), + .B(rtc_ctrl4_0_a3_12_5), + .C(rtc_ctrl4_10), + .D(un1_rcount_1_0_a3_1), + .Z(un1_rcount_1_0_a3) +); +defparam un1_rcount_1_0_a3_cZ.init=16'h8000; +// @16:1278 + LUT4 lock_1_sqmuxa_i_cZ ( + .A(lock), + .B(pdiff_sync), + .C(pdiff_sync_p1), + .D(VCC), + .Z(lock_1_sqmuxa_i) +); +defparam lock_1_sqmuxa_i_cZ.init=16'h7575; +// @16:1278 + LUT4 unlock_1_sqmuxa_i_cZ ( + .A(pdiff_sync), + .B(pdiff_sync_p1), + .C(unlock), + .D(VCC), + .Z(unlock_1_sqmuxa_i) +); +defparam unlock_1_sqmuxa_i_cZ.init=16'h4F4F; +// @16:1334 + LUT4 rtc_pul5_0_o3_cZ ( + .A(N_6), + .B(rcount[1]), + .C(rcount[2]), + .D(rcount[3]), + .Z(rtc_pul5_0_o3) +); +defparam rtc_pul5_0_o3_cZ.init=16'hAAAB; +// @16:1334 + LUT4 rtc_pul5_0_a3_7_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rtc_pul5_0_a3_5), + .D(VCC), + .Z(rtc_pul5_0_a3_7) +); +defparam rtc_pul5_0_a3_7_cZ.init=16'h1010; +// @16:1801 + LUT4 \sll_state_ns_i_m4[1] ( + .A(lock), + .B(rtc_pul), + .C(rtc_pul_p1), + .D(sll_state[1]), + .Z(N_99) +); +defparam \sll_state_ns_i_m4[1] .init=16'hEF20; +// @16:1879 + LUT4 pll_lock_RNO ( + .A(sll_state[0]), + .B(sll_state[1]), + .C(VCC), + .D(VCC), + .Z(N_53_i) +); +defparam pll_lock_RNO.init=16'h8888; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[2] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(phb_cnt[2]), + .D(VCC), + .Z(phb_cnt_RNO[2]) +); +defparam \phb_cnt_RNO_cZ[2] .init=16'h7878; +// @16:1801 + LUT4 \sll_state_ns_i_o4[0] ( + .A(rtc_pul), + .B(rtc_pul_p1), + .C(sll_state[1]), + .D(VCC), + .Z(N_98) +); +defparam \sll_state_ns_i_o4[0] .init=16'hBFBF; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_10 ( + .A(rcount[1]), + .B(rcount[3]), + .C(rcount[6]), + .D(rcount[15]), + .Z(rtc_ctrl4_10) +); +defparam rtc_ctrl4_0_a3_10.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_4_cZ ( + .A(rhb_wait_cnt[4]), + .B(rhb_wait_cnt[5]), + .C(rhb_wait_cnt[6]), + .D(rhb_wait_cnt[7]), + .Z(un1_rhb_wait_cnt_4) +); +defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_5_cZ ( + .A(rhb_wait_cnt[0]), + .B(rhb_wait_cnt[1]), + .C(rhb_wait_cnt[2]), + .D(rhb_wait_cnt[3]), + .Z(un1_rhb_wait_cnt_5) +); +defparam un1_rhb_wait_cnt_5_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_4_cZ ( + .A(rcount[11]), + .B(rcount[12]), + .C(rcount[13]), + .D(rcount[14]), + .Z(rtc_ctrl4_0_a3_12_4) +); +defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_5_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rcount[9]), + .D(rcount[10]), + .Z(rtc_ctrl4_0_a3_12_5) +); +defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000; +// @16:1334 + LUT4 rtc_pul5_0_a3_5_cZ ( + .A(rcount[6]), + .B(rcount[13]), + .C(rcount[14]), + .D(rcount[15]), + .Z(rtc_pul5_0_a3_5) +); +defparam rtc_pul5_0_a3_5_cZ.init=16'h0001; +// @16:1334 + LUT4 rtc_pul5_0_a3_6_cZ ( + .A(rcount[9]), + .B(rcount[10]), + .C(rcount[11]), + .D(rcount[12]), + .Z(rtc_pul5_0_a3_6) +); +defparam rtc_pul5_0_a3_6_cZ.init=16'h0001; +// @16:1768 + LUT4 pcount10_0_o3 ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(VCC), + .D(VCC), + .Z(N_8) +); +defparam pcount10_0_o3.init=16'hDDDD; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[1] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(VCC), + .D(VCC), + .Z(phb_cnt_RNO[1]) +); +defparam \phb_cnt_RNO_cZ[1] .init=16'h6666; +// @16:1328 + LUT4 rtc_ctrl4_0_o3 ( + .A(rcount[4]), + .B(rcount[5]), + .C(VCC), + .D(VCC), + .Z(N_6) +); +defparam rtc_ctrl4_0_o3.init=16'h7777; +// @16:1286 + LUT4 unlock_5_cZ ( + .A(pdiff_sync), + .B(un13_unlock_cry_21), + .C(VCC), + .D(VCC), + .Z(unlock_5) +); +defparam unlock_5_cZ.init=16'h8888; +// @16:1292 + LUT4 lock_5_cZ ( + .A(pdiff_sync), + .B(un13_lock_cry_21_i), + .C(VCC), + .D(VCC), + .Z(lock_5) +); +defparam lock_5_cZ.init=16'h8888; +// @16:1389 + LUT4 rhb_wait_cnt12_cZ ( + .A(rhb_sync_p1), + .B(rhb_sync_p2), + .C(VCC), + .D(VCC), + .Z(rhb_wait_cnt12) +); +defparam rhb_wait_cnt12_cZ.init=16'h2222; +// @16:1786 + LUT4 \un1_pcount_diff_cZ[0] ( + .A(un13_lock_0), + .B(pcount[0]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff[0]) +); +defparam \un1_pcount_diff_cZ[0] .init=16'h5355; +// @16:1319 + LUT4 un1_rcount_1_0_a3_1_cZ ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(un1_rcount_1_0_a3_1) +); +defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000; +// @16:1350 + LUT4 rhb_sync_p2_RNIU9TG1 ( + .A(un1_rhb_wait_cnt_5), + .B(un1_rhb_wait_cnt_4), + .C(rhb_sync_p2), + .D(rhb_sync_p1), + .Z(rhb_wait_cnt_scalar) +); +defparam rhb_sync_p2_RNIU9TG1.init=16'h7077; + CCU2C \pcount_cry_0[0] ( + .A0(VCC), + .B0(N_8), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_9), + .COUT(pcount_cry[0]), + .S0(pcount_cry_0_S0[0]), + .S1(pcount_s[0]) +); +defparam \pcount_cry_0[0] .INIT0=16'h500c; +defparam \pcount_cry_0[0] .INIT1=16'h8000; +defparam \pcount_cry_0[0] .INJECT1_0="NO"; +defparam \pcount_cry_0[0] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[1] ( + .A0(N_8), + .B0(pcount[1]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[0]), + .COUT(pcount_cry[2]), + .S0(pcount_s[1]), + .S1(pcount_s[2]) +); +defparam \pcount_cry_0[1] .INIT0=16'h8000; +defparam \pcount_cry_0[1] .INIT1=16'h8000; +defparam \pcount_cry_0[1] .INJECT1_0="NO"; +defparam \pcount_cry_0[1] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[3] ( + .A0(N_8), + .B0(pcount[3]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[2]), + .COUT(pcount_cry[4]), + .S0(pcount_s[3]), + .S1(pcount_s[4]) +); +defparam \pcount_cry_0[3] .INIT0=16'h8000; +defparam \pcount_cry_0[3] .INIT1=16'h8000; +defparam \pcount_cry_0[3] .INJECT1_0="NO"; +defparam \pcount_cry_0[3] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[5] ( + .A0(N_8), + .B0(pcount[5]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[4]), + .COUT(pcount_cry[6]), + .S0(pcount_s[5]), + .S1(pcount_s[6]) +); +defparam \pcount_cry_0[5] .INIT0=16'h8000; +defparam \pcount_cry_0[5] .INIT1=16'h8000; +defparam \pcount_cry_0[5] .INJECT1_0="NO"; +defparam \pcount_cry_0[5] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[7] ( + .A0(N_8), + .B0(pcount[7]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[6]), + .COUT(pcount_cry[8]), + .S0(pcount_s[7]), + .S1(pcount_s[8]) +); +defparam \pcount_cry_0[7] .INIT0=16'h8000; +defparam \pcount_cry_0[7] .INIT1=16'h8000; +defparam \pcount_cry_0[7] .INJECT1_0="NO"; +defparam \pcount_cry_0[7] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[9] ( + .A0(N_8), + .B0(pcount[9]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[8]), + .COUT(pcount_cry[10]), + .S0(pcount_s[9]), + .S1(pcount_s[10]) +); +defparam \pcount_cry_0[9] .INIT0=16'h8000; +defparam \pcount_cry_0[9] .INIT1=16'h8000; +defparam \pcount_cry_0[9] .INJECT1_0="NO"; +defparam \pcount_cry_0[9] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[11] ( + .A0(N_8), + .B0(pcount[11]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[10]), + .COUT(pcount_cry[12]), + .S0(pcount_s[11]), + .S1(pcount_s[12]) +); +defparam \pcount_cry_0[11] .INIT0=16'h8000; +defparam \pcount_cry_0[11] .INIT1=16'h8000; +defparam \pcount_cry_0[11] .INJECT1_0="NO"; +defparam \pcount_cry_0[11] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[13] ( + .A0(N_8), + .B0(pcount[13]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[12]), + .COUT(pcount_cry[14]), + .S0(pcount_s[13]), + .S1(pcount_s[14]) +); +defparam \pcount_cry_0[13] .INIT0=16'h8000; +defparam \pcount_cry_0[13] .INIT1=16'h8000; +defparam \pcount_cry_0[13] .INJECT1_0="NO"; +defparam \pcount_cry_0[13] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[15] ( + .A0(N_8), + .B0(pcount[15]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[16]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[14]), + .COUT(pcount_cry[16]), + .S0(pcount_s[15]), + .S1(pcount_s[16]) +); +defparam \pcount_cry_0[15] .INIT0=16'h8000; +defparam \pcount_cry_0[15] .INIT1=16'h8000; +defparam \pcount_cry_0[15] .INJECT1_0="NO"; +defparam \pcount_cry_0[15] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[17] ( + .A0(N_8), + .B0(pcount[17]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[18]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[16]), + .COUT(pcount_cry[18]), + .S0(pcount_s[17]), + .S1(pcount_s[18]) +); +defparam \pcount_cry_0[17] .INIT0=16'h8000; +defparam \pcount_cry_0[17] .INIT1=16'h8000; +defparam \pcount_cry_0[17] .INJECT1_0="NO"; +defparam \pcount_cry_0[17] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[19] ( + .A0(N_8), + .B0(pcount[19]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[20]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[18]), + .COUT(pcount_cry[20]), + .S0(pcount_s[19]), + .S1(pcount_s[20]) +); +defparam \pcount_cry_0[19] .INIT0=16'h8000; +defparam \pcount_cry_0[19] .INIT1=16'h8000; +defparam \pcount_cry_0[19] .INJECT1_0="NO"; +defparam \pcount_cry_0[19] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_s_0[21] ( + .A0(N_8), + .B0(pcount[21]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[20]), + .COUT(pcount_s_0_COUT[21]), + .S0(pcount_s[21]), + .S1(pcount_s_0_S1[21]) +); +defparam \pcount_s_0[21] .INIT0=16'h800a; +defparam \pcount_s_0[21] .INIT1=16'h5003; +defparam \pcount_s_0[21] .INJECT1_0="NO"; +defparam \pcount_s_0[21] .INJECT1_1="NO"; + CCU2C \rcount_cry_0[0] ( + .A0(VCC), + .B0(un1_rcount_1_0_a3), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(rcount_cry[0]), + .S0(rcount_cry_0_S0[0]), + .S1(rcount_s[0]) +); +defparam \rcount_cry_0[0] .INIT0=16'h5003; +defparam \rcount_cry_0[0] .INIT1=16'h4000; +defparam \rcount_cry_0[0] .INJECT1_0="NO"; +defparam \rcount_cry_0[0] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[1] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[1]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[0]), + .COUT(rcount_cry[2]), + .S0(rcount_s[1]), + .S1(rcount_s[2]) +); +defparam \rcount_cry_0[1] .INIT0=16'h4000; +defparam \rcount_cry_0[1] .INIT1=16'h4000; +defparam \rcount_cry_0[1] .INJECT1_0="NO"; +defparam \rcount_cry_0[1] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[3] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[3]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[2]), + .COUT(rcount_cry[4]), + .S0(rcount_s[3]), + .S1(rcount_s[4]) +); +defparam \rcount_cry_0[3] .INIT0=16'h4000; +defparam \rcount_cry_0[3] .INIT1=16'h4000; +defparam \rcount_cry_0[3] .INJECT1_0="NO"; +defparam \rcount_cry_0[3] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[5] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[5]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[4]), + .COUT(rcount_cry[6]), + .S0(rcount_s[5]), + .S1(rcount_s[6]) +); +defparam \rcount_cry_0[5] .INIT0=16'h4000; +defparam \rcount_cry_0[5] .INIT1=16'h4000; +defparam \rcount_cry_0[5] .INJECT1_0="NO"; +defparam \rcount_cry_0[5] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[7] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[7]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[6]), + .COUT(rcount_cry[8]), + .S0(rcount_s[7]), + .S1(rcount_s[8]) +); +defparam \rcount_cry_0[7] .INIT0=16'h4000; +defparam \rcount_cry_0[7] .INIT1=16'h4000; +defparam \rcount_cry_0[7] .INJECT1_0="NO"; +defparam \rcount_cry_0[7] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[9] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[9]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[8]), + .COUT(rcount_cry[10]), + .S0(rcount_s[9]), + .S1(rcount_s[10]) +); +defparam \rcount_cry_0[9] .INIT0=16'h4000; +defparam \rcount_cry_0[9] .INIT1=16'h4000; +defparam \rcount_cry_0[9] .INJECT1_0="NO"; +defparam \rcount_cry_0[9] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[11] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[11]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[10]), + .COUT(rcount_cry[12]), + .S0(rcount_s[11]), + .S1(rcount_s[12]) +); +defparam \rcount_cry_0[11] .INIT0=16'h4000; +defparam \rcount_cry_0[11] .INIT1=16'h4000; +defparam \rcount_cry_0[11] .INJECT1_0="NO"; +defparam \rcount_cry_0[11] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[13] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[13]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[12]), + .COUT(rcount_cry[14]), + .S0(rcount_s[13]), + .S1(rcount_s[14]) +); +defparam \rcount_cry_0[13] .INIT0=16'h4000; +defparam \rcount_cry_0[13] .INIT1=16'h4000; +defparam \rcount_cry_0[13] .INJECT1_0="NO"; +defparam \rcount_cry_0[13] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_s_0[15] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[15]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[14]), + .COUT(rcount_s_0_COUT[15]), + .S0(rcount_s[15]), + .S1(rcount_s_0_S1[15]) +); +defparam \rcount_s_0[15] .INIT0=16'h4005; +defparam \rcount_s_0[15] .INIT1=16'h5003; +defparam \rcount_s_0[15] .INJECT1_0="NO"; +defparam \rcount_s_0[15] .INJECT1_1="NO"; + CCU2C \rhb_wait_cnt_cry_0[0] ( + .A0(VCC), + .B0(rhb_wait_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rhb_wait_cnt_cry[0]), + .S0(rhb_wait_cnt_cry_0_S0[0]), + .S1(rhb_wait_cnt_s[0]) +); +defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c; +defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[1] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[0]), + .COUT(rhb_wait_cnt_cry[2]), + .S0(rhb_wait_cnt_s[1]), + .S1(rhb_wait_cnt_s[2]) +); +defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[3] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[2]), + .COUT(rhb_wait_cnt_cry[4]), + .S0(rhb_wait_cnt_s[3]), + .S1(rhb_wait_cnt_s[4]) +); +defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[5] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[4]), + .COUT(rhb_wait_cnt_cry[6]), + .S0(rhb_wait_cnt_s[5]), + .S1(rhb_wait_cnt_s[6]) +); +defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_s_0[7] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[6]), + .COUT(rhb_wait_cnt_s_0_COUT[7]), + .S0(rhb_wait_cnt_s[7]), + .S1(rhb_wait_cnt_s_0_S1[7]) +); +defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a; +defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO"; + CCU2C un1_pcount_diff_1_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff[0]), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(un1_pcount_diff_1_cry_0), + .S0(un1_pcount_diff_1_cry_0_0_S0), + .S1(un1_pcount_diff_1_cry_0_0_S1) +); +defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003; +defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_1_0 ( + .A0(un1_pcount_diff_1_axb_1), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_2), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_0), + .COUT(un1_pcount_diff_1_cry_2), + .S0(un1_pcount_diff_1_cry_1_0_S0), + .S1(un1_pcount_diff_1_cry_1_0_S1) +); +defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_3_0 ( + .A0(un1_pcount_diff_1_axb_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_2), + .COUT(un1_pcount_diff_1_cry_4), + .S0(un1_pcount_diff_1_cry_3_0_S0), + .S1(un1_pcount_diff_1_cry_3_0_S1) +); +defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_5_0 ( + .A0(un1_pcount_diff_1_axb_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_4), + .COUT(un1_pcount_diff_1_cry_6), + .S0(un1_pcount_diff_1_cry_5_0_S0), + .S1(un1_pcount_diff_1_cry_5_0_S1) +); +defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_7_0 ( + .A0(un1_pcount_diff_1_axb_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_6), + .COUT(un1_pcount_diff_1_cry_8), + .S0(un1_pcount_diff_1_cry_7_0_S0), + .S1(un1_pcount_diff_1_cry_7_0_S1) +); +defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_9_0 ( + .A0(un1_pcount_diff_1_axb_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_8), + .COUT(un1_pcount_diff_1_cry_10), + .S0(un1_pcount_diff_1_cry_9_0_S0), + .S1(un1_pcount_diff_1_cry_9_0_S1) +); +defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_11_0 ( + .A0(un1_pcount_diff_1_axb_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_10), + .COUT(un1_pcount_diff_1_cry_12), + .S0(un1_pcount_diff_1_cry_11_0_S0), + .S1(un1_pcount_diff_1_cry_11_0_S1) +); +defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_13_0 ( + .A0(un1_pcount_diff_1_axb_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_12), + .COUT(un1_pcount_diff_1_cry_14), + .S0(un1_pcount_diff_1_cry_13_0_S0), + .S1(un1_pcount_diff_1_cry_13_0_S1) +); +defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_15_0 ( + .A0(un1_pcount_diff_1_axb_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_14), + .COUT(un1_pcount_diff_1_cry_16), + .S0(un1_pcount_diff_1_cry_15_0_S0), + .S1(un1_pcount_diff_1_cry_15_0_S1) +); +defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_17_0 ( + .A0(N_8), + .B0(rdiff_comp_lock[2]), + .C0(un1_pcount_diff_1_cry_17_0_RNO), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_16), + .COUT(un1_pcount_diff_1_cry_18), + .S0(un1_pcount_diff_1_cry_17_0_S0), + .S1(un1_pcount_diff_1_cry_17_0_S1) +); +defparam un1_pcount_diff_1_cry_17_0.INIT0=16'hb404; +defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_19_0 ( + .A0(un1_pcount_diff_1_axb_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_18), + .COUT(un1_pcount_diff_1_cry_20), + .S0(un1_pcount_diff_1_cry_19_0_S0), + .S1(un1_pcount_diff_1_cry_19_0_S1) +); +defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_s_21_0 ( + .A0(pcount[21]), + .B0(un13_lock_21), + .C0(N_8), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_20), + .COUT(un1_pcount_diff_1_s_21_0_COUT), + .S0(un1_pcount_diff_1_s_21_0_S0), + .S1(un1_pcount_diff_1_s_21_0_S1) +); +defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a; +defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003; +defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO"; + CCU2C un13_lock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(un13_lock_cry_0), + .S0(un13_lock_cry_0_0_S0), + .S1(un13_lock_cry_0_0_S1) +); +defparam un13_lock_cry_0_0.INIT0=16'h5003; +defparam un13_lock_cry_0_0.INIT1=16'h900a; +defparam un13_lock_cry_0_0.INJECT1_0="NO"; +defparam un13_lock_cry_0_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_0), + .COUT(un13_lock_cry_2), + .S0(un13_lock_cry_1_0_S0), + .S1(un13_lock_cry_1_0_S1) +); +defparam un13_lock_cry_1_0.INIT0=16'h900a; +defparam un13_lock_cry_1_0.INIT1=16'h900a; +defparam un13_lock_cry_1_0.INJECT1_0="NO"; +defparam un13_lock_cry_1_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_3_0 ( + .A0(un13_lock_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_2), + .COUT(un13_lock_cry_4), + .S0(un13_lock_cry_3_0_S0), + .S1(un13_lock_cry_3_0_S1) +); +defparam un13_lock_cry_3_0.INIT0=16'h500a; +defparam un13_lock_cry_3_0.INIT1=16'h500a; +defparam un13_lock_cry_3_0.INJECT1_0="NO"; +defparam un13_lock_cry_3_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_5_0 ( + .A0(un13_lock_5), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_4), + .COUT(un13_lock_cry_6), + .S0(un13_lock_cry_5_0_S0), + .S1(un13_lock_cry_5_0_S1) +); +defparam un13_lock_cry_5_0.INIT0=16'h900a; +defparam un13_lock_cry_5_0.INIT1=16'h500a; +defparam un13_lock_cry_5_0.INJECT1_0="NO"; +defparam un13_lock_cry_5_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_6), + .COUT(un13_lock_cry_8), + .S0(un13_lock_cry_7_0_S0), + .S1(un13_lock_cry_7_0_S1) +); +defparam un13_lock_cry_7_0.INIT0=16'h500a; +defparam un13_lock_cry_7_0.INIT1=16'h500a; +defparam un13_lock_cry_7_0.INJECT1_0="NO"; +defparam un13_lock_cry_7_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_8), + .COUT(un13_lock_cry_10), + .S0(un13_lock_cry_9_0_S0), + .S1(un13_lock_cry_9_0_S1) +); +defparam un13_lock_cry_9_0.INIT0=16'h500a; +defparam un13_lock_cry_9_0.INIT1=16'h500a; +defparam un13_lock_cry_9_0.INJECT1_0="NO"; +defparam un13_lock_cry_9_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_10), + .COUT(un13_lock_cry_12), + .S0(un13_lock_cry_11_0_S0), + .S1(un13_lock_cry_11_0_S1) +); +defparam un13_lock_cry_11_0.INIT0=16'h500a; +defparam un13_lock_cry_11_0.INIT1=16'h500a; +defparam un13_lock_cry_11_0.INJECT1_0="NO"; +defparam un13_lock_cry_11_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_12), + .COUT(un13_lock_cry_14), + .S0(un13_lock_cry_13_0_S0), + .S1(un13_lock_cry_13_0_S1) +); +defparam un13_lock_cry_13_0.INIT0=16'h500a; +defparam un13_lock_cry_13_0.INIT1=16'h500a; +defparam un13_lock_cry_13_0.INJECT1_0="NO"; +defparam un13_lock_cry_13_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_14), + .COUT(un13_lock_cry_16), + .S0(un13_lock_cry_15_0_S0), + .S1(un13_lock_cry_15_0_S1) +); +defparam un13_lock_cry_15_0.INIT0=16'h500a; +defparam un13_lock_cry_15_0.INIT1=16'h500a; +defparam un13_lock_cry_15_0.INJECT1_0="NO"; +defparam un13_lock_cry_15_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_16), + .COUT(un13_lock_cry_18), + .S0(un13_lock_cry_17_0_S0), + .S1(un13_lock_cry_17_0_S1) +); +defparam un13_lock_cry_17_0.INIT0=16'h500a; +defparam un13_lock_cry_17_0.INIT1=16'h500a; +defparam un13_lock_cry_17_0.INJECT1_0="NO"; +defparam un13_lock_cry_17_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_18), + .COUT(un13_lock_cry_20), + .S0(un13_lock_cry_19_0_S0), + .S1(un13_lock_cry_19_0_S1) +); +defparam un13_lock_cry_19_0.INIT0=16'h500a; +defparam un13_lock_cry_19_0.INIT1=16'h500a; +defparam un13_lock_cry_19_0.INJECT1_0="NO"; +defparam un13_lock_cry_19_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_20), + .COUT(un13_lock_cry_21_0_COUT), + .S0(un13_lock_cry_21_0_S0), + .S1(un13_lock_cry_21_i) +); +defparam un13_lock_cry_21_0.INIT0=16'h500f; +defparam un13_lock_cry_21_0.INIT1=16'ha003; +defparam un13_lock_cry_21_0.INJECT1_0="NO"; +defparam un13_lock_cry_21_0.INJECT1_1="NO"; + CCU2C un13_unlock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(un13_unlock_cry_0), + .S0(un13_unlock_cry_0_0_S0), + .S1(un13_unlock_cry_0_0_S1) +); +defparam un13_unlock_cry_0_0.INIT0=16'h5003; +defparam un13_unlock_cry_0_0.INIT1=16'h500a; +defparam un13_unlock_cry_0_0.INJECT1_0="NO"; +defparam un13_unlock_cry_0_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_0), + .COUT(un13_unlock_cry_2), + .S0(un13_unlock_cry_1_0_S0), + .S1(un13_unlock_cry_1_0_S1) +); +defparam un13_unlock_cry_1_0.INIT0=16'h900a; +defparam un13_unlock_cry_1_0.INIT1=16'h900a; +defparam un13_unlock_cry_1_0.INJECT1_0="NO"; +defparam un13_unlock_cry_1_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_3_0 ( + .A0(un13_lock_3), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_2), + .COUT(un13_unlock_cry_4), + .S0(un13_unlock_cry_3_0_S0), + .S1(un13_unlock_cry_3_0_S1) +); +defparam un13_unlock_cry_3_0.INIT0=16'h900a; +defparam un13_unlock_cry_3_0.INIT1=16'h500a; +defparam un13_unlock_cry_3_0.INJECT1_0="NO"; +defparam un13_unlock_cry_3_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_5_0 ( + .A0(un13_lock_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_4), + .COUT(un13_unlock_cry_6), + .S0(un13_unlock_cry_5_0_S0), + .S1(un13_unlock_cry_5_0_S1) +); +defparam un13_unlock_cry_5_0.INIT0=16'h500a; +defparam un13_unlock_cry_5_0.INIT1=16'h900a; +defparam un13_unlock_cry_5_0.INJECT1_0="NO"; +defparam un13_unlock_cry_5_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_6), + .COUT(un13_unlock_cry_8), + .S0(un13_unlock_cry_7_0_S0), + .S1(un13_unlock_cry_7_0_S1) +); +defparam un13_unlock_cry_7_0.INIT0=16'h500a; +defparam un13_unlock_cry_7_0.INIT1=16'h500a; +defparam un13_unlock_cry_7_0.INJECT1_0="NO"; +defparam un13_unlock_cry_7_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_8), + .COUT(un13_unlock_cry_10), + .S0(un13_unlock_cry_9_0_S0), + .S1(un13_unlock_cry_9_0_S1) +); +defparam un13_unlock_cry_9_0.INIT0=16'h500a; +defparam un13_unlock_cry_9_0.INIT1=16'h500a; +defparam un13_unlock_cry_9_0.INJECT1_0="NO"; +defparam un13_unlock_cry_9_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_10), + .COUT(un13_unlock_cry_12), + .S0(un13_unlock_cry_11_0_S0), + .S1(un13_unlock_cry_11_0_S1) +); +defparam un13_unlock_cry_11_0.INIT0=16'h500a; +defparam un13_unlock_cry_11_0.INIT1=16'h500a; +defparam un13_unlock_cry_11_0.INJECT1_0="NO"; +defparam un13_unlock_cry_11_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_12), + .COUT(un13_unlock_cry_14), + .S0(un13_unlock_cry_13_0_S0), + .S1(un13_unlock_cry_13_0_S1) +); +defparam un13_unlock_cry_13_0.INIT0=16'h500a; +defparam un13_unlock_cry_13_0.INIT1=16'h500a; +defparam un13_unlock_cry_13_0.INJECT1_0="NO"; +defparam un13_unlock_cry_13_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_14), + .COUT(un13_unlock_cry_16), + .S0(un13_unlock_cry_15_0_S0), + .S1(un13_unlock_cry_15_0_S1) +); +defparam un13_unlock_cry_15_0.INIT0=16'h500a; +defparam un13_unlock_cry_15_0.INIT1=16'h500a; +defparam un13_unlock_cry_15_0.INJECT1_0="NO"; +defparam un13_unlock_cry_15_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_16), + .COUT(un13_unlock_cry_18), + .S0(un13_unlock_cry_17_0_S0), + .S1(un13_unlock_cry_17_0_S1) +); +defparam un13_unlock_cry_17_0.INIT0=16'h500a; +defparam un13_unlock_cry_17_0.INIT1=16'h500a; +defparam un13_unlock_cry_17_0.INJECT1_0="NO"; +defparam un13_unlock_cry_17_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_18), + .COUT(un13_unlock_cry_20), + .S0(un13_unlock_cry_19_0_S0), + .S1(un13_unlock_cry_19_0_S1) +); +defparam un13_unlock_cry_19_0.INIT0=16'h500a; +defparam un13_unlock_cry_19_0.INIT1=16'h500a; +defparam un13_unlock_cry_19_0.INJECT1_0="NO"; +defparam un13_unlock_cry_19_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_20), + .COUT(un13_unlock_cry_21_0_COUT), + .S0(un13_unlock_cry_21_0_S0), + .S1(un13_unlock_cry_21) +); +defparam un13_unlock_cry_21_0.INIT0=16'h500f; +defparam un13_unlock_cry_21_0.INIT1=16'h5003; +defparam un13_unlock_cry_21_0.INJECT1_0="NO"; +defparam un13_unlock_cry_21_0.INJECT1_1="NO"; +//@16:1801 +//@8:424 +// @16:1211 + sync_0s phb_sync_inst ( + .phb(phb), + .rhb_sync(rhb_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); +// @16:1220 + sync_0s_6 rtc_sync_inst ( + .rtc_pul(rtc_pul), + .ppul_sync(ppul_sync), + .sli_rst(sli_rst), + .tx_pclk(tx_pclk) +); +// @16:1228 + sync_0s_0 pdiff_sync_inst ( + .ppul_sync(ppul_sync), + .pdiff_sync(pdiff_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sgmii_ecp5sll_core_Z1_layer1 */ + +module sgmii_ecp5rsl_core_Z2_layer1 ( + rx_pcs_rst_c, + tx_pcs_rst_c, + tx_serdes_rst_c, + serdes_rst_dual_c, + rsl_tx_pcs_rst_c, + rsl_rx_serdes_rst_c, + rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c, + rsl_tx_rdy, + pll_lock_i, + pll_refclki, + rsl_rx_rdy, + rsl_rst, + rxrefclk, + rsl_disable, + rx_serdes_rst_c, + rsl_rx_pcs_rst_c, + rst_dual_c, + rx_cdr_lol_s, + rx_los_low_s +) +; +input rx_pcs_rst_c ; +input tx_pcs_rst_c ; +input tx_serdes_rst_c ; +input serdes_rst_dual_c ; +output rsl_tx_pcs_rst_c ; +output rsl_rx_serdes_rst_c ; +output rsl_serdes_rst_dual_c ; +output rsl_tx_serdes_rst_c ; +output rsl_tx_rdy ; +input pll_lock_i ; +input pll_refclki ; +output rsl_rx_rdy ; +input rsl_rst ; +input rxrefclk ; +input rsl_disable ; +input rx_serdes_rst_c ; +output rsl_rx_pcs_rst_c ; +input rst_dual_c ; +input rx_cdr_lol_s ; +input rx_los_low_s ; +wire rx_pcs_rst_c ; +wire tx_pcs_rst_c ; +wire tx_serdes_rst_c ; +wire serdes_rst_dual_c ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire rsl_tx_rdy ; +wire pll_lock_i ; +wire pll_refclki ; +wire rsl_rx_rdy ; +wire rsl_rst ; +wire rxrefclk ; +wire rsl_disable ; +wire rx_serdes_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rst_dual_c ; +wire rx_cdr_lol_s ; +wire rx_los_low_s ; +wire [1:0] rxs_cnt; +wire [1:0] rxs_cnt_3; +wire [0:0] rxpr_appd_RNO; +wire [2:0] plol0_cnt; +wire [2:0] plol0_cnt_3; +wire [0:0] rxsr_appd; +wire [1:0] rxs_cnt_QN; +wire [3:0] rlos_db_cnt; +wire [3:0] rlos_db_cnt_QN; +wire [17:0] rlols0_cnt_s; +wire [17:0] rlols0_cnt; +wire [17:0] rlols0_cnt_QN; +wire [3:0] rlol_db_cnt; +wire [3:0] rlol_db_cnt_QN; +wire [18:0] rlol1_cnt_s; +wire [18:0] rlol1_cnt; +wire [18:0] rlol1_cnt_QN; +wire [11:0] rxr_wt_cnt_s; +wire [11:0] rxr_wt_cnt; +wire [11:0] rxr_wt_cnt_QN; +wire [0:0] rxsr_appd_QN; +wire [0:0] rxpr_appd; +wire [0:0] rxpr_appd_QN; +wire [1:0] txs_cnt; +wire [1:0] txs_cnt_QN; +wire [1:1] txs_cnt_RNO; +wire [1:0] txp_cnt; +wire [1:0] txp_cnt_QN; +wire [1:1] txp_cnt_RNO; +wire [19:0] plol_cnt_s; +wire [19:0] plol_cnt; +wire [19:0] plol_cnt_QN; +wire [2:0] plol0_cnt_QN; +wire [11:0] txr_wt_cnt_s; +wire [11:0] txr_wt_cnt; +wire [11:0] txr_wt_cnt_QN; +wire [0:0] txpr_appd; +wire [0:0] txpr_appd_QN; +wire [0:0] un1_rlol_db_cnt_zero; +wire [0:0] un1_rlos_db_cnt_zero; +wire [0:0] un1_rlol_db_cnt_zero_bm; +wire [0:0] un1_rlol_db_cnt_zero_am; +wire [0:0] un1_rlos_db_cnt_zero_bm; +wire [0:0] un1_rlos_db_cnt_zero_am; +wire [16:0] rlol1_cnt_cry; +wire [0:0] rlol1_cnt_cry_0_S0; +wire [17:17] rlol1_cnt_cry_0_COUT; +wire [16:0] rlols0_cnt_cry; +wire [0:0] rlols0_cnt_cry_0_S0; +wire [17:17] rlols0_cnt_s_0_COUT; +wire [17:17] rlols0_cnt_s_0_S1; +wire [10:0] txr_wt_cnt_cry; +wire [0:0] txr_wt_cnt_cry_0_S0; +wire [11:11] txr_wt_cnt_s_0_COUT; +wire [11:11] txr_wt_cnt_s_0_S1; +wire [10:0] rxr_wt_cnt_cry; +wire [0:0] rxr_wt_cnt_cry_0_S0; +wire [11:11] rxr_wt_cnt_s_0_COUT; +wire [11:11] rxr_wt_cnt_s_0_S1; +wire [18:0] plol_cnt_cry; +wire [0:0] plol_cnt_cry_0_S0; +wire [19:19] plol_cnt_s_0_COUT; +wire [19:19] plol_cnt_s_0_S1; +wire rxs_rst ; +wire VCC ; +wire dual_or_rserd_rst ; +wire plol0_cnt9 ; +wire waita_plol0 ; +wire rlos_db_p1 ; +wire rlos_db ; +wire rxp_rst25 ; +wire rlol_db ; +wire un1_rui_rst_dual_c_1_1 ; +wire rx_all_well ; +wire un3_rx_all_well_2 ; +wire un17_rxr_wt_tc ; +wire un3_rx_all_well_1 ; +wire rx_any_rst ; +wire rxr_wt_cnt9 ; +wire un1_rui_rst_dual_c_1_i ; +wire rlol1_cnt_tc_1 ; +wire rlol1_cnt_scalar ; +wire rxr_wt_en ; +wire rxr_wt_cnte ; +wire rlols0_cnt_tc_1 ; +wire un2_rlos_redge_1_i ; +wire un18_txr_wt_tc ; +wire tx_any_rst ; +wire pll_lol_p2 ; +wire un2_plol_fedge_5_i ; +wire N_2124_0 ; +wire waita_rlols06 ; +wire un1_rlols0_cnt_tc ; +wire waita_rlols0 ; +wire waita_rlols0_QN ; +wire wait_calib_RNO ; +wire un1_rlos_fedge_1 ; +wire wait_calib ; +wire wait_calib_QN ; +wire rxs_rst6 ; +wire un1_rxs_cnt_tc ; +wire rxs_rst_QN ; +wire rxp_rst2 ; +wire rxp_rst2_QN ; +wire rlos_p1 ; +wire rlos_p2 ; +wire rlos_p2_QN ; +wire rlos_p1_QN ; +wire rlos_db_p1_QN ; +wire rlos_db_cnt_axb_0 ; +wire rlos_db_cnt_cry_1_0_S0 ; +wire rlos_db_cnt_cry_1_0_S1 ; +wire rlos_db_cnt_s_3_0_S0 ; +wire un1_rlos_db_cnt_max ; +wire rlos_db_QN ; +wire rlols0_cnte ; +wire rlol_p1 ; +wire rlol_p2 ; +wire rlol_p2_QN ; +wire rlol_p1_QN ; +wire rlol_db_p1 ; +wire rlol_db_p1_QN ; +wire rlol_db_cnt_axb_0 ; +wire rlol_db_cnt_cry_1_0_S0 ; +wire rlol_db_cnt_cry_1_0_S1 ; +wire rlol_db_cnt_s_3_0_S0 ; +wire un1_rlol_db_cnt_max ; +wire rlol_db_QN ; +wire rlol1_cnte ; +wire rxsdr_appd_2 ; +wire rxsdr_appd_4 ; +wire rxsdr_appd_QN ; +wire un1_dual_or_rserd_rst_2_i ; +wire rxr_wt_en_QN ; +wire rxdpr_appd ; +wire rxdpr_appd_QN ; +wire ruo_rx_rdyr_QN ; +wire un2_rdo_serdes_rst_dual_c_2_i ; +wire plol_fedge ; +wire un1_plol0_cnt_tc_1_i ; +wire waita_plol0_QN ; +wire un1_plol_cnt_tc ; +wire un2_plol_cnt_tc ; +wire txs_rst ; +wire txs_rst_QN ; +wire N_10_i ; +wire un9_plol0_cnt_tc ; +wire un1_plol0_cnt_tc_1 ; +wire txp_rst ; +wire txp_rst_QN ; +wire N_11_i ; +wire pll_lol_p3 ; +wire pll_lol_p3_QN ; +wire pll_lol_p1 ; +wire pll_lol_p2_QN ; +wire pll_lol_p1_QN ; +wire txsr_appd_2 ; +wire txsr_appd_4 ; +wire txsr_appd_QN ; +wire un1_dual_or_serd_rst_1_1 ; +wire un1_dual_or_serd_rst_1_i ; +wire txr_wt_en ; +wire txr_wt_en_QN ; +wire txr_wt_cnte ; +wire un2_plol_fedge_2 ; +wire un2_plol_fedge_3_i ; +wire txdpr_appd ; +wire txdpr_appd_QN ; +wire un2_plol_fedge_5_1 ; +wire ruo_tx_rdyr_QN ; +wire un2_plol_fedge_8_i ; +wire rlos_redge ; +wire rlols0_cnt11_0 ; +wire plol_cnt_scalar ; +wire rlols0_cnt_scalar ; +wire un8_rxs_cnt_tc ; +wire un1_txsr_appd ; +wire un3_rx_all_well_2_1 ; +wire un1_rxsdr_or_sr_appd ; +wire un2_rdo_serdes_rst_dual_c_1_1 ; +wire rlols0_cnt_tc_1_10 ; +wire rlols0_cnt_tc_1_11 ; +wire rlols0_cnt_tc_1_12 ; +wire rlols0_cnt_tc_1_13 ; +wire un1_plol_cnt_tc_11 ; +wire un1_plol_cnt_tc_12 ; +wire un1_plol_cnt_tc_13 ; +wire un1_plol_cnt_tc_14 ; +wire rlol1_cnt_tc_1_11 ; +wire rlol1_cnt_tc_1_12 ; +wire rlol1_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_14 ; +wire CO0_2 ; +wire un18_txr_wt_tc_6 ; +wire un18_txr_wt_tc_7 ; +wire un18_txr_wt_tc_8 ; +wire un17_rxr_wt_tc_6 ; +wire un17_rxr_wt_tc_7 ; +wire un17_rxr_wt_tc_8 ; +wire rlols0_cnt_tc_1_9 ; +wire un1_plol_cnt_tc_10 ; +wire rlol1_cnt_tc_1_10 ; +wire txr_wt_cnt_scalar ; +wire rlos_db_cnt_cry_0 ; +wire rlos_db_cnt_cry_0_0_S0 ; +wire rlos_db_cnt_cry_0_0_S1 ; +wire rlos_db_cnt_cry_2 ; +wire rlos_db_cnt_s_3_0_COUT ; +wire rlos_db_cnt_s_3_0_S1 ; +wire rlol_db_cnt_cry_0 ; +wire rlol_db_cnt_cry_0_0_S0 ; +wire rlol_db_cnt_cry_0_0_S1 ; +wire rlol_db_cnt_cry_2 ; +wire rlol_db_cnt_s_3_0_COUT ; +wire rlol_db_cnt_s_3_0_S1 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_6 ; +wire N_7 ; + LUT4 \genblk2.rxs_cnt_RNO[0] ( + .A(rxs_rst), + .B(rxs_cnt[0]), + .C(rxs_cnt[1]), + .D(VCC), + .Z(rxs_cnt_3[0]) +); +defparam \genblk2.rxs_cnt_RNO[0] .init=16'h2626; + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] ( + .A(dual_or_rserd_rst), + .B(rx_los_low_s), + .C(rx_cdr_lol_s), + .D(VCC), + .Z(rxpr_appd_RNO[0]) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'h0101; + LUT4 \genblk1.plol0_cnt_RNO[1] ( + .A(plol0_cnt[1]), + .B(plol0_cnt9), + .C(waita_plol0), + .D(plol0_cnt[0]), + .Z(plol0_cnt_3[1]) +); +defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222; + LUT4 \genblk2.rxp_rst2_RNO ( + .A(dual_or_rserd_rst), + .B(rlos_db_p1), + .C(rlos_db), + .D(VCC), + .Z(rxp_rst25) +); +defparam \genblk2.rxp_rst2_RNO .init=16'hBABA; + LUT4 \genblk2.genblk3.rxdpr_appd_RNO ( + .A(dual_or_rserd_rst), + .B(rlos_db), + .C(rlol_db), + .D(VCC), + .Z(un1_rui_rst_dual_c_1_1) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'h0101; + LUT4 \genblk2.genblk3.ruo_rx_rdyr_RNO ( + .A(rx_all_well), + .B(rst_dual_c), + .C(rsl_rx_pcs_rst_c), + .D(dual_or_rserd_rst), + .Z(un3_rx_all_well_2) +); +defparam \genblk2.genblk3.ruo_rx_rdyr_RNO .init=16'h0002; + LUT4 \genblk2.genblk3.rxr_wt_en_RNO ( + .A(un17_rxr_wt_tc), + .B(rx_all_well), + .C(dual_or_rserd_rst), + .D(VCC), + .Z(un3_rx_all_well_1) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h0404; + LUT4 rx_any_rst_RNIFD021 ( + .A(rx_any_rst), + .B(un17_rxr_wt_tc), + .C(rlos_db), + .D(rlol_db), + .Z(rxr_wt_cnt9) +); +defparam rx_any_rst_RNIFD021.init=16'hFFFE; + LUT4 \genblk2.genblk3.rxdpr_appd_RNO_0 ( + .A(rst_dual_c), + .B(rx_all_well), + .C(dual_or_rserd_rst), + .D(VCC), + .Z(un1_rui_rst_dual_c_1_i) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO_0 .init=16'hFBFB; + LUT4 \genblk2.rxs_rst_RNIS0OP ( + .A(rlol1_cnt_tc_1), + .B(rxs_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlol1_cnt_scalar) +); +defparam \genblk2.rxs_rst_RNIS0OP .init=16'h1011; + LUT4 \genblk2.genblk3.rxr_wt_en_RNIQF0H1 ( + .A(rxr_wt_en), + .B(rx_any_rst), + .C(rx_all_well), + .D(un17_rxr_wt_tc), + .Z(rxr_wt_cnte) +); +defparam \genblk2.genblk3.rxr_wt_en_RNIQF0H1 .init=16'hFFEF; + LUT4 \genblk2.rxp_rst2_RNO_0 ( + .A(rlols0_cnt_tc_1), + .B(dual_or_rserd_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(un2_rlos_redge_1_i) +); +defparam \genblk2.rxp_rst2_RNO_0 .init=16'hEFEE; + LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO ( + .A(un18_txr_wt_tc), + .B(tx_any_rst), + .C(pll_lol_p2), + .D(VCC), + .Z(un2_plol_fedge_5_i) +); +defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hFEFE; + LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] ( + .A(rxsr_appd[0]), + .B(rx_serdes_rst_c), + .C(rxs_rst), + .D(rsl_disable), + .Z(N_2124_0) +); +defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE; +// @16:759 + FD1P3DX \genblk2.waita_rlols0 ( + .D(waita_rlols06), + .SP(un1_rlols0_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(waita_rlols0) +); +// @16:656 + FD1P3BX \genblk2.wait_calib ( + .D(wait_calib_RNO), + .SP(un1_rlos_fedge_1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(wait_calib) +); +// @16:694 + FD1P3DX \genblk2.rxs_rst ( + .D(rxs_rst6), + .SP(un1_rxs_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_rst) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[0] ( + .D(rxs_cnt_3[0]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[0]) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[1] ( + .D(rxs_cnt_3[1]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[1]) +); +// @16:806 + FD1P3BX \genblk2.rxp_rst2 ( + .D(rxp_rst25), + .SP(un2_rlos_redge_1_i), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxp_rst2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p2 ( + .D(rlos_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p1 ( + .D(rx_los_low_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p1) +); +// @16:567 + FD1S3BX \genblk2.rlos_db_p1 ( + .D(rlos_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_p1) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[0] ( + .D(rlos_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[0]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[1] ( + .D(rlos_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[1]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[2] ( + .D(rlos_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[2]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[3] ( + .D(rlos_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[3]) +); +// @16:649 + FD1P3BX \genblk2.rlos_db ( + .D(rlos_db_cnt[1]), + .SP(un1_rlos_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[0] ( + .D(rlols0_cnt_s[0]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[0]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[1] ( + .D(rlols0_cnt_s[1]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[1]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[2] ( + .D(rlols0_cnt_s[2]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[2]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[3] ( + .D(rlols0_cnt_s[3]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[3]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[4] ( + .D(rlols0_cnt_s[4]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[4]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[5] ( + .D(rlols0_cnt_s[5]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[5]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[6] ( + .D(rlols0_cnt_s[6]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[6]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[7] ( + .D(rlols0_cnt_s[7]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[7]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[8] ( + .D(rlols0_cnt_s[8]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[8]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[9] ( + .D(rlols0_cnt_s[9]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[9]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[10] ( + .D(rlols0_cnt_s[10]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[10]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[11] ( + .D(rlols0_cnt_s[11]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[11]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[12] ( + .D(rlols0_cnt_s[12]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[12]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[13] ( + .D(rlols0_cnt_s[13]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[13]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[14] ( + .D(rlols0_cnt_s[14]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[14]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[15] ( + .D(rlols0_cnt_s[15]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[15]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[16] ( + .D(rlols0_cnt_s[16]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[16]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[17] ( + .D(rlols0_cnt_s[17]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[17]) +); +// @16:567 + FD1S3DX \genblk2.rlol_p2 ( + .D(rlol_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p2) +); +// @16:567 + FD1S3DX \genblk2.rlol_p1 ( + .D(rx_cdr_lol_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p1) +); +// @16:567 + FD1S3BX \genblk2.rlol_db_p1 ( + .D(rlol_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_p1) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[0] ( + .D(rlol_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[0]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[1] ( + .D(rlol_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[1]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[2] ( + .D(rlol_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[2]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[3] ( + .D(rlol_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[3]) +); +// @16:633 + FD1P3BX \genblk2.rlol_db ( + .D(rlol_db_cnt[1]), + .SP(un1_rlol_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[0] ( + .D(rlol1_cnt_s[0]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[0]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[1] ( + .D(rlol1_cnt_s[1]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[1]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[2] ( + .D(rlol1_cnt_s[2]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[2]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[3] ( + .D(rlol1_cnt_s[3]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[3]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[4] ( + .D(rlol1_cnt_s[4]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[4]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[5] ( + .D(rlol1_cnt_s[5]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[5]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[6] ( + .D(rlol1_cnt_s[6]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[6]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[7] ( + .D(rlol1_cnt_s[7]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[7]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[8] ( + .D(rlol1_cnt_s[8]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[8]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[9] ( + .D(rlol1_cnt_s[9]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[9]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[10] ( + .D(rlol1_cnt_s[10]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[10]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[11] ( + .D(rlol1_cnt_s[11]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[11]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[12] ( + .D(rlol1_cnt_s[12]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[12]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[13] ( + .D(rlol1_cnt_s[13]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[13]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[14] ( + .D(rlol1_cnt_s[14]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[14]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[15] ( + .D(rlol1_cnt_s[15]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[15]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[16] ( + .D(rlol1_cnt_s[16]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[16]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[17] ( + .D(rlol1_cnt_s[17]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[17]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[18] ( + .D(rlol1_cnt_s[18]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[18]) +); +// @16:865 + FD1S3BX \genblk2.genblk3.rxsdr_appd ( + .D(rxsdr_appd_2), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxsdr_appd_4) +); +// @16:900 + FD1P3DX \genblk2.genblk3.rxr_wt_en ( + .D(un3_rx_all_well_1), + .SP(un1_dual_or_rserd_rst_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_en) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0] ( + .D(rxr_wt_cnt_s[0]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[0]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1] ( + .D(rxr_wt_cnt_s[1]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[1]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2] ( + .D(rxr_wt_cnt_s[2]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[2]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3] ( + .D(rxr_wt_cnt_s[3]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[3]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4] ( + .D(rxr_wt_cnt_s[4]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[4]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5] ( + .D(rxr_wt_cnt_s[5]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[5]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6] ( + .D(rxr_wt_cnt_s[6]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[6]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7] ( + .D(rxr_wt_cnt_s[7]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[7]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8] ( + .D(rxr_wt_cnt_s[8]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[8]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9] ( + .D(rxr_wt_cnt_s[9]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[9]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10] ( + .D(rxr_wt_cnt_s[10]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[10]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11] ( + .D(rxr_wt_cnt_s[11]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[11]) +); +// @16:871 + FD1P3DX \genblk2.genblk3.rxdpr_appd ( + .D(un1_rui_rst_dual_c_1_1), + .SP(un1_rui_rst_dual_c_1_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxdpr_appd) +); +// @16:920 + FD1P3DX \genblk2.genblk3.ruo_rx_rdyr ( + .D(un3_rx_all_well_2), + .SP(rxr_wt_cnt9), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rsl_rx_rdy) +); +// @16:882 + FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0] ( + .D(N_2124_0), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxsr_appd[0]) +); +// @16:888 + FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0] ( + .D(rxpr_appd_RNO[0]), + .SP(un2_rdo_serdes_rst_dual_c_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxpr_appd[0]) +); +// @16:443 + FD1P3DX \genblk1.waita_plol0 ( + .D(plol_fedge), + .SP(un1_plol0_cnt_tc_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(waita_plol0) +); +// @16:422 + FD1P3DX \genblk1.txs_rst ( + .D(un1_plol_cnt_tc), + .SP(un2_plol_cnt_tc), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_rst) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[0] ( + .D(N_10_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[0]) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[1] ( + .D(txs_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[1]) +); +// @16:461 + FD1P3DX \genblk1.txp_rst ( + .D(un9_plol0_cnt_tc), + .SP(un1_plol0_cnt_tc_1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_rst) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[0] ( + .D(N_11_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[0]) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[1] ( + .D(txp_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[0] ( + .D(plol_cnt_s[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[0]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[1] ( + .D(plol_cnt_s[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[2] ( + .D(plol_cnt_s[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[2]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[3] ( + .D(plol_cnt_s[3]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[3]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[4] ( + .D(plol_cnt_s[4]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[4]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[5] ( + .D(plol_cnt_s[5]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[5]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[6] ( + .D(plol_cnt_s[6]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[6]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[7] ( + .D(plol_cnt_s[7]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[7]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[8] ( + .D(plol_cnt_s[8]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[8]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[9] ( + .D(plol_cnt_s[9]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[9]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[10] ( + .D(plol_cnt_s[10]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[10]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[11] ( + .D(plol_cnt_s[11]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[11]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[12] ( + .D(plol_cnt_s[12]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[12]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[13] ( + .D(plol_cnt_s[13]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[13]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[14] ( + .D(plol_cnt_s[14]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[14]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[15] ( + .D(plol_cnt_s[15]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[15]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[16] ( + .D(plol_cnt_s[16]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[16]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[17] ( + .D(plol_cnt_s[17]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[17]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[18] ( + .D(plol_cnt_s[18]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[18]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[19] ( + .D(plol_cnt_s[19]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[19]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[0] ( + .D(plol0_cnt_3[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[0]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[1] ( + .D(plol0_cnt_3[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[1]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[2] ( + .D(plol0_cnt_3[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[2]) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p3 ( + .D(pll_lol_p2), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p3) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p2 ( + .D(pll_lol_p1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p2) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p1 ( + .D(pll_lock_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p1) +); +// @16:492 + FD1S3BX \genblk1.genblk2.txsr_appd ( + .D(txsr_appd_2), + .CK(pll_refclki), + .PD(rsl_rst), + .Q(txsr_appd_4) +); +// @16:519 + FD1P3DX \genblk1.genblk2.txr_wt_en ( + .D(un1_dual_or_serd_rst_1_1), + .SP(un1_dual_or_serd_rst_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_en) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[0] ( + .D(txr_wt_cnt_s[0]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[0]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[1] ( + .D(txr_wt_cnt_s[1]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[1]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[2] ( + .D(txr_wt_cnt_s[2]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[2]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[3] ( + .D(txr_wt_cnt_s[3]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[3]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[4] ( + .D(txr_wt_cnt_s[4]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[4]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[5] ( + .D(txr_wt_cnt_s[5]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[5]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[6] ( + .D(txr_wt_cnt_s[6]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[6]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[7] ( + .D(txr_wt_cnt_s[7]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[7]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[8] ( + .D(txr_wt_cnt_s[8]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[8]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[9] ( + .D(txr_wt_cnt_s[9]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[9]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[10] ( + .D(txr_wt_cnt_s[10]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[10]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[11] ( + .D(txr_wt_cnt_s[11]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[11]) +); +// @16:498 + FD1P3DX \genblk1.genblk2.txdpr_appd ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_3_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txdpr_appd) +); +// @16:537 + FD1P3DX \genblk1.genblk2.ruo_tx_rdyr ( + .D(un2_plol_fedge_5_1), + .SP(un2_plol_fedge_5_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(rsl_tx_rdy) +); +// @16:509 + FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0] ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_8_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txpr_appd[0]) +); +// @16:422 + LUT4 \genblk1.txs_cnt_RNO[0] ( + .A(txs_cnt[0]), + .B(txs_rst), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(N_10_i) +); +defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6; +// @16:434 + LUT4 \genblk1.txs_cnt_RNO[1] ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(txs_rst), + .D(un1_plol_cnt_tc), + .Z(txs_cnt_RNO[1]) +); +defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C; +// @16:519 + LUT4 \genblk1.genblk2.txr_wt_en_RNO ( + .A(txpr_appd[0]), + .B(pll_lol_p2), + .C(un1_dual_or_serd_rst_1_1), + .D(rsl_tx_rdy), + .Z(un1_dual_or_serd_rst_1_i) +); +defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F; +// @16:317 + LUT4 \genblk2.rxs_rst6 ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(rxs_rst6) +); +defparam \genblk2.rxs_rst6 .init=16'h2020; +// @8:394 + LUT4 \genblk2.wait_calib_RNIKRP81 ( + .A(rxs_rst), + .B(wait_calib), + .C(rlol1_cnt_tc_1), + .D(rlos_redge), + .Z(rlol1_cnte) +); +defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE; +// @8:394 + LUT4 \genblk2.waita_rlols0_RNI266C ( + .A(rlols0_cnt11_0), + .B(waita_rlols0), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(rlols0_cnte) +); +defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE; +// @16:412 + LUT4 \genblk1.plol_cnt11_i ( + .A(pll_lol_p2), + .B(un1_plol_cnt_tc), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(plol_cnt_scalar) +); +defparam \genblk1.plol_cnt11_i .init=16'h0202; +// @16:778 + LUT4 \genblk2.rlols0_cnt11_i ( + .A(rlols0_cnt11_0), + .B(rlols0_cnt_tc_1), + .C(VCC), + .D(VCC), + .Z(rlols0_cnt_scalar) +); +defparam \genblk2.rlols0_cnt11_i .init=16'h1111; +// @16:317 + LUT4 \genblk2.un1_rxs_cnt_tc ( + .A(rlol_db), + .B(rlos_db), + .C(un8_rxs_cnt_tc), + .D(rlol1_cnt_tc_1), + .Z(un1_rxs_cnt_tc) +); +defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC; +// @8:394 + LUT4 \genblk2.wait_calib_RNO ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(wait_calib_RNO) +); +defparam \genblk2.wait_calib_RNO .init=16'hA3A3; +// @16:509 + LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] ( + .A(un1_txsr_appd), + .B(pll_lol_p2), + .C(rsl_serdes_rst_dual_c), + .D(rsl_tx_serdes_rst_c), + .Z(un2_plol_fedge_8_i) +); +defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFFFE; +// @16:900 + LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0 ( + .A(dual_or_rserd_rst), + .B(un3_rx_all_well_2_1), + .C(un17_rxr_wt_tc), + .D(rx_all_well), + .Z(un1_dual_or_rserd_rst_2_i) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFEFF; +// @16:888 + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] ( + .A(un1_rxsdr_or_sr_appd), + .B(un2_rdo_serdes_rst_dual_c_1_1), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un2_rdo_serdes_rst_dual_c_2_i) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] .init=16'hFFFB; +// @16:259 + LUT4 \genblk1.un2_plol_cnt_tc ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(un2_plol_cnt_tc) +); +defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8; +// @8:394 + LUT4 \genblk1.genblk2.txr_wt_en_RNICEBT ( + .A(txr_wt_en), + .B(un18_txr_wt_tc), + .C(tx_any_rst), + .D(VCC), + .Z(txr_wt_cnte) +); +defparam \genblk1.genblk2.txr_wt_en_RNICEBT .init=16'hFEFE; +// @16:322 + LUT4 \genblk2.un1_rlos_fedge_1 ( + .A(rlos_db), + .B(rlos_db_p1), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(un1_rlos_fedge_1) +); +defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6; +// @16:340 + LUT4 \genblk2.un1_rlols0_cnt_tc ( + .A(rlols0_cnt11_0), + .B(waita_rlols06), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(un1_rlols0_cnt_tc) +); +defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE; +// @16:498 + LUT4 \genblk1.genblk2.txdpr_appd_RNO ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(rst_dual_c), + .Z(un2_plol_fedge_3_i) +); +defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFFFE; +// @16:461 + LUT4 \genblk1.txp_cnt_RNO[0] ( + .A(txp_cnt[0]), + .B(txp_rst), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(N_11_i) +); +defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6; +// @16:282 + LUT4 un2_plol_fedge_5_1_cZ ( + .A(pll_lol_p2), + .B(tx_any_rst), + .C(VCC), + .D(VCC), + .Z(un2_plol_fedge_5_1) +); +defparam un2_plol_fedge_5_1_cZ.init=16'h1111; +// @16:522 + LUT4 un1_dual_or_serd_rst_1_1_cZ ( + .A(un18_txr_wt_tc), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un1_dual_or_serd_rst_1_1) +); +defparam un1_dual_or_serd_rst_1_1_cZ.init=16'h0101; +// @16:473 + LUT4 \genblk1.txp_cnt_RNO[1] ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(txp_rst), + .D(un9_plol0_cnt_tc), + .Z(txp_cnt_RNO[1]) +); +defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C; +// @16:388 + LUT4 rlols0_cnt_tc_1_cZ ( + .A(rlols0_cnt_tc_1_10), + .B(rlols0_cnt_tc_1_11), + .C(rlols0_cnt_tc_1_12), + .D(rlols0_cnt_tc_1_13), + .Z(rlols0_cnt_tc_1) +); +defparam rlols0_cnt_tc_1_cZ.init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc ( + .A(un1_plol_cnt_tc_11), + .B(un1_plol_cnt_tc_12), + .C(un1_plol_cnt_tc_13), + .D(un1_plol_cnt_tc_14), + .Z(un1_plol_cnt_tc) +); +defparam \genblk1.un1_plol_cnt_tc .init=16'h8000; +// @16:387 + LUT4 rlol1_cnt_tc_1_cZ ( + .A(rlol1_cnt_tc_1_11), + .B(rlol1_cnt_tc_1_12), + .C(rlol1_cnt_tc_1_13), + .D(rlol1_cnt_tc_1_14), + .Z(rlol1_cnt_tc_1) +); +defparam rlol1_cnt_tc_1_cZ.init=16'h8000; +// @16:625 + LUT4 \un1_genblk2.rlol_db_cnt_axb_0 ( + .A(rlol_db_cnt[0]), + .B(un1_rlol_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlol_db_cnt_axb_0) +); +defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999; +// @16:641 + LUT4 \un1_genblk2.rlos_db_cnt_axb_0 ( + .A(rlos_db_cnt[0]), + .B(un1_rlos_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlos_db_cnt_axb_0) +); +defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999; +// @16:443 + LUT4 \genblk1.waita_plol0_RNO ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1_i) +); +defparam \genblk1.waita_plol0_RNO .init=16'hF6F6; +// @16:514 + LUT4 \genblk1.genblk2.mfor[0].un1_txsr_appd ( + .A(txdpr_appd), + .B(txsr_appd_4), + .C(rsl_tx_pcs_rst_c), + .D(VCC), + .Z(un1_txsr_appd) +); +defparam \genblk1.genblk2.mfor[0].un1_txsr_appd .init=16'hC8C8; +// @16:493 + LUT4 \genblk1.genblk2.txsr_appd_2 ( + .A(txsr_appd_4), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(txsr_appd_2) +); +defparam \genblk1.genblk2.txsr_appd_2 .init=16'hFEFE; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[0] ( + .A(plol0_cnt9), + .B(plol0_cnt[0]), + .C(waita_plol0), + .D(VCC), + .Z(plol0_cnt_3[0]) +); +defparam \genblk1.plol0_cnt_3[0] .init=16'h1414; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[2] ( + .A(CO0_2), + .B(plol0_cnt9), + .C(plol0_cnt[1]), + .D(plol0_cnt[2]), + .Z(plol0_cnt_3[2]) +); +defparam \genblk1.plol0_cnt_3[2] .init=16'h1320; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc ( + .A(un18_txr_wt_tc_6), + .B(un18_txr_wt_tc_7), + .C(un18_txr_wt_tc_8), + .D(VCC), + .Z(un18_txr_wt_tc) +); +defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080; +// @16:211 + LUT4 un2_plol_fedge_2_cZ ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un2_plol_fedge_2) +); +defparam un2_plol_fedge_2_cZ.init=16'h0101; +// @16:490 + LUT4 tx_any_rst_cZ ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_tx_pcs_rst_c), + .C(rsl_tx_serdes_rst_c), + .D(rst_dual_c), + .Z(tx_any_rst) +); +defparam tx_any_rst_cZ.init=16'hFFFE; +// @16:863 + LUT4 rx_any_rst_cZ ( + .A(dual_or_rserd_rst), + .B(rsl_rx_pcs_rst_c), + .C(rst_dual_c), + .D(VCC), + .Z(rx_any_rst) +); +defparam rx_any_rst_cZ.init=16'hFEFE; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc ( + .A(un17_rxr_wt_tc_6), + .B(un17_rxr_wt_tc_7), + .C(un17_rxr_wt_tc_8), + .D(VCC), + .Z(un17_rxr_wt_tc) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_bm[0]) +); +defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlol_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlol_db_cnt_zero_bm[0]), + .BLUT(un1_rlol_db_cnt_zero_am[0]), + .C0(rlol_p2), + .Z(un1_rlol_db_cnt_zero[0]) +); +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_bm[0]) +); +defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlos_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlos_db_cnt_zero_bm[0]), + .BLUT(un1_rlos_db_cnt_zero_am[0]), + .C0(rlos_p2), + .Z(un1_rlos_db_cnt_zero[0]) +); +// @16:309 + LUT4 \genblk2.un1_rlol_db_cnt_max ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_max) +); +defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001; +// @16:315 + LUT4 \genblk2.un1_rlos_db_cnt_max ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_max) +); +defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001; +// @16:269 + LUT4 \genblk1.un1_plol0_cnt_tc_1 ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1) +); +defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8; +// @16:764 + LUT4 \genblk2.waita_rlols06 ( + .A(rlol_db), + .B(rlol_db_p1), + .C(rlos_db), + .D(rlos_db_p1), + .Z(waita_rlols06) +); +defparam \genblk2.waita_rlols06 .init=16'h0504; +// @16:708 + LUT4 \rxs_cnt_3_cZ[1] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[1]) +); +defparam \rxs_cnt_3_cZ[1] .init=16'h6464; +// @16:893 + LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd ( + .A(rxsr_appd[0]), + .B(rx_all_well), + .C(rxsdr_appd_4), + .D(rsl_rx_pcs_rst_c), + .Z(un1_rxsdr_or_sr_appd) +); +defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd .init=16'h3200; +// @16:388 + LUT4 rlols0_cnt_tc_1_13_cZ ( + .A(rlols0_cnt[16]), + .B(rlols0_cnt[17]), + .C(rlols0_cnt_tc_1_9), + .D(VCC), + .Z(rlols0_cnt_tc_1_13) +); +defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_14 ( + .A(plol_cnt[4]), + .B(plol_cnt[5]), + .C(plol_cnt[18]), + .D(un1_plol_cnt_tc_10), + .Z(un1_plol_cnt_tc_14) +); +defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_14_cZ ( + .A(rlol1_cnt[11]), + .B(rlol1_cnt[12]), + .C(rlol1_cnt[18]), + .D(rlol1_cnt_tc_1_10), + .Z(rlol1_cnt_tc_1_14) +); +defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100; +// @16:906 + LUT4 \genblk2.genblk3.un3_rx_all_well_2_1 ( + .A(rxpr_appd[0]), + .B(rxdpr_appd), + .C(rsl_rx_rdy), + .D(VCC), + .Z(un3_rx_all_well_2_1) +); +defparam \genblk2.genblk3.un3_rx_all_well_2_1 .init=16'h0E0E; +// @16:375 + LUT4 rdo_serdes_rst_dual_c ( + .A(rsl_disable), + .B(rsl_rst), + .C(serdes_rst_dual_c), + .D(VCC), + .Z(rsl_serdes_rst_dual_c) +); +defparam rdo_serdes_rst_dual_c.init=16'hF4F4; +// @16:438 + LUT4 rdo_tx_serdes_rst_c ( + .A(rsl_disable), + .B(txs_rst), + .C(tx_serdes_rst_c), + .D(VCC), + .Z(rsl_tx_serdes_rst_c) +); +defparam rdo_tx_serdes_rst_c.init=16'hF4F4; +// @16:479 + LUT4 \rdo_tx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(txp_rst), + .C(tx_pcs_rst_c), + .D(VCC), + .Z(rsl_tx_pcs_rst_c) +); +defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:743 + LUT4 \rdo_rx_serdes_rst_c_1[0] ( + .A(rsl_disable), + .B(rxs_rst), + .C(rx_serdes_rst_c), + .D(VCC), + .Z(rsl_rx_serdes_rst_c) +); +defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4; +// @16:852 + LUT4 \rdo_rx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(rxp_rst2), + .C(rx_pcs_rst_c), + .D(VCC), + .Z(rsl_rx_pcs_rst_c) +); +defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:459 + LUT4 \genblk1.un9_plol0_cnt_tc ( + .A(plol0_cnt[0]), + .B(plol0_cnt[1]), + .C(plol0_cnt[2]), + .D(VCC), + .Z(un9_plol0_cnt_tc) +); +defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6 ( + .A(rxr_wt_cnt[0]), + .B(rxr_wt_cnt[8]), + .C(rxr_wt_cnt[9]), + .D(rxr_wt_cnt[11]), + .Z(un17_rxr_wt_tc_6) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7 ( + .A(rxr_wt_cnt[3]), + .B(rxr_wt_cnt[4]), + .C(rxr_wt_cnt[5]), + .D(rxr_wt_cnt[7]), + .Z(un17_rxr_wt_tc_7) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8 ( + .A(rxr_wt_cnt[1]), + .B(rxr_wt_cnt[2]), + .C(rxr_wt_cnt[6]), + .D(rxr_wt_cnt[10]), + .Z(un17_rxr_wt_tc_8) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_6 ( + .A(txr_wt_cnt[0]), + .B(txr_wt_cnt[8]), + .C(txr_wt_cnt[9]), + .D(txr_wt_cnt[11]), + .Z(un18_txr_wt_tc_6) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_7 ( + .A(txr_wt_cnt[3]), + .B(txr_wt_cnt[4]), + .C(txr_wt_cnt[5]), + .D(txr_wt_cnt[7]), + .Z(un18_txr_wt_tc_7) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_8 ( + .A(txr_wt_cnt[1]), + .B(txr_wt_cnt[2]), + .C(txr_wt_cnt[6]), + .D(txr_wt_cnt[10]), + .Z(un18_txr_wt_tc_8) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_9_cZ ( + .A(rlols0_cnt[1]), + .B(rlols0_cnt[2]), + .C(rlols0_cnt[3]), + .D(rlols0_cnt[4]), + .Z(rlols0_cnt_tc_1_9) +); +defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_10_cZ ( + .A(rlols0_cnt[0]), + .B(rlols0_cnt[10]), + .C(rlols0_cnt[14]), + .D(rlols0_cnt[15]), + .Z(rlols0_cnt_tc_1_10) +); +defparam rlols0_cnt_tc_1_10_cZ.init=16'h4000; +// @16:388 + LUT4 rlols0_cnt_tc_1_11_cZ ( + .A(rlols0_cnt[9]), + .B(rlols0_cnt[11]), + .C(rlols0_cnt[12]), + .D(rlols0_cnt[13]), + .Z(rlols0_cnt_tc_1_11) +); +defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_12_cZ ( + .A(rlols0_cnt[5]), + .B(rlols0_cnt[6]), + .C(rlols0_cnt[7]), + .D(rlols0_cnt[8]), + .Z(rlols0_cnt_tc_1_12) +); +defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_10 ( + .A(plol_cnt[2]), + .B(plol_cnt[3]), + .C(plol_cnt[17]), + .D(plol_cnt[19]), + .Z(un1_plol_cnt_tc_10) +); +defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h1000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_11 ( + .A(plol_cnt[13]), + .B(plol_cnt[14]), + .C(plol_cnt[15]), + .D(plol_cnt[16]), + .Z(un1_plol_cnt_tc_11) +); +defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_12 ( + .A(plol_cnt[7]), + .B(plol_cnt[8]), + .C(plol_cnt[9]), + .D(plol_cnt[11]), + .Z(un1_plol_cnt_tc_12) +); +defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_13 ( + .A(plol_cnt[1]), + .B(plol_cnt[6]), + .C(plol_cnt[10]), + .D(plol_cnt[12]), + .Z(un1_plol_cnt_tc_13) +); +defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0008; +// @16:387 + LUT4 rlol1_cnt_tc_1_10_cZ ( + .A(rlol1_cnt[7]), + .B(rlol1_cnt[8]), + .C(rlol1_cnt[9]), + .D(rlol1_cnt[10]), + .Z(rlol1_cnt_tc_1_10) +); +defparam rlol1_cnt_tc_1_10_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_11_cZ ( + .A(rlol1_cnt[3]), + .B(rlol1_cnt[4]), + .C(rlol1_cnt[5]), + .D(rlol1_cnt[6]), + .Z(rlol1_cnt_tc_1_11) +); +defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_12_cZ ( + .A(rlol1_cnt[0]), + .B(rlol1_cnt[1]), + .C(rlol1_cnt[2]), + .D(rlol1_cnt[17]), + .Z(rlol1_cnt_tc_1_12) +); +defparam rlol1_cnt_tc_1_12_cZ.init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_13_cZ ( + .A(rlol1_cnt[13]), + .B(rlol1_cnt[14]), + .C(rlol1_cnt[15]), + .D(rlol1_cnt[16]), + .Z(rlol1_cnt_tc_1_13) +); +defparam rlol1_cnt_tc_1_13_cZ.init=16'h0040; +// @16:866 + LUT4 \genblk2.genblk3.rxsdr_appd_2 ( + .A(rxsdr_appd_4), + .B(serdes_rst_dual_c), + .C(VCC), + .D(VCC), + .Z(rxsdr_appd_2) +); +defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE; +// @16:601 + LUT4 rx_all_well_cZ ( + .A(rlol_db), + .B(rlos_db), + .C(VCC), + .D(VCC), + .Z(rx_all_well) +); +defparam rx_all_well_cZ.init=16'h1111; +// @16:436 + LUT4 \genblk2.un8_rxs_cnt_tc ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(VCC), + .D(VCC), + .Z(un8_rxs_cnt_tc) +); +defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888; +// @16:441 + LUT4 plol_fedge_cZ ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(VCC), + .D(VCC), + .Z(plol_fedge) +); +defparam plol_fedge_cZ.init=16'h4444; +// @16:757 + LUT4 rlos_redge_cZ ( + .A(rlos_db), + .B(rlos_db_p1), + .C(VCC), + .D(VCC), + .Z(rlos_redge) +); +defparam rlos_redge_cZ.init=16'h2222; +// @16:457 + LUT4 \genblk1.plol0_cnt_3_RNO[2] ( + .A(plol0_cnt[0]), + .B(waita_plol0), + .C(VCC), + .D(VCC), + .Z(CO0_2) +); +defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888; +// @16:891 + LUT4 un2_rdo_serdes_rst_dual_c_1_1_cZ ( + .A(rx_cdr_lol_s), + .B(rx_los_low_s), + .C(VCC), + .D(VCC), + .Z(un2_rdo_serdes_rst_dual_c_1_1) +); +defparam un2_rdo_serdes_rst_dual_c_1_1_cZ.init=16'h1111; +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_am_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_am[0]) +); +defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_am_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_am[0]) +); +defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:861 + LUT4 dual_or_rserd_rst_cZ ( + .A(rsl_rx_serdes_rst_c), + .B(serdes_rst_dual_c), + .C(rsl_rst), + .D(rsl_disable), + .Z(dual_or_rserd_rst) +); +defparam dual_or_rserd_rst_cZ.init=16'hEEFE; +// @16:454 + LUT4 \genblk1.plol0_cnt9 ( + .A(pll_lol_p2), + .B(plol0_cnt[2]), + .C(plol0_cnt[1]), + .D(plol0_cnt[0]), + .Z(plol0_cnt9) +); +defparam \genblk1.plol0_cnt9 .init=16'hAAAE; +// @16:783 + LUT4 \genblk2.rlols0_cnt11_0 ( + .A(rlol_db_p1), + .B(rlol_db), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlols0_cnt11_0) +); +defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44; +// @16:527 + LUT4 \genblk1.genblk2.txr_wt_cnt9_i ( + .A(tx_any_rst), + .B(un18_txr_wt_tc_8), + .C(un18_txr_wt_tc_7), + .D(un18_txr_wt_tc_6), + .Z(txr_wt_cnt_scalar) +); +defparam \genblk1.genblk2.txr_wt_cnt9_i .init=16'h1555; + CCU2C \genblk2.rlol1_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlol1_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_7), + .COUT(rlol1_cnt_cry[0]), + .S0(rlol1_cnt_cry_0_S0[0]), + .S1(rlol1_cnt_s[0]) +); +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[1] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[0]), + .COUT(rlol1_cnt_cry[2]), + .S0(rlol1_cnt_s[1]), + .S1(rlol1_cnt_s[2]) +); +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[3] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[2]), + .COUT(rlol1_cnt_cry[4]), + .S0(rlol1_cnt_s[3]), + .S1(rlol1_cnt_s[4]) +); +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[5] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[4]), + .COUT(rlol1_cnt_cry[6]), + .S0(rlol1_cnt_s[5]), + .S1(rlol1_cnt_s[6]) +); +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[7] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[6]), + .COUT(rlol1_cnt_cry[8]), + .S0(rlol1_cnt_s[7]), + .S1(rlol1_cnt_s[8]) +); +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[9] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[8]), + .COUT(rlol1_cnt_cry[10]), + .S0(rlol1_cnt_s[9]), + .S1(rlol1_cnt_s[10]) +); +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[11] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[10]), + .COUT(rlol1_cnt_cry[12]), + .S0(rlol1_cnt_s[11]), + .S1(rlol1_cnt_s[12]) +); +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[13] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[12]), + .COUT(rlol1_cnt_cry[14]), + .S0(rlol1_cnt_s[13]), + .S1(rlol1_cnt_s[14]) +); +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[15] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[14]), + .COUT(rlol1_cnt_cry[16]), + .S0(rlol1_cnt_s[15]), + .S1(rlol1_cnt_s[16]) +); +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[17] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[16]), + .COUT(rlol1_cnt_cry_0_COUT[17]), + .S0(rlol1_cnt_s[17]), + .S1(rlol1_cnt_s[18]) +); +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO"; + CCU2C \genblk2.rlols0_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlols0_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_6), + .COUT(rlols0_cnt_cry[0]), + .S0(rlols0_cnt_cry_0_S0[0]), + .S1(rlols0_cnt_s[0]) +); +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[1] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[0]), + .COUT(rlols0_cnt_cry[2]), + .S0(rlols0_cnt_s[1]), + .S1(rlols0_cnt_s[2]) +); +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[3] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[2]), + .COUT(rlols0_cnt_cry[4]), + .S0(rlols0_cnt_s[3]), + .S1(rlols0_cnt_s[4]) +); +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[5] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[4]), + .COUT(rlols0_cnt_cry[6]), + .S0(rlols0_cnt_s[5]), + .S1(rlols0_cnt_s[6]) +); +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[7] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[6]), + .COUT(rlols0_cnt_cry[8]), + .S0(rlols0_cnt_s[7]), + .S1(rlols0_cnt_s[8]) +); +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[9] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[8]), + .COUT(rlols0_cnt_cry[10]), + .S0(rlols0_cnt_s[9]), + .S1(rlols0_cnt_s[10]) +); +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[11] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[10]), + .COUT(rlols0_cnt_cry[12]), + .S0(rlols0_cnt_s[11]), + .S1(rlols0_cnt_s[12]) +); +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[13] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[12]), + .COUT(rlols0_cnt_cry[14]), + .S0(rlols0_cnt_s[13]), + .S1(rlols0_cnt_s[14]) +); +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[15] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[14]), + .COUT(rlols0_cnt_cry[16]), + .S0(rlols0_cnt_s[15]), + .S1(rlols0_cnt_s[16]) +); +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_s_0[17] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[16]), + .COUT(rlols0_cnt_s_0_COUT[17]), + .S0(rlols0_cnt_s[17]), + .S1(rlols0_cnt_s_0_S1[17]) +); +defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a; +defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO"; + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(txr_wt_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(txr_wt_cnt_cry[0]), + .S0(txr_wt_cnt_cry_0_S0[0]), + .S1(txr_wt_cnt_s[0]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[0]), + .COUT(txr_wt_cnt_cry[2]), + .S0(txr_wt_cnt_s[1]), + .S1(txr_wt_cnt_s[2]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[2]), + .COUT(txr_wt_cnt_cry[4]), + .S0(txr_wt_cnt_s[3]), + .S1(txr_wt_cnt_s[4]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[4]), + .COUT(txr_wt_cnt_cry[6]), + .S0(txr_wt_cnt_s[5]), + .S1(txr_wt_cnt_s[6]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[6]), + .COUT(txr_wt_cnt_cry[8]), + .S0(txr_wt_cnt_s[7]), + .S1(txr_wt_cnt_s[8]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[8]), + .COUT(txr_wt_cnt_cry[10]), + .S0(txr_wt_cnt_s[9]), + .S1(txr_wt_cnt_s[10]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[10]), + .COUT(txr_wt_cnt_s_0_COUT[11]), + .S0(txr_wt_cnt_s[11]), + .S1(txr_wt_cnt_s_0_S1[11]) +); +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h800a; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(rxr_wt_cnt9), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rxr_wt_cnt_cry[0]), + .S0(rxr_wt_cnt_cry_0_S0[0]), + .S1(rxr_wt_cnt_s[0]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[0]), + .COUT(rxr_wt_cnt_cry[2]), + .S0(rxr_wt_cnt_s[1]), + .S1(rxr_wt_cnt_s[2]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[2]), + .COUT(rxr_wt_cnt_cry[4]), + .S0(rxr_wt_cnt_s[3]), + .S1(rxr_wt_cnt_s[4]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[4]), + .COUT(rxr_wt_cnt_cry[6]), + .S0(rxr_wt_cnt_s[5]), + .S1(rxr_wt_cnt_s[6]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[6]), + .COUT(rxr_wt_cnt_cry[8]), + .S0(rxr_wt_cnt_s[7]), + .S1(rxr_wt_cnt_s[8]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[8]), + .COUT(rxr_wt_cnt_cry[10]), + .S0(rxr_wt_cnt_s[9]), + .S1(rxr_wt_cnt_s[10]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[10]), + .COUT(rxr_wt_cnt_s_0_COUT[11]), + .S0(rxr_wt_cnt_s[11]), + .S1(rxr_wt_cnt_s_0_S1[11]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk1.plol_cnt_cry_0[0] ( + .A0(VCC), + .B0(plol_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(plol_cnt_cry[0]), + .S0(plol_cnt_cry_0_S0[0]), + .S1(plol_cnt_s[0]) +); +defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[1] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[0]), + .COUT(plol_cnt_cry[2]), + .S0(plol_cnt_s[1]), + .S1(plol_cnt_s[2]) +); +defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[3] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[2]), + .COUT(plol_cnt_cry[4]), + .S0(plol_cnt_s[3]), + .S1(plol_cnt_s[4]) +); +defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[5] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[4]), + .COUT(plol_cnt_cry[6]), + .S0(plol_cnt_s[5]), + .S1(plol_cnt_s[6]) +); +defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[7] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[6]), + .COUT(plol_cnt_cry[8]), + .S0(plol_cnt_s[7]), + .S1(plol_cnt_s[8]) +); +defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[9] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[8]), + .COUT(plol_cnt_cry[10]), + .S0(plol_cnt_s[9]), + .S1(plol_cnt_s[10]) +); +defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[11] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[10]), + .COUT(plol_cnt_cry[12]), + .S0(plol_cnt_s[11]), + .S1(plol_cnt_s[12]) +); +defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[13] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[12]), + .COUT(plol_cnt_cry[14]), + .S0(plol_cnt_s[13]), + .S1(plol_cnt_s[14]) +); +defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[15] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[14]), + .COUT(plol_cnt_cry[16]), + .S0(plol_cnt_s[15]), + .S1(plol_cnt_s[16]) +); +defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[17] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[16]), + .COUT(plol_cnt_cry[18]), + .S0(plol_cnt_s[17]), + .S1(plol_cnt_s[18]) +); +defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_s_0[19] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[19]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[18]), + .COUT(plol_cnt_s_0_COUT[19]), + .S0(plol_cnt_s[19]), + .S1(plol_cnt_s_0_S1[19]) +); +defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a; +defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlos_db_cnt[0]), + .B1(un1_rlos_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(rlos_db_cnt_cry_0), + .S0(rlos_db_cnt_cry_0_0_S0), + .S1(rlos_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0 ( + .A0(un1_rlos_db_cnt_zero[0]), + .B0(rlos_p2), + .C0(rlos_db_cnt[1]), + .D0(VCC), + .A1(un1_rlos_db_cnt_zero[0]), + .B1(rlos_p2), + .C1(rlos_db_cnt[2]), + .D1(VCC), + .CIN(rlos_db_cnt_cry_0), + .COUT(rlos_db_cnt_cry_2), + .S0(rlos_db_cnt_cry_1_0_S0), + .S1(rlos_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_s_3_0 ( + .A0(rlos_db_cnt[3]), + .B0(rlos_p2), + .C0(un1_rlos_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlos_db_cnt_cry_2), + .COUT(rlos_db_cnt_s_3_0_COUT), + .S0(rlos_db_cnt_s_3_0_S0), + .S1(rlos_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlol_db_cnt[0]), + .B1(un1_rlol_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(rlol_db_cnt_cry_0), + .S0(rlol_db_cnt_cry_0_0_S0), + .S1(rlol_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0 ( + .A0(un1_rlol_db_cnt_zero[0]), + .B0(rlol_p2), + .C0(rlol_db_cnt[1]), + .D0(VCC), + .A1(un1_rlol_db_cnt_zero[0]), + .B1(rlol_p2), + .C1(rlol_db_cnt[2]), + .D1(VCC), + .CIN(rlol_db_cnt_cry_0), + .COUT(rlol_db_cnt_cry_2), + .S0(rlol_db_cnt_cry_1_0_S0), + .S1(rlol_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_s_3_0 ( + .A0(rlol_db_cnt[3]), + .B0(rlol_p2), + .C0(un1_rlol_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlol_db_cnt_cry_2), + .COUT(rlol_db_cnt_s_3_0_COUT), + .S0(rlol_db_cnt_s_3_0_S0), + .S1(rlol_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO"; +//@16:865 +//@16:492 + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sgmii_ecp5rsl_core_Z2_layer1 */ + +module sgmii_ecp5 ( + hdoutp, + hdoutn, + hdinp, + hdinn, + rxrefclk, + tx_pclk, + txi_clk, + txdata, + tx_k, + xmit, + tx_disp_correct, + rxdata, + rx_k, + rx_disp_err, + rx_cv_err, + signal_detect_c, + rx_los_low_s, + lsm_status_s, + ctc_urun_s, + ctc_orun_s, + rx_cdr_lol_s, + ctc_ins_s, + ctc_del_s, + sli_rst, + tx_pwrup_c, + rx_pwrup_c, + sci_wrdata, + sci_addr, + sci_rddata, + sci_en_dual, + sci_sel_dual, + sci_en, + sci_sel, + sci_rd, + sci_wrn, + sci_int, + cyawstn, + serdes_pdb, + pll_refclki, + rsl_disable, + rsl_rst, + serdes_rst_dual_c, + rst_dual_c, + tx_serdes_rst_c, + tx_pcs_rst_c, + pll_lol, + rsl_tx_rdy, + rx_serdes_rst_c, + rx_pcs_rst_c, + rsl_rx_rdy +) +; +output hdoutp ; +output hdoutn ; +input hdinp ; +input hdinn ; +input rxrefclk ; +output tx_pclk ; +input txi_clk ; +input [7:0] txdata ; +input [0:0] tx_k ; +input [0:0] xmit ; +input [0:0] tx_disp_correct ; +output [7:0] rxdata ; +output [0:0] rx_k ; +output [0:0] rx_disp_err ; +output [0:0] rx_cv_err ; +input signal_detect_c ; +output rx_los_low_s ; +output lsm_status_s ; +output ctc_urun_s ; +output ctc_orun_s ; +output rx_cdr_lol_s ; +output ctc_ins_s ; +output ctc_del_s ; +input sli_rst ; +input tx_pwrup_c ; +input rx_pwrup_c ; +input [7:0] sci_wrdata ; +input [5:0] sci_addr ; +output [7:0] sci_rddata ; +input sci_en_dual ; +input sci_sel_dual ; +input sci_en ; +input sci_sel ; +input sci_rd ; +input sci_wrn ; +output sci_int ; +input cyawstn ; +input serdes_pdb ; +input pll_refclki ; +input rsl_disable ; +input rsl_rst ; +input serdes_rst_dual_c ; +input rst_dual_c ; +input tx_serdes_rst_c ; +input tx_pcs_rst_c ; +output pll_lol ; +output rsl_tx_rdy ; +input rx_serdes_rst_c ; +input rx_pcs_rst_c ; +output rsl_rx_rdy ; +wire hdoutp ; +wire hdoutn ; +wire hdinp ; +wire hdinn ; +wire rxrefclk ; +wire tx_pclk ; +wire txi_clk ; +wire signal_detect_c ; +wire rx_los_low_s ; +wire lsm_status_s ; +wire ctc_urun_s ; +wire ctc_orun_s ; +wire rx_cdr_lol_s ; +wire ctc_ins_s ; +wire ctc_del_s ; +wire sli_rst ; +wire tx_pwrup_c ; +wire rx_pwrup_c ; +wire sci_en_dual ; +wire sci_sel_dual ; +wire sci_en ; +wire sci_sel ; +wire sci_rd ; +wire sci_wrn ; +wire sci_int ; +wire cyawstn ; +wire serdes_pdb ; +wire pll_refclki ; +wire rsl_disable ; +wire rsl_rst ; +wire serdes_rst_dual_c ; +wire rst_dual_c ; +wire tx_serdes_rst_c ; +wire tx_pcs_rst_c ; +wire pll_lol ; +wire rsl_tx_rdy ; +wire rx_serdes_rst_c ; +wire rx_pcs_rst_c ; +wire rsl_rx_rdy ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire n47_1 ; +wire n48_1 ; +wire n1_1 ; +wire n2_1 ; +wire n3_1 ; +wire n4_1 ; +wire n5_1 ; +wire n49_1 ; +wire n6_1 ; +wire n50_1 ; +wire n7_1 ; +wire n51_1 ; +wire n8_1 ; +wire n52_1 ; +wire n9_1 ; +wire n53_1 ; +wire n54_1 ; +wire n55_1 ; +wire n56_1 ; +wire n57_1 ; +wire n58_1 ; +wire n59_1 ; +wire n60_1 ; +wire n61_1 ; +wire n62_1 ; +wire n63_1 ; +wire n64_1 ; +wire n65_1 ; +wire n10_1 ; +wire n66_1 ; +wire n67_1 ; +wire n68_1 ; +wire n69_1 ; +wire n70_1 ; +wire n71_1 ; +wire n72_1 ; +wire n73_1 ; +wire n74_1 ; +wire n75_1 ; +wire n76_1 ; +wire n77_1 ; +wire n78_1 ; +wire n79_1 ; +wire n80_1 ; +wire n81_1 ; +wire n82_1 ; +wire n83_1 ; +wire n84_1 ; +wire n85_1 ; +wire n86_1 ; +wire n87_1 ; +wire n88_1 ; +wire n11_1 ; +wire n89_1 ; +wire n12_1 ; +wire n90_1 ; +wire n13_1 ; +wire n91_1 ; +wire n92_1 ; +wire n93_1 ; +wire n94_1 ; +wire n95_1 ; +wire n14_1 ; +wire n96_1 ; +wire n15_1 ; +wire n97_1 ; +wire n98_1 ; +wire n99_1 ; +wire n100_1 ; +wire n101_1 ; +wire n112_1 ; +wire n16_1 ; +wire n17_1 ; +wire n18_1 ; +wire n19_1 ; +wire n20_1 ; +wire n21_1 ; +wire n22_1 ; +wire n23_1 ; +wire n24_1 ; +wire n25_1 ; +wire n26_1 ; +wire n27_1 ; +wire n28_1 ; +wire n29_1 ; +wire n30_1 ; +wire n31_1 ; +wire n32_1 ; +wire n33_1 ; +wire n34_1 ; +wire n35_1 ; +wire n36_1 ; +wire n37_1 ; +wire n38_1 ; +wire n39_1 ; +wire n40_1 ; +wire n41_1 ; +wire n42_1 ; +wire n43_1 ; +wire n46_1 ; +wire GND ; +wire VCC ; + VHI VCC_0 ( + .Z(VCC) +); + VLO GND_0 ( + .Z(GND) +); +// @16:865 + PUR PUR_INST ( + .PUR(VCC) +); +// @16:865 + GSR GSR_INST ( + .GSR(VCC) +); +// @8:162 +(* CHAN="CH0" *) DCUA DCU0_inst ( + .CH0_HDINP(hdinp), + .CH1_HDINP(GND), + .CH0_HDINN(hdinn), + .CH1_HDINN(GND), + .D_TXBIT_CLKP_FROM_ND(GND), + .D_TXBIT_CLKN_FROM_ND(GND), + .D_SYNC_ND(GND), + .D_TXPLL_LOL_FROM_ND(GND), + .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(GND), + .CH0_FF_RXI_CLK(tx_pclk), + .CH1_FF_RXI_CLK(VCC), + .CH0_FF_TXI_CLK(txi_clk), + .CH1_FF_TXI_CLK(VCC), + .CH0_FF_EBRD_CLK(tx_pclk), + .CH1_FF_EBRD_CLK(VCC), + .CH0_FF_TX_D_0(txdata[0]), + .CH1_FF_TX_D_0(GND), + .CH0_FF_TX_D_1(txdata[1]), + .CH1_FF_TX_D_1(GND), + .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(GND), + .CH0_FF_TX_D_3(txdata[3]), + .CH1_FF_TX_D_3(GND), + .CH0_FF_TX_D_4(txdata[4]), + .CH1_FF_TX_D_4(GND), + .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(GND), + .CH0_FF_TX_D_6(txdata[6]), + .CH1_FF_TX_D_6(GND), + .CH0_FF_TX_D_7(txdata[7]), + .CH1_FF_TX_D_7(GND), + .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(GND), + .CH0_FF_TX_D_9(GND), + .CH1_FF_TX_D_9(GND), + .CH0_FF_TX_D_10(xmit[0]), + .CH1_FF_TX_D_10(GND), + .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(GND), + .CH0_FF_TX_D_12(GND), + .CH1_FF_TX_D_12(GND), + .CH0_FF_TX_D_13(GND), + .CH1_FF_TX_D_13(GND), + .CH0_FF_TX_D_14(GND), + .CH1_FF_TX_D_14(GND), + .CH0_FF_TX_D_15(GND), + .CH1_FF_TX_D_15(GND), + .CH0_FF_TX_D_16(GND), + .CH1_FF_TX_D_16(GND), + .CH0_FF_TX_D_17(GND), + .CH1_FF_TX_D_17(GND), + .CH0_FF_TX_D_18(GND), + .CH1_FF_TX_D_18(GND), + .CH0_FF_TX_D_19(GND), + .CH1_FF_TX_D_19(GND), + .CH0_FF_TX_D_20(GND), + .CH1_FF_TX_D_20(GND), + .CH0_FF_TX_D_21(GND), + .CH1_FF_TX_D_21(GND), + .CH0_FF_TX_D_22(GND), + .CH1_FF_TX_D_22(GND), + .CH0_FF_TX_D_23(GND), + .CH1_FF_TX_D_23(GND), + .CH0_FFC_EI_EN(GND), + .CH1_FFC_EI_EN(GND), + .CH0_FFC_PCIE_DET_EN(GND), + .CH1_FFC_PCIE_DET_EN(GND), + .CH0_FFC_PCIE_CT(GND), + .CH1_FFC_PCIE_CT(GND), + .CH0_FFC_SB_INV_RX(GND), + .CH1_FFC_SB_INV_RX(GND), + .CH0_FFC_ENABLE_CGALIGN(GND), + .CH1_FFC_ENABLE_CGALIGN(GND), + .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(GND), + .CH0_FFC_FB_LOOPBACK(GND), + .CH1_FFC_FB_LOOPBACK(GND), + .CH0_FFC_SB_PFIFO_LP(GND), + .CH1_FFC_SB_PFIFO_LP(GND), + .CH0_FFC_PFIFO_CLR(GND), + .CH1_FFC_PFIFO_CLR(GND), + .CH0_FFC_RATE_MODE_RX(GND), + .CH1_FFC_RATE_MODE_RX(GND), + .CH0_FFC_RATE_MODE_TX(GND), + .CH1_FFC_RATE_MODE_TX(GND), + .CH0_FFC_DIV11_MODE_RX(GND), + .CH1_FFC_DIV11_MODE_RX(GND), + .CH0_FFC_RX_GEAR_MODE(GND), + .CH1_FFC_RX_GEAR_MODE(GND), + .CH0_FFC_TX_GEAR_MODE(GND), + .CH1_FFC_TX_GEAR_MODE(GND), + .CH0_FFC_DIV11_MODE_TX(GND), + .CH1_FFC_DIV11_MODE_TX(GND), + .CH0_FFC_LDR_CORE2TX_EN(GND), + .CH1_FFC_LDR_CORE2TX_EN(GND), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), + .CH1_FFC_LANE_TX_RST(GND), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), + .CH1_FFC_LANE_RX_RST(GND), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), + .CH1_FFC_RRST(GND), + .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(GND), + .CH0_FFC_RXPWDNB(rx_pwrup_c), + .CH1_FFC_RXPWDNB(GND), + .CH0_LDR_CORE2TX(GND), + .CH1_LDR_CORE2TX(GND), + .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), + .D_SCIWDATA2(sci_wrdata[2]), + .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), + .D_SCIWDATA5(sci_wrdata[5]), + .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), + .D_SCIADDR0(sci_addr[0]), + .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), + .D_SCIADDR3(sci_addr[3]), + .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), + .D_SCIENAUX(sci_en_dual), + .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), + .CH1_SCIEN(GND), + .CH0_SCISEL(sci_sel), + .CH1_SCISEL(GND), + .D_SCIRD(sci_rd), + .D_SCIWSTN(sci_wrn), + .D_CYAWSTN(cyawstn), + .D_FFC_SYNC_TOGGLE(GND), + .D_FFC_DUAL_RST(rst_dual_c), + .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), + .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(GND), + .CH1_FFC_CDR_EN_BITSLIP(GND), + .D_SCAN_ENABLE(GND), + .D_SCAN_IN_0(GND), + .D_SCAN_IN_1(GND), + .D_SCAN_IN_2(GND), + .D_SCAN_IN_3(GND), + .D_SCAN_IN_4(GND), + .D_SCAN_IN_5(GND), + .D_SCAN_IN_6(GND), + .D_SCAN_IN_7(GND), + .D_SCAN_MODE(GND), + .D_SCAN_RESET(GND), + .D_CIN0(GND), + .D_CIN1(GND), + .D_CIN2(GND), + .D_CIN3(GND), + .D_CIN4(GND), + .D_CIN5(GND), + .D_CIN6(GND), + .D_CIN7(GND), + .D_CIN8(GND), + .D_CIN9(GND), + .D_CIN10(GND), + .D_CIN11(GND), + .CH0_HDOUTP(hdoutp), + .CH1_HDOUTP(n47_1), + .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n48_1), + .D_TXBIT_CLKP_TO_ND(n1_1), + .D_TXBIT_CLKN_TO_ND(n2_1), + .D_SYNC_PULSE2ND(n3_1), + .D_TXPLL_LOL_TO_ND(n4_1), + .CH0_FF_RX_F_CLK(n5_1), + .CH1_FF_RX_F_CLK(n49_1), + .CH0_FF_RX_H_CLK(n6_1), + .CH1_FF_RX_H_CLK(n50_1), + .CH0_FF_TX_F_CLK(n7_1), + .CH1_FF_TX_F_CLK(n51_1), + .CH0_FF_TX_H_CLK(n8_1), + .CH1_FF_TX_H_CLK(n52_1), + .CH0_FF_RX_PCLK(n9_1), + .CH1_FF_RX_PCLK(n53_1), + .CH0_FF_TX_PCLK(tx_pclk), + .CH1_FF_TX_PCLK(n54_1), + .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n55_1), + .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n56_1), + .CH0_FF_RX_D_2(rxdata[2]), + .CH1_FF_RX_D_2(n57_1), + .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n58_1), + .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n59_1), + .CH0_FF_RX_D_5(rxdata[5]), + .CH1_FF_RX_D_5(n60_1), + .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n61_1), + .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n62_1), + .CH0_FF_RX_D_8(rx_k[0]), + .CH1_FF_RX_D_8(n63_1), + .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n64_1), + .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n65_1), + .CH0_FF_RX_D_11(n10_1), + .CH1_FF_RX_D_11(n66_1), + .CH0_FF_RX_D_12(n67_1), + .CH1_FF_RX_D_12(n68_1), + .CH0_FF_RX_D_13(n69_1), + .CH1_FF_RX_D_13(n70_1), + .CH0_FF_RX_D_14(n71_1), + .CH1_FF_RX_D_14(n72_1), + .CH0_FF_RX_D_15(n73_1), + .CH1_FF_RX_D_15(n74_1), + .CH0_FF_RX_D_16(n75_1), + .CH1_FF_RX_D_16(n76_1), + .CH0_FF_RX_D_17(n77_1), + .CH1_FF_RX_D_17(n78_1), + .CH0_FF_RX_D_18(n79_1), + .CH1_FF_RX_D_18(n80_1), + .CH0_FF_RX_D_19(n81_1), + .CH1_FF_RX_D_19(n82_1), + .CH0_FF_RX_D_20(n83_1), + .CH1_FF_RX_D_20(n84_1), + .CH0_FF_RX_D_21(n85_1), + .CH1_FF_RX_D_21(n86_1), + .CH0_FF_RX_D_22(n87_1), + .CH1_FF_RX_D_22(n88_1), + .CH0_FF_RX_D_23(n11_1), + .CH1_FF_RX_D_23(n89_1), + .CH0_FFS_PCIE_DONE(n12_1), + .CH1_FFS_PCIE_DONE(n90_1), + .CH0_FFS_PCIE_CON(n13_1), + .CH1_FFS_PCIE_CON(n91_1), + .CH0_FFS_RLOS(rx_los_low_s), + .CH1_FFS_RLOS(n92_1), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n93_1), + .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n94_1), + .CH0_FFS_CC_OVERRUN(ctc_orun_s), + .CH1_FFS_CC_OVERRUN(n95_1), + .CH0_FFS_RXFBFIFO_ERROR(n14_1), + .CH1_FFS_RXFBFIFO_ERROR(n96_1), + .CH0_FFS_TXFBFIFO_ERROR(n15_1), + .CH1_FFS_TXFBFIFO_ERROR(n97_1), + .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n98_1), + .CH0_FFS_SKP_ADDED(ctc_ins_s), + .CH1_FFS_SKP_ADDED(n99_1), + .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n100_1), + .CH0_LDR_RX2CORE(n101_1), + .CH1_LDR_RX2CORE(n112_1), + .D_SCIRDATA0(sci_rddata[0]), + .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), + .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), + .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n16_1), + .D_SCAN_OUT_1(n17_1), + .D_SCAN_OUT_2(n18_1), + .D_SCAN_OUT_3(n19_1), + .D_SCAN_OUT_4(n20_1), + .D_SCAN_OUT_5(n21_1), + .D_SCAN_OUT_6(n22_1), + .D_SCAN_OUT_7(n23_1), + .D_COUT0(n24_1), + .D_COUT1(n25_1), + .D_COUT2(n26_1), + .D_COUT3(n27_1), + .D_COUT4(n28_1), + .D_COUT5(n29_1), + .D_COUT6(n30_1), + .D_COUT7(n31_1), + .D_COUT8(n32_1), + .D_COUT9(n33_1), + .D_COUT10(n34_1), + .D_COUT11(n35_1), + .D_COUT12(n36_1), + .D_COUT13(n37_1), + .D_COUT14(n38_1), + .D_COUT15(n39_1), + .D_COUT16(n40_1), + .D_COUT17(n41_1), + .D_COUT18(n42_1), + .D_COUT19(n43_1), + .D_REFCLKI(pll_refclki), + .D_FFS_PLOL(n46_1) +); +defparam DCU0_inst.D_MACROPDB = "0b1"; +defparam DCU0_inst.D_IB_PWDNB = "0b1"; +defparam DCU0_inst.D_XGE_MODE = "0b0"; +defparam DCU0_inst.D_LOW_MARK = "0d4"; +defparam DCU0_inst.D_HIGH_MARK = "0d12"; +defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; +defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; +defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; +defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; +defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; +defparam DCU0_inst.CH0_UC_MODE = "0b0"; +defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; +defparam DCU0_inst.CH0_RIO_MODE = "0b0"; +defparam DCU0_inst.CH0_WA_MODE = "0b0"; +defparam DCU0_inst.CH0_INVERT_RX = "0b0"; +defparam DCU0_inst.CH0_INVERT_TX = "0b0"; +defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; +defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0"; +defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; +defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; +defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; +defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; +defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; +defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_CTC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; +defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1"; +defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; +defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; +defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC"; +defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050"; +defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; +defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; +defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; +defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010"; +defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; +defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00"; +defparam DCU0_inst.CH0_REQ_EN = "0b1"; +defparam DCU0_inst.CH0_RTERM_RX = "0d22"; +defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; +defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; +defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; +defparam DCU0_inst.CH0_TPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0"; +defparam DCU0_inst.CH0_RTERM_TX = "0d19"; +defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; +defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101"; +defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; +defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; +defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; +defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_RPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0"; +defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; +defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010"; +defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; +defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; +defparam DCU0_inst.CH0_RX_LOS_EN = "0b1"; +defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0"; +defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; +defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; +defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; +defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; +defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; +defparam DCU0_inst.CH0_RXIN_CM = "0b11"; +defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; +defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; +defparam DCU0_inst.D_TX_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100"; +defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; +defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; +defparam DCU0_inst.CH0_PROTOCOL = "GBE"; +defparam DCU0_inst.D_ISETLOS = "0d0"; +defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; +defparam DCU0_inst.D_SETICONST_AUX = "0b00"; +defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; +defparam DCU0_inst.D_SETICONST_CH = "0b00"; +defparam DCU0_inst.D_REQ_ISET = "0b000"; +defparam DCU0_inst.D_PD_ISET = "0b00"; +defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; +defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; +defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; +defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; +defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; +defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; +defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; +defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; +defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; +defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; +defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; +defparam DCU0_inst.CH0_DCOSTEP = "0b00"; +defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; +defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; +defparam DCU0_inst.CH0_DCOITUNE = "0b00"; +defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; +defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; +defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; +defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; +defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; +defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; +defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; +defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; +defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; +defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; +defparam DCU0_inst.D_SETPLLRC = "0d1"; +defparam DCU0_inst.D_REFCK_MODE = "0b001"; +defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; +defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; +defparam DCU0_inst.D_RG_EN = "0b0"; +defparam DCU0_inst.D_RG_SET = "0b00"; +defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; +defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; +defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; +defparam DCU0_inst.D_CMUSETZGM = "0b000"; +defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; +defparam DCU0_inst.D_CMUSETP1GM = "0b000"; +defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; +defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; +defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; +defparam DCU0_inst.D_CMUSETICP4P = "0b01"; +defparam DCU0_inst.D_CMUSETBIASI = "0b00"; +// @8:424 + sgmii_ecp5sll_core_Z1_layer1 sll_inst ( + .tx_pclk(tx_pclk), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki), + .pll_lock_i(pll_lol) +); +// @8:394 + sgmii_ecp5rsl_core_Z2_layer1 rsl_inst ( + .rx_pcs_rst_c(rx_pcs_rst_c), + .tx_pcs_rst_c(tx_pcs_rst_c), + .tx_serdes_rst_c(tx_serdes_rst_c), + .serdes_rst_dual_c(serdes_rst_dual_c), + .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c), + .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c), + .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c), + .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rsl_tx_rdy(rsl_tx_rdy), + .pll_lock_i(pll_lol), + .pll_refclki(pll_refclki), + .rsl_rx_rdy(rsl_rx_rdy), + .rsl_rst(rsl_rst), + .rxrefclk(rxrefclk), + .rsl_disable(rsl_disable), + .rx_serdes_rst_c(rx_serdes_rst_c), + .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c), + .rst_dual_c(rst_dual_c), + .rx_cdr_lol_s(rx_cdr_lol_s), + .rx_los_low_s(rx_los_low_s) +); +endmodule /* sgmii_ecp5 */ + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 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Build 1796R. +# + +# Period Constraints +#FREQUENCY PORT "pll_refclki" 100.0 MHz; +#FREQUENCY PORT "rxrefclk" 100.0 MHz; +#FREQUENCY NET "tx_pclk" 100.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk"; +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap new file mode 100644 index 0000000..3910cac --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap new file mode 100644 index 0000000..af92e0b --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap new file mode 100644 index 0000000..3793ead --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap @@ -0,0 +1 @@ +./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/metrics.db new file mode 100644 index 0000000000000000000000000000000000000000..8452dbd30faf5a61ca8f47f4286531d22ade14d9 GIT binary patch literal 20480 zcmeI3O=}xR7{_;Q*;-LXTN8pYMs$jjDlU~HS@Mghp>b1_w6znO7(xy~tX3m=vS#AHEJ2^#Mh{qqs}Ft*NyUDuNVbn*d4<@&i}~%qz)Pg zfB*=900@8p2!H?xfB*=*g9Oe$&SY2D*3657c3QsBUf{{@@c+`?M~4R|hy3K=%cDbH z8cvpOg{|kp)qLP6_ta6J@jz(hxs&n0@%v&j>`PBali~BQH5s^J5C}P?)l**JsF%k> z$yONp!jT*2Uo2)<%VqPTns{{m&^>Fqp&SSmd7*rLoSF6g`tp^0gBuIk)%A7r;-lmn zsJY#xD2!H?xfB*=900@8p2!H?xfWUi4U_WEA;tDH#o716o{APzr^{Bd+7VYXJp5(G0 zw1nbehu{C|h>zCSDZl<->FN5xg2l>|cATRLuj7e!^9?h3 zs@%SBT5N-SKbuIro%OL&T>mfI9~kx@_D}XJyJhdt01X5{00ck)1V8`;KmY_l00ck) z1m0f)8_O13FRT|?&ZQEc&KJ}+_jc-A^=c&OutYoR^tw(naC$wVK3%d{AqiE&@rSXy zjrwlA^6%Iiw8ucQYh&5!W+iE9Xio_ey-9lsq)1UC#kpah(B1)w6{f_t8#|T8UMe=) zdMMEb0m)I^L~dud*4P^v90kVpzr|h{_AmAi_ICc){P+0+`;8{hKmY_l00ck)1V8`; zKmY_l00jOYfv1+m8a6AQ?#!JM+qJnjdIQaUs_bvtZ0%vrbGuC?wBt#78iuwnY!-Jm}-5C8!X009sH0T2KI t5C8!X009sHfp?0)t#~`2utG-}o`fpW{IT!2XZ6iWy|!Jc$mx>|{{UwLq5}W` literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt new file mode 100644 index 0000000..f5277c3 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt @@ -0,0 +1,16 @@ +@N|Running in 64-bit mode +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +@N|Running in 64-bit mode + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml new file mode 100644 index 0000000..978b9de --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml @@ -0,0 +1,41 @@ + + + + + + /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr + Synopsys HDL Compiler + + + Completed + + + + 15 + /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt + + + 76 + /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt + + + 0 + /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt + + + - + + + 00h:00m:02s + + + - + + + 1557731345 + + + \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt new file mode 100644 index 0000000..8e5c4f5 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt @@ -0,0 +1,77 @@ +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml new file mode 100644 index 0000000..c262d0f --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt +Resource Usage + + +221 + + +0 + + +0 + + +0 + + +154 + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt new file mode 100644 index 0000000..b2d9ac0 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt @@ -0,0 +1,22 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..68d4e92 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +3 / 0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..686a424 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +22 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt + + + +4 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt + + + +0h:00m:03s + + +0h:00m:03s + + +153MB + + +1557731351 + + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..92b3753 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml @@ -0,0 +1,41 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +sgmii_ecp5|pll_refclki +100.0 MHz +168.9 MHz +4.079 + + +sgmii_ecp5|rxrefclk +100.0 MHz +167.9 MHz +4.043 + + +sgmii_ecp5|tx_pclk_inferred_clock +100.0 MHz +237.5 MHz +5.789 + + +System +100.0 MHz +840.7 MHz +8.810 + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt new file mode 100644 index 0000000..a40a3f6 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt @@ -0,0 +1,4 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt new file mode 100644 index 0000000..958d4b4 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt @@ -0,0 +1,9 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml new file mode 100644 index 0000000..552c1b6 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +9 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt + + + +3 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +144MB + + +1557731347 + + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt new file mode 100644 index 0000000..71c6352 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt @@ -0,0 +1,3 @@ +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr new file mode 100644 index 0000000..7b9d5ac --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr @@ -0,0 +1,351 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Mon May 13 09:09:04 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Mon May 13 09:09:04 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Mon May 13 09:09:04 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Mon May 13 09:09:05 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:09:05 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon May 13 09:09:05 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..22032b27c0e6d592fd8ff3ba504bfa3cf705b99a GIT binary patch literal 28672 zcmeI5-ESLN6~OI$Ip1zmN*0#DrMt9UNbUJ_Z1-cg+f74gLc47dXrp!*k8hH($1~HJ zalY0FITF$eUJ<mpSGt>6Xm1_&YT9{>;V#?!v^WyOkp;M_ZL>|yJ++00Duim{Tp zi9L4i@7%9*&b{a4&YLT`htay_G*l0XsS~MmI`tYtsZ?qhzBBOMd8FZoq0TQ*lHZ^9 z7*1XI_?;=ZE1msm3civ@B7sB#i3Ab}Boas@kVqhrKq7%e0*M3?2_zEuKbL@)&dkou zrP~)hwPN4~c3pJ?yPb02+U>=wcNfv!tFNytqRzAD^(xv@9c@!}=8>VB_3m#6w{)MV z>t@f*HoQ|ey;q2lKa~BD$Uc+(PxhniqwI$hAB_KN?9u2aqnXUi$lUPxAz|>+!1eU4 z)LTbsqPBZ#bhfRvAG|nlZAIXUXY!j?1LxJMqpN0qL-+EYQ;}UQ@8O1Rs2d{7E1K1?m8NM}T78X|%iO(#HzIBx zK5RpGJ?y{_4QmTmQDqldwx>7rJ=N1KGqtSJRn6sOjn|)bx#l$b~H7+}39GOj+chesJLn!P-%Qb!D2{ z;(hVWv<9F~=axvF7KBcnh_uXS+AbXwGcB6t=-&H|G28%pLa(&4aJ8%iK>fKQ{AM*=6o` zZs^#|bL=t)=jiSUv12oTgdy%!D%iO+C00o!L>US+8n#I!DTxX z+6(N`2Hgjt(9W|<8+06mLi;UtX~WkpYTu-^Ebdi=uUyn#VHP%g-J*7$S=gY1AdEp< zJI5?+_8{T9bd6`1|CM8L0OwJ{Y0p<*2UM*+ z1_Ku&>!KaFqAZq0_<}+zbmRWEb%>vccLwEHHQ{; z!qiD$qCyH7qluB#$zDPy7XR)4o4jQGH46Ftcp!Nnk}pdOkAWmzFf!0fuTs##c={vf zgL0%b594HMe{>Fp+7UbBl`FLRnOLeX!5RR=2@0tv%-65JVHxfoX{jRusFx|gYAhX1 zf~k)H6v~p&>1fVj%_Hk$7cWu9bUcmZ&v_EedBWrS*b!Uk{zY2*rFdG%pYJ3nN{1~3 zL&I^Sn*#2a;{^2QIthvZV3c#*4@(sAMl3BT6zLd)LgEiw5SmZfRzXjWYQ4Htq=@lM z4*8Efi%RkoelM1U3MB!;{^9b}WD1V^ zUuv4eyoiTBVSXVbJMh6B3QJG3M{V*R5w?5u z^Wad87!LFP+1rG9pBPmuLeyD#0(mey4Sbk%2z*v9l8J2_bR>4!=}|ekECBoRI#`OZ za#PcoCL|&mL$O&UMkn4>w{#1#jzT)mEt0Z`IJfL3eEc?8pTy*(sY$``bmxibdGO-8 zV>Rf_o@FBgZ(*ZrV(*`SlL~5$6+snOw~XA<<TBe)UdXrg#T`w z@G{Zr1x|hne3Q1kt+~WvQ?$rh{zt2Hh8T{g+k^j~z)NMBe^R&i;lXiV#ZmL`t;E^* z)NLhj;I?|=um^r`M~S@g_h)Yayt03pHh#oDq7-xNy#XCqBtY1@K{jW1a8WNa)osdL_f>Jm0^0u#@l{B(of&WCU new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 4.90ns 155 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Mon May 13 09:09:11 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.043 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.902 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.043 + + Number of logic level(s): 11 + Starting point: rsl_inst.genblk2\.rxs_rst / Q + Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - +rxs_rst Net - - - - 6 +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - +rsl_rx_serdes_rst_c Net - - - - 3 +rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - +rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - +dual_or_rserd_rst Net - - - - 9 +rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - +rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - +rx_any_rst Net - - - - 2 +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - +rxr_wt_cnt9 Net - - - - 14 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - +rxr_wt_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - +rxr_wt_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - +rxr_wt_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - +rxr_wt_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - +rxr_wt_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - +rxr_wt_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - +rxr_wt_cnt_s[11] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - +================================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 154 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Mon May 13 09:09:11 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..ff725bb590d99c244888547ebe5b829a39a361c2 GIT binary patch literal 16384 zcmeHOO>f&a7`Br%A8p)pO}nfe3J^IZKqFiJO5$Fcq;WBzS=%H zMI9@YOI%4LlZm?sB@&4t_>91(yCmVu`}^HGHFkl!k41DGcsN~qpty{_V9fd0asS_!2mB{XPXl-+SWqTcMudF^; zN8O`y)I&`y+!_|QQ9#-5;a;c6;elPs`U;0|C1q;<06Myg%EK2&~YX9~rqf-1_YX#HLp z`7|IUl&s)eSV&(6w{43r z#&5K7yAh+emuCk8wujr1+*bjwQrBwEmh9!FrBWu|6jnS>)4a0v{M$8WbNxO77DFOb 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 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uQpjB7cbS-F*)`{!amLtrN{glG@TUKEuz}n1Y}Ahc0000 + + + + + + + + + + + + + + + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg new file mode 100644 index 0000000..bab41a3 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg @@ -0,0 +1,28 @@ +@P: Worst Slack : 4.043 +@P: sgmii_ecp5|pll_refclki - Estimated Frequency : 168.9 MHz +@P: sgmii_ecp5|pll_refclki - Requested Frequency : 100.0 MHz +@P: sgmii_ecp5|pll_refclki - Estimated Period : 5.921 +@P: sgmii_ecp5|pll_refclki - Requested Period : 10.000 +@P: sgmii_ecp5|pll_refclki - Slack : 4.079 +@P: sgmii_ecp5|rxrefclk - Estimated Frequency : 167.9 MHz +@P: sgmii_ecp5|rxrefclk - Requested Frequency : 100.0 MHz +@P: sgmii_ecp5|rxrefclk - Estimated Period : 5.957 +@P: sgmii_ecp5|rxrefclk - Requested Period : 10.000 +@P: sgmii_ecp5|rxrefclk - Slack : 4.043 +@P: sgmii_ecp5|tx_pclk_inferred_clock - Estimated Frequency : 237.5 MHz +@P: sgmii_ecp5|tx_pclk_inferred_clock - Requested Frequency : 100.0 MHz +@P: sgmii_ecp5|tx_pclk_inferred_clock - Estimated Period : 4.211 +@P: sgmii_ecp5|tx_pclk_inferred_clock - Requested Period : 10.000 +@P: sgmii_ecp5|tx_pclk_inferred_clock - Slack : 5.789 +@P: System - Estimated Frequency : 840.7 MHz +@P: System - Requested Frequency : 100.0 MHz +@P: System - Estimated Period : 1.190 +@P: System - Requested Period : 10.000 +@P: System - Slack : 8.810 +@P: Total Area : 157.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: CPU Time : 0h:00m:03s diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm new file mode 100644 index 0000000..363baae --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm @@ -0,0 +1,1162 @@ +
    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:09:03 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : sgmii_ecp5.vhd(30) | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : sgmii_ecp5.vhd(30) | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N:CD630 : sgmii_ecp5.vhd(30) | Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : sgmii_ecp5_softlogic.v(1968) | Synthesizing module sync in library work.
+
+	PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:CG364 : sgmii_ecp5_softlogic.v(1051) | Synthesizing module sgmii_ecp5sll_core in library work.
+
+	PPROTOCOL=24'b010001110100001001000101
+	PLOL_SETTING=32'b00000000000000000000000000000000
+	PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+	PPCIE_MAX_RATE=24'b001100100010111000110101
+	PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+	PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+	PPCLK_TC=32'b00000000000000100000000000000000
+	PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+	PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+	PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+	LPLL_LOSS_ST=2'b00
+	LPLL_PRELOSS_ST=2'b01
+	LPLL_PRELOCK_ST=2'b10
+	LPLL_LOCK_ST=2'b11
+	LRCLK_TC=16'b1111111111111111
+	LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+	LHB_WAIT_CNT=8'b11111111
+	LPCLK_TC_0=32'b00000000000000001000000000000000
+	LPCLK_TC_1=32'b00000000000000010000000000000000
+	LPCLK_TC_2=32'b00000000000000100000000000000000
+	LPCLK_TC_3=32'b00000000000000101000000000000000
+	LPCLK_TC_4=32'b00000000000000010000000000000000
+	LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+	LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+	LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+	LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+	LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+	LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+	LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+	LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+	LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+	LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+	LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+	LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+	LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+	LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+	LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+	LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+	LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+	LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+	LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N:CG179 : sgmii_ecp5_softlogic.v(1287) | Removing redundant assignment.
+@N:CG179 : sgmii_ecp5_softlogic.v(1293) | Removing redundant assignment.
+@W:CL169 : sgmii_ecp5_softlogic.v(1350) | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : sgmii_ecp5_softlogic.v(92) | Synthesizing module sgmii_ecp5rsl_core in library work.
+
+	pnum_channels=32'b00000000000000000000000000000001
+	pprotocol=24'b010001110100001001000101
+	pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+	pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_tx_rdy=32'b00000000000000000000101110111000
+	pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_rx_rdy=32'b00000000000000000000101110111000
+	wa_num_cycles=32'b00000000000000000000010000000000
+	dac_num_cycles=32'b00000000000000000000000000000011
+	lreset_pwidth=32'b00000000000000000000000000000011
+	lwait_b4_trst=32'b00000000000010111110101111000010
+	lwait_b4_trst_s=32'b00000000000000000000001100001101
+	lplol_cnt_width=32'b00000000000000000000000000010100
+	lwait_after_plol0=32'b00000000000000000000000000000100
+	lwait_b4_rrst=32'b00000000000000101100000000000000
+	lrrst_wait_width=32'b00000000000000000000000000010100
+	lwait_after_rrst=32'b00000000000011000011010100000000
+	lwait_b4_rrst_s=32'b00000000000000000000000111001100
+	lrlol_cnt_width=32'b00000000000000000000000000010011
+	lwait_after_lols=32'b00000000000000001100010000000000
+	lwait_after_lols_s=32'b00000000000000000000000010010110
+	llols_cnt_width=32'b00000000000000000000000000010010
+	lrdb_max=32'b00000000000000000000000000001111
+	ltxr_wait_width=32'b00000000000000000000000000001100
+	lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W:CG133 : sgmii_ecp5_softlogic.v(326) | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(327) | Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(328) | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(341) | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(342) | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(343) | Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(346) | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(347) | Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W:CG360 : sgmii_ecp5_softlogic.v(350) | Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(351) | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(352) | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(353) | Removing wire data_loop_b_tc, as there is no assignment to it.
+@W:CL169 : sgmii_ecp5_softlogic.v(806) | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(567) | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(567) | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W:CL190 : sgmii_ecp5_softlogic.v(694) | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : sgmii_ecp5_softlogic.v(461) | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : sgmii_ecp5_softlogic.v(422) | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL260 : sgmii_ecp5_softlogic.v(422) | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : sgmii_ecp5_softlogic.v(461) | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : sgmii_ecp5_softlogic.v(694) | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL246 : sgmii_ecp5_softlogic.v(200) | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(204) | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(205) | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(206) | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(207) | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL279 : sgmii_ecp5_softlogic.v(1739) | Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL279 : sgmii_ecp5_softlogic.v(1739) | Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL169 : sgmii_ecp5_softlogic.v(1739) | Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(1739) | Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N:CL201 : sgmii_ecp5_softlogic.v(1801) | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+
+
    +
    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:06 2019
+
+###########################################################]
+
+
     +
    +
+Pre-mapping Report
+
+
+
     +
    +
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+Linked File: sgmii_ecp5_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N:BN362 : sgmii_ecp5_softlogic.v(1408) | Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1244) | Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1252) | Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1236) | Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1268) | Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1260) | Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W:MT529 : sgmii_ecp5_softlogic.v(1988) | Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : sgmii_ecp5_softlogic.v(567) | Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : sgmii_ecp5_softlogic.v(1988) | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:MO225 : sgmii_ecp5_softlogic.v(1801) | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:09:07 2019
+
+###########################################################]
+
+
     +
    +
+Map & Optimize Report
+
+
+
     +
    +
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:MO225 : sgmii_ecp5_softlogic.v(1801) | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N:MO231 : sgmii_ecp5_softlogic.v(1350) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(1304) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(1759) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(412) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(909) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(527) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(778) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(680) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     4.90ns		 155 /       221
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+ClockId0001        pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+ClockId0002        rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+ClockId0003        DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W:MT246 : sgmii_ecp5.vhd(162) | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:09:11 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Mon May 13 09:09:11 2019
+
+###########################################################]
+
+
     diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm new file mode 100644 index 0000000..d978345 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/statusReport.html b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..4f4bf5c --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/statusReport.html @@ -0,0 +1,115 @@ + + + Project Status Summary Page + + + + + + +
    + + + + + + + + + + +
    Project Settings
    Project Name sgmii_ecp5 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module sgmii_ecp5
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete15760-00m:02s-5/13/19
    9:09 AM
    (premap)Complete9300m:00s0m:00s144MB5/13/19
    9:09 AM
    (fpga_mapper)Complete22400m:03s0m:03s153MB5/13/19
    9:09 AM
    Multi-srs GeneratorComplete5/13/19
    9:09 AM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 221I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 154

    + + + + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    sgmii_ecp5|pll_refclki100.0 MHz168.9 MHz4.079
    sgmii_ecp5|rxrefclk100.0 MHz167.9 MHz4.043
    sgmii_ecp5|tx_pclk_inferred_clock100.0 MHz237.5 MHz5.789
    System100.0 MHz840.7 MHz8.810
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 3 / 0

    +
    +
    + \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/.cckTransfer b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/.cckTransfer new file mode 100644 index 0000000000000000000000000000000000000000..c8ef476e3afdcd10b3d97832b285a939d0788984 GIT binary patch literal 456 zcmV;(0XP01iwFP!0000015#C0RVXORFG)=yf5o@a)#_;GC@l6eLj-wxqbfz8gbMy>?(>W*ENrczeEr zu?%;@L;gkJY#akI%iW0 zqz5sBG8PwMq2Nu0)WqQg#64v#=~%~_42~mTGT-#Er)>{El*`&Xq@y(*Ub-8S^ISVF zDy5N--grx0q7AB)qSj)7!8Sv zv`geO208SqC8y?ERnUh_Rx*Rw>+MC~PEQ!e`{^FjdNWRKb*--dtqRI6ukOr#sHR5o y<t>Dk!q98E zLAG3HzKtu~{rGmMZXxwTYfE}2Ws@jVM|^Pz6@f{o(q~KC>f55hm7jKZ1B;jWQoI={ zsPJ7G2+tF*7}-^#x0N{aKI?oo*ls07`TqMGZT*Dyx-(uoQ>%_y-9+p^}~4N<3ha1#At(JlXM!<(qe}FtB=6RpNO_6{cS15Isk!?LoLgGIcQd?u|m)6SFzQf8WhoJGUQcT zukmJV@MmgN&WuTS&U%DEm{+oP&*Yfe-a{c%dS?55dSbohUVOE7uqKg1Hz8GbT-Lq8 zXlA8q`A4rP)(zvMneByZW5;$atCALVWB9JW*iJHiKC!mK=59SqbL(3+1OI%gR&|zu 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b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg.db new file mode 100644 index 0000000000000000000000000000000000000000..e466bdc128a17948b85351cd89a8dc9d34b82897 GIT binary patch literal 8192 zcmeI#&r8EF6bJCM2%cmz5Kn`!lY%xIWfSJbIg6JK)a@==o3*iRT9Pn-;AJ=QKlWy) z8{5r`w|yT;Uh;T3*Jv6a%!KX8VCqL00Izz00bZa0SG_<0uX?}jtf|4|G3d`7MGS!Gm#5pcr461yMu?I zKMClhe?1K7x_TlbI_Ek}xIUwqRO#llYS|Q0skWNS>ZVlo^!IO`l3Kds{CGYDAOHaf zKmY;|fB*y_009U<;C}=b_3DSe7>$nH!A;k1HCa;Rg7HX8u2?KBvwGSwA+sVcGj0Vd zb@3!Z%WkLQE;PZ5)nXQADKl{{<)aA8&eqnOCsDKKw|W=LrQLlWzbcyuBj2Qo>2sk| OZ*$L^w>?!@q3YilyJZak literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdep b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdep new file mode 100644 index 0000000..fbef846 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdep @@ -0,0 +1,22 @@ +#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761 +#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557731344 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630 +#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557731342 +#numinternalfiles:6 +#defaultlanguage:verilog +0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog +#Dependency Lists(Uses List) +0 -1 +#Dependency Lists(Users Of) +0 -1 +#Design Unit to File Association +module work sgmii_ecp5rsl_core 0 +module work sync 0 +module work sgmii_ecp5sll_core 0 +#Unbound instances to file Association. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr new file mode 100644 index 0000000..37d628b --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr @@ -0,0 +1 @@ +#XMR Information diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info new file mode 100644 index 0000000..ddcec68 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info @@ -0,0 +1,2 @@ +|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter 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zbJy+oWE?(|GmW&?R@GFF!+z%}lScPT>gA9KDkb(gko9ksZVN@6RSj P4@G|$duS$b_|X3WREeG! literal 0 HcmV?d00001 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg new file mode 100644 index 0000000..f6f3666 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg @@ -0,0 +1,252 @@ +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. 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true + disable_io_insertion: true + force_gsr: false + frequency: 100 + fanout_limit: 50 + retiming: false + pipe: false + part: LFE5UM-85F + speed_grade: 8 + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cst b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cst new file mode 100644 index 0000000..36253a2 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cst @@ -0,0 +1,3 @@ +Date=05/10/2019 +Time=14:33:07 + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.lpc b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.lpc new file mode 100644 index 0000000..bedc69e --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_200_125_100 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/10/2019 +Time=14:33:07 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=200 +CLKI_DIV=2 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=200 +CLKOP_TOL=0.0 +CLKOP_DIV=1 +CLKOP_ACTUAL_FREQ=200.000000 +CLKOP_MUXA=ENABLED +CLKOS_Enable=ENABLED +CLKOS_FREQ=100.00 +CLKOS_TOL=0.0 +CLKOS_DIV=5 +CLKOS_ACTUAL_FREQ=100.000000 +CLKOS_MUXB=DISABLED +CLKOS2_Enable=ENABLED +CLKOS2_FREQ=125.00 +CLKOS2_TOL=0.0 +CLKOS2_DIV=4 +CLKOS2_ACTUAL_FREQ=125.000000 +CLKOS2_MUXC=DISABLED +CLKOS3_Enable=DISABLED +CLKOS3_FREQ=125.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=1 +CLKOS3_ACTUAL_FREQ=0.000000 +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=INT_OS +CLKFB_DIV=1 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=500.000 +PLL_BW=10.695 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=ENABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n pll_200_125_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 125.00 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z531NB`+wX!jYIeFjqJaHFf7giaQ<`v(xX3qhk!#}!M1imCI*$14w rpeQFU2-|)PiQ^mOgar+8vV!n0(S*-!<|KuCffE$8g_D!-MNaHLndEu@ literal 0 HcmV?d00001 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd new file mode 100644 index 0000000..0b816a7 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd @@ -0,0 +1,82 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.7 +--/home/soft/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_200_125_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 125.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -lock -fb_mode 6 -fdc /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc + +-- Fri May 10 14:33:09 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_200_125_100 is + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic; + LOCK: out std_logic); +end pll_200_125_100; + +architecture Structure of pll_200_125_100 is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "125.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "13"; + attribute LPF_RESISTOR of PLLInst_0 : label is "24"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 3, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 4, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 0, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA=> "REFCLK", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 4, CLKOS_DIV=> 5, CLKOP_DIV=> 1, CLKFB_DIV=> 1, + CLKI_DIV=> 2, FEEDBK_PATH=> "INT_OS") + port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>CLKFB_t); + + CLKOS2 <= CLKOS2_t; + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100_ngd.asd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_240_100.lpc b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_240_100.lpc new file mode 100644 index 0000000..ffe81c0 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_240_100.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_240_100 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=07/11/2016 +Time=18:43:16 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=200 +CLKI_DIV=2 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=200 +CLKOP_TOL=0.0 +CLKOP_DIV=1 +CLKOP_ACTUAL_FREQ=200.000000 +CLKOP_MUXA=ENABLED +CLKOS_Enable=ENABLED +CLKOS_FREQ=100.00 +CLKOS_TOL=0.0 +CLKOS_DIV=6 +CLKOS_ACTUAL_FREQ=100.000000 +CLKOS_MUXB=DISABLED +CLKOS2_Enable=ENABLED +CLKOS2_FREQ=200 +CLKOS2_TOL=0.0 +CLKOS2_DIV=3 +CLKOS2_ACTUAL_FREQ=200.000000 +CLKOS2_MUXC=DISABLED +CLKOS3_Enable=ENABLED +CLKOS3_FREQ=120.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=5 +CLKOS3_ACTUAL_FREQ=120.000000 +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=INT_OS +CLKFB_DIV=1 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=600.000 +PLL_BW=8.185 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=ENABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 6 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/.recordref b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_CMD_.CML b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_CMD_.CML new file mode 100644 index 0000000..98806d1 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs -top pll_200_125_100 -hdllog /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml new file mode 100644 index 0000000..60abe88 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top pll_200_125_100 -osyn /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..8d0ce64 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm @@ -0,0 +1,163 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +SS1SS1SS1S +SF<1kCsOR"b=/lEFCF/#VD0/NH00O8C/HFNlMd8/3_4jG/nc#b$MLCN#/LDH/8PE/bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S> +SF<1kCsOR"b=/lEFC8/NsMHN/0oH/L0s6/#O0bClDCN0/Fbs[0CO/DbD_j.j_j.j_64._j4j/DbD_j.j_64._j4j/DbD_j.j_64._j4j38PE"=RN"RU"DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/ +"/ 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a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.areasrr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.areasrr new file mode 100644 index 0000000..9d560b3 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.areasrr @@ -0,0 +1,15 @@ +---------------------------------------------------------------------- +Report for cell pll_200_125_100.structure + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + EHXPLLL 1 100.0 + GSR 1 100.0 + PUR 1 100.0 + VHI 1 100.0 + VLO 1 100.0 + + TOTAL 5 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.fse b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.fse new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm new file mode 100644 index 0000000..a052015 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm @@ -0,0 +1,9 @@ + + + syntmp/pll_200_125_100_srr.htm log file + + + + + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj new file mode 100644 index 0000000..63c7206 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj @@ -0,0 +1,46 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj +#-- Written on Fri May 10 14:33:10 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" +add_file -constraint {"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"} + +#-- top module name +set_option -top_module pll_200_125_100 + +#-- set result format/file last +project -result_file "pll_200_125_100.edn" + +#-- error message log file +project -log_file pll_200_125_100.srf + +#-- run Synplify with 'arrange VHDL file' +project -run diff --git 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syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_200_125_100.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:12 2019 + +###########################################################] +Pre-mapping Report + +# Fri May 10 14:33:12 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc +@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 14:33:13 2019 + +###########################################################] +Map & Optimize Report + +# Fri May 10 14:33:13 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 14:33:15 2019 +# + + +Top view: pll_200_125_100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 +=================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 +================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKINTFB + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - +CLKFB_t Net - - - - 1 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +==================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +EHXPLLL: 1 +GSR: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Fri May 10 14:33:15 2019 + +###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm new file mode 100644 index 0000000000000000000000000000000000000000..cbb05bb7b732d977f12e9578bc15a1d612001329 GIT binary patch literal 5633 zcmV+c7XIlUiwFP!0000015#C0RVXORFG)=OcNV;JpN4zcQ2s${|u_%{Ey{7~JeKmn6)XEmfnA zoy`ple?tJ?V^G|IRL-)^4FN`WZZ=DdaUC1#O}udceh(i54nvnenH+`eJno!@@Xi=C{>zYPUDDzG= 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b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr @@ -0,0 +1,403 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 14:33:10 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_200_125_100.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:12 2019 + +###########################################################] +Pre-mapping Report + +# Fri May 10 14:33:12 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc +@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 14:33:13 2019 + +###########################################################] +Map & Optimize Report + +# Fri May 10 14:33:13 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 14:33:15 2019 +# + + +Top view: pll_200_125_100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 +=================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 +================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKINTFB + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - +CLKFB_t Net - - - - 1 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +==================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + 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HcmV?d00001 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm new file mode 100644 index 0000000..6274441 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm @@ -0,0 +1,108 @@ +-- +-- Written by Synplicity +-- Product Version "M-2017.03L-SP1-1" +-- Program "Synplify Pro", Mapper "maplat, Build 1796R" +-- Fri May 10 14:33:15 2019 +-- + +-- +-- Written by Synplify Pro version Build 1796R +-- Fri May 10 14:33:15 2019 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_200_125_100 is +port( + CLKI : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + CLKOS2 : out std_logic; + LOCK : out std_logic); +end pll_200_125_100; + +architecture beh of pll_200_125_100 is + signal CLKOS3 : std_logic ; + signal INTLOCK : std_logic ; + signal CLKFB_T : std_logic ; + signal REFCLK : std_logic ; + signal GND : std_logic ; + signal VCC : std_logic ; +begin +GND_0: VLO port map ( + Z => GND); +VCC_0: VHI port map ( + Z => VCC); +PUR_INST: PUR port map ( + PUR => VCC); +GSR_INST: GSR port map ( + GSR => VCC); +PLLINST_0: EHXPLLL + generic map( + CLKI_DIV => 2, + CLKFB_DIV => 1, + CLKOP_DIV => 1, + CLKOS_DIV => 5, + CLKOS2_DIV => 4, + CLKOS3_DIV => 1, + CLKOP_ENABLE => "ENABLED", + CLKOS_ENABLE => "ENABLED", + CLKOS2_ENABLE => "ENABLED", + CLKOS3_ENABLE => "DISABLED", + CLKOP_CPHASE => 0, + CLKOS_CPHASE => 4, + CLKOS2_CPHASE => 3, + CLKOS3_CPHASE => 0, + CLKOP_FPHASE => 0, + CLKOS_FPHASE => 0, + CLKOS2_FPHASE => 0, + CLKOS3_FPHASE => 0, + FEEDBK_PATH => "INT_OS", + CLKOP_TRIM_POL => "FALLING", + CLKOP_TRIM_DELAY => 0, + CLKOS_TRIM_POL => "FALLING", + CLKOS_TRIM_DELAY => 0, + OUTDIVIDER_MUXA => "REFCLK", + OUTDIVIDER_MUXB => "DIVB", + OUTDIVIDER_MUXC => "DIVC", + OUTDIVIDER_MUXD => "DIVD", + PLL_LOCK_MODE => 0, + STDBY_ENABLE => "DISABLED", + DPHASE_SOURCE => "DISABLED", + PLLRST_ENA => "DISABLED", + INTFB_WAKE => "DISABLED" + ) + port map ( + CLKI => CLKI, + CLKFB => CLKFB_T, + PHASESEL1 => GND, + PHASESEL0 => GND, + PHASEDIR => GND, + PHASESTEP => GND, + PHASELOADREG => GND, + STDBY => GND, + PLLWAKESYNC => GND, + RST => GND, + ENCLKOP => GND, + ENCLKOS => GND, + ENCLKOS2 => GND, + ENCLKOS3 => GND, + CLKOP => CLKOP, + CLKOS => CLKOS, + CLKOS2 => CLKOS2, + CLKOS3 => CLKOS3, + LOCK => LOCK, + INTLOCK => INTLOCK, + REFCLK => REFCLK, + CLKINTFB => CLKFB_T); +end beh; + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm new file mode 100644 index 0000000..bae9f65 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm @@ -0,0 +1,117 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Fri May 10 14:33:14 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 11 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc " + +`timescale 100 ps/100 ps +(* NGD_DRC_MASK=1 *)module pll_200_125_100 ( + CLKI, + CLKOP, + CLKOS, + CLKOS2, + LOCK +) +; +input CLKI ; +output CLKOP ; +output CLKOS ; +output CLKOS2 ; +output LOCK ; +wire CLKI ; +wire CLKOP ; +wire CLKOS ; +wire CLKOS2 ; +wire LOCK ; +wire CLKOS3 ; +wire INTLOCK ; +wire CLKFB_t ; +wire REFCLK ; +wire GND ; +wire VCC ; + VLO GND_0 ( + .Z(GND) +); + VHI VCC_0 ( + .Z(VCC) +); + PUR PUR_INST ( + .PUR(VCC) +); + GSR GSR_INST ( + .GSR(VCC) +); +// @8:56 +(* LPF_RESISTOR="24" , ICP_CURRENT="13" , FREQUENCY_PIN_CLKI="200.000000" , FREQUENCY_PIN_CLKOP="200.000000" , FREQUENCY_PIN_CLKOS="100.000000" , FREQUENCY_PIN_CLKOS2="125.000000" *) EHXPLLL PLLInst_0 ( + .CLKI(CLKI), + .CLKFB(CLKFB_t), + .PHASESEL1(GND), + .PHASESEL0(GND), + .PHASEDIR(GND), + .PHASESTEP(GND), + .PHASELOADREG(GND), + .STDBY(GND), + .PLLWAKESYNC(GND), + .RST(GND), + .ENCLKOP(GND), + .ENCLKOS(GND), + .ENCLKOS2(GND), + .ENCLKOS3(GND), + .CLKOP(CLKOP), + .CLKOS(CLKOS), + .CLKOS2(CLKOS2), + .CLKOS3(CLKOS3), + .LOCK(LOCK), + .INTLOCK(INTLOCK), + .REFCLK(REFCLK), + .CLKINTFB(CLKFB_t) +); +defparam PLLInst_0.CLKI_DIV = 2; +defparam PLLInst_0.CLKFB_DIV = 1; +defparam PLLInst_0.CLKOP_DIV = 1; +defparam PLLInst_0.CLKOS_DIV = 5; +defparam PLLInst_0.CLKOS2_DIV = 4; +defparam PLLInst_0.CLKOS3_DIV = 1; +defparam PLLInst_0.CLKOP_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED"; +defparam PLLInst_0.CLKOP_CPHASE = 0; +defparam PLLInst_0.CLKOS_CPHASE = 4; +defparam PLLInst_0.CLKOS2_CPHASE = 3; +defparam PLLInst_0.CLKOS3_CPHASE = 0; +defparam PLLInst_0.CLKOP_FPHASE = 0; +defparam PLLInst_0.CLKOS_FPHASE = 0; +defparam PLLInst_0.CLKOS2_FPHASE = 0; +defparam PLLInst_0.CLKOS3_FPHASE = 0; +defparam PLLInst_0.FEEDBK_PATH = "INT_OS"; +defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING"; +defparam PLLInst_0.CLKOP_TRIM_DELAY = 0; +defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING"; +defparam PLLInst_0.CLKOS_TRIM_DELAY = 0; +defparam PLLInst_0.OUTDIVIDER_MUXA = "REFCLK"; +defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB"; +defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC"; +defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD"; +defparam PLLInst_0.PLL_LOCK_MODE = 0; +defparam PLLInst_0.STDBY_ENABLE = "DISABLED"; +defparam PLLInst_0.DPHASE_SOURCE = "DISABLED"; +defparam PLLInst_0.PLLRST_ENA = "DISABLED"; +defparam PLLInst_0.INTFB_WAKE = "DISABLED"; +endmodule /* pll_200_125_100 */ + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf new file mode 100644 index 0000000..8e445e1 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf @@ -0,0 +1,20 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp2.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp4.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp8.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt new file mode 100644 index 0000000..f45a913 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt @@ -0,0 +1,75 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt +#-- Written on Fri May 10 14:33:10 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "pll_200_125_100" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./pll_200_125_100.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf" +impl -active "syn_results" diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scemi_cfg.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs new file mode 100644 index 0000000..6e19e6b --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs @@ -0,0 +1,73 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "pll_200_125_100" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf" +impl -active "syn_results" diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap new file mode 100644 index 0000000..3910cac --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr new file mode 100644 index 0000000..4501cf1 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr @@ -0,0 +1,51 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_200_125_100.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 14:33:11 2019 + +###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..b43ab41e45c47969ad26458f91fdda0c85ae5af4 GIT binary patch literal 8192 zcmeH~%}x|S5XWa11QT757{kGkbnu`?oSqN%BkMsCi5D&c7f+j>nSyC|rhDw}S-@~v zPR1wjHGCGI#+x8Rmie(IpD{NIf^=lPG%4a}-7e{t|*hb3SMSOS)SC143y0+xU!UpvM^#&>LRUr~V%t{S}8x7k@v29&R2htNPx$J698+Fvg;j*T`S;T(OZ6mpE;9nMd zELGo~w#K9lTy0btn^M8#4?V+s|M2nKN^Lv%gX+RIqS_?my7B`=*Fi1eNDN?kVo4dE T1HpEXS!uWw#9(*maXI}2tvZET literal 0 HcmV?d00001 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap new file mode 100644 index 0000000..4edadfd --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap @@ -0,0 +1 @@ +./synlog/pll_200_125_100_compiler.srr,pll_200_125_100_compiler.srr,Compile Log diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr new file mode 100644 index 0000000..fbbc4b8 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr @@ -0,0 +1,265 @@ +# Fri May 10 14:33:13 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 14:33:15 2019 +# + + +Top view: pll_200_125_100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 +=================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 +================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKINTFB + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - +CLKFB_t Net - - - - 1 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +==================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +EHXPLLL: 1 +GSR: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Fri May 10 14:33:15 2019 + +###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..b870b13d4949eba0a1365bfb82d753f885ed911c GIT binary patch literal 8192 zcmeH~&u`l{6vt(+YZ|m}wgG`L3;`Z;N`TsyU0W;C%aY9A2Dn(77-+E`3|e}UxJaZx zQf|GQa~k&F?Xttp`xAEAZI7~?30*-(q;0QPZj({WJ2si?c zfFs}tI0FB30;aLkJ~(KspBuKwFh{Lff_i&xo?nhnXJeS1o=wNF9X;X^ESU;Zrk+5? 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc +@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 14:33:13 2019 + +###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..d3d49fbbcb447f8a3dbecf9cf1e7bbb3fb033d75 GIT binary patch literal 8192 zcmeI#F;Buk6bJBYV`L(@7$%YzCP;)tC5;J-NN~bIWMgPb`zR;v9cfRaBb)I9`d!?- zLkMoh+5by>ukY@)O@7;ZxF1Wyw9rK!8M+iF!t=y6kr2Y)-8OB*v+L3B*(F#17QX0w zzEy3PS9=%sLO=il5P$##AOHafKmY;|fB*#kxq$I1^+v4>I-oAHSDyDgc}b5z93s5qlcs@0*|wH!89QvGON+c%{$Z8w|ywV9}W*aZOr2tWV= z5P$##AOHafKmY;|fWTh`Uj0hFx|yB&ceg3fc7^iwFP!0000016+-<4#F@DM0dWzOE-kmN?n+`urjenX=B=;w25qk1mfdK zk;;H{me1DHT~$?(IVlagZSwXSBJH~F{Ju;af;YQ)FA=bU?}lPpsrO>~)_H=tsftk9)3L#a8Rr6uF8 z1R1?8Ir#IWpmf}KQck-N#=p9o&gwFRyRo}I>vEHNU^3&($td)517&O!sFJmkmzJh? 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To preserve this instance, use the syn_noprune synthesis directive. + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml new file mode 100644 index 0000000..243c347 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_resourceusage.rpt +Resource Usage + + +0 + + +0 + + +0 + + +0 + + +0 + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt new file mode 100644 index 0000000..5e801a0 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt @@ -0,0 +1,8 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..7832235 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +0 / 0 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..b0bf07a --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +8 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt + + + +1 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt + + + +0h:00m:02s + + +0h:00m:02s + + +146MB + + +1557491595 + + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..60b8b51 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml @@ -0,0 +1,23 @@ + + + + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +System +100.0 MHz +NA +10.000 + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt new file mode 100644 index 0000000..ebff314 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt @@ -0,0 +1 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt new file mode 100644 index 0000000..eed8756 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt @@ -0,0 +1,2 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml new file mode 100644 index 0000000..00fedf8 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +2 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +143MB + + +1557491593 + + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap new file mode 100644 index 0000000..0213fed --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap @@ -0,0 +1 @@ +./pll_200_125_100_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/closed.png b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/closed.png new file mode 100644 index 0000000000000000000000000000000000000000..0d78634f322a904e7bd0c9466498c0a42777589f GIT binary patch literal 3672 zcmeH}={wX77sr2=$PzQiz6{y-jN4KYF_wtIP-F`kBBt#7AfeD8`@T=sp)7-;LX(KG zMk;%mvP`%|gL&rp8=kk%xjyH6uJhu1o$H)eClzjGdX8O~9RPrH=4QsW^a`dY=UFDY zzNFTs(+e}w@P;7(v}Qz8ZL;Y-#M8|71^^^;13(%*Pw1w20|1DL008n+0MJ_p0HM(! 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    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 14:33:10 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : pll_200_125_100.vhd(12) | Top entity is set to pll_200_125_100.
+VHDL syntax check successful!
+@N:CD630 : pll_200_125_100.vhd(12) | Synthesizing work.pll_200_125_100.structure.
+@N:CD630 : ecp5um.vhd(2083) | Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N:CD630 : ecp5um.vhd(832) | Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N:CD630 : ecp5um.vhd(825) | Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_200_125_100.structure
+@W:CL168 : pll_200_125_100.vhd(50) | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+
+
    +
    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:12 2019
+
+###########################################################]
+
+
     +
    +
+Pre-mapping Report
+
+
+
     +
    +
+# Fri May 10 14:33:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+Linked File: pll_200_125_100_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_200_125_100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 14:33:13 2019
+
+###########################################################]
+
+
     +
    +
+Map & Optimize Report
+
+
+
     +
    +
+# Fri May 10 14:33:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W:MT246 : pll_200_125_100.vhd(56) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 14:33:15 2019
+#
+
+
+Top view:               pll_200_125_100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 14:33:15 2019
+
+###########################################################]
+
+
     diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm new file mode 100644 index 0000000..75d317d --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml new file mode 100644 index 0000000..35a3688 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..c4d093f --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html @@ -0,0 +1,112 @@ + + + Project Status Summary Page + + + + + + +
    + + + + + + + + + + +
    Project Settings
    Project Name pll_200_125_100 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module pll_200_125_100
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete910-00m:01s-5/10/19
    2:33 PM
    (premap)Complete2000m:00s0m:00s143MB5/10/19
    2:33 PM
    (fpga_mapper)Complete8100m:02s0m:02s146MB5/10/19
    2:33 PM
    Multi-srs GeneratorComplete5/10/19
    2:33 PM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 0I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 0

    + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    System100.0 MHzNA10.000
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 0 / 0

    +
    +
    + \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer new file mode 100644 index 0000000000000000000000000000000000000000..8d68b51ffc123b9e9915c50b3dcd0e75f3d66b87 GIT binary patch literal 456 zcmV;(0XP01iwFP!0000015#C0RVXORFG)=a{vaLcI6*^mGAZ z9&d$5|4m>w&WRYZ^EqN=LB_ZWh}q~zk2Uk~$$!>h^&qn$=dq*jHKwE;j_u+XZtHC~ zDNT4e?*X*S(*o6H9cA=h&$Pzfmm}Kaa{u{+cCnIZV+gS}JPc0_dT99AVHbpaleyTW z4!H}+L1lQ)Hzb*CX3|WO4L&m5Wz@{%6d@nk5$cD=2BdNn=ZsD)GPd9;qzR+vFc}e~ z2Qh;jbI7n%R4Y?LN*0BzTz?sj^@BY}(sz)5lWgP>C2WvXKbnlYvQysXt zlt$8U)tl>rHmTB(wH5=!6KU{Cw^SU!7Z277ipzuK2 z4HO-tYY2GTmY0HmXs%6>Hv#?gpA>+}_^lTNUo9bKj7XSeN{{sNLV`sjt0ssK%qu^!$ literal 0 HcmV?d00001 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info new file mode 100644 index 0000000..37bc105 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info @@ -0,0 +1 @@ +|1| diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep new file mode 100644 index 0000000..0d906a3 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep @@ -0,0 +1,28 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 +0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work pll_200_125_100 structure 0 +module work pll_200_125_100 0 + + +# Configuration files used diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig new file mode 100644 index 0000000..7b38ff3 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig @@ -0,0 +1,24 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589 +0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work pll_200_125_100 structure 0 +module work pll_200_125_100 0 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs new file mode 100644 index 0000000000000000000000000000000000000000..b9cb7b8176f7c01c4120f5032e22ba2349cb106b GIT binary patch literal 6188 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:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_200_125_100.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. 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a/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.sbx b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.sbx new file mode 100644 index 0000000..e683721 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.sbx @@ -0,0 +1,617 @@ + + + + LATTICE + LOCAL + pll_200_200_125_100 + 1.0 + + + Diamond_Synthesis + synthesis + + ./pll_200_200_125_100.vhd + vhdlSource + + + + Diamond_Simulation + simulation + + ./pll_200_200_125_100.vhd + vhdlSource + + + + + + + + + pll_200_125_100_CLKI + pll_200_125_100_CLKI + + in + + + + pll_200_125_100.CLKI + + + + + pll_200_125_100_CLKOP + pll_200_125_100_CLKOP + + out + + + + pll_200_125_100.CLKOP + + + + + pll_200_125_100_CLKOS + pll_200_125_100_CLKOS + + out + + + + pll_200_125_100.CLKOS + + + + + pll_200_125_100_CLKOS2 + pll_200_125_100_CLKOS2 + + out + + + + pll_200_125_100.CLKOS2 + + + + + pll_200_125_100_LOCK + pll_200_125_100_LOCK + + out + + + + pll_200_125_100.LOCK + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-05-10.02:28:17 PM + 2019-05-10.02:38:07 PM + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + pll_200_200_125_100 + 1.0 + + + pll_200_125_100 + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.8 + + + Diamond_Simulation + simulation + + ./pll_200_125_100/pll_200_125_100.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./pll_200_125_100/pll_200_125_100.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + CLKI + CLKI + + in + + + + CLKOP + CLKOP + + out + + + + CLKOS + CLKOS + + out + + + + CLKOS2 + CLKOS2 + + out + + + + LOCK + LOCK + + out + + + + + + synplify + 2019-05-10.02:38:07 PM + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/10/2019 + + + ModuleName + pll_200_125_100 + + + ParameterFileVersion + 1.0 + + + SourceFormat + VHDL + + + Time + 14:33:07 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 1 + + + CLKI_DIV + 2 + + + CLKI_FREQ + 200 + + + CLKOP_ACTUAL_FREQ + 200.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 1 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 200 + + + CLKOP_MUXA + ENABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + 125.000000 + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 4 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + ENABLED + + + CLKOS2_FREQ + 125.00 + + + CLKOS2_MUXC + DISABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + 0.000000 + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 125.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + 100.000000 + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 5 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + ENABLED + + + CLKOS_FREQ + 100.00 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + INT_OS + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 10.695 + + + PLL_LOCK_MODE + ENABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 500.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_200_125_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 125.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -lock -fb_mode 6 + + + + + + + + + + pll_200_125_100_CLKI + pll_200_125_100_CLKI + + + + + pll_200_125_100_CLKOP + pll_200_125_100_CLKOP + + + + + pll_200_125_100_CLKOS + pll_200_125_100_CLKOS + + + + + pll_200_125_100_CLKOS2 + pll_200_125_100_CLKOS2 + + + + + pll_200_125_100_LOCK + pll_200_125_100_LOCK + + + + + + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.vhd b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.vhd new file mode 100644 index 0000000..4d11d32 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.vhd @@ -0,0 +1,39 @@ + + +-- +-- Verific VHDL Description of module pll_200_200_125_100 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity pll_200_200_125_100 is + port (pll_200_125_100_CLKI: in std_logic; + pll_200_125_100_CLKOP: out std_logic; + pll_200_125_100_CLKOS: out std_logic; + pll_200_125_100_CLKOS2: out std_logic; + pll_200_125_100_LOCK: out std_logic + ); + +end entity pll_200_200_125_100; -- sbp_module=true + +architecture pll_200_200_125_100 of pll_200_200_125_100 is + component pll_200_125_100 is + port (CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic; + LOCK: out std_logic + ); + + end component pll_200_125_100; -- not_need_bbox=true + + + +begin + pll_200_125_100_inst: component pll_200_125_100 port map (CLKI=>pll_200_125_100_CLKI, + CLKOP=>pll_200_125_100_CLKOP,CLKOS=>pll_200_125_100_CLKOS,CLKOS2=>pll_200_125_100_CLKOS2, + LOCK=>pll_200_125_100_LOCK); + +end architecture pll_200_200_125_100; -- sbp_module=true + diff --git a/gbe/cores/pll_200_200_125_100/pll_200_200_125_100_tmpl.v b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100_tmpl.v new file mode 100644 index 0000000..b457271 --- /dev/null +++ b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100_tmpl.v @@ -0,0 +1,4 @@ +//Verilog instantiation template + +pll_200_200_125_100 _inst (.pll_200_125_100_CLKI(), .pll_200_125_100_CLKOP(), + .pll_200_125_100_CLKOS(), .pll_200_125_100_CLKOS2(), .pll_200_125_100_LOCK()); \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/PCSD.cmd b/gbe/cores/sgmii/PCSD/PCSD.cmd new file mode 100644 index 0000000..3271b96 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/PCSD.cmd @@ -0,0 +1,18 @@ +PROJECT: PCSD + working_path: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results" + module: PCSD + verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" + vlog_std_v2001: true + constraint_file_name: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc" + suffix_name: edn + output_file_name: PCSD + write_prf: true + disable_io_insertion: true + force_gsr: false + frequency: 100 + fanout_limit: 50 + retiming: false + pipe: false + part: LFE5UM-85F + speed_grade: 8 + diff --git a/gbe/cores/sgmii/PCSD/PCSD.cst b/gbe/cores/sgmii/PCSD/PCSD.cst new file mode 100644 index 0000000..d8a88c1 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/PCSD.cst @@ -0,0 +1,3 @@ +Date=04/29/2019 +Time=14:57:43 + diff --git a/gbe/cores/sgmii/PCSD/PCSD.fdc b/gbe/cores/sgmii/PCSD/PCSD.fdc new file mode 100644 index 0000000..c667056 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/PCSD.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU0_CH1} diff --git a/gbe/cores/sgmii/PCSD/PCSD.lpc b/gbe/cores/sgmii/PCSD/PCSD.lpc new file mode 100644 index 0000000..5b775f6 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/PCSD.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=04/29/2019 +ModuleName=PCSD +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=14:57:43 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=10X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=2 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Disabled +SOFTLOL=Disabled +TX8B10B=Enabled +TXAMPLITUDE=1100 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +PCSD.pp=pp +PCSD.sym=sym +PCSD.tft=tft +PCSD.txt=pcs_module +[SYSTEMPNR] +LN0=DCU0_CH1 diff --git a/gbe/cores/sgmii/PCSD/PCSD.ngd b/gbe/cores/sgmii/PCSD/PCSD.ngd new file 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zt+Cx^5WCLL#?!EmSYgy0XJ8F7IvrvaDx($-%ZqEYq&i2b6mtvkeiD=_K-vA_I`E`)d;qij!z9~fd=FNhy(l)VVzhv;nU z4e`T`vV9=l#Lu?AIJKBj_F{U;}qe~&)TxZk|;w_D`mqEOZpKU>ipKaLs zL%c(dZC60Ni-86}Tq&~cN{CA%^5B-d;g7~EYMuQ;UKgeh>#IFo7x*FnFXBZ8E z_%#JaLm@sg$LJb}SNB#9gZQ{C+lJ$;4h+gd5KkMnYjMVd3>!y4{6?dekr2N*&$dwz zpW$P49mMID6_?QvzbDUV48-T>7>$Ma0tWd0ocO{b!*LK_oMAK`;!BOP6Cl1U&$ckc zmm6gx5PzOc_|}g2>HtF(;_EVu$|1hqC|d#XH}Y(YL42c8HV$#)`UKw<5Z`Q+P2w}D zM%fg^w;5$CA+8%`(-7ZYAlXD`v=)-bWf`r5WYZiY?9e;a zu)Pe)7Hq;{`(!JH;j54g6d1h*$#w>M9g^o6Xagj>`q=v>B>M#!y#>j^I-`w{tiGdq z8W7Bx3L@5(XyFC^!N7<~%K z`5L3oAo&1;G98i&bcSE!+%tYg-{6chK}O#~a;?tjJ4mkgGujEsHw^SWBsUu92S{!* zP!XSqH_(re{3ujL%TJK}R%7%tB!9>-`UR3dD~xtQ@>c`x#-|*8Z2J|G{}|{uNYypa z?~tl*pgoXkXrMnJby$!~{0XTe4D=VIjyBNWkUHK#|3Ip#PH}h*mO3TJs1Br>8weoP zQej(NNS$S%10dDbKnFsqeTKdDAl1o0^&!>OKnFppyMYddR4)THfK=an87_4iLaLv! zjYg2_Po}auhv07oGK>y|)SxV*!yq-pu=yZ0%*VFFAr&ezY7D878lxj{JTk!ONJw2D zWONjcJrXFZ(*#nHETf|#Rjx8R22yc9qhleJEHXL{Qt1q%;~_Q4$LIt|P1YEli1QK! z7&WCKC`KpI@Dn3H4LvbBnTDMhokBxSj83KDCPvL@sEN^OG_u5~ISnK+I-SOi7`32b zB1UJ>s1T!;Gzi3~6^;2YYE45tjLxJH9Y$x-01l%zG+x6fK*KYP&Zf~AMr~>Eh0!@Q z*1`x!UXIimol7GrjM~${38V99oP<#a8Wv&Hkw!rnb)rEJMxANEgVFgk*ue;|!v<=M zy3!yAqi!_7!APOO4MrExzy_o4G^oL-2MuU2x{wAl81O%t;jQY}`1*3~;z=F{wG+4ptQW~gW)Q<)!7+ppK6pVs2IKk+08kk_zp9UouT|om9 zj0VtP1fwfyAcE0A8iZhU6%9Zz8bpH+j0V%d1EZ^H(1Fnq8gO7Vlm;6ZT|)y6jE2!5 z1Eb+Iz`!U(gA0tVrGW)TBWO^8(MTFlU^I#b6Bu1b0||^q(;xz)F*Ja{Xeda?!Gj-%Mx`jIN8Qn@9_>87g=RKp_sN"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n112,CH1_HDINP=>hdinp,CH0_HDINN=>n112,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n112,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n111,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n111,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n111,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n112,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n112,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n112,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n112,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n112,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n112,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n112,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n112,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n112,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n112,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n112,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n112,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n112,CH1_FF_TX_D_12=>n112,CH0_FF_TX_D_13=>n112,CH1_FF_TX_D_13=>n112, + CH0_FF_TX_D_14=>n112,CH1_FF_TX_D_14=>n112,CH0_FF_TX_D_15=>n112,CH1_FF_TX_D_15=>n112, + CH0_FF_TX_D_16=>n112,CH1_FF_TX_D_16=>n112,CH0_FF_TX_D_17=>n112,CH1_FF_TX_D_17=>n112, + CH0_FF_TX_D_18=>n112,CH1_FF_TX_D_18=>n112,CH0_FF_TX_D_19=>n112,CH1_FF_TX_D_19=>n112, + CH0_FF_TX_D_20=>n112,CH1_FF_TX_D_20=>n112,CH0_FF_TX_D_21=>n112,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n112,CH1_FF_TX_D_22=>n112,CH0_FF_TX_D_23=>n112,CH1_FF_TX_D_23=>n112, + CH0_FFC_EI_EN=>n112,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n112,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n112,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n112,CH1_FFC_SB_INV_RX=>n112, + CH0_FFC_ENABLE_CGALIGN=>n112,CH1_FFC_ENABLE_CGALIGN=>n112,CH0_FFC_SIGNAL_DETECT=>n112, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n112,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n112,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n112, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n112,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n112,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n112, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n112,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n112,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n112, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n112,CH1_FFC_LDR_CORE2TX_EN=>n112, + CH0_FFC_LANE_TX_RST=>n112,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n112, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n112,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n112,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n112, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n112,CH1_LDR_CORE2TX=>n112, + D_SCIWDATA0=>n112,D_SCIWDATA1=>n112,D_SCIWDATA2=>n112,D_SCIWDATA3=>n112, + D_SCIWDATA4=>n112,D_SCIWDATA5=>n112,D_SCIWDATA6=>n112,D_SCIWDATA7=>n112, + D_SCIADDR0=>n112,D_SCIADDR1=>n112,D_SCIADDR2=>n112,D_SCIADDR3=>n112, + D_SCIADDR4=>n112,D_SCIADDR5=>n112,D_SCIENAUX=>n112,D_SCISELAUX=>n112, + CH0_SCIEN=>n112,CH1_SCIEN=>n112,CH0_SCISEL=>n112,CH1_SCISEL=>n112,D_SCIRD=>n112, + D_SCIWSTN=>n112,D_CYAWSTN=>n112,D_FFC_SYNC_TOGGLE=>n112,D_FFC_DUAL_RST=>rsl_rst_dual_c, + D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c, + CH0_FFC_CDR_EN_BITSLIP=>n112,CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44, + D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44,D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44, + D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44,D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44, + D_SCAN_MODE=>n44,D_SCAN_RESET=>n44,D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44, + D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44,D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44, + D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44,CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp, + CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2, + D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5, + CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7, + CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9, + CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0), + CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2), + CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4), + CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6), + CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0), + CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n65, + CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66,CH1_FF_RX_D_11=>n10, + CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69,CH1_FF_RX_D_13=>n70, + CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73,CH1_FF_RX_D_15=>n74, + CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77,CH1_FF_RX_D_17=>n78, + CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81,CH1_FF_RX_D_19=>n82, + CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85,CH1_FF_RX_D_21=>n86, + CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89,CH1_FF_RX_D_23=>n11, + CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91,CH1_FFS_PCIE_CON=>n13, + CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n93, + CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94,CH1_FFS_CC_UNDERRUN=>ctc_urun_s, + CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s,CH0_FFS_RXFBFIFO_ERROR=>n96, + CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97,CH1_FFS_TXFBFIFO_ERROR=>n15, + CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n99, + CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100,CH1_FFS_SKP_DELETED=>ctc_del_s, + CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n102,D_SCIRDATA0=>n103,D_SCIRDATA1=>n104, + D_SCIRDATA2=>n105,D_SCIRDATA3=>n106,D_SCIRDATA4=>n107,D_SCIRDATA5=>n108, + D_SCIRDATA6=>n109,D_SCIRDATA7=>n110,D_SCIINT=>n121,D_SCAN_OUT_0=>n16, + D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19,D_SCAN_OUT_4=>n20, + D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23,D_COUT0=>n24,D_COUT1=>n25, + D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29,D_COUT6=>n30,D_COUT7=>n31, + D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35,D_COUT12=>n36, + D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40,D_COUT17=>n41, + D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n112 <= '0' ; + n111 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n102 <= 'Z' ; + n103 <= 'Z' ; + n104 <= 'Z' ; + n105 <= 'Z' ; + n106 <= 'Z' ; + n107 <= 'Z' ; + n108 <= 'Z' ; + n109 <= 'Z' ; + n110 <= 'Z' ; + n121 <= 'Z' ; + rsl_inst: component PCSDrsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>gnd, + rui_tx_pcs_rst_c(2)=>gnd,rui_tx_pcs_rst_c(1)=>gnd,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>gnd, + rui_rx_serdes_rst_c(2)=>gnd,rui_rx_serdes_rst_c(1)=>gnd,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>gnd,rui_rx_pcs_rst_c(2)=>gnd,rui_rx_pcs_rst_c(1)=>gnd, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>gnd,rdi_rx_los_low_s(2)=>gnd, + rdi_rx_los_low_s(1)=>gnd,rdi_rx_los_low_s(0)=>rx_los_low_s_c,rdi_rx_cdr_lol_s(3)=>gnd, + rdi_rx_cdr_lol_s(2)=>gnd,rdi_rx_cdr_lol_s(1)=>gnd,rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c, + rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,rdo_rst_dual_c=>rsl_rst_dual_c, + ruo_tx_rdy=>n122,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,rdo_tx_pcs_rst_c(3)=>n123, + rdo_tx_pcs_rst_c(2)=>n124,rdo_tx_pcs_rst_c(1)=>n125,rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c, + ruo_rx_rdy=>n126,rdo_rx_serdes_rst_c(3)=>n127,rdo_rx_serdes_rst_c(2)=>n128, + rdo_rx_serdes_rst_c(1)=>n129,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n130,rdo_rx_pcs_rst_c(2)=>n131,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n120 <= '1' ; + n119 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + n122 <= 'Z' ; + n123 <= 'Z' ; + n124 <= 'Z' ; + n125 <= 'Z' ; + n126 <= 'Z' ; + n127 <= 'Z' ; + n128 <= 'Z' ; + n129 <= 'Z' ; + n130 <= 'Z' ; + n131 <= 'Z' ; + \_Z\ <= 'Z' ; + +end architecture v1; + diff --git a/gbe/cores/sgmii/PCSD/PCSD_ngd.asd b/gbe/cores/sgmii/PCSD/PCSD_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/PCSD_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/sgmii/PCSD/PCSD_softlogic.v b/gbe/cores/sgmii/PCSD/PCSD_softlogic.v new file mode 100644 index 0000000..fa4373f --- /dev/null +++ b/gbe/cores/sgmii/PCSD/PCSD_softlogic.v @@ -0,0 +1,943 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module PCSDrsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i + + syntmp/PCSD_srr.htm log file + + + + + + diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.prj b/gbe/cores/sgmii/PCSD/syn_results/PCSD.prj new file mode 100644 index 0000000..a95f061 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.prj @@ -0,0 +1,47 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.prj +#-- Written on Tue Apr 30 12:09:44 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" +add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" +add_file -constraint {"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc"} + +#-- top module name +set_option -top_module PCSD + +#-- set result format/file last +project -result_file "PCSD.edn" + +#-- error message log file +project -log_file PCSD.srf + +#-- run Synplify with 'arrange VHDL file' +project -run diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srd b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srd new file mode 100644 index 0000000000000000000000000000000000000000..dc4f84c592f696354e402972201947c1f8949424 GIT binary patch literal 41535 zcmaI7cQl;e7x0^eL`07udO{Fg^g1FEy(9?HBStrRXNahYGSQK7X9`>{ItyYoB$_+Mm5yqaNP*-$yVqqv^c#>?zTSKj6L_&ABKw zYF59w%-(-lw0M!c^%*Gy#6bG6YAFD>E>_;tqF&T+dLKwgA#Z`kcu2pSO}!&4i+N_t zO{1ZfxV9+zwVj(lpO0|xF3BK6-hHzTpc3n>`hoW%?FfN>O{Xb;6$Kjv+@Qb(W)@Aa zdYo(G$DmBZmR@9Irq1yv9*}cDGI)`fEH%D1BV>EzB|bUsh`tp9$(0*A9yF*$0!4eD zJv0=gUJl@sToGS=q3se?y}H=QS?4R(<1c_O=3+YQtOkv9L1~0ufN*zReu(EQmsa~J zoXe{>@Soi{`7jC%k}bj^Yr*u3^{0R#J;5D}+q{y_-OcBr0Rs6^Gg*MMzK1~%Q(5o2 z{mdr-x)MfiQ<}$cW7ShKhETRodHFAwz0bcIUdNoSq`z{eU|z&ouHAUcewxkp7cz3q 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z{JR6g;%~=&s=jUG4y$LB#lL?vtbhL~AD`<1{l0f5*YC*{-!~l=e<^M8t-2xm9$m-1 zcq+a#TAPO!SVw+3|Hf!BuCuwOzDxiAAXWj$fEfDyb2(g-hi($mm$Dh^pInke^D-(Y zBi3c&KZF{!{bgnmFG<+>odwyYOcG`@dLEZJ*eCNmH}c3T3D)-zp+g65SI)oZ<=)5% s{Z>q7`6TH2UU#M4cJQD71pom5|Kf5`-~s>u0RR630Ib-HhPnR&0J2`~VE_OC literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srf b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srf new file mode 100644 index 0000000..6d9a5e2 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srf @@ -0,0 +1,829 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Tue Apr 30 12:09:44 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) + + +Process completed successfully. +# Tue Apr 30 12:09:44 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1. +Post processing for work.pcsd.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = PCSDrsl_core_Z1_layer1 +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:46 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:46 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:47 2019 + +###########################################################] +# Tue Apr 30 12:09:47 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist PCSD + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +----------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59 + +0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 33 +===================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Apr 30 12:09:48 2019 + +###########################################################] +# Tue Apr 30 12:09:48 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:00s 5.36ns 63 / 92 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=================================== Non-Gated/Non-Generated Clocks ==================================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +------------------------------------------------------------------------------------------------------- +@K:CKID0001 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18] +@K:CKID0002 pll_refclki port 33 rsl_inst.genblk1\.pll_lol_p1 +======================================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Apr 30 12:09:50 2019 +# + + +Top view: PCSD +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------- +PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup +========================================================================================================================= + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths - +PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths - +PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths - +PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +=========================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PCSD|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by PCSD|pll_refclki [rising] on pin CK + The end point is clocked by PCSD|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: PCSD|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[16] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[17] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +=============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by PCSD|rxrefclk [rising] on pin CK + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946 +DCU0_inst System DCUA CH0_FF_TX_PCLK tx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_EBRD_CLK tx_pclk 10.000 10.000 +DCU0_inst System DCUA CH0_FF_RXI_CLK tx_pclk 10.000 10.000 +================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 9.946 + + Number of logic level(s): 0 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.rlol_p1 / D + The start point is clocked by System [rising] + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 2 +rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 - +=================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 92 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 37 +DCUA: 1 +FD1P3BX: 4 +FD1P3DX: 42 +FD1S3BX: 10 +FD1S3DX: 36 +GSR: 1 +ORCALUT4: 63 +PFUMX: 2 +PUR: 1 +VHI: 2 +VLO: 2 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Tue Apr 30 12:09:51 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srm b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srm new file mode 100644 index 0000000000000000000000000000000000000000..ad3a4ed9d936a32ea5e4176f9fc9e80060ff5db1 GIT binary patch literal 27644 zcmaI;cT^MI7x0gYfQYmQk=|4UL?ATjO;A8VKt*~7X+r2NhK>}e(tA+^q;~=YLMQYt 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+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Tue Apr 30 12:09:44 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) + + +Process completed successfully. +# Tue Apr 30 12:09:44 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1. +Post processing for work.pcsd.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = PCSDrsl_core_Z1_layer1 +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:46 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:46 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:47 2019 + +###########################################################] +# Tue Apr 30 12:09:47 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist PCSD + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +----------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59 + +0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 33 +===================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Apr 30 12:09:48 2019 + +###########################################################] +# Tue Apr 30 12:09:48 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:00s 5.36ns 63 / 92 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=================================== Non-Gated/Non-Generated Clocks ==================================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +------------------------------------------------------------------------------------------------------- +@K:CKID0001 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18] +@K:CKID0002 pll_refclki port 33 rsl_inst.genblk1\.pll_lol_p1 +======================================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Apr 30 12:09:50 2019 +# + + +Top view: PCSD +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------- +PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup +========================================================================================================================= + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths - +PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths - +PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths - +PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +=========================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PCSD|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by PCSD|pll_refclki [rising] on pin CK + The end point is clocked by PCSD|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: PCSD|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[16] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[17] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +=============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by PCSD|rxrefclk [rising] on pin CK + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946 +DCU0_inst System DCUA CH0_FF_TX_PCLK tx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_EBRD_CLK tx_pclk 10.000 10.000 +DCU0_inst System DCUA CH0_FF_RXI_CLK tx_pclk 10.000 10.000 +================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 9.946 + + Number of logic level(s): 0 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.rlol_p1 / D + The start point is clocked by System [rising] + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 2 +rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 - +=================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 92 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 37 +DCUA: 1 +FD1P3BX: 4 +FD1P3DX: 42 +FD1S3BX: 10 +FD1S3DX: 36 +GSR: 1 +ORCALUT4: 63 +PFUMX: 2 +PUR: 1 +VHI: 2 +VLO: 2 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Tue Apr 30 12:09:51 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr.db b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..147c921bedeb062df4c5f1fba1a344132df57a44 GIT binary patch literal 24576 zcmeHP-)|gO6<$035hvcb4Ru2)fg6{!b{p^R%OGb?t1X- z%yedUZAV6EtxBMZzks)tMdeS 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Program "Synplify Pro", Mapper "maplat, Build 1796R" +-- Tue Apr 30 12:09:50 2019 +-- + +-- +-- Written by Synplify Pro version Build 1796R +-- Tue Apr 30 12:09:50 2019 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity PCSDrsl_core_Z1_layer1 is +port( + serdes_rst_dual_c : in std_logic; + rx_serdes_rst_c : in std_logic; + tx_serdes_rst_c : in std_logic; + rsl_rx_pcs_rst_c : out std_logic; + rx_pcs_rst_c : in std_logic; + rsl_tx_pcs_rst_c : out std_logic; + tx_pcs_rst_c : in std_logic; + rsl_disable : in std_logic; + rsl_tx_serdes_rst_c : out std_logic; + pll_lol : in std_logic; + pll_refclki : in std_logic; + rx_cdr_lol_s : in std_logic; + rx_los_low_s : in std_logic; + rsl_rst : in std_logic; + rxrefclk : in std_logic; + rsl_rx_serdes_rst_c : out std_logic; + rsl_serdes_rst_dual_c : out std_logic); +end PCSDrsl_core_Z1_layer1; + +architecture beh of PCSDrsl_core_Z1_layer1 is + signal PLOL0_CNT : std_logic_vector(2 downto 0); + signal PLOL0_CNT_3 : std_logic_vector(2 downto 0); + signal RXS_CNT_3 : std_logic_vector(1 downto 0); + signal RXS_CNT : std_logic_vector(1 downto 0); + signal RXS_CNT_QN : std_logic_vector(1 downto 0); + signal RLOS_DB_CNT : std_logic_vector(3 downto 0); + signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0); + signal RLOLS0_CNT_S : std_logic_vector(17 downto 0); + signal RLOLS0_CNT : std_logic_vector(17 downto 0); + signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0); + signal RLOL_DB_CNT : std_logic_vector(3 downto 0); + signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0); + signal RLOL1_CNT_S : std_logic_vector(18 downto 0); + signal RLOL1_CNT : std_logic_vector(18 downto 0); + signal RLOL1_CNT_QN : std_logic_vector(18 downto 0); + signal TXS_CNT : std_logic_vector(1 downto 0); + signal TXS_CNT_QN : std_logic_vector(1 downto 0); + signal TXS_CNT_RNO : std_logic_vector(1 to 1); + signal TXP_CNT : std_logic_vector(1 downto 0); + signal TXP_CNT_QN : std_logic_vector(1 downto 0); + signal TXP_CNT_RNO : std_logic_vector(1 to 1); + signal PLOL_CNT_S : std_logic_vector(19 downto 0); + signal PLOL_CNT : std_logic_vector(19 downto 0); + signal PLOL_CNT_QN : std_logic_vector(19 downto 0); + signal PLOL0_CNT_QN : std_logic_vector(2 downto 0); + signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0); + signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0); + signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); + signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); + signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); + signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); + signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0); + signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0); + signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17); + signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0); + signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0); + signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17); + signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17); + signal PLOL_CNT_CRY : std_logic_vector(18 downto 0); + signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0); + signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19); + signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19); + signal RSL_SERDES_RST_DUAL_C_6 : std_logic ; + signal RSL_RX_SERDES_RST_C_5 : std_logic ; + signal RLOS_DB_P1 : std_logic ; + signal RLOS_DB : std_logic ; + signal RXP_RST25 : std_logic ; + signal PLOL0_CNT9 : std_logic ; + signal WAITA_PLOL0 : std_logic ; + signal RLOL1_CNT_TC_1 : std_logic ; + signal RXS_RST : std_logic ; + signal \RLOL1_CNT_\ : std_logic ; + signal WAITA_RLOLS06 : std_logic ; + signal UN1_RLOLS0_CNT_TC : std_logic ; + signal WAITA_RLOLS0 : std_logic ; + signal WAITA_RLOLS0_QN : std_logic ; + signal VCC : std_logic ; + signal WAIT_CALIB_RNO : std_logic ; + signal UN1_RLOS_FEDGE_1 : std_logic ; + signal WAIT_CALIB : std_logic ; + signal WAIT_CALIB_QN : std_logic ; + signal RXS_RST6 : std_logic ; + signal UN1_RXS_CNT_TC : std_logic ; + signal RXS_RST_QN : std_logic ; + signal UN2_RLOS_REDGE_1_I : std_logic ; + signal RXP_RST2 : std_logic ; + signal RXP_RST2_QN : std_logic ; + signal RLOS_P1 : std_logic ; + signal RLOS_P2 : std_logic ; + signal RLOS_P2_QN : std_logic ; + signal RLOS_P1_QN : std_logic ; + signal RLOS_DB_P1_QN : std_logic ; + signal RLOS_DB_CNT_AXB_0 : std_logic ; + signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ; + signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ; + signal RLOS_DB_CNT_S_3_0_S0 : std_logic ; + signal UN1_RLOS_DB_CNT_MAX : std_logic ; + signal RLOS_DB_QN : std_logic ; + signal RLOLS0_CNTE : std_logic ; + signal RLOL_P1 : std_logic ; + signal RLOL_P2 : std_logic ; + signal RLOL_P2_QN : std_logic ; + signal RLOL_P1_QN : std_logic ; + signal RLOL_DB : std_logic ; + signal RLOL_DB_P1 : std_logic ; + signal RLOL_DB_P1_QN : std_logic ; + signal RLOL_DB_CNT_AXB_0 : std_logic ; + signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ; + signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ; + signal RLOL_DB_CNT_S_3_0_S0 : std_logic ; + signal UN1_RLOL_DB_CNT_MAX : std_logic ; + signal RLOL_DB_QN : std_logic ; + signal RLOL1_CNTE : std_logic ; + signal PLOL_FEDGE : std_logic ; + signal UN1_PLOL0_CNT_TC_1_I : std_logic ; + signal WAITA_PLOL0_QN : std_logic ; + signal UN1_PLOL_CNT_TC : std_logic ; + signal UN2_PLOL_CNT_TC : std_logic ; + signal TXS_RST : std_logic ; + signal TXS_RST_QN : std_logic ; + signal N_12_I : std_logic ; + signal UN9_PLOL0_CNT_TC : std_logic ; + signal UN1_PLOL0_CNT_TC_1 : std_logic ; + signal TXP_RST : std_logic ; + signal TXP_RST_QN : std_logic ; + signal N_13_I : std_logic ; + signal PLL_LOL_P2 : std_logic ; + signal PLL_LOL_P3 : std_logic ; + signal PLL_LOL_P3_QN : std_logic ; + signal PLL_LOL_P1 : std_logic ; + signal PLL_LOL_P2_QN : std_logic ; + signal PLL_LOL_P1_QN : std_logic ; + signal RLOLS0_CNT_TC_1 : std_logic ; + signal RLOS_REDGE : std_logic ; + signal RLOLS0_CNT11_0 : std_logic ; + signal RSL_TX_SERDES_RST_C_4 : std_logic ; + signal \PLOL_CNT_\ : std_logic ; + signal \RLOLS0_CNT_\ : std_logic ; + signal UN8_RXS_CNT_TC : std_logic ; + signal UN1_PLOL_CNT_TC_11 : std_logic ; + signal UN1_PLOL_CNT_TC_12 : std_logic ; + signal UN1_PLOL_CNT_TC_13 : std_logic ; + signal UN1_PLOL_CNT_TC_14 : std_logic ; + signal RLOLS0_CNT_TC_1_10 : std_logic ; + signal RLOLS0_CNT_TC_1_11 : std_logic ; + signal RLOLS0_CNT_TC_1_12 : std_logic ; + signal RLOLS0_CNT_TC_1_13 : std_logic ; + signal RLOL1_CNT_TC_1_11 : std_logic ; + signal RLOL1_CNT_TC_1_12 : std_logic ; + signal RLOL1_CNT_TC_1_13 : std_logic ; + signal RLOL1_CNT_TC_1_14 : std_logic ; + signal CO0_2 : std_logic ; + signal RLOLS0_CNT_TC_1_9 : std_logic ; + signal UN1_PLOL_CNT_TC_10 : std_logic ; + signal RLOL1_CNT_TC_1_10 : std_logic ; + signal RLOS_DB_CNT_CRY_0 : std_logic ; + signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ; + signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ; + signal RLOS_DB_CNT_CRY_2 : std_logic ; + signal RLOS_DB_CNT_S_3_0_COUT : std_logic ; + signal RLOS_DB_CNT_S_3_0_S1 : std_logic ; + signal RLOL_DB_CNT_CRY_0 : std_logic ; + signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ; + signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ; + signal RLOL_DB_CNT_CRY_2 : std_logic ; + signal RLOL_DB_CNT_S_3_0_COUT : std_logic ; + signal RLOL_DB_CNT_S_3_0_S1 : std_logic ; + signal GND : std_logic ; + signal N_1 : std_logic ; + signal N_2 : std_logic ; + signal N_3 : std_logic ; + signal N_4 : std_logic ; + signal N_5 : std_logic ; +begin +\GENBLK2.RXP_RST2_RNO\: LUT4 +generic map( + init => X"EFEE" +) +port map ( + A => RSL_SERDES_RST_DUAL_C_6, + B => RSL_RX_SERDES_RST_C_5, + C => RLOS_DB_P1, + D => RLOS_DB, + Z => RXP_RST25); +\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 +generic map( + init => X"1222" +) +port map ( + A => PLOL0_CNT(1), + B => PLOL0_CNT9, + C => WAITA_PLOL0, + D => PLOL0_CNT(0), + Z => PLOL0_CNT_3(1)); +\GENBLK2.RXS_RST_RNIS0OP\: LUT4 +generic map( + init => X"1011" +) +port map ( + A => RLOL1_CNT_TC_1, + B => RXS_RST, + C => RLOS_DB_P1, + D => RLOS_DB, + Z => \RLOL1_CNT_\); +\GENBLK2.WAITA_RLOLS0_REG_Z428\: FD1P3DX port map ( + D => WAITA_RLOLS06, + SP => UN1_RLOLS0_CNT_TC, + CK => rxrefclk, + CD => rsl_rst, + Q => WAITA_RLOLS0); +\GENBLK2.WAIT_CALIB_REG_Z430\: FD1P3BX port map ( + D => WAIT_CALIB_RNO, + SP => UN1_RLOS_FEDGE_1, + CK => rxrefclk, + PD => rsl_rst, + Q => WAIT_CALIB); +\GENBLK2.RXS_RST_REG_Z432\: FD1P3DX port map ( + D => RXS_RST6, + SP => UN1_RXS_CNT_TC, + CK => rxrefclk, + CD => rsl_rst, + Q => RXS_RST); +\GENBLK2.RXS_CNT[0]_REG_Z434\: FD1S3DX port map ( + D => RXS_CNT_3(0), + CK => rxrefclk, + CD => rsl_rst, + Q => RXS_CNT(0)); +\GENBLK2.RXS_CNT[1]_REG_Z436\: FD1S3DX port map ( + D => RXS_CNT_3(1), + CK => rxrefclk, + CD => rsl_rst, + Q => RXS_CNT(1)); +\GENBLK2.RXP_RST2_REG_Z438\: FD1P3BX port map ( + D => RXP_RST25, + SP => UN2_RLOS_REDGE_1_I, + CK => rxrefclk, + PD => rsl_rst, + Q => RXP_RST2); +\GENBLK2.RLOS_P2_REG_Z440\: FD1S3DX port map ( + D => RLOS_P1, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOS_P2); +\GENBLK2.RLOS_P1_REG_Z442\: FD1S3DX port map ( + D => rx_los_low_s, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOS_P1); +\GENBLK2.RLOS_DB_P1_REG_Z444\: FD1S3BX port map ( + D => RLOS_DB, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOS_DB_P1); +\GENBLK2.RLOS_DB_CNT[0]_REG_Z446\: FD1S3BX port map ( + D => RLOS_DB_CNT_AXB_0, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOS_DB_CNT(0)); +\GENBLK2.RLOS_DB_CNT[1]_REG_Z448\: FD1S3BX port map ( + D => RLOS_DB_CNT_CRY_1_0_S0, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOS_DB_CNT(1)); +\GENBLK2.RLOS_DB_CNT[2]_REG_Z450\: FD1S3BX port map ( + D => RLOS_DB_CNT_CRY_1_0_S1, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOS_DB_CNT(2)); +\GENBLK2.RLOS_DB_CNT[3]_REG_Z452\: FD1S3BX port map ( + D => RLOS_DB_CNT_S_3_0_S0, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOS_DB_CNT(3)); +\GENBLK2.RLOS_DB_REG_Z454\: FD1P3BX port map ( + D => RLOS_DB_CNT(3), + SP => UN1_RLOS_DB_CNT_MAX, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOS_DB); +\GENBLK2.RLOLS0_CNT[0]_REG_Z456\: FD1P3DX port map ( + D => RLOLS0_CNT_S(0), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(0)); +\GENBLK2.RLOLS0_CNT[1]_REG_Z458\: FD1P3DX port map ( + D => RLOLS0_CNT_S(1), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(1)); +\GENBLK2.RLOLS0_CNT[2]_REG_Z460\: FD1P3DX port map ( + D => RLOLS0_CNT_S(2), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(2)); +\GENBLK2.RLOLS0_CNT[3]_REG_Z462\: FD1P3DX port map ( + D => RLOLS0_CNT_S(3), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(3)); +\GENBLK2.RLOLS0_CNT[4]_REG_Z464\: FD1P3DX port map ( + D => RLOLS0_CNT_S(4), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(4)); +\GENBLK2.RLOLS0_CNT[5]_REG_Z466\: FD1P3DX port map ( + D => RLOLS0_CNT_S(5), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(5)); +\GENBLK2.RLOLS0_CNT[6]_REG_Z468\: FD1P3DX port map ( + D => RLOLS0_CNT_S(6), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(6)); +\GENBLK2.RLOLS0_CNT[7]_REG_Z470\: FD1P3DX port map ( + D => RLOLS0_CNT_S(7), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(7)); +\GENBLK2.RLOLS0_CNT[8]_REG_Z472\: FD1P3DX port map ( + D => RLOLS0_CNT_S(8), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(8)); +\GENBLK2.RLOLS0_CNT[9]_REG_Z474\: FD1P3DX port map ( + D => RLOLS0_CNT_S(9), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(9)); +\GENBLK2.RLOLS0_CNT[10]_REG_Z476\: FD1P3DX port map ( + D => RLOLS0_CNT_S(10), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(10)); +\GENBLK2.RLOLS0_CNT[11]_REG_Z478\: FD1P3DX port map ( + D => RLOLS0_CNT_S(11), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(11)); +\GENBLK2.RLOLS0_CNT[12]_REG_Z480\: FD1P3DX port map ( + D => RLOLS0_CNT_S(12), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(12)); +\GENBLK2.RLOLS0_CNT[13]_REG_Z482\: FD1P3DX port map ( + D => RLOLS0_CNT_S(13), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(13)); +\GENBLK2.RLOLS0_CNT[14]_REG_Z484\: FD1P3DX port map ( + D => RLOLS0_CNT_S(14), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(14)); +\GENBLK2.RLOLS0_CNT[15]_REG_Z486\: FD1P3DX port map ( + D => RLOLS0_CNT_S(15), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(15)); +\GENBLK2.RLOLS0_CNT[16]_REG_Z488\: FD1P3DX port map ( + D => RLOLS0_CNT_S(16), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(16)); +\GENBLK2.RLOLS0_CNT[17]_REG_Z490\: FD1P3DX port map ( + D => RLOLS0_CNT_S(17), + SP => RLOLS0_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOLS0_CNT(17)); +\GENBLK2.RLOL_P2_REG_Z492\: FD1S3DX port map ( + D => RLOL_P1, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL_P2); +\GENBLK2.RLOL_P1_REG_Z494\: FD1S3DX port map ( + D => rx_cdr_lol_s, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL_P1); +\GENBLK2.RLOL_DB_P1_REG_Z496\: FD1S3BX port map ( + D => RLOL_DB, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOL_DB_P1); +\GENBLK2.RLOL_DB_CNT[0]_REG_Z498\: FD1S3BX port map ( + D => RLOL_DB_CNT_AXB_0, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOL_DB_CNT(0)); +\GENBLK2.RLOL_DB_CNT[1]_REG_Z500\: FD1S3BX port map ( + D => RLOL_DB_CNT_CRY_1_0_S0, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOL_DB_CNT(1)); +\GENBLK2.RLOL_DB_CNT[2]_REG_Z502\: FD1S3BX port map ( + D => RLOL_DB_CNT_CRY_1_0_S1, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOL_DB_CNT(2)); +\GENBLK2.RLOL_DB_CNT[3]_REG_Z504\: FD1S3BX port map ( + D => RLOL_DB_CNT_S_3_0_S0, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOL_DB_CNT(3)); +\GENBLK2.RLOL_DB_REG_Z506\: FD1P3BX port map ( + D => RLOL_DB_CNT(3), + SP => UN1_RLOL_DB_CNT_MAX, + CK => rxrefclk, + PD => rsl_rst, + Q => RLOL_DB); +\GENBLK2.RLOL1_CNT[0]_REG_Z508\: FD1P3DX port map ( + D => RLOL1_CNT_S(0), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(0)); +\GENBLK2.RLOL1_CNT[1]_REG_Z510\: FD1P3DX port map ( + D => RLOL1_CNT_S(1), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(1)); +\GENBLK2.RLOL1_CNT[2]_REG_Z512\: FD1P3DX port map ( + D => RLOL1_CNT_S(2), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(2)); +\GENBLK2.RLOL1_CNT[3]_REG_Z514\: FD1P3DX port map ( + D => RLOL1_CNT_S(3), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(3)); +\GENBLK2.RLOL1_CNT[4]_REG_Z516\: FD1P3DX port map ( + D => RLOL1_CNT_S(4), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(4)); +\GENBLK2.RLOL1_CNT[5]_REG_Z518\: FD1P3DX port map ( + D => RLOL1_CNT_S(5), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(5)); +\GENBLK2.RLOL1_CNT[6]_REG_Z520\: FD1P3DX port map ( + D => RLOL1_CNT_S(6), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(6)); +\GENBLK2.RLOL1_CNT[7]_REG_Z522\: FD1P3DX port map ( + D => RLOL1_CNT_S(7), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(7)); +\GENBLK2.RLOL1_CNT[8]_REG_Z524\: FD1P3DX port map ( + D => RLOL1_CNT_S(8), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(8)); +\GENBLK2.RLOL1_CNT[9]_REG_Z526\: FD1P3DX port map ( + D => RLOL1_CNT_S(9), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(9)); +\GENBLK2.RLOL1_CNT[10]_REG_Z528\: FD1P3DX port map ( + D => RLOL1_CNT_S(10), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(10)); +\GENBLK2.RLOL1_CNT[11]_REG_Z530\: FD1P3DX port map ( + D => RLOL1_CNT_S(11), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(11)); +\GENBLK2.RLOL1_CNT[12]_REG_Z532\: FD1P3DX port map ( + D => RLOL1_CNT_S(12), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(12)); +\GENBLK2.RLOL1_CNT[13]_REG_Z534\: FD1P3DX port map ( + D => RLOL1_CNT_S(13), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(13)); +\GENBLK2.RLOL1_CNT[14]_REG_Z536\: FD1P3DX port map ( + D => RLOL1_CNT_S(14), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(14)); +\GENBLK2.RLOL1_CNT[15]_REG_Z538\: FD1P3DX port map ( + D => RLOL1_CNT_S(15), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(15)); +\GENBLK2.RLOL1_CNT[16]_REG_Z540\: FD1P3DX port map ( + D => RLOL1_CNT_S(16), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(16)); +\GENBLK2.RLOL1_CNT[17]_REG_Z542\: FD1P3DX port map ( + D => RLOL1_CNT_S(17), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(17)); +\GENBLK2.RLOL1_CNT[18]_REG_Z544\: FD1P3DX port map ( + D => RLOL1_CNT_S(18), + SP => RLOL1_CNTE, + CK => rxrefclk, + CD => rsl_rst, + Q => RLOL1_CNT(18)); +\GENBLK1.WAITA_PLOL0_REG_Z546\: FD1P3DX port map ( + D => PLOL_FEDGE, + SP => UN1_PLOL0_CNT_TC_1_I, + CK => pll_refclki, + CD => rsl_rst, + Q => WAITA_PLOL0); +\GENBLK1.TXS_RST_REG_Z548\: FD1P3DX port map ( + D => UN1_PLOL_CNT_TC, + SP => UN2_PLOL_CNT_TC, + CK => pll_refclki, + CD => rsl_rst, + Q => TXS_RST); +\GENBLK1.TXS_CNT[0]_REG_Z550\: FD1S3DX port map ( + D => N_12_I, + CK => pll_refclki, + CD => rsl_rst, + Q => TXS_CNT(0)); +\GENBLK1.TXS_CNT[1]_REG_Z552\: FD1S3DX port map ( + D => TXS_CNT_RNO(1), + CK => pll_refclki, + CD => rsl_rst, + Q => TXS_CNT(1)); +\GENBLK1.TXP_RST_REG_Z554\: FD1P3DX port map ( + D => UN9_PLOL0_CNT_TC, + SP => UN1_PLOL0_CNT_TC_1, + CK => pll_refclki, + CD => rsl_rst, + Q => TXP_RST); +\GENBLK1.TXP_CNT[0]_REG_Z556\: FD1S3DX port map ( + D => N_13_I, + CK => pll_refclki, + CD => rsl_rst, + Q => TXP_CNT(0)); +\GENBLK1.TXP_CNT[1]_REG_Z558\: FD1S3DX port map ( + D => TXP_CNT_RNO(1), + CK => pll_refclki, + CD => rsl_rst, + Q => TXP_CNT(1)); +\GENBLK1.PLOL_CNT[0]_REG_Z560\: FD1S3DX port map ( + D => PLOL_CNT_S(0), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(0)); +\GENBLK1.PLOL_CNT[1]_REG_Z562\: FD1S3DX port map ( + D => PLOL_CNT_S(1), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(1)); +\GENBLK1.PLOL_CNT[2]_REG_Z564\: FD1S3DX port map ( + D => PLOL_CNT_S(2), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(2)); +\GENBLK1.PLOL_CNT[3]_REG_Z566\: FD1S3DX port map ( + D => PLOL_CNT_S(3), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(3)); +\GENBLK1.PLOL_CNT[4]_REG_Z568\: FD1S3DX port map ( + D => PLOL_CNT_S(4), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(4)); +\GENBLK1.PLOL_CNT[5]_REG_Z570\: FD1S3DX port map ( + D => PLOL_CNT_S(5), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(5)); +\GENBLK1.PLOL_CNT[6]_REG_Z572\: FD1S3DX port map ( + D => PLOL_CNT_S(6), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(6)); +\GENBLK1.PLOL_CNT[7]_REG_Z574\: FD1S3DX port map ( + D => PLOL_CNT_S(7), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(7)); +\GENBLK1.PLOL_CNT[8]_REG_Z576\: FD1S3DX port map ( + D => PLOL_CNT_S(8), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(8)); +\GENBLK1.PLOL_CNT[9]_REG_Z578\: FD1S3DX port map ( + D => PLOL_CNT_S(9), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(9)); +\GENBLK1.PLOL_CNT[10]_REG_Z580\: FD1S3DX port map ( + D => PLOL_CNT_S(10), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(10)); +\GENBLK1.PLOL_CNT[11]_REG_Z582\: FD1S3DX port map ( + D => PLOL_CNT_S(11), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(11)); +\GENBLK1.PLOL_CNT[12]_REG_Z584\: FD1S3DX port map ( + D => PLOL_CNT_S(12), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(12)); +\GENBLK1.PLOL_CNT[13]_REG_Z586\: FD1S3DX port map ( + D => PLOL_CNT_S(13), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(13)); +\GENBLK1.PLOL_CNT[14]_REG_Z588\: FD1S3DX port map ( + D => PLOL_CNT_S(14), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(14)); +\GENBLK1.PLOL_CNT[15]_REG_Z590\: FD1S3DX port map ( + D => PLOL_CNT_S(15), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(15)); +\GENBLK1.PLOL_CNT[16]_REG_Z592\: FD1S3DX port map ( + D => PLOL_CNT_S(16), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(16)); +\GENBLK1.PLOL_CNT[17]_REG_Z594\: FD1S3DX port map ( + D => PLOL_CNT_S(17), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(17)); +\GENBLK1.PLOL_CNT[18]_REG_Z596\: FD1S3DX port map ( + D => PLOL_CNT_S(18), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(18)); +\GENBLK1.PLOL_CNT[19]_REG_Z598\: FD1S3DX port map ( + D => PLOL_CNT_S(19), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL_CNT(19)); +\GENBLK1.PLOL0_CNT[0]_REG_Z600\: FD1S3DX port map ( + D => PLOL0_CNT_3(0), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL0_CNT(0)); +\GENBLK1.PLOL0_CNT[1]_REG_Z602\: FD1S3DX port map ( + D => PLOL0_CNT_3(1), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL0_CNT(1)); +\GENBLK1.PLOL0_CNT[2]_REG_Z604\: FD1S3DX port map ( + D => PLOL0_CNT_3(2), + CK => pll_refclki, + CD => rsl_rst, + Q => PLOL0_CNT(2)); +\GENBLK1.PLL_LOL_P3_REG_Z606\: FD1S3DX port map ( + D => PLL_LOL_P2, + CK => pll_refclki, + CD => rsl_rst, + Q => PLL_LOL_P3); +\GENBLK1.PLL_LOL_P2_REG_Z608\: FD1S3DX port map ( + D => PLL_LOL_P1, + CK => pll_refclki, + CD => rsl_rst, + Q => PLL_LOL_P2); +\GENBLK1.PLL_LOL_P1_REG_Z610\: FD1S3DX port map ( + D => pll_lol, + CK => pll_refclki, + CD => rsl_rst, + Q => PLL_LOL_P1); +\GENBLK1.TXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( + A => TXS_CNT(0), + B => TXS_RST, + C => UN1_PLOL_CNT_TC, + D => VCC, + Z => N_12_I); +\GENBLK1.TXS_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( + A => TXS_CNT(0), + B => TXS_CNT(1), + C => TXS_RST, + D => UN1_PLOL_CNT_TC, + Z => TXS_CNT_RNO(1)); +\GENBLK2.RXP_RST2_RNO_0\: LUT4 +generic map( + init => X"FFFE" +) +port map ( + A => RLOLS0_CNT_TC_1, + B => RLOS_REDGE, + C => RSL_RX_SERDES_RST_C_5, + D => RSL_SERDES_RST_DUAL_C_6, + Z => UN2_RLOS_REDGE_1_I); +\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 +generic map( + init => X"FEFE" +) +port map ( + A => RLOLS0_CNT11_0, + B => WAITA_RLOLS0, + C => RLOLS0_CNT_TC_1, + D => VCC, + Z => RLOLS0_CNTE); +\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 +generic map( + init => X"FFFE" +) +port map ( + A => RXS_RST, + B => WAIT_CALIB, + C => RLOL1_CNT_TC_1, + D => RLOS_REDGE, + Z => RLOL1_CNTE); +\GENBLK2.RXS_RST6\: LUT4 +generic map( + init => X"2020" +) +port map ( + A => RLOL_DB, + B => RLOS_DB, + C => RLOL1_CNT_TC_1, + D => VCC, + Z => RXS_RST6); +\GENBLK1.PLOL_CNT11_I\: LUT4 +generic map( + init => X"0202" +) +port map ( + A => PLL_LOL_P2, + B => UN1_PLOL_CNT_TC, + C => RSL_TX_SERDES_RST_C_4, + D => VCC, + Z => \PLOL_CNT_\); +\GENBLK2.RLOLS0_CNT11_I\: LUT4 +generic map( + init => X"1111" +) +port map ( + A => RLOLS0_CNT11_0, + B => RLOLS0_CNT_TC_1, + C => VCC, + D => VCC, + Z => \RLOLS0_CNT_\); +\GENBLK2.UN1_RXS_CNT_TC\: LUT4 +generic map( + init => X"FEFC" +) +port map ( + A => RLOL_DB, + B => RLOS_DB, + C => UN8_RXS_CNT_TC, + D => RLOL1_CNT_TC_1, + Z => UN1_RXS_CNT_TC); +\GENBLK2.WAIT_CALIB_RNO\: LUT4 +generic map( + init => X"A3A3" +) +port map ( + A => RLOL_DB, + B => RLOS_DB, + C => RLOL1_CNT_TC_1, + D => VCC, + Z => WAIT_CALIB_RNO); +\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 +generic map( + init => X"F8F8" +) +port map ( + A => TXS_CNT(0), + B => TXS_CNT(1), + C => UN1_PLOL_CNT_TC, + D => VCC, + Z => UN2_PLOL_CNT_TC); +\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 +generic map( + init => X"FEFE" +) +port map ( + A => RLOLS0_CNT11_0, + B => WAITA_RLOLS06, + C => RLOLS0_CNT_TC_1, + D => VCC, + Z => UN1_RLOLS0_CNT_TC); +\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 +generic map( + init => X"F6F6" +) +port map ( + A => RLOS_DB, + B => RLOS_DB_P1, + C => RLOL1_CNT_TC_1, + D => VCC, + Z => UN1_RLOS_FEDGE_1); +\GENBLK1.TXP_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( + A => TXP_CNT(0), + B => TXP_RST, + C => UN9_PLOL0_CNT_TC, + D => VCC, + Z => N_13_I); +\GENBLK1.TXP_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( + A => TXP_CNT(0), + B => TXP_CNT(1), + C => TXP_RST, + D => UN9_PLOL0_CNT_TC, + Z => TXP_CNT_RNO(1)); +\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 +generic map( + init => X"8000" +) +port map ( + A => UN1_PLOL_CNT_TC_11, + B => UN1_PLOL_CNT_TC_12, + C => UN1_PLOL_CNT_TC_13, + D => UN1_PLOL_CNT_TC_14, + Z => UN1_PLOL_CNT_TC); +RLOLS0_CNT_TC_1_Z627: LUT4 +generic map( + init => X"8000" +) +port map ( + A => RLOLS0_CNT_TC_1_10, + B => RLOLS0_CNT_TC_1_11, + C => RLOLS0_CNT_TC_1_12, + D => RLOLS0_CNT_TC_1_13, + Z => RLOLS0_CNT_TC_1); +RLOL1_CNT_TC_1_Z628: LUT4 +generic map( + init => X"8000" +) +port map ( + A => RLOL1_CNT_TC_1_11, + B => RLOL1_CNT_TC_1_12, + C => RLOL1_CNT_TC_1_13, + D => RLOL1_CNT_TC_1_14, + Z => RLOL1_CNT_TC_1); +\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( + A => RLOL_DB_CNT(0), + B => UN1_RLOL_DB_CNT_ZERO(0), + C => VCC, + D => VCC, + Z => RLOL_DB_CNT_AXB_0); +\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( + A => RLOS_DB_CNT(0), + B => UN1_RLOS_DB_CNT_ZERO(0), + C => VCC, + D => VCC, + Z => RLOS_DB_CNT_AXB_0); +\GENBLK1.WAITA_PLOL0_RNO\: LUT4 +generic map( + init => X"F6F6" +) +port map ( + A => PLL_LOL_P2, + B => PLL_LOL_P3, + C => UN9_PLOL0_CNT_TC, + D => VCC, + Z => UN1_PLOL0_CNT_TC_1_I); +\GENBLK1.PLOL0_CNT_3[2]\: LUT4 +generic map( + init => X"1320" +) +port map ( + A => CO0_2, + B => PLOL0_CNT9, + C => PLOL0_CNT(1), + D => PLOL0_CNT(2), + Z => PLOL0_CNT_3(2)); +\GENBLK1.PLOL0_CNT_3[0]\: LUT4 +generic map( + init => X"1414" +) +port map ( + A => PLOL0_CNT9, + B => PLOL0_CNT(0), + C => WAITA_PLOL0, + D => VCC, + Z => PLOL0_CNT_3(0)); +\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z634\: LUT4 +generic map( + init => X"8000" +) +port map ( + A => RLOL_DB_CNT(0), + B => RLOL_DB_CNT(1), + C => RLOL_DB_CNT(2), + D => RLOL_DB_CNT(3), + Z => UN1_RLOL_DB_CNT_ZERO_BM(0)); +\UN1_RLOL_DB_CNT_ZERO[0]_Z635\: PFUMX port map ( + ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0), + BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0), + C0 => RLOL_P2, + Z => UN1_RLOL_DB_CNT_ZERO(0)); +\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z636\: LUT4 +generic map( + init => X"8000" +) +port map ( + A => RLOS_DB_CNT(0), + B => RLOS_DB_CNT(1), + C => RLOS_DB_CNT(2), + D => RLOS_DB_CNT(3), + Z => UN1_RLOS_DB_CNT_ZERO_BM(0)); +\UN1_RLOS_DB_CNT_ZERO[0]_Z637\: PFUMX port map ( + ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0), + BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0), + C0 => RLOS_P2, + Z => UN1_RLOS_DB_CNT_ZERO(0)); +\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 +generic map( + init => X"F8F8" +) +port map ( + A => TXP_CNT(0), + B => TXP_CNT(1), + C => UN9_PLOL0_CNT_TC, + D => VCC, + Z => UN1_PLOL0_CNT_TC_1); +\RXS_CNT_3[1]_Z639\: LUT4 +generic map( + init => X"6464" +) +port map ( + A => RXS_CNT(0), + B => RXS_CNT(1), + C => RXS_RST, + D => VCC, + Z => RXS_CNT_3(1)); +\GENBLK2.WAITA_RLOLS06\: LUT4 +generic map( + init => X"0504" +) +port map ( + A => RLOL_DB, + B => RLOL_DB_P1, + C => RLOS_DB, + D => RLOS_DB_P1, + Z => WAITA_RLOLS06); +\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( + A => RLOL_DB_CNT(0), + B => RLOL_DB_CNT(1), + C => RLOL_DB_CNT(2), + D => RLOL_DB_CNT(3), + Z => UN1_RLOL_DB_CNT_MAX); +\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( + A => RLOS_DB_CNT(0), + B => RLOS_DB_CNT(1), + C => RLOS_DB_CNT(2), + D => RLOS_DB_CNT(3), + Z => UN1_RLOS_DB_CNT_MAX); +RLOLS0_CNT_TC_1_13_Z643: LUT4 +generic map( + init => X"1010" +) +port map ( + A => RLOLS0_CNT(12), + B => RLOLS0_CNT(13), + C => RLOLS0_CNT_TC_1_9, + D => VCC, + Z => RLOLS0_CNT_TC_1_13); +\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 +generic map( + init => X"0100" +) +port map ( + A => PLOL_CNT(5), + B => PLOL_CNT(10), + C => PLOL_CNT(18), + D => UN1_PLOL_CNT_TC_10, + Z => UN1_PLOL_CNT_TC_14); +RLOL1_CNT_TC_1_14_Z645: LUT4 +generic map( + init => X"0100" +) +port map ( + A => RLOL1_CNT(12), + B => RLOL1_CNT(13), + C => RLOL1_CNT(18), + D => RLOL1_CNT_TC_1_10, + Z => RLOL1_CNT_TC_1_14); +\RDO_TX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( + A => rsl_disable, + B => TXP_RST, + C => tx_pcs_rst_c, + D => VCC, + Z => rsl_tx_pcs_rst_c); +\RDO_RX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( + A => rsl_disable, + B => RXP_RST2, + C => rx_pcs_rst_c, + D => VCC, + Z => rsl_rx_pcs_rst_c); +RDO_TX_SERDES_RST_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( + A => rsl_disable, + B => TXS_RST, + C => tx_serdes_rst_c, + D => VCC, + Z => RSL_TX_SERDES_RST_C_4); +\RXS_CNT_3[0]_Z649\: LUT4 +generic map( + init => X"5252" +) +port map ( + A => RXS_CNT(0), + B => RXS_CNT(1), + C => RXS_RST, + D => VCC, + Z => RXS_CNT_3(0)); +\RDO_RX_SERDES_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( + A => rsl_disable, + B => RXS_RST, + C => rx_serdes_rst_c, + D => VCC, + Z => RSL_RX_SERDES_RST_C_5); +RDO_SERDES_RST_DUAL_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( + A => rsl_disable, + B => rsl_rst, + C => serdes_rst_dual_c, + D => VCC, + Z => RSL_SERDES_RST_DUAL_C_6); +\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 +generic map( + init => X"1010" +) +port map ( + A => PLOL0_CNT(0), + B => PLOL0_CNT(1), + C => PLOL0_CNT(2), + D => VCC, + Z => UN9_PLOL0_CNT_TC); +RLOLS0_CNT_TC_1_9_Z653: LUT4 +generic map( + init => X"0008" +) +port map ( + A => RLOLS0_CNT(10), + B => RLOLS0_CNT(14), + C => RLOLS0_CNT(16), + D => RLOLS0_CNT(17), + Z => RLOLS0_CNT_TC_1_9); +RLOLS0_CNT_TC_1_10_Z654: LUT4 +generic map( + init => X"0100" +) +port map ( + A => RLOLS0_CNT(0), + B => RLOLS0_CNT(1), + C => RLOLS0_CNT(2), + D => RLOLS0_CNT(15), + Z => RLOLS0_CNT_TC_1_10); +RLOLS0_CNT_TC_1_11_Z655: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOLS0_CNT(3), + B => RLOLS0_CNT(4), + C => RLOLS0_CNT(5), + D => RLOLS0_CNT(6), + Z => RLOLS0_CNT_TC_1_11); +RLOLS0_CNT_TC_1_12_Z656: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOLS0_CNT(7), + B => RLOLS0_CNT(8), + C => RLOLS0_CNT(9), + D => RLOLS0_CNT(11), + Z => RLOLS0_CNT_TC_1_12); +\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 +generic map( + init => X"0080" +) +port map ( + A => PLOL_CNT(1), + B => PLOL_CNT(6), + C => PLOL_CNT(7), + D => PLOL_CNT(12), + Z => UN1_PLOL_CNT_TC_10); +\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 +generic map( + init => X"8000" +) +port map ( + A => PLOL_CNT(8), + B => PLOL_CNT(9), + C => PLOL_CNT(11), + D => PLOL_CNT(13), + Z => UN1_PLOL_CNT_TC_11); +\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 +generic map( + init => X"8000" +) +port map ( + A => PLOL_CNT(14), + B => PLOL_CNT(15), + C => PLOL_CNT(16), + D => PLOL_CNT(17), + Z => UN1_PLOL_CNT_TC_12); +\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 +generic map( + init => X"0100" +) +port map ( + A => PLOL_CNT(2), + B => PLOL_CNT(3), + C => PLOL_CNT(4), + D => PLOL_CNT(19), + Z => UN1_PLOL_CNT_TC_13); +RLOL1_CNT_TC_1_10_Z661: LUT4 +generic map( + init => X"0800" +) +port map ( + A => RLOL1_CNT(14), + B => RLOL1_CNT(15), + C => RLOL1_CNT(16), + D => RLOL1_CNT(17), + Z => RLOL1_CNT_TC_1_10); +RLOL1_CNT_TC_1_11_Z662: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOL1_CNT(0), + B => RLOL1_CNT(1), + C => RLOL1_CNT(2), + D => RLOL1_CNT(3), + Z => RLOL1_CNT_TC_1_11); +RLOL1_CNT_TC_1_12_Z663: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOL1_CNT(4), + B => RLOL1_CNT(5), + C => RLOL1_CNT(6), + D => RLOL1_CNT(7), + Z => RLOL1_CNT_TC_1_12); +RLOL1_CNT_TC_1_13_Z664: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOL1_CNT(8), + B => RLOL1_CNT(9), + C => RLOL1_CNT(10), + D => RLOL1_CNT(11), + Z => RLOL1_CNT_TC_1_13); +\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 +generic map( + init => X"8888" +) +port map ( + A => PLOL0_CNT(0), + B => WAITA_PLOL0, + C => VCC, + D => VCC, + Z => CO0_2); +PLOL_FEDGE_Z666: LUT4 +generic map( + init => X"4444" +) +port map ( + A => PLL_LOL_P2, + B => PLL_LOL_P3, + C => VCC, + D => VCC, + Z => PLOL_FEDGE); +RLOS_REDGE_Z667: LUT4 +generic map( + init => X"2222" +) +port map ( + A => RLOS_DB, + B => RLOS_DB_P1, + C => VCC, + D => VCC, + Z => RLOS_REDGE); +\GENBLK2.UN8_RXS_CNT_TC\: LUT4 +generic map( + init => X"8888" +) +port map ( + A => RXS_CNT(0), + B => RXS_CNT(1), + C => VCC, + D => VCC, + Z => UN8_RXS_CNT_TC); +\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z669\: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOS_DB_CNT(0), + B => RLOS_DB_CNT(1), + C => RLOS_DB_CNT(2), + D => RLOS_DB_CNT(3), + Z => UN1_RLOS_DB_CNT_ZERO_AM(0)); +\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z670\: LUT4 +generic map( + init => X"0001" +) +port map ( + A => RLOL_DB_CNT(0), + B => RLOL_DB_CNT(1), + C => RLOL_DB_CNT(2), + D => RLOL_DB_CNT(3), + Z => UN1_RLOL_DB_CNT_ZERO_AM(0)); +\GENBLK1.PLOL0_CNT9\: LUT4 +generic map( + init => X"AAAE" +) +port map ( + A => PLL_LOL_P2, + B => PLOL0_CNT(2), + C => PLOL0_CNT(1), + D => PLOL0_CNT(0), + Z => PLOL0_CNT9); +\GENBLK2.RLOLS0_CNT11_0\: LUT4 +generic map( + init => X"4F44" +) +port map ( + A => RLOL_DB_P1, + B => RLOL_DB, + C => RLOS_DB_P1, + D => RLOS_DB, + Z => RLOLS0_CNT11_0); +\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => VCC, + B0 => \RLOL1_CNT_\, + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(0), + C1 => VCC, + D1 => VCC, + CIN => N_5, + COUT => RLOL1_CNT_CRY(0), + S0 => RLOL1_CNT_CRY_0_S0(0), + S1 => RLOL1_CNT_S(0)); +\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(1), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(2), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(0), + COUT => RLOL1_CNT_CRY(2), + S0 => RLOL1_CNT_S(1), + S1 => RLOL1_CNT_S(2)); +\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(3), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(4), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(2), + COUT => RLOL1_CNT_CRY(4), + S0 => RLOL1_CNT_S(3), + S1 => RLOL1_CNT_S(4)); +\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(5), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(6), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(4), + COUT => RLOL1_CNT_CRY(6), + S0 => RLOL1_CNT_S(5), + S1 => RLOL1_CNT_S(6)); +\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(7), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(8), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(6), + COUT => RLOL1_CNT_CRY(8), + S0 => RLOL1_CNT_S(7), + S1 => RLOL1_CNT_S(8)); +\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(9), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(10), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(8), + COUT => RLOL1_CNT_CRY(10), + S0 => RLOL1_CNT_S(9), + S1 => RLOL1_CNT_S(10)); +\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(11), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(12), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(10), + COUT => RLOL1_CNT_CRY(12), + S0 => RLOL1_CNT_S(11), + S1 => RLOL1_CNT_S(12)); +\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(13), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(14), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(12), + COUT => RLOL1_CNT_CRY(14), + S0 => RLOL1_CNT_S(13), + S1 => RLOL1_CNT_S(14)); +\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(15), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(16), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(14), + COUT => RLOL1_CNT_CRY(16), + S0 => RLOL1_CNT_S(15), + S1 => RLOL1_CNT_S(16)); +\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"800a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOL1_CNT_\, + B0 => RLOL1_CNT(17), + C0 => VCC, + D0 => VCC, + A1 => \RLOL1_CNT_\, + B1 => RLOL1_CNT(18), + C1 => VCC, + D1 => VCC, + CIN => RLOL1_CNT_CRY(16), + COUT => RLOL1_CNT_CRY_0_COUT(17), + S0 => RLOL1_CNT_S(17), + S1 => RLOL1_CNT_S(18)); +\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => VCC, + B0 => \RLOLS0_CNT_\, + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(0), + C1 => VCC, + D1 => VCC, + CIN => N_4, + COUT => RLOLS0_CNT_CRY(0), + S0 => RLOLS0_CNT_CRY_0_S0(0), + S1 => RLOLS0_CNT_S(0)); +\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(1), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(2), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(0), + COUT => RLOLS0_CNT_CRY(2), + S0 => RLOLS0_CNT_S(1), + S1 => RLOLS0_CNT_S(2)); +\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(3), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(4), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(2), + COUT => RLOLS0_CNT_CRY(4), + S0 => RLOLS0_CNT_S(3), + S1 => RLOLS0_CNT_S(4)); +\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(5), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(6), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(4), + COUT => RLOLS0_CNT_CRY(6), + S0 => RLOLS0_CNT_S(5), + S1 => RLOLS0_CNT_S(6)); +\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(7), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(8), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(6), + COUT => RLOLS0_CNT_CRY(8), + S0 => RLOLS0_CNT_S(7), + S1 => RLOLS0_CNT_S(8)); +\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(9), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(10), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(8), + COUT => RLOLS0_CNT_CRY(10), + S0 => RLOLS0_CNT_S(9), + S1 => RLOLS0_CNT_S(10)); +\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(11), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(12), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(10), + COUT => RLOLS0_CNT_CRY(12), + S0 => RLOLS0_CNT_S(11), + S1 => RLOLS0_CNT_S(12)); +\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(13), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(14), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(12), + COUT => RLOLS0_CNT_CRY(14), + S0 => RLOLS0_CNT_S(13), + S1 => RLOLS0_CNT_S(14)); +\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(15), + C0 => VCC, + D0 => VCC, + A1 => \RLOLS0_CNT_\, + B1 => RLOLS0_CNT(16), + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(14), + COUT => RLOLS0_CNT_CRY(16), + S0 => RLOLS0_CNT_S(15), + S1 => RLOLS0_CNT_S(16)); +\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \RLOLS0_CNT_\, + B0 => RLOLS0_CNT(17), + C0 => VCC, + D0 => VCC, + A1 => VCC, + B1 => VCC, + C1 => VCC, + D1 => VCC, + CIN => RLOLS0_CNT_CRY(16), + COUT => RLOLS0_CNT_S_0_COUT(17), + S0 => RLOLS0_CNT_S(17), + S1 => RLOLS0_CNT_S_0_S1(17)); +\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => VCC, + B0 => \PLOL_CNT_\, + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(0), + C1 => VCC, + D1 => VCC, + CIN => N_3, + COUT => PLOL_CNT_CRY(0), + S0 => PLOL_CNT_CRY_0_S0(0), + S1 => PLOL_CNT_S(0)); +\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(1), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(2), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(0), + COUT => PLOL_CNT_CRY(2), + S0 => PLOL_CNT_S(1), + S1 => PLOL_CNT_S(2)); +\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(3), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(4), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(2), + COUT => PLOL_CNT_CRY(4), + S0 => PLOL_CNT_S(3), + S1 => PLOL_CNT_S(4)); +\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(5), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(6), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(4), + COUT => PLOL_CNT_CRY(6), + S0 => PLOL_CNT_S(5), + S1 => PLOL_CNT_S(6)); +\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(7), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(8), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(6), + COUT => PLOL_CNT_CRY(8), + S0 => PLOL_CNT_S(7), + S1 => PLOL_CNT_S(8)); +\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(9), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(10), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(8), + COUT => PLOL_CNT_CRY(10), + S0 => PLOL_CNT_S(9), + S1 => PLOL_CNT_S(10)); +\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(11), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(12), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(10), + COUT => PLOL_CNT_CRY(12), + S0 => PLOL_CNT_S(11), + S1 => PLOL_CNT_S(12)); +\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(13), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(14), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(12), + COUT => PLOL_CNT_CRY(14), + S0 => PLOL_CNT_S(13), + S1 => PLOL_CNT_S(14)); +\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(15), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(16), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(14), + COUT => PLOL_CNT_CRY(16), + S0 => PLOL_CNT_S(15), + S1 => PLOL_CNT_S(16)); +\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(17), + C0 => VCC, + D0 => VCC, + A1 => \PLOL_CNT_\, + B1 => PLOL_CNT(18), + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(16), + COUT => PLOL_CNT_CRY(18), + S0 => PLOL_CNT_S(17), + S1 => PLOL_CNT_S(18)); +\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => \PLOL_CNT_\, + B0 => PLOL_CNT(19), + C0 => VCC, + D0 => VCC, + A1 => VCC, + B1 => VCC, + C1 => VCC, + D1 => VCC, + CIN => PLOL_CNT_CRY(18), + COUT => PLOL_CNT_S_0_COUT(19), + S0 => PLOL_CNT_S(19), + S1 => PLOL_CNT_S_0_S1(19)); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => VCC, + B0 => VCC, + C0 => VCC, + D0 => VCC, + A1 => RLOS_DB_CNT(0), + B1 => UN1_RLOS_DB_CNT_ZERO(0), + C1 => VCC, + D1 => VCC, + CIN => N_2, + COUT => RLOS_DB_CNT_CRY_0, + S0 => RLOS_DB_CNT_CRY_0_0_S0, + S1 => RLOS_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => UN1_RLOS_DB_CNT_ZERO(0), + B0 => RLOS_P2, + C0 => RLOS_DB_CNT(1), + D0 => VCC, + A1 => UN1_RLOS_DB_CNT_ZERO(0), + B1 => RLOS_P2, + C1 => RLOS_DB_CNT(2), + D1 => VCC, + CIN => RLOS_DB_CNT_CRY_0, + COUT => RLOS_DB_CNT_CRY_2, + S0 => RLOS_DB_CNT_CRY_1_0_S0, + S1 => RLOS_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => RLOS_DB_CNT(3), + B0 => RLOS_P2, + C0 => UN1_RLOS_DB_CNT_ZERO(0), + D0 => VCC, + A1 => VCC, + B1 => VCC, + C1 => VCC, + D1 => VCC, + CIN => RLOS_DB_CNT_CRY_2, + COUT => RLOS_DB_CNT_S_3_0_COUT, + S0 => RLOS_DB_CNT_S_3_0_S0, + S1 => RLOS_DB_CNT_S_3_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => VCC, + B0 => VCC, + C0 => VCC, + D0 => VCC, + A1 => RLOL_DB_CNT(0), + B1 => UN1_RLOL_DB_CNT_ZERO(0), + C1 => VCC, + D1 => VCC, + CIN => N_1, + COUT => RLOL_DB_CNT_CRY_0, + S0 => RLOL_DB_CNT_CRY_0_0_S0, + S1 => RLOL_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => UN1_RLOL_DB_CNT_ZERO(0), + B0 => RLOL_P2, + C0 => RLOL_DB_CNT(1), + D0 => VCC, + A1 => UN1_RLOL_DB_CNT_ZERO(0), + B1 => RLOL_P2, + C1 => RLOL_DB_CNT(2), + D1 => VCC, + CIN => RLOL_DB_CNT_CRY_0, + COUT => RLOL_DB_CNT_CRY_2, + S0 => RLOL_DB_CNT_CRY_1_0_S0, + S1 => RLOL_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( + A0 => RLOL_DB_CNT(3), + B0 => RLOL_P2, + C0 => UN1_RLOL_DB_CNT_ZERO(0), + D0 => VCC, + A1 => VCC, + B1 => VCC, + C1 => VCC, + D1 => VCC, + CIN => RLOL_DB_CNT_CRY_2, + COUT => RLOL_DB_CNT_S_3_0_COUT, + S0 => RLOL_DB_CNT_S_3_0_S0, + S1 => RLOL_DB_CNT_S_3_0_S1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_4; +rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_5; +rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_6; +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity PCSD is +port( +hdoutp : out std_logic; +hdoutn : out std_logic; +hdinp : in std_logic; +hdinn : in std_logic; +rxrefclk : in std_logic; +tx_pclk : out std_logic; +txi_clk : in std_logic; +txdata : in std_logic_vector(7 downto 0); +tx_k : in std_logic_vector(0 downto 0); +xmit : in std_logic_vector(0 downto 0); +tx_disp_correct : in std_logic_vector(0 downto 0); +rxdata : out std_logic_vector(7 downto 0); +rx_k : out std_logic_vector(0 downto 0); +rx_disp_err : out std_logic_vector(0 downto 0); +rx_cv_err : out std_logic_vector(0 downto 0); +signal_detect_c : in std_logic; +rx_los_low_s : out std_logic; +lsm_status_s : out std_logic; +ctc_urun_s : out std_logic; +ctc_orun_s : out std_logic; +rx_cdr_lol_s : out std_logic; +ctc_ins_s : out std_logic; +ctc_del_s : out std_logic; +tx_pwrup_c : in std_logic; +rx_pwrup_c : in std_logic; +serdes_pdb : in std_logic; +pll_refclki : in std_logic; +rsl_disable : in std_logic; +rsl_rst : in std_logic; +serdes_rst_dual_c : in std_logic; +rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +pll_lol : in std_logic; +rx_serdes_rst_c : in std_logic; +rx_pcs_rst_c : in std_logic); +end PCSD; + +architecture beh of PCSD is +signal TX_PCLK_7 : std_logic ; +signal RX_LOS_LOW_S_8 : std_logic ; +signal RX_CDR_LOL_S_9 : std_logic ; +signal RSL_TX_PCS_RST_C : std_logic ; +signal RSL_RX_PCS_RST_C : std_logic ; +signal RSL_RX_SERDES_RST_C : std_logic ; +signal RSL_SERDES_RST_DUAL_C : std_logic ; +signal RSL_TX_SERDES_RST_C : std_logic ; +signal N47_1 : std_logic ; +signal N48_1 : std_logic ; +signal N1_1 : std_logic ; +signal N2_1 : std_logic ; +signal N3_1 : std_logic ; +signal N4_1 : std_logic ; +signal N5_1 : std_logic ; +signal N49_1 : std_logic ; +signal N6_1 : std_logic ; +signal N50_1 : std_logic ; +signal N7_1 : std_logic ; +signal N51_1 : std_logic ; +signal N8_1 : std_logic ; +signal N52_1 : std_logic ; +signal N9_1 : std_logic ; +signal N53_1 : std_logic ; +signal N54_1 : std_logic ; +signal N55_1 : std_logic ; +signal N56_1 : std_logic ; +signal N57_1 : std_logic ; +signal N58_1 : std_logic ; +signal N59_1 : std_logic ; +signal N60_1 : std_logic ; +signal N61_1 : std_logic ; +signal N62_1 : std_logic ; +signal N63_1 : std_logic ; +signal N64_1 : std_logic ; +signal N65_1 : std_logic ; +signal N10_1 : std_logic ; +signal N66_1 : std_logic ; +signal N67_1 : std_logic ; +signal N68_1 : std_logic ; +signal N69_1 : std_logic ; +signal N70_1 : std_logic ; +signal N71_1 : std_logic ; +signal N72_1 : std_logic ; +signal N73_1 : std_logic ; +signal N74_1 : std_logic ; +signal N75_1 : std_logic ; +signal N76_1 : std_logic ; +signal N77_1 : std_logic ; +signal N78_1 : std_logic ; +signal N79_1 : std_logic ; +signal N80_1 : std_logic ; +signal N81_1 : std_logic ; +signal N82_1 : std_logic ; +signal N83_1 : std_logic ; +signal N84_1 : std_logic ; +signal N85_1 : std_logic ; +signal N86_1 : std_logic ; +signal N87_1 : std_logic ; +signal N88_1 : std_logic ; +signal N11_1 : std_logic ; +signal N89_1 : std_logic ; +signal N12_1 : std_logic ; +signal N90_1 : std_logic ; +signal N13_1 : std_logic ; +signal N91_1 : std_logic ; +signal N92_1 : std_logic ; +signal N93_1 : std_logic ; +signal N94_1 : std_logic ; +signal N95_1 : std_logic ; +signal N14_1 : std_logic ; +signal N96_1 : std_logic ; +signal N15_1 : std_logic ; +signal N97_1 : std_logic ; +signal N98_1 : std_logic ; +signal N99_1 : std_logic ; +signal N100_1 : std_logic ; +signal N101_1 : std_logic ; +signal N102_1 : std_logic ; +signal N103_1 : std_logic ; +signal N104_1 : std_logic ; +signal N105_1 : std_logic ; +signal N106_1 : std_logic ; +signal N107_1 : std_logic ; +signal N108_1 : std_logic ; +signal N109_1 : std_logic ; +signal N110_1 : std_logic ; +signal N121_1 : std_logic ; +signal N16_1 : std_logic ; +signal N17_1 : std_logic ; +signal N18_1 : std_logic ; +signal N19_1 : std_logic ; +signal N20_1 : std_logic ; +signal N21_1 : std_logic ; +signal N22_1 : std_logic ; +signal N23_1 : std_logic ; +signal N24_1 : std_logic ; +signal N25_1 : std_logic ; +signal N26_1 : std_logic ; +signal N27_1 : std_logic ; +signal N28_1 : std_logic ; +signal N29_1 : std_logic ; +signal N30_1 : std_logic ; +signal N31_1 : std_logic ; +signal N32_1 : std_logic ; +signal N33_1 : std_logic ; +signal N34_1 : std_logic ; +signal N35_1 : std_logic ; +signal N36_1 : std_logic ; +signal N37_1 : std_logic ; +signal N38_1 : std_logic ; +signal N39_1 : std_logic ; +signal N40_1 : std_logic ; +signal N41_1 : std_logic ; +signal N42_1 : std_logic ; +signal N43_1 : std_logic ; +signal N46_1 : std_logic ; +signal GND : std_logic ; +signal VCC : std_logic ; +component PCSDrsl_core_Z1_layer1 + port( + serdes_rst_dual_c : in std_logic; + rx_serdes_rst_c : in std_logic; + tx_serdes_rst_c : in std_logic; + rsl_rx_pcs_rst_c : out std_logic; + rx_pcs_rst_c : in std_logic; + rsl_tx_pcs_rst_c : out std_logic; + tx_pcs_rst_c : in std_logic; + rsl_disable : in std_logic; + rsl_tx_serdes_rst_c : out std_logic; + pll_lol : in std_logic; + pll_refclki : in std_logic; + rx_cdr_lol_s : in std_logic; + rx_los_low_s : in std_logic; + rsl_rst : in std_logic; + rxrefclk : in std_logic; + rsl_rx_serdes_rst_c : out std_logic; + rsl_serdes_rst_dual_c : out std_logic ); +end component; +begin +GND_0: VLO port map ( + Z => GND); +VCC_0: VHI port map ( + Z => VCC); +PUR_INST: PUR port map ( + PUR => VCC); +GSR_INST: GSR port map ( + GSR => VCC); +DCU0_INST: DCUA +generic map( + D_MACROPDB => "0b1", + D_IB_PWDNB => "0b1", + D_XGE_MODE => "0b0", + D_LOW_MARK => "0d4", + D_HIGH_MARK => "0d12", + D_BUS8BIT_SEL => "0b0", + D_CDR_LOL_SET => "0b00", + D_BITCLK_LOCAL_EN => "0b1", + D_BITCLK_ND_EN => "0b0", + D_BITCLK_FROM_ND_EN => "0b0", + D_SYNC_LOCAL_EN => "0b1", + D_SYNC_ND_EN => "0b0", + CH0_UC_MODE => "0b0", + CH0_PCIE_MODE => "0b0", + CH0_RIO_MODE => "0b0", + CH0_WA_MODE => "0b0", + CH0_INVERT_RX => "0b0", + CH0_INVERT_TX => "0b0", + CH0_PRBS_SELECTION => "0b0", + CH0_GE_AN_ENABLE => "0b0", + CH0_PRBS_LOCK => "0b0", + CH0_PRBS_ENABLE => "0b0", + CH0_ENABLE_CG_ALIGN => "0b1", + CH0_TX_GEAR_MODE => "0b0", + CH0_RX_GEAR_MODE => "0b0", + CH0_PCS_DET_TIME_SEL => "0b00", + CH0_PCIE_EI_EN => "0b0", + CH0_TX_GEAR_BYPASS => "0b0", + CH0_ENC_BYPASS => "0b0", + CH0_SB_BYPASS => "0b0", + CH0_RX_SB_BYPASS => "0b0", + CH0_WA_BYPASS => "0b0", + CH0_DEC_BYPASS => "0b0", + CH0_CTC_BYPASS => "0b0", + CH0_RX_GEAR_BYPASS => "0b0", + CH0_LSM_DISABLE => "0b0", + CH0_MATCH_2_ENABLE => "0b1", + CH0_MATCH_4_ENABLE => "0b0", + CH0_MIN_IPG_CNT => "0b11", + CH0_CC_MATCH_1 => "0x000", + CH0_CC_MATCH_2 => "0x000", + CH0_CC_MATCH_3 => "0x1BC", + CH0_CC_MATCH_4 => "0x050", + CH0_UDF_COMMA_MASK => "0x3ff", + CH0_UDF_COMMA_A => "0x283", + CH0_UDF_COMMA_B => "0x17C", + CH0_RX_DCO_CK_DIV => "0b010", + CH0_RCV_DCC_EN => "0b0", + CH0_REQ_LVL_SET => "0b00", + CH0_REQ_EN => "0b1", + CH0_RTERM_RX => "0d22", + CH0_PDEN_SEL => "0b1", + CH0_LDR_RX2CORE_SEL => "0b0", + CH0_LDR_CORE2TX_SEL => "0b0", + CH0_TPWDNB => "0b1", + CH0_RATE_MODE_TX => "0b0", + CH0_RTERM_TX => "0d19", + CH0_TX_CM_SEL => "0b00", + CH0_TDRV_PRE_EN => "0b0", + CH0_TDRV_SLICE0_SEL => "0b01", + CH0_TDRV_SLICE1_SEL => "0b00", + CH0_TDRV_SLICE2_SEL => "0b01", + CH0_TDRV_SLICE3_SEL => "0b01", + CH0_TDRV_SLICE4_SEL => "0b01", + CH0_TDRV_SLICE5_SEL => "0b01", + CH0_TDRV_SLICE0_CUR => "0b101", + CH0_TDRV_SLICE1_CUR => "0b000", + CH0_TDRV_SLICE2_CUR => "0b11", + CH0_TDRV_SLICE3_CUR => "0b11", + CH0_TDRV_SLICE4_CUR => "0b11", + CH0_TDRV_SLICE5_CUR => "0b00", + CH0_TDRV_DAT_SEL => "0b00", + CH0_TX_DIV11_SEL => "0b0", + CH0_RPWDNB => "0b1", + CH0_RATE_MODE_RX => "0b0", + CH0_RLOS_SEL => "0b1", + CH0_RX_LOS_LVL => "0b010", + CH0_RX_LOS_CEQ => "0b11", + CH0_RX_LOS_HYST_EN => "0b0", + CH0_RX_LOS_EN => "0b1", + CH0_RX_DIV11_SEL => "0b0", + CH0_SEL_SD_RX_CLK => "0b0", + CH0_FF_RX_H_CLK_EN => "0b0", + CH0_FF_RX_F_CLK_DIS => "0b0", + CH0_FF_TX_H_CLK_EN => "0b0", + CH0_FF_TX_F_CLK_DIS => "0b0", + CH0_RX_RATE_SEL => "0d8", + CH0_TDRV_POST_EN => "0b0", + CH0_TX_POST_SIGN => "0b0", + CH0_TX_PRE_SIGN => "0b0", + CH0_RXTERM_CM => "0b11", + CH0_RXIN_CM => "0b11", + CH0_LEQ_OFFSET_SEL => "0b0", + CH0_LEQ_OFFSET_TRIM => "0b000", + D_TX_MAX_RATE => "1.25", + CH0_CDR_MAX_RATE => "1.25", + CH0_TXAMPLITUDE => "0d1100", + CH0_TXDEPRE => "DISABLED", + CH0_TXDEPOST => "DISABLED", + CH0_PROTOCOL => "GBE", + D_ISETLOS => "0d0", + D_SETIRPOLY_AUX => "0b00", + D_SETICONST_AUX => "0b00", + D_SETIRPOLY_CH => "0b00", + D_SETICONST_CH => "0b00", + D_REQ_ISET => "0b000", + D_PD_ISET => "0b00", + D_DCO_CALIB_TIME_SEL => "0b00", + CH0_DCOCTLGI => "0b010", + CH0_DCOATDDLY => "0b00", + CH0_DCOATDCFG => "0b00", + CH0_DCOBYPSATD => "0b1", + CH0_DCOSCALEI => "0b00", + CH0_DCOITUNE4LSB => "0b111", + CH0_DCOIOSTUNE => "0b000", + CH0_DCODISBDAVOID => "0b0", + CH0_DCOCALDIV => "0b001", + CH0_DCONUOFLSB => "0b101", + CH0_DCOIUPDNX2 => "0b1", + CH0_DCOSTEP => "0b00", + CH0_DCOSTARTVAL => "0b000", + CH0_DCOFLTDAC => "0b01", + CH0_DCOITUNE => "0b00", + CH0_DCOFTNRG => "0b110", + CH0_CDR_CNT4SEL => "0b00", + CH0_CDR_CNT8SEL => "0b00", + CH0_BAND_THRESHOLD => "0d0", + CH0_AUTO_FACQ_EN => "0b1", + CH0_AUTO_CALIB_EN => "0b1", + CH0_CALIB_CK_MODE => "0b0", + CH0_REG_BAND_OFFSET => "0d0", + CH0_REG_BAND_SEL => "0d0", + CH0_REG_IDAC_SEL => "0d0", + CH0_REG_IDAC_EN => "0b0", + D_TXPLL_PWDNB => "0b1", + D_SETPLLRC => "0d1", + D_REFCK_MODE => "0b001", + D_TX_VCO_CK_DIV => "0b010", + D_PLL_LOL_SET => "0b00", + D_RG_EN => "0b0", + D_RG_SET => "0b00", + D_CMUSETISCL4VCO => "0b000", + D_CMUSETI4VCO => "0b00", + D_CMUSETINITVCT => "0b00", + D_CMUSETZGM => "0b000", + D_CMUSETP2AGM => "0b000", + D_CMUSETP1GM => "0b000", + D_CMUSETI4CPZ => "0d3", + D_CMUSETI4CPP => "0d3", + D_CMUSETICP4Z => "0b101", + D_CMUSETICP4P => "0b01", + D_CMUSETBIASI => "0b00" +) +port map ( + CH0_HDINP => hdinp, + CH1_HDINP => GND, + CH0_HDINN => hdinn, + CH1_HDINN => GND, + D_TXBIT_CLKP_FROM_ND => GND, + D_TXBIT_CLKN_FROM_ND => GND, + D_SYNC_ND => GND, + D_TXPLL_LOL_FROM_ND => GND, + CH0_RX_REFCLK => rxrefclk, + CH1_RX_REFCLK => GND, + CH0_FF_RXI_CLK => TX_PCLK_7, + CH1_FF_RXI_CLK => VCC, + CH0_FF_TXI_CLK => txi_clk, + CH1_FF_TXI_CLK => VCC, + CH0_FF_EBRD_CLK => TX_PCLK_7, + CH1_FF_EBRD_CLK => VCC, + CH0_FF_TX_D_0 => txdata(0), + CH1_FF_TX_D_0 => GND, + CH0_FF_TX_D_1 => txdata(1), + CH1_FF_TX_D_1 => GND, + CH0_FF_TX_D_2 => txdata(2), + CH1_FF_TX_D_2 => GND, + CH0_FF_TX_D_3 => txdata(3), + CH1_FF_TX_D_3 => GND, + CH0_FF_TX_D_4 => txdata(4), + CH1_FF_TX_D_4 => GND, + CH0_FF_TX_D_5 => txdata(5), + CH1_FF_TX_D_5 => GND, + CH0_FF_TX_D_6 => txdata(6), + CH1_FF_TX_D_6 => GND, + CH0_FF_TX_D_7 => txdata(7), + CH1_FF_TX_D_7 => GND, + CH0_FF_TX_D_8 => tx_k(0), + CH1_FF_TX_D_8 => GND, + CH0_FF_TX_D_9 => GND, + CH1_FF_TX_D_9 => GND, + CH0_FF_TX_D_10 => xmit(0), + CH1_FF_TX_D_10 => GND, + CH0_FF_TX_D_11 => tx_disp_correct(0), + CH1_FF_TX_D_11 => GND, + CH0_FF_TX_D_12 => GND, + CH1_FF_TX_D_12 => GND, + CH0_FF_TX_D_13 => GND, + CH1_FF_TX_D_13 => GND, + CH0_FF_TX_D_14 => GND, + CH1_FF_TX_D_14 => GND, + CH0_FF_TX_D_15 => GND, + CH1_FF_TX_D_15 => GND, + CH0_FF_TX_D_16 => GND, + CH1_FF_TX_D_16 => GND, + CH0_FF_TX_D_17 => GND, + CH1_FF_TX_D_17 => GND, + CH0_FF_TX_D_18 => GND, + CH1_FF_TX_D_18 => GND, + CH0_FF_TX_D_19 => GND, + CH1_FF_TX_D_19 => GND, + CH0_FF_TX_D_20 => GND, + CH1_FF_TX_D_20 => GND, + CH0_FF_TX_D_21 => GND, + CH1_FF_TX_D_21 => GND, + CH0_FF_TX_D_22 => GND, + CH1_FF_TX_D_22 => GND, + CH0_FF_TX_D_23 => GND, + CH1_FF_TX_D_23 => GND, + CH0_FFC_EI_EN => GND, + CH1_FFC_EI_EN => GND, + CH0_FFC_PCIE_DET_EN => GND, + CH1_FFC_PCIE_DET_EN => GND, + CH0_FFC_PCIE_CT => GND, + CH1_FFC_PCIE_CT => GND, + CH0_FFC_SB_INV_RX => GND, + CH1_FFC_SB_INV_RX => GND, + CH0_FFC_ENABLE_CGALIGN => GND, + CH1_FFC_ENABLE_CGALIGN => GND, + CH0_FFC_SIGNAL_DETECT => signal_detect_c, + CH1_FFC_SIGNAL_DETECT => GND, + CH0_FFC_FB_LOOPBACK => GND, + CH1_FFC_FB_LOOPBACK => GND, + CH0_FFC_SB_PFIFO_LP => GND, + CH1_FFC_SB_PFIFO_LP => GND, + CH0_FFC_PFIFO_CLR => GND, + CH1_FFC_PFIFO_CLR => GND, + CH0_FFC_RATE_MODE_RX => GND, + CH1_FFC_RATE_MODE_RX => GND, + CH0_FFC_RATE_MODE_TX => GND, + CH1_FFC_RATE_MODE_TX => GND, + CH0_FFC_DIV11_MODE_RX => GND, + CH1_FFC_DIV11_MODE_RX => GND, + CH0_FFC_RX_GEAR_MODE => GND, + CH1_FFC_RX_GEAR_MODE => GND, + CH0_FFC_TX_GEAR_MODE => GND, + CH1_FFC_TX_GEAR_MODE => GND, + CH0_FFC_DIV11_MODE_TX => GND, + CH1_FFC_DIV11_MODE_TX => GND, + CH0_FFC_LDR_CORE2TX_EN => GND, + CH1_FFC_LDR_CORE2TX_EN => GND, + CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C, + CH1_FFC_LANE_TX_RST => GND, + CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C, + CH1_FFC_LANE_RX_RST => GND, + CH0_FFC_RRST => RSL_RX_SERDES_RST_C, + CH1_FFC_RRST => GND, + CH0_FFC_TXPWDNB => tx_pwrup_c, + CH1_FFC_TXPWDNB => GND, + CH0_FFC_RXPWDNB => rx_pwrup_c, + CH1_FFC_RXPWDNB => GND, + CH0_LDR_CORE2TX => GND, + CH1_LDR_CORE2TX => GND, + D_SCIWDATA0 => GND, + D_SCIWDATA1 => GND, + D_SCIWDATA2 => GND, + D_SCIWDATA3 => GND, + D_SCIWDATA4 => GND, + D_SCIWDATA5 => GND, + D_SCIWDATA6 => GND, + D_SCIWDATA7 => GND, + D_SCIADDR0 => GND, + D_SCIADDR1 => GND, + D_SCIADDR2 => GND, + D_SCIADDR3 => GND, + D_SCIADDR4 => GND, + D_SCIADDR5 => GND, + D_SCIENAUX => GND, + D_SCISELAUX => GND, + CH0_SCIEN => GND, + CH1_SCIEN => GND, + CH0_SCISEL => GND, + CH1_SCISEL => GND, + D_SCIRD => GND, + D_SCIWSTN => GND, + D_CYAWSTN => GND, + D_FFC_SYNC_TOGGLE => GND, + D_FFC_DUAL_RST => rst_dual_c, + D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C, + D_FFC_MACROPDB => serdes_pdb, + D_FFC_TRST => RSL_TX_SERDES_RST_C, + CH0_FFC_CDR_EN_BITSLIP => GND, + CH1_FFC_CDR_EN_BITSLIP => GND, + D_SCAN_ENABLE => GND, + D_SCAN_IN_0 => GND, + D_SCAN_IN_1 => GND, + D_SCAN_IN_2 => GND, + D_SCAN_IN_3 => GND, + D_SCAN_IN_4 => GND, + D_SCAN_IN_5 => GND, + D_SCAN_IN_6 => GND, + D_SCAN_IN_7 => GND, + D_SCAN_MODE => GND, + D_SCAN_RESET => GND, + D_CIN0 => GND, + D_CIN1 => GND, + D_CIN2 => GND, + D_CIN3 => GND, + D_CIN4 => GND, + D_CIN5 => GND, + D_CIN6 => GND, + D_CIN7 => GND, + D_CIN8 => GND, + D_CIN9 => GND, + D_CIN10 => GND, + D_CIN11 => GND, + CH0_HDOUTP => hdoutp, + CH1_HDOUTP => N47_1, + CH0_HDOUTN => hdoutn, + CH1_HDOUTN => N48_1, + D_TXBIT_CLKP_TO_ND => N1_1, + D_TXBIT_CLKN_TO_ND => N2_1, + D_SYNC_PULSE2ND => N3_1, + D_TXPLL_LOL_TO_ND => N4_1, + CH0_FF_RX_F_CLK => N5_1, + CH1_FF_RX_F_CLK => N49_1, + CH0_FF_RX_H_CLK => N6_1, + CH1_FF_RX_H_CLK => N50_1, + CH0_FF_TX_F_CLK => N7_1, + CH1_FF_TX_F_CLK => N51_1, + CH0_FF_TX_H_CLK => N8_1, + CH1_FF_TX_H_CLK => N52_1, + CH0_FF_RX_PCLK => N9_1, + CH1_FF_RX_PCLK => N53_1, + CH0_FF_TX_PCLK => TX_PCLK_7, + CH1_FF_TX_PCLK => N54_1, + CH0_FF_RX_D_0 => rxdata(0), + CH1_FF_RX_D_0 => N55_1, + CH0_FF_RX_D_1 => rxdata(1), + CH1_FF_RX_D_1 => N56_1, + CH0_FF_RX_D_2 => rxdata(2), + CH1_FF_RX_D_2 => N57_1, + CH0_FF_RX_D_3 => rxdata(3), + CH1_FF_RX_D_3 => N58_1, + CH0_FF_RX_D_4 => rxdata(4), + CH1_FF_RX_D_4 => N59_1, + CH0_FF_RX_D_5 => rxdata(5), + CH1_FF_RX_D_5 => N60_1, + CH0_FF_RX_D_6 => rxdata(6), + CH1_FF_RX_D_6 => N61_1, + CH0_FF_RX_D_7 => rxdata(7), + CH1_FF_RX_D_7 => N62_1, + CH0_FF_RX_D_8 => rx_k(0), + CH1_FF_RX_D_8 => N63_1, + CH0_FF_RX_D_9 => rx_disp_err(0), + CH1_FF_RX_D_9 => N64_1, + CH0_FF_RX_D_10 => rx_cv_err(0), + CH1_FF_RX_D_10 => N65_1, + CH0_FF_RX_D_11 => N10_1, + CH1_FF_RX_D_11 => N66_1, + CH0_FF_RX_D_12 => N67_1, + CH1_FF_RX_D_12 => N68_1, + CH0_FF_RX_D_13 => N69_1, + CH1_FF_RX_D_13 => N70_1, + CH0_FF_RX_D_14 => N71_1, + CH1_FF_RX_D_14 => N72_1, + CH0_FF_RX_D_15 => N73_1, + CH1_FF_RX_D_15 => N74_1, + CH0_FF_RX_D_16 => N75_1, + CH1_FF_RX_D_16 => N76_1, + CH0_FF_RX_D_17 => N77_1, + CH1_FF_RX_D_17 => N78_1, + CH0_FF_RX_D_18 => N79_1, + CH1_FF_RX_D_18 => N80_1, + CH0_FF_RX_D_19 => N81_1, + CH1_FF_RX_D_19 => N82_1, + CH0_FF_RX_D_20 => N83_1, + CH1_FF_RX_D_20 => N84_1, + CH0_FF_RX_D_21 => N85_1, + CH1_FF_RX_D_21 => N86_1, + CH0_FF_RX_D_22 => N87_1, + CH1_FF_RX_D_22 => N88_1, + CH0_FF_RX_D_23 => N11_1, + CH1_FF_RX_D_23 => N89_1, + CH0_FFS_PCIE_DONE => N12_1, + CH1_FFS_PCIE_DONE => N90_1, + CH0_FFS_PCIE_CON => N13_1, + CH1_FFS_PCIE_CON => N91_1, + CH0_FFS_RLOS => RX_LOS_LOW_S_8, + CH1_FFS_RLOS => N92_1, + CH0_FFS_LS_SYNC_STATUS => lsm_status_s, + CH1_FFS_LS_SYNC_STATUS => N93_1, + CH0_FFS_CC_UNDERRUN => ctc_urun_s, + CH1_FFS_CC_UNDERRUN => N94_1, + CH0_FFS_CC_OVERRUN => ctc_orun_s, + CH1_FFS_CC_OVERRUN => N95_1, + CH0_FFS_RXFBFIFO_ERROR => N14_1, + CH1_FFS_RXFBFIFO_ERROR => N96_1, + CH0_FFS_TXFBFIFO_ERROR => N15_1, + CH1_FFS_TXFBFIFO_ERROR => N97_1, + CH0_FFS_RLOL => RX_CDR_LOL_S_9, + CH1_FFS_RLOL => N98_1, + CH0_FFS_SKP_ADDED => ctc_ins_s, + CH1_FFS_SKP_ADDED => N99_1, + CH0_FFS_SKP_DELETED => ctc_del_s, + CH1_FFS_SKP_DELETED => N100_1, + CH0_LDR_RX2CORE => N101_1, + CH1_LDR_RX2CORE => N102_1, + D_SCIRDATA0 => N103_1, + D_SCIRDATA1 => N104_1, + D_SCIRDATA2 => N105_1, + D_SCIRDATA3 => N106_1, + D_SCIRDATA4 => N107_1, + D_SCIRDATA5 => N108_1, + D_SCIRDATA6 => N109_1, + D_SCIRDATA7 => N110_1, + D_SCIINT => N121_1, + D_SCAN_OUT_0 => N16_1, + D_SCAN_OUT_1 => N17_1, + D_SCAN_OUT_2 => N18_1, + D_SCAN_OUT_3 => N19_1, + D_SCAN_OUT_4 => N20_1, + D_SCAN_OUT_5 => N21_1, + D_SCAN_OUT_6 => N22_1, + D_SCAN_OUT_7 => N23_1, + D_COUT0 => N24_1, + D_COUT1 => N25_1, + D_COUT2 => N26_1, + D_COUT3 => N27_1, + D_COUT4 => N28_1, + D_COUT5 => N29_1, + D_COUT6 => N30_1, + D_COUT7 => N31_1, + D_COUT8 => N32_1, + D_COUT9 => N33_1, + D_COUT10 => N34_1, + D_COUT11 => N35_1, + D_COUT12 => N36_1, + D_COUT13 => N37_1, + D_COUT14 => N38_1, + D_COUT15 => N39_1, + D_COUT16 => N40_1, + D_COUT17 => N41_1, + D_COUT18 => N42_1, + D_COUT19 => N43_1, + D_REFCLKI => pll_refclki, + D_FFS_PLOL => N46_1); +RSL_INST: PCSDrsl_core_Z1_layer1 port map ( + serdes_rst_dual_c => serdes_rst_dual_c, + rx_serdes_rst_c => rx_serdes_rst_c, + tx_serdes_rst_c => tx_serdes_rst_c, + rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C, + rx_pcs_rst_c => rx_pcs_rst_c, + rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C, + tx_pcs_rst_c => tx_pcs_rst_c, + rsl_disable => rsl_disable, + rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C, + pll_lol => pll_lol, + pll_refclki => pll_refclki, + rx_cdr_lol_s => RX_CDR_LOL_S_9, + rx_los_low_s => RX_LOS_LOW_S_8, + rsl_rst => rsl_rst, + rxrefclk => rxrefclk, + rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C, + rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C); +tx_pclk <= TX_PCLK_7; +rx_los_low_s <= RX_LOS_LOW_S_8; +rx_cdr_lol_s <= RX_CDR_LOL_S_9; +end beh; + diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.vm b/gbe/cores/sgmii/PCSD/syn_results/PCSD.vm new file mode 100644 index 0000000..0a8dd16 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.vm @@ -0,0 +1,2907 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Tue Apr 30 12:09:50 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v " +// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v " +// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v " +// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v " +// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v " +// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh " +// file 16 "\/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v " +// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 18 "\/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc " + +`timescale 100 ps/100 ps +module PCSDrsl_core_Z1_layer1 ( + serdes_rst_dual_c, + rx_serdes_rst_c, + tx_serdes_rst_c, + rsl_rx_pcs_rst_c, + rx_pcs_rst_c, + rsl_tx_pcs_rst_c, + tx_pcs_rst_c, + rsl_disable, + rsl_tx_serdes_rst_c, + pll_lol, + pll_refclki, + rx_cdr_lol_s, + rx_los_low_s, + rsl_rst, + rxrefclk, + rsl_rx_serdes_rst_c, + rsl_serdes_rst_dual_c +) +; +input serdes_rst_dual_c ; +input rx_serdes_rst_c ; +input tx_serdes_rst_c ; +output rsl_rx_pcs_rst_c ; +input rx_pcs_rst_c ; +output rsl_tx_pcs_rst_c ; +input tx_pcs_rst_c ; +input rsl_disable ; +output rsl_tx_serdes_rst_c ; +input pll_lol ; +input pll_refclki ; +input rx_cdr_lol_s ; +input rx_los_low_s ; +input rsl_rst ; +input rxrefclk ; +output rsl_rx_serdes_rst_c ; +output rsl_serdes_rst_dual_c ; +wire serdes_rst_dual_c ; +wire rx_serdes_rst_c ; +wire tx_serdes_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rx_pcs_rst_c ; +wire rsl_tx_pcs_rst_c ; +wire tx_pcs_rst_c ; +wire rsl_disable ; +wire rsl_tx_serdes_rst_c ; +wire pll_lol ; +wire pll_refclki ; +wire rx_cdr_lol_s ; +wire rx_los_low_s ; +wire rsl_rst ; +wire rxrefclk ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire [2:0] plol0_cnt; +wire [2:0] plol0_cnt_3; +wire [1:0] rxs_cnt_3; +wire [1:0] rxs_cnt; +wire [1:0] rxs_cnt_QN; +wire [3:0] rlos_db_cnt; +wire [3:0] rlos_db_cnt_QN; +wire [17:0] rlols0_cnt_s; +wire [17:0] rlols0_cnt; +wire [17:0] rlols0_cnt_QN; +wire [3:0] rlol_db_cnt; +wire [3:0] rlol_db_cnt_QN; +wire [18:0] rlol1_cnt_s; +wire [18:0] rlol1_cnt; +wire [18:0] rlol1_cnt_QN; +wire [1:0] txs_cnt; +wire [1:0] txs_cnt_QN; +wire [1:1] txs_cnt_RNO; +wire [1:0] txp_cnt; +wire [1:0] txp_cnt_QN; +wire [1:1] txp_cnt_RNO; +wire [19:0] plol_cnt_s; +wire [19:0] plol_cnt; +wire [19:0] plol_cnt_QN; +wire [2:0] plol0_cnt_QN; +wire [0:0] un1_rlol_db_cnt_zero; +wire [0:0] un1_rlos_db_cnt_zero; +wire [0:0] un1_rlol_db_cnt_zero_bm; +wire [0:0] un1_rlol_db_cnt_zero_am; +wire [0:0] un1_rlos_db_cnt_zero_bm; +wire [0:0] un1_rlos_db_cnt_zero_am; +wire [16:0] rlol1_cnt_cry; +wire [0:0] rlol1_cnt_cry_0_S0; +wire [17:17] rlol1_cnt_cry_0_COUT; +wire [16:0] rlols0_cnt_cry; +wire [0:0] rlols0_cnt_cry_0_S0; +wire [17:17] rlols0_cnt_s_0_COUT; +wire [17:17] rlols0_cnt_s_0_S1; +wire [18:0] plol_cnt_cry; +wire [0:0] plol_cnt_cry_0_S0; +wire [19:19] plol_cnt_s_0_COUT; +wire [19:19] plol_cnt_s_0_S1; +wire rlos_db_p1 ; +wire rlos_db ; +wire rxp_rst25 ; +wire plol0_cnt9 ; +wire waita_plol0 ; +wire rlol1_cnt_tc_1 ; +wire rxs_rst ; +wire rlol1_cnt_scalar ; +wire waita_rlols06 ; +wire un1_rlols0_cnt_tc ; +wire waita_rlols0 ; +wire waita_rlols0_QN ; +wire VCC ; +wire wait_calib_RNO ; +wire un1_rlos_fedge_1 ; +wire wait_calib ; +wire wait_calib_QN ; +wire rxs_rst6 ; +wire un1_rxs_cnt_tc ; +wire rxs_rst_QN ; +wire un2_rlos_redge_1_i ; +wire rxp_rst2 ; +wire rxp_rst2_QN ; +wire rlos_p1 ; +wire rlos_p2 ; +wire rlos_p2_QN ; +wire rlos_p1_QN ; +wire rlos_db_p1_QN ; +wire rlos_db_cnt_axb_0 ; +wire rlos_db_cnt_cry_1_0_S0 ; +wire rlos_db_cnt_cry_1_0_S1 ; +wire rlos_db_cnt_s_3_0_S0 ; +wire un1_rlos_db_cnt_max ; +wire rlos_db_QN ; +wire rlols0_cnte ; +wire rlol_p1 ; +wire rlol_p2 ; +wire rlol_p2_QN ; +wire rlol_p1_QN ; +wire rlol_db ; +wire rlol_db_p1 ; +wire rlol_db_p1_QN ; +wire rlol_db_cnt_axb_0 ; +wire rlol_db_cnt_cry_1_0_S0 ; +wire rlol_db_cnt_cry_1_0_S1 ; +wire rlol_db_cnt_s_3_0_S0 ; +wire un1_rlol_db_cnt_max ; +wire rlol_db_QN ; +wire rlol1_cnte ; +wire plol_fedge ; +wire un1_plol0_cnt_tc_1_i ; +wire waita_plol0_QN ; +wire un1_plol_cnt_tc ; +wire un2_plol_cnt_tc ; +wire txs_rst ; +wire txs_rst_QN ; +wire N_12_i ; +wire un9_plol0_cnt_tc ; +wire un1_plol0_cnt_tc_1 ; +wire txp_rst ; +wire txp_rst_QN ; +wire N_13_i ; +wire pll_lol_p2 ; +wire pll_lol_p3 ; +wire pll_lol_p3_QN ; +wire pll_lol_p1 ; +wire pll_lol_p2_QN ; +wire pll_lol_p1_QN ; +wire rlols0_cnt_tc_1 ; +wire rlos_redge ; +wire rlols0_cnt11_0 ; +wire plol_cnt_scalar ; +wire rlols0_cnt_scalar ; +wire un8_rxs_cnt_tc ; +wire un1_plol_cnt_tc_11 ; +wire un1_plol_cnt_tc_12 ; +wire un1_plol_cnt_tc_13 ; +wire un1_plol_cnt_tc_14 ; +wire rlols0_cnt_tc_1_10 ; +wire rlols0_cnt_tc_1_11 ; +wire rlols0_cnt_tc_1_12 ; +wire rlols0_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_11 ; +wire rlol1_cnt_tc_1_12 ; +wire rlol1_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_14 ; +wire CO0_2 ; +wire rlols0_cnt_tc_1_9 ; +wire un1_plol_cnt_tc_10 ; +wire rlol1_cnt_tc_1_10 ; +wire rlos_db_cnt_cry_0 ; +wire rlos_db_cnt_cry_0_0_S0 ; +wire rlos_db_cnt_cry_0_0_S1 ; +wire rlos_db_cnt_cry_2 ; +wire rlos_db_cnt_s_3_0_COUT ; +wire rlos_db_cnt_s_3_0_S1 ; +wire rlol_db_cnt_cry_0 ; +wire rlol_db_cnt_cry_0_0_S0 ; +wire rlol_db_cnt_cry_0_0_S1 ; +wire rlol_db_cnt_cry_2 ; +wire rlol_db_cnt_s_3_0_COUT ; +wire rlol_db_cnt_s_3_0_S1 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; + LUT4 \genblk2.rxp_rst2_RNO ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_rx_serdes_rst_c), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rxp_rst25) +); +defparam \genblk2.rxp_rst2_RNO .init=16'hEFEE; + LUT4 \genblk1.plol0_cnt_RNO[1] ( + .A(plol0_cnt[1]), + .B(plol0_cnt9), + .C(waita_plol0), + .D(plol0_cnt[0]), + .Z(plol0_cnt_3[1]) +); +defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222; + LUT4 \genblk2.rxs_rst_RNIS0OP ( + .A(rlol1_cnt_tc_1), + .B(rxs_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlol1_cnt_scalar) +); +defparam \genblk2.rxs_rst_RNIS0OP .init=16'h1011; +// @16:759 + FD1P3DX \genblk2.waita_rlols0 ( + .D(waita_rlols06), + .SP(un1_rlols0_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(waita_rlols0) +); +// @16:656 + FD1P3BX \genblk2.wait_calib ( + .D(wait_calib_RNO), + .SP(un1_rlos_fedge_1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(wait_calib) +); +// @16:694 + FD1P3DX \genblk2.rxs_rst ( + .D(rxs_rst6), + .SP(un1_rxs_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_rst) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[0] ( + .D(rxs_cnt_3[0]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[0]) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[1] ( + .D(rxs_cnt_3[1]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[1]) +); +// @16:806 + FD1P3BX \genblk2.rxp_rst2 ( + .D(rxp_rst25), + .SP(un2_rlos_redge_1_i), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxp_rst2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p2 ( + .D(rlos_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p1 ( + .D(rx_los_low_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p1) +); +// @16:567 + FD1S3BX \genblk2.rlos_db_p1 ( + .D(rlos_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_p1) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[0] ( + .D(rlos_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[0]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[1] ( + .D(rlos_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[1]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[2] ( + .D(rlos_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[2]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[3] ( + .D(rlos_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[3]) +); +// @16:649 + FD1P3BX \genblk2.rlos_db ( + .D(rlos_db_cnt[3]), + .SP(un1_rlos_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[0] ( + .D(rlols0_cnt_s[0]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[0]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[1] ( + .D(rlols0_cnt_s[1]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[1]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[2] ( + .D(rlols0_cnt_s[2]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[2]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[3] ( + .D(rlols0_cnt_s[3]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[3]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[4] ( + .D(rlols0_cnt_s[4]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[4]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[5] ( + .D(rlols0_cnt_s[5]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[5]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[6] ( + .D(rlols0_cnt_s[6]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[6]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[7] ( + .D(rlols0_cnt_s[7]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[7]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[8] ( + .D(rlols0_cnt_s[8]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[8]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[9] ( + .D(rlols0_cnt_s[9]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[9]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[10] ( + .D(rlols0_cnt_s[10]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[10]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[11] ( + .D(rlols0_cnt_s[11]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[11]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[12] ( + .D(rlols0_cnt_s[12]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[12]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[13] ( + .D(rlols0_cnt_s[13]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[13]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[14] ( + .D(rlols0_cnt_s[14]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[14]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[15] ( + .D(rlols0_cnt_s[15]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[15]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[16] ( + .D(rlols0_cnt_s[16]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[16]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[17] ( + .D(rlols0_cnt_s[17]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[17]) +); +// @16:567 + FD1S3DX \genblk2.rlol_p2 ( + .D(rlol_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p2) +); +// @16:567 + FD1S3DX \genblk2.rlol_p1 ( + .D(rx_cdr_lol_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p1) +); +// @16:567 + FD1S3BX \genblk2.rlol_db_p1 ( + .D(rlol_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_p1) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[0] ( + .D(rlol_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[0]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[1] ( + .D(rlol_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[1]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[2] ( + .D(rlol_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[2]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[3] ( + .D(rlol_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[3]) +); +// @16:633 + FD1P3BX \genblk2.rlol_db ( + .D(rlol_db_cnt[3]), + .SP(un1_rlol_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[0] ( + .D(rlol1_cnt_s[0]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[0]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[1] ( + .D(rlol1_cnt_s[1]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[1]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[2] ( + .D(rlol1_cnt_s[2]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[2]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[3] ( + .D(rlol1_cnt_s[3]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[3]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[4] ( + .D(rlol1_cnt_s[4]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[4]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[5] ( + .D(rlol1_cnt_s[5]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[5]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[6] ( + .D(rlol1_cnt_s[6]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[6]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[7] ( + .D(rlol1_cnt_s[7]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[7]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[8] ( + .D(rlol1_cnt_s[8]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[8]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[9] ( + .D(rlol1_cnt_s[9]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[9]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[10] ( + .D(rlol1_cnt_s[10]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[10]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[11] ( + .D(rlol1_cnt_s[11]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[11]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[12] ( + .D(rlol1_cnt_s[12]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[12]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[13] ( + .D(rlol1_cnt_s[13]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[13]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[14] ( + .D(rlol1_cnt_s[14]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[14]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[15] ( + .D(rlol1_cnt_s[15]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[15]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[16] ( + .D(rlol1_cnt_s[16]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[16]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[17] ( + .D(rlol1_cnt_s[17]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[17]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[18] ( + .D(rlol1_cnt_s[18]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[18]) +); +// @16:443 + FD1P3DX \genblk1.waita_plol0 ( + .D(plol_fedge), + .SP(un1_plol0_cnt_tc_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(waita_plol0) +); +// @16:422 + FD1P3DX \genblk1.txs_rst ( + .D(un1_plol_cnt_tc), + .SP(un2_plol_cnt_tc), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_rst) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[0] ( + .D(N_12_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[0]) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[1] ( + .D(txs_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[1]) +); +// @16:461 + FD1P3DX \genblk1.txp_rst ( + .D(un9_plol0_cnt_tc), + .SP(un1_plol0_cnt_tc_1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_rst) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[0] ( + .D(N_13_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[0]) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[1] ( + .D(txp_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[0] ( + .D(plol_cnt_s[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[0]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[1] ( + .D(plol_cnt_s[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[2] ( + .D(plol_cnt_s[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[2]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[3] ( + .D(plol_cnt_s[3]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[3]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[4] ( + .D(plol_cnt_s[4]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[4]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[5] ( + .D(plol_cnt_s[5]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[5]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[6] ( + .D(plol_cnt_s[6]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[6]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[7] ( + .D(plol_cnt_s[7]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[7]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[8] ( + .D(plol_cnt_s[8]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[8]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[9] ( + .D(plol_cnt_s[9]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[9]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[10] ( + .D(plol_cnt_s[10]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[10]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[11] ( + .D(plol_cnt_s[11]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[11]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[12] ( + .D(plol_cnt_s[12]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[12]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[13] ( + .D(plol_cnt_s[13]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[13]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[14] ( + .D(plol_cnt_s[14]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[14]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[15] ( + .D(plol_cnt_s[15]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[15]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[16] ( + .D(plol_cnt_s[16]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[16]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[17] ( + .D(plol_cnt_s[17]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[17]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[18] ( + .D(plol_cnt_s[18]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[18]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[19] ( + .D(plol_cnt_s[19]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[19]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[0] ( + .D(plol0_cnt_3[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[0]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[1] ( + .D(plol0_cnt_3[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[1]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[2] ( + .D(plol0_cnt_3[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[2]) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p3 ( + .D(pll_lol_p2), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p3) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p2 ( + .D(pll_lol_p1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p2) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p1 ( + .D(pll_lol), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p1) +); +// @16:422 + LUT4 \genblk1.txs_cnt_RNO[0] ( + .A(txs_cnt[0]), + .B(txs_rst), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(N_12_i) +); +defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6; +// @16:434 + LUT4 \genblk1.txs_cnt_RNO[1] ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(txs_rst), + .D(un1_plol_cnt_tc), + .Z(txs_cnt_RNO[1]) +); +defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C; +// @16:806 + LUT4 \genblk2.rxp_rst2_RNO_0 ( + .A(rlols0_cnt_tc_1), + .B(rlos_redge), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un2_rlos_redge_1_i) +); +defparam \genblk2.rxp_rst2_RNO_0 .init=16'hFFFE; +// @8:357 + LUT4 \genblk2.waita_rlols0_RNI266C ( + .A(rlols0_cnt11_0), + .B(waita_rlols0), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(rlols0_cnte) +); +defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE; +// @8:357 + LUT4 \genblk2.wait_calib_RNIKRP81 ( + .A(rxs_rst), + .B(wait_calib), + .C(rlol1_cnt_tc_1), + .D(rlos_redge), + .Z(rlol1_cnte) +); +defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE; +// @16:317 + LUT4 \genblk2.rxs_rst6 ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(rxs_rst6) +); +defparam \genblk2.rxs_rst6 .init=16'h2020; +// @16:412 + LUT4 \genblk1.plol_cnt11_i ( + .A(pll_lol_p2), + .B(un1_plol_cnt_tc), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(plol_cnt_scalar) +); +defparam \genblk1.plol_cnt11_i .init=16'h0202; +// @16:778 + LUT4 \genblk2.rlols0_cnt11_i ( + .A(rlols0_cnt11_0), + .B(rlols0_cnt_tc_1), + .C(VCC), + .D(VCC), + .Z(rlols0_cnt_scalar) +); +defparam \genblk2.rlols0_cnt11_i .init=16'h1111; +// @16:317 + LUT4 \genblk2.un1_rxs_cnt_tc ( + .A(rlol_db), + .B(rlos_db), + .C(un8_rxs_cnt_tc), + .D(rlol1_cnt_tc_1), + .Z(un1_rxs_cnt_tc) +); +defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC; +// @8:357 + LUT4 \genblk2.wait_calib_RNO ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(wait_calib_RNO) +); +defparam \genblk2.wait_calib_RNO .init=16'hA3A3; +// @16:259 + LUT4 \genblk1.un2_plol_cnt_tc ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(un2_plol_cnt_tc) +); +defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8; +// @16:340 + LUT4 \genblk2.un1_rlols0_cnt_tc ( + .A(rlols0_cnt11_0), + .B(waita_rlols06), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(un1_rlols0_cnt_tc) +); +defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE; +// @16:322 + LUT4 \genblk2.un1_rlos_fedge_1 ( + .A(rlos_db), + .B(rlos_db_p1), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(un1_rlos_fedge_1) +); +defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6; +// @16:461 + LUT4 \genblk1.txp_cnt_RNO[0] ( + .A(txp_cnt[0]), + .B(txp_rst), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(N_13_i) +); +defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6; +// @16:473 + LUT4 \genblk1.txp_cnt_RNO[1] ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(txp_rst), + .D(un9_plol0_cnt_tc), + .Z(txp_cnt_RNO[1]) +); +defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc ( + .A(un1_plol_cnt_tc_11), + .B(un1_plol_cnt_tc_12), + .C(un1_plol_cnt_tc_13), + .D(un1_plol_cnt_tc_14), + .Z(un1_plol_cnt_tc) +); +defparam \genblk1.un1_plol_cnt_tc .init=16'h8000; +// @16:388 + LUT4 rlols0_cnt_tc_1_cZ ( + .A(rlols0_cnt_tc_1_10), + .B(rlols0_cnt_tc_1_11), + .C(rlols0_cnt_tc_1_12), + .D(rlols0_cnt_tc_1_13), + .Z(rlols0_cnt_tc_1) +); +defparam rlols0_cnt_tc_1_cZ.init=16'h8000; +// @16:387 + LUT4 rlol1_cnt_tc_1_cZ ( + .A(rlol1_cnt_tc_1_11), + .B(rlol1_cnt_tc_1_12), + .C(rlol1_cnt_tc_1_13), + .D(rlol1_cnt_tc_1_14), + .Z(rlol1_cnt_tc_1) +); +defparam rlol1_cnt_tc_1_cZ.init=16'h8000; +// @16:625 + LUT4 \un1_genblk2.rlol_db_cnt_axb_0 ( + .A(rlol_db_cnt[0]), + .B(un1_rlol_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlol_db_cnt_axb_0) +); +defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999; +// @16:641 + LUT4 \un1_genblk2.rlos_db_cnt_axb_0 ( + .A(rlos_db_cnt[0]), + .B(un1_rlos_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlos_db_cnt_axb_0) +); +defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999; +// @16:443 + LUT4 \genblk1.waita_plol0_RNO ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1_i) +); +defparam \genblk1.waita_plol0_RNO .init=16'hF6F6; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[2] ( + .A(CO0_2), + .B(plol0_cnt9), + .C(plol0_cnt[1]), + .D(plol0_cnt[2]), + .Z(plol0_cnt_3[2]) +); +defparam \genblk1.plol0_cnt_3[2] .init=16'h1320; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[0] ( + .A(plol0_cnt9), + .B(plol0_cnt[0]), + .C(waita_plol0), + .D(VCC), + .Z(plol0_cnt_3[0]) +); +defparam \genblk1.plol0_cnt_3[0] .init=16'h1414; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_bm[0]) +); +defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlol_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlol_db_cnt_zero_bm[0]), + .BLUT(un1_rlol_db_cnt_zero_am[0]), + .C0(rlol_p2), + .Z(un1_rlol_db_cnt_zero[0]) +); +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_bm[0]) +); +defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlos_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlos_db_cnt_zero_bm[0]), + .BLUT(un1_rlos_db_cnt_zero_am[0]), + .C0(rlos_p2), + .Z(un1_rlos_db_cnt_zero[0]) +); +// @16:269 + LUT4 \genblk1.un1_plol0_cnt_tc_1 ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1) +); +defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8; +// @16:708 + LUT4 \rxs_cnt_3_cZ[1] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[1]) +); +defparam \rxs_cnt_3_cZ[1] .init=16'h6464; +// @16:764 + LUT4 \genblk2.waita_rlols06 ( + .A(rlol_db), + .B(rlol_db_p1), + .C(rlos_db), + .D(rlos_db_p1), + .Z(waita_rlols06) +); +defparam \genblk2.waita_rlols06 .init=16'h0504; +// @16:309 + LUT4 \genblk2.un1_rlol_db_cnt_max ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_max) +); +defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001; +// @16:315 + LUT4 \genblk2.un1_rlos_db_cnt_max ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_max) +); +defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001; +// @16:388 + LUT4 rlols0_cnt_tc_1_13_cZ ( + .A(rlols0_cnt[12]), + .B(rlols0_cnt[13]), + .C(rlols0_cnt_tc_1_9), + .D(VCC), + .Z(rlols0_cnt_tc_1_13) +); +defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_14 ( + .A(plol_cnt[5]), + .B(plol_cnt[10]), + .C(plol_cnt[18]), + .D(un1_plol_cnt_tc_10), + .Z(un1_plol_cnt_tc_14) +); +defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_14_cZ ( + .A(rlol1_cnt[12]), + .B(rlol1_cnt[13]), + .C(rlol1_cnt[18]), + .D(rlol1_cnt_tc_1_10), + .Z(rlol1_cnt_tc_1_14) +); +defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100; +// @16:479 + LUT4 \rdo_tx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(txp_rst), + .C(tx_pcs_rst_c), + .D(VCC), + .Z(rsl_tx_pcs_rst_c) +); +defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:852 + LUT4 \rdo_rx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(rxp_rst2), + .C(rx_pcs_rst_c), + .D(VCC), + .Z(rsl_rx_pcs_rst_c) +); +defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:438 + LUT4 rdo_tx_serdes_rst_c ( + .A(rsl_disable), + .B(txs_rst), + .C(tx_serdes_rst_c), + .D(VCC), + .Z(rsl_tx_serdes_rst_c) +); +defparam rdo_tx_serdes_rst_c.init=16'hF4F4; +// @16:708 + LUT4 \rxs_cnt_3_cZ[0] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[0]) +); +defparam \rxs_cnt_3_cZ[0] .init=16'h5252; +// @16:743 + LUT4 \rdo_rx_serdes_rst_c_1[0] ( + .A(rsl_disable), + .B(rxs_rst), + .C(rx_serdes_rst_c), + .D(VCC), + .Z(rsl_rx_serdes_rst_c) +); +defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4; +// @16:375 + LUT4 rdo_serdes_rst_dual_c ( + .A(rsl_disable), + .B(rsl_rst), + .C(serdes_rst_dual_c), + .D(VCC), + .Z(rsl_serdes_rst_dual_c) +); +defparam rdo_serdes_rst_dual_c.init=16'hF4F4; +// @16:459 + LUT4 \genblk1.un9_plol0_cnt_tc ( + .A(plol0_cnt[0]), + .B(plol0_cnt[1]), + .C(plol0_cnt[2]), + .D(VCC), + .Z(un9_plol0_cnt_tc) +); +defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010; +// @16:388 + LUT4 rlols0_cnt_tc_1_9_cZ ( + .A(rlols0_cnt[10]), + .B(rlols0_cnt[14]), + .C(rlols0_cnt[16]), + .D(rlols0_cnt[17]), + .Z(rlols0_cnt_tc_1_9) +); +defparam rlols0_cnt_tc_1_9_cZ.init=16'h0008; +// @16:388 + LUT4 rlols0_cnt_tc_1_10_cZ ( + .A(rlols0_cnt[0]), + .B(rlols0_cnt[1]), + .C(rlols0_cnt[2]), + .D(rlols0_cnt[15]), + .Z(rlols0_cnt_tc_1_10) +); +defparam rlols0_cnt_tc_1_10_cZ.init=16'h0100; +// @16:388 + LUT4 rlols0_cnt_tc_1_11_cZ ( + .A(rlols0_cnt[3]), + .B(rlols0_cnt[4]), + .C(rlols0_cnt[5]), + .D(rlols0_cnt[6]), + .Z(rlols0_cnt_tc_1_11) +); +defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_12_cZ ( + .A(rlols0_cnt[7]), + .B(rlols0_cnt[8]), + .C(rlols0_cnt[9]), + .D(rlols0_cnt[11]), + .Z(rlols0_cnt_tc_1_12) +); +defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_10 ( + .A(plol_cnt[1]), + .B(plol_cnt[6]), + .C(plol_cnt[7]), + .D(plol_cnt[12]), + .Z(un1_plol_cnt_tc_10) +); +defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h0080; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_11 ( + .A(plol_cnt[8]), + .B(plol_cnt[9]), + .C(plol_cnt[11]), + .D(plol_cnt[13]), + .Z(un1_plol_cnt_tc_11) +); +defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_12 ( + .A(plol_cnt[14]), + .B(plol_cnt[15]), + .C(plol_cnt[16]), + .D(plol_cnt[17]), + .Z(un1_plol_cnt_tc_12) +); +defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_13 ( + .A(plol_cnt[2]), + .B(plol_cnt[3]), + .C(plol_cnt[4]), + .D(plol_cnt[19]), + .Z(un1_plol_cnt_tc_13) +); +defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_10_cZ ( + .A(rlol1_cnt[14]), + .B(rlol1_cnt[15]), + .C(rlol1_cnt[16]), + .D(rlol1_cnt[17]), + .Z(rlol1_cnt_tc_1_10) +); +defparam rlol1_cnt_tc_1_10_cZ.init=16'h0800; +// @16:387 + LUT4 rlol1_cnt_tc_1_11_cZ ( + .A(rlol1_cnt[0]), + .B(rlol1_cnt[1]), + .C(rlol1_cnt[2]), + .D(rlol1_cnt[3]), + .Z(rlol1_cnt_tc_1_11) +); +defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_12_cZ ( + .A(rlol1_cnt[4]), + .B(rlol1_cnt[5]), + .C(rlol1_cnt[6]), + .D(rlol1_cnt[7]), + .Z(rlol1_cnt_tc_1_12) +); +defparam rlol1_cnt_tc_1_12_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_13_cZ ( + .A(rlol1_cnt[8]), + .B(rlol1_cnt[9]), + .C(rlol1_cnt[10]), + .D(rlol1_cnt[11]), + .Z(rlol1_cnt_tc_1_13) +); +defparam rlol1_cnt_tc_1_13_cZ.init=16'h0001; +// @16:457 + LUT4 \genblk1.plol0_cnt_3_RNO[2] ( + .A(plol0_cnt[0]), + .B(waita_plol0), + .C(VCC), + .D(VCC), + .Z(CO0_2) +); +defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888; +// @16:441 + LUT4 plol_fedge_cZ ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(VCC), + .D(VCC), + .Z(plol_fedge) +); +defparam plol_fedge_cZ.init=16'h4444; +// @16:757 + LUT4 rlos_redge_cZ ( + .A(rlos_db), + .B(rlos_db_p1), + .C(VCC), + .D(VCC), + .Z(rlos_redge) +); +defparam rlos_redge_cZ.init=16'h2222; +// @16:436 + LUT4 \genblk2.un8_rxs_cnt_tc ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(VCC), + .D(VCC), + .Z(un8_rxs_cnt_tc) +); +defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888; +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_am_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_am[0]) +); +defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_am_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_am[0]) +); +defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:454 + LUT4 \genblk1.plol0_cnt9 ( + .A(pll_lol_p2), + .B(plol0_cnt[2]), + .C(plol0_cnt[1]), + .D(plol0_cnt[0]), + .Z(plol0_cnt9) +); +defparam \genblk1.plol0_cnt9 .init=16'hAAAE; +// @16:783 + LUT4 \genblk2.rlols0_cnt11_0 ( + .A(rlol_db_p1), + .B(rlol_db), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlols0_cnt11_0) +); +defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44; + CCU2C \genblk2.rlol1_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlol1_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(rlol1_cnt_cry[0]), + .S0(rlol1_cnt_cry_0_S0[0]), + .S1(rlol1_cnt_s[0]) +); +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[1] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[0]), + .COUT(rlol1_cnt_cry[2]), + .S0(rlol1_cnt_s[1]), + .S1(rlol1_cnt_s[2]) +); +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[3] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[2]), + .COUT(rlol1_cnt_cry[4]), + .S0(rlol1_cnt_s[3]), + .S1(rlol1_cnt_s[4]) +); +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[5] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[4]), + .COUT(rlol1_cnt_cry[6]), + .S0(rlol1_cnt_s[5]), + .S1(rlol1_cnt_s[6]) +); +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[7] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[6]), + .COUT(rlol1_cnt_cry[8]), + .S0(rlol1_cnt_s[7]), + .S1(rlol1_cnt_s[8]) +); +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[9] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[8]), + .COUT(rlol1_cnt_cry[10]), + .S0(rlol1_cnt_s[9]), + .S1(rlol1_cnt_s[10]) +); +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[11] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[10]), + .COUT(rlol1_cnt_cry[12]), + .S0(rlol1_cnt_s[11]), + .S1(rlol1_cnt_s[12]) +); +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[13] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[12]), + .COUT(rlol1_cnt_cry[14]), + .S0(rlol1_cnt_s[13]), + .S1(rlol1_cnt_s[14]) +); +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[15] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[14]), + .COUT(rlol1_cnt_cry[16]), + .S0(rlol1_cnt_s[15]), + .S1(rlol1_cnt_s[16]) +); +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[17] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[16]), + .COUT(rlol1_cnt_cry_0_COUT[17]), + .S0(rlol1_cnt_s[17]), + .S1(rlol1_cnt_s[18]) +); +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO"; + CCU2C \genblk2.rlols0_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlols0_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rlols0_cnt_cry[0]), + .S0(rlols0_cnt_cry_0_S0[0]), + .S1(rlols0_cnt_s[0]) +); +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[1] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[0]), + .COUT(rlols0_cnt_cry[2]), + .S0(rlols0_cnt_s[1]), + .S1(rlols0_cnt_s[2]) +); +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[3] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[2]), + .COUT(rlols0_cnt_cry[4]), + .S0(rlols0_cnt_s[3]), + .S1(rlols0_cnt_s[4]) +); +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[5] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[4]), + .COUT(rlols0_cnt_cry[6]), + .S0(rlols0_cnt_s[5]), + .S1(rlols0_cnt_s[6]) +); +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[7] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[6]), + .COUT(rlols0_cnt_cry[8]), + .S0(rlols0_cnt_s[7]), + .S1(rlols0_cnt_s[8]) +); +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[9] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[8]), + .COUT(rlols0_cnt_cry[10]), + .S0(rlols0_cnt_s[9]), + .S1(rlols0_cnt_s[10]) +); +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[11] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[10]), + .COUT(rlols0_cnt_cry[12]), + .S0(rlols0_cnt_s[11]), + .S1(rlols0_cnt_s[12]) +); +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[13] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[12]), + .COUT(rlols0_cnt_cry[14]), + .S0(rlols0_cnt_s[13]), + .S1(rlols0_cnt_s[14]) +); +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[15] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[14]), + .COUT(rlols0_cnt_cry[16]), + .S0(rlols0_cnt_s[15]), + .S1(rlols0_cnt_s[16]) +); +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_s_0[17] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[16]), + .COUT(rlols0_cnt_s_0_COUT[17]), + .S0(rlols0_cnt_s[17]), + .S1(rlols0_cnt_s_0_S1[17]) +); +defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a; +defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO"; + CCU2C \genblk1.plol_cnt_cry_0[0] ( + .A0(VCC), + .B0(plol_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(plol_cnt_cry[0]), + .S0(plol_cnt_cry_0_S0[0]), + .S1(plol_cnt_s[0]) +); +defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[1] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[0]), + .COUT(plol_cnt_cry[2]), + .S0(plol_cnt_s[1]), + .S1(plol_cnt_s[2]) +); +defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[3] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[2]), + .COUT(plol_cnt_cry[4]), + .S0(plol_cnt_s[3]), + .S1(plol_cnt_s[4]) +); +defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[5] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[4]), + .COUT(plol_cnt_cry[6]), + .S0(plol_cnt_s[5]), + .S1(plol_cnt_s[6]) +); +defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[7] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[6]), + .COUT(plol_cnt_cry[8]), + .S0(plol_cnt_s[7]), + .S1(plol_cnt_s[8]) +); +defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[9] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[8]), + .COUT(plol_cnt_cry[10]), + .S0(plol_cnt_s[9]), + .S1(plol_cnt_s[10]) +); +defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[11] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[10]), + .COUT(plol_cnt_cry[12]), + .S0(plol_cnt_s[11]), + .S1(plol_cnt_s[12]) +); +defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[13] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[12]), + .COUT(plol_cnt_cry[14]), + .S0(plol_cnt_s[13]), + .S1(plol_cnt_s[14]) +); +defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[15] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[14]), + .COUT(plol_cnt_cry[16]), + .S0(plol_cnt_s[15]), + .S1(plol_cnt_s[16]) +); +defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[17] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[16]), + .COUT(plol_cnt_cry[18]), + .S0(plol_cnt_s[17]), + .S1(plol_cnt_s[18]) +); +defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_s_0[19] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[19]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[18]), + .COUT(plol_cnt_s_0_COUT[19]), + .S0(plol_cnt_s[19]), + .S1(plol_cnt_s_0_S1[19]) +); +defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a; +defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlos_db_cnt[0]), + .B1(un1_rlos_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(rlos_db_cnt_cry_0), + .S0(rlos_db_cnt_cry_0_0_S0), + .S1(rlos_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0 ( + .A0(un1_rlos_db_cnt_zero[0]), + .B0(rlos_p2), + .C0(rlos_db_cnt[1]), + .D0(VCC), + .A1(un1_rlos_db_cnt_zero[0]), + .B1(rlos_p2), + .C1(rlos_db_cnt[2]), + .D1(VCC), + .CIN(rlos_db_cnt_cry_0), + .COUT(rlos_db_cnt_cry_2), + .S0(rlos_db_cnt_cry_1_0_S0), + .S1(rlos_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_s_3_0 ( + .A0(rlos_db_cnt[3]), + .B0(rlos_p2), + .C0(un1_rlos_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlos_db_cnt_cry_2), + .COUT(rlos_db_cnt_s_3_0_COUT), + .S0(rlos_db_cnt_s_3_0_S0), + .S1(rlos_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlol_db_cnt[0]), + .B1(un1_rlol_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(rlol_db_cnt_cry_0), + .S0(rlol_db_cnt_cry_0_0_S0), + .S1(rlol_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0 ( + .A0(un1_rlol_db_cnt_zero[0]), + .B0(rlol_p2), + .C0(rlol_db_cnt[1]), + .D0(VCC), + .A1(un1_rlol_db_cnt_zero[0]), + .B1(rlol_p2), + .C1(rlol_db_cnt[2]), + .D1(VCC), + .CIN(rlol_db_cnt_cry_0), + .COUT(rlol_db_cnt_cry_2), + .S0(rlol_db_cnt_cry_1_0_S0), + .S1(rlol_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_s_3_0 ( + .A0(rlol_db_cnt[3]), + .B0(rlol_p2), + .C0(un1_rlol_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlol_db_cnt_cry_2), + .COUT(rlol_db_cnt_s_3_0_COUT), + .S0(rlol_db_cnt_s_3_0_S0), + .S1(rlol_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO"; + VHI VCC_0 ( + .Z(VCC) +); + VLO GND_cZ ( + .Z(GND) +); +endmodule /* PCSDrsl_core_Z1_layer1 */ + +module PCSD ( + hdoutp, + hdoutn, + hdinp, + hdinn, + rxrefclk, + tx_pclk, + txi_clk, + txdata, + tx_k, + xmit, + tx_disp_correct, + rxdata, + rx_k, + rx_disp_err, + rx_cv_err, + signal_detect_c, + rx_los_low_s, + lsm_status_s, + ctc_urun_s, + ctc_orun_s, + rx_cdr_lol_s, + ctc_ins_s, + ctc_del_s, + tx_pwrup_c, + rx_pwrup_c, + serdes_pdb, + pll_refclki, + rsl_disable, + rsl_rst, + serdes_rst_dual_c, + rst_dual_c, + tx_serdes_rst_c, + tx_pcs_rst_c, + pll_lol, + rx_serdes_rst_c, + rx_pcs_rst_c +) +; +output hdoutp ; +output hdoutn ; +input hdinp ; +input hdinn ; +input rxrefclk ; +output tx_pclk ; +input txi_clk ; +input [7:0] txdata ; +input [0:0] tx_k ; +input [0:0] xmit ; +input [0:0] tx_disp_correct ; +output [7:0] rxdata ; +output [0:0] rx_k ; +output [0:0] rx_disp_err ; +output [0:0] rx_cv_err ; +input signal_detect_c ; +output rx_los_low_s ; +output lsm_status_s ; +output ctc_urun_s ; +output ctc_orun_s ; +output rx_cdr_lol_s ; +output ctc_ins_s ; +output ctc_del_s ; +input tx_pwrup_c ; +input rx_pwrup_c ; +input serdes_pdb ; +input pll_refclki ; +input rsl_disable ; +input rsl_rst ; +input serdes_rst_dual_c ; +input rst_dual_c ; +input tx_serdes_rst_c ; +input tx_pcs_rst_c ; +input pll_lol ; +input rx_serdes_rst_c ; +input rx_pcs_rst_c ; +wire hdoutp ; +wire hdoutn ; +wire hdinp ; +wire hdinn ; +wire rxrefclk ; +wire tx_pclk ; +wire txi_clk ; +wire signal_detect_c ; +wire rx_los_low_s ; +wire lsm_status_s ; +wire ctc_urun_s ; +wire ctc_orun_s ; +wire rx_cdr_lol_s ; +wire ctc_ins_s ; +wire ctc_del_s ; +wire tx_pwrup_c ; +wire rx_pwrup_c ; +wire serdes_pdb ; +wire pll_refclki ; +wire rsl_disable ; +wire rsl_rst ; +wire serdes_rst_dual_c ; +wire rst_dual_c ; +wire tx_serdes_rst_c ; +wire tx_pcs_rst_c ; +wire pll_lol ; +wire rx_serdes_rst_c ; +wire rx_pcs_rst_c ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire n47_1 ; +wire n48_1 ; +wire n1_1 ; +wire n2_1 ; +wire n3_1 ; +wire n4_1 ; +wire n5_1 ; +wire n49_1 ; +wire n6_1 ; +wire n50_1 ; +wire n7_1 ; +wire n51_1 ; +wire n8_1 ; +wire n52_1 ; +wire n9_1 ; +wire n53_1 ; +wire n54_1 ; +wire n55_1 ; +wire n56_1 ; +wire n57_1 ; +wire n58_1 ; +wire n59_1 ; +wire n60_1 ; +wire n61_1 ; +wire n62_1 ; +wire n63_1 ; +wire n64_1 ; +wire n65_1 ; +wire n10_1 ; +wire n66_1 ; +wire n67_1 ; +wire n68_1 ; +wire n69_1 ; +wire n70_1 ; +wire n71_1 ; +wire n72_1 ; +wire n73_1 ; +wire n74_1 ; +wire n75_1 ; +wire n76_1 ; +wire n77_1 ; +wire n78_1 ; +wire n79_1 ; +wire n80_1 ; +wire n81_1 ; +wire n82_1 ; +wire n83_1 ; +wire n84_1 ; +wire n85_1 ; +wire n86_1 ; +wire n87_1 ; +wire n88_1 ; +wire n11_1 ; +wire n89_1 ; +wire n12_1 ; +wire n90_1 ; +wire n13_1 ; +wire n91_1 ; +wire n92_1 ; +wire n93_1 ; +wire n94_1 ; +wire n95_1 ; +wire n14_1 ; +wire n96_1 ; +wire n15_1 ; +wire n97_1 ; +wire n98_1 ; +wire n99_1 ; +wire n100_1 ; +wire n101_1 ; +wire n102_1 ; +wire n103_1 ; +wire n104_1 ; +wire n105_1 ; +wire n106_1 ; +wire n107_1 ; +wire n108_1 ; +wire n109_1 ; +wire n110_1 ; +wire n121_1 ; +wire n16_1 ; +wire n17_1 ; +wire n18_1 ; +wire n19_1 ; +wire n20_1 ; +wire n21_1 ; +wire n22_1 ; +wire n23_1 ; +wire n24_1 ; +wire n25_1 ; +wire n26_1 ; +wire n27_1 ; +wire n28_1 ; +wire n29_1 ; +wire n30_1 ; +wire n31_1 ; +wire n32_1 ; +wire n33_1 ; +wire n34_1 ; +wire n35_1 ; +wire n36_1 ; +wire n37_1 ; +wire n38_1 ; +wire n39_1 ; +wire n40_1 ; +wire n41_1 ; +wire n42_1 ; +wire n43_1 ; +wire n46_1 ; +wire GND ; +wire VCC ; + VLO GND_0 ( + .Z(GND) +); + VHI VCC_0 ( + .Z(VCC) +); + PUR PUR_INST ( + .PUR(VCC) +); + GSR GSR_INST ( + .GSR(VCC) +); +// @8:118 +(* CHAN="CH0" *) DCUA DCU0_inst ( + .CH0_HDINP(hdinp), + .CH1_HDINP(GND), + .CH0_HDINN(hdinn), + .CH1_HDINN(GND), + .D_TXBIT_CLKP_FROM_ND(GND), + .D_TXBIT_CLKN_FROM_ND(GND), + .D_SYNC_ND(GND), + .D_TXPLL_LOL_FROM_ND(GND), + .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(GND), + .CH0_FF_RXI_CLK(tx_pclk), + .CH1_FF_RXI_CLK(VCC), + .CH0_FF_TXI_CLK(txi_clk), + .CH1_FF_TXI_CLK(VCC), + .CH0_FF_EBRD_CLK(tx_pclk), + .CH1_FF_EBRD_CLK(VCC), + .CH0_FF_TX_D_0(txdata[0]), + .CH1_FF_TX_D_0(GND), + .CH0_FF_TX_D_1(txdata[1]), + .CH1_FF_TX_D_1(GND), + .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(GND), + .CH0_FF_TX_D_3(txdata[3]), + .CH1_FF_TX_D_3(GND), + .CH0_FF_TX_D_4(txdata[4]), + .CH1_FF_TX_D_4(GND), + .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(GND), + .CH0_FF_TX_D_6(txdata[6]), + .CH1_FF_TX_D_6(GND), + .CH0_FF_TX_D_7(txdata[7]), + .CH1_FF_TX_D_7(GND), + .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(GND), + .CH0_FF_TX_D_9(GND), + .CH1_FF_TX_D_9(GND), + .CH0_FF_TX_D_10(xmit[0]), + .CH1_FF_TX_D_10(GND), + .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(GND), + .CH0_FF_TX_D_12(GND), + .CH1_FF_TX_D_12(GND), + .CH0_FF_TX_D_13(GND), + .CH1_FF_TX_D_13(GND), + .CH0_FF_TX_D_14(GND), + .CH1_FF_TX_D_14(GND), + .CH0_FF_TX_D_15(GND), + .CH1_FF_TX_D_15(GND), + .CH0_FF_TX_D_16(GND), + .CH1_FF_TX_D_16(GND), + .CH0_FF_TX_D_17(GND), + .CH1_FF_TX_D_17(GND), + .CH0_FF_TX_D_18(GND), + .CH1_FF_TX_D_18(GND), + .CH0_FF_TX_D_19(GND), + .CH1_FF_TX_D_19(GND), + .CH0_FF_TX_D_20(GND), + .CH1_FF_TX_D_20(GND), + .CH0_FF_TX_D_21(GND), + .CH1_FF_TX_D_21(GND), + .CH0_FF_TX_D_22(GND), + .CH1_FF_TX_D_22(GND), + .CH0_FF_TX_D_23(GND), + .CH1_FF_TX_D_23(GND), + .CH0_FFC_EI_EN(GND), + .CH1_FFC_EI_EN(GND), + .CH0_FFC_PCIE_DET_EN(GND), + .CH1_FFC_PCIE_DET_EN(GND), + .CH0_FFC_PCIE_CT(GND), + .CH1_FFC_PCIE_CT(GND), + .CH0_FFC_SB_INV_RX(GND), + .CH1_FFC_SB_INV_RX(GND), + .CH0_FFC_ENABLE_CGALIGN(GND), + .CH1_FFC_ENABLE_CGALIGN(GND), + .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(GND), + .CH0_FFC_FB_LOOPBACK(GND), + .CH1_FFC_FB_LOOPBACK(GND), + .CH0_FFC_SB_PFIFO_LP(GND), + .CH1_FFC_SB_PFIFO_LP(GND), + .CH0_FFC_PFIFO_CLR(GND), + .CH1_FFC_PFIFO_CLR(GND), + .CH0_FFC_RATE_MODE_RX(GND), + .CH1_FFC_RATE_MODE_RX(GND), + .CH0_FFC_RATE_MODE_TX(GND), + .CH1_FFC_RATE_MODE_TX(GND), + .CH0_FFC_DIV11_MODE_RX(GND), + .CH1_FFC_DIV11_MODE_RX(GND), + .CH0_FFC_RX_GEAR_MODE(GND), + .CH1_FFC_RX_GEAR_MODE(GND), + .CH0_FFC_TX_GEAR_MODE(GND), + .CH1_FFC_TX_GEAR_MODE(GND), + .CH0_FFC_DIV11_MODE_TX(GND), + .CH1_FFC_DIV11_MODE_TX(GND), + .CH0_FFC_LDR_CORE2TX_EN(GND), + .CH1_FFC_LDR_CORE2TX_EN(GND), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), + .CH1_FFC_LANE_TX_RST(GND), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), + .CH1_FFC_LANE_RX_RST(GND), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), + .CH1_FFC_RRST(GND), + .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(GND), + .CH0_FFC_RXPWDNB(rx_pwrup_c), + .CH1_FFC_RXPWDNB(GND), + .CH0_LDR_CORE2TX(GND), + .CH1_LDR_CORE2TX(GND), + .D_SCIWDATA0(GND), + .D_SCIWDATA1(GND), + .D_SCIWDATA2(GND), + .D_SCIWDATA3(GND), + .D_SCIWDATA4(GND), + .D_SCIWDATA5(GND), + .D_SCIWDATA6(GND), + .D_SCIWDATA7(GND), + .D_SCIADDR0(GND), + .D_SCIADDR1(GND), + .D_SCIADDR2(GND), + .D_SCIADDR3(GND), + .D_SCIADDR4(GND), + .D_SCIADDR5(GND), + .D_SCIENAUX(GND), + .D_SCISELAUX(GND), + .CH0_SCIEN(GND), + .CH1_SCIEN(GND), + .CH0_SCISEL(GND), + .CH1_SCISEL(GND), + .D_SCIRD(GND), + .D_SCIWSTN(GND), + .D_CYAWSTN(GND), + .D_FFC_SYNC_TOGGLE(GND), + .D_FFC_DUAL_RST(rst_dual_c), + .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), + .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(GND), + .CH1_FFC_CDR_EN_BITSLIP(GND), + .D_SCAN_ENABLE(GND), + .D_SCAN_IN_0(GND), + .D_SCAN_IN_1(GND), + .D_SCAN_IN_2(GND), + .D_SCAN_IN_3(GND), + .D_SCAN_IN_4(GND), + .D_SCAN_IN_5(GND), + .D_SCAN_IN_6(GND), + .D_SCAN_IN_7(GND), + .D_SCAN_MODE(GND), + .D_SCAN_RESET(GND), + .D_CIN0(GND), + .D_CIN1(GND), + .D_CIN2(GND), + .D_CIN3(GND), + .D_CIN4(GND), + .D_CIN5(GND), + .D_CIN6(GND), + .D_CIN7(GND), + .D_CIN8(GND), + .D_CIN9(GND), + .D_CIN10(GND), + .D_CIN11(GND), + .CH0_HDOUTP(hdoutp), + .CH1_HDOUTP(n47_1), + .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n48_1), + .D_TXBIT_CLKP_TO_ND(n1_1), + .D_TXBIT_CLKN_TO_ND(n2_1), + .D_SYNC_PULSE2ND(n3_1), + .D_TXPLL_LOL_TO_ND(n4_1), + .CH0_FF_RX_F_CLK(n5_1), + .CH1_FF_RX_F_CLK(n49_1), + .CH0_FF_RX_H_CLK(n6_1), + .CH1_FF_RX_H_CLK(n50_1), + .CH0_FF_TX_F_CLK(n7_1), + .CH1_FF_TX_F_CLK(n51_1), + .CH0_FF_TX_H_CLK(n8_1), + .CH1_FF_TX_H_CLK(n52_1), + .CH0_FF_RX_PCLK(n9_1), + .CH1_FF_RX_PCLK(n53_1), + .CH0_FF_TX_PCLK(tx_pclk), + .CH1_FF_TX_PCLK(n54_1), + .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n55_1), + .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n56_1), + .CH0_FF_RX_D_2(rxdata[2]), + .CH1_FF_RX_D_2(n57_1), + .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n58_1), + .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n59_1), + .CH0_FF_RX_D_5(rxdata[5]), + .CH1_FF_RX_D_5(n60_1), + .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n61_1), + .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n62_1), + .CH0_FF_RX_D_8(rx_k[0]), + .CH1_FF_RX_D_8(n63_1), + .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n64_1), + .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n65_1), + .CH0_FF_RX_D_11(n10_1), + .CH1_FF_RX_D_11(n66_1), + .CH0_FF_RX_D_12(n67_1), + .CH1_FF_RX_D_12(n68_1), + .CH0_FF_RX_D_13(n69_1), + .CH1_FF_RX_D_13(n70_1), + .CH0_FF_RX_D_14(n71_1), + .CH1_FF_RX_D_14(n72_1), + .CH0_FF_RX_D_15(n73_1), + .CH1_FF_RX_D_15(n74_1), + .CH0_FF_RX_D_16(n75_1), + .CH1_FF_RX_D_16(n76_1), + .CH0_FF_RX_D_17(n77_1), + .CH1_FF_RX_D_17(n78_1), + .CH0_FF_RX_D_18(n79_1), + .CH1_FF_RX_D_18(n80_1), + .CH0_FF_RX_D_19(n81_1), + .CH1_FF_RX_D_19(n82_1), + .CH0_FF_RX_D_20(n83_1), + .CH1_FF_RX_D_20(n84_1), + .CH0_FF_RX_D_21(n85_1), + .CH1_FF_RX_D_21(n86_1), + .CH0_FF_RX_D_22(n87_1), + .CH1_FF_RX_D_22(n88_1), + .CH0_FF_RX_D_23(n11_1), + .CH1_FF_RX_D_23(n89_1), + .CH0_FFS_PCIE_DONE(n12_1), + .CH1_FFS_PCIE_DONE(n90_1), + .CH0_FFS_PCIE_CON(n13_1), + .CH1_FFS_PCIE_CON(n91_1), + .CH0_FFS_RLOS(rx_los_low_s), + .CH1_FFS_RLOS(n92_1), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n93_1), + .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n94_1), + .CH0_FFS_CC_OVERRUN(ctc_orun_s), + .CH1_FFS_CC_OVERRUN(n95_1), + .CH0_FFS_RXFBFIFO_ERROR(n14_1), + .CH1_FFS_RXFBFIFO_ERROR(n96_1), + .CH0_FFS_TXFBFIFO_ERROR(n15_1), + .CH1_FFS_TXFBFIFO_ERROR(n97_1), + .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n98_1), + .CH0_FFS_SKP_ADDED(ctc_ins_s), + .CH1_FFS_SKP_ADDED(n99_1), + .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n100_1), + .CH0_LDR_RX2CORE(n101_1), + .CH1_LDR_RX2CORE(n102_1), + .D_SCIRDATA0(n103_1), + .D_SCIRDATA1(n104_1), + .D_SCIRDATA2(n105_1), + .D_SCIRDATA3(n106_1), + .D_SCIRDATA4(n107_1), + .D_SCIRDATA5(n108_1), + .D_SCIRDATA6(n109_1), + .D_SCIRDATA7(n110_1), + .D_SCIINT(n121_1), + .D_SCAN_OUT_0(n16_1), + .D_SCAN_OUT_1(n17_1), + .D_SCAN_OUT_2(n18_1), + .D_SCAN_OUT_3(n19_1), + .D_SCAN_OUT_4(n20_1), + .D_SCAN_OUT_5(n21_1), + .D_SCAN_OUT_6(n22_1), + .D_SCAN_OUT_7(n23_1), + .D_COUT0(n24_1), + .D_COUT1(n25_1), + .D_COUT2(n26_1), + .D_COUT3(n27_1), + .D_COUT4(n28_1), + .D_COUT5(n29_1), + .D_COUT6(n30_1), + .D_COUT7(n31_1), + .D_COUT8(n32_1), + .D_COUT9(n33_1), + .D_COUT10(n34_1), + .D_COUT11(n35_1), + .D_COUT12(n36_1), + .D_COUT13(n37_1), + .D_COUT14(n38_1), + .D_COUT15(n39_1), + .D_COUT16(n40_1), + .D_COUT17(n41_1), + .D_COUT18(n42_1), + .D_COUT19(n43_1), + .D_REFCLKI(pll_refclki), + .D_FFS_PLOL(n46_1) +); +defparam DCU0_inst.D_MACROPDB = "0b1"; +defparam DCU0_inst.D_IB_PWDNB = "0b1"; +defparam DCU0_inst.D_XGE_MODE = "0b0"; +defparam DCU0_inst.D_LOW_MARK = "0d4"; +defparam DCU0_inst.D_HIGH_MARK = "0d12"; +defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; +defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; +defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; +defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; +defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; +defparam DCU0_inst.CH0_UC_MODE = "0b0"; +defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; +defparam DCU0_inst.CH0_RIO_MODE = "0b0"; +defparam DCU0_inst.CH0_WA_MODE = "0b0"; +defparam DCU0_inst.CH0_INVERT_RX = "0b0"; +defparam DCU0_inst.CH0_INVERT_TX = "0b0"; +defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; +defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0"; +defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; +defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; +defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; +defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; +defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; +defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_CTC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; +defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1"; +defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; +defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; +defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC"; +defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050"; +defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; +defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; +defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; +defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010"; +defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; +defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00"; +defparam DCU0_inst.CH0_REQ_EN = "0b1"; +defparam DCU0_inst.CH0_RTERM_RX = "0d22"; +defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; +defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; +defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; +defparam DCU0_inst.CH0_TPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0"; +defparam DCU0_inst.CH0_RTERM_TX = "0d19"; +defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; +defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101"; +defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; +defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; +defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; +defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_RPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0"; +defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; +defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010"; +defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; +defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; +defparam DCU0_inst.CH0_RX_LOS_EN = "0b1"; +defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0"; +defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; +defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; +defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; +defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; +defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; +defparam DCU0_inst.CH0_RXIN_CM = "0b11"; +defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; +defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; +defparam DCU0_inst.D_TX_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100"; +defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; +defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; +defparam DCU0_inst.CH0_PROTOCOL = "GBE"; +defparam DCU0_inst.D_ISETLOS = "0d0"; +defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; +defparam DCU0_inst.D_SETICONST_AUX = "0b00"; +defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; +defparam DCU0_inst.D_SETICONST_CH = "0b00"; +defparam DCU0_inst.D_REQ_ISET = "0b000"; +defparam DCU0_inst.D_PD_ISET = "0b00"; +defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; +defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; +defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; +defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; +defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; +defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; +defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; +defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; +defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; +defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; +defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; +defparam DCU0_inst.CH0_DCOSTEP = "0b00"; +defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; +defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; +defparam DCU0_inst.CH0_DCOITUNE = "0b00"; +defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; +defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; +defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; +defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; +defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; +defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; +defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; +defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; +defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; +defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; +defparam DCU0_inst.D_SETPLLRC = "0d1"; +defparam DCU0_inst.D_REFCK_MODE = "0b001"; +defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; +defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; +defparam DCU0_inst.D_RG_EN = "0b0"; +defparam DCU0_inst.D_RG_SET = "0b00"; +defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; +defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; +defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; +defparam DCU0_inst.D_CMUSETZGM = "0b000"; +defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; +defparam DCU0_inst.D_CMUSETP1GM = "0b000"; +defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; +defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; +defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; +defparam DCU0_inst.D_CMUSETICP4P = "0b01"; +defparam DCU0_inst.D_CMUSETBIASI = "0b00"; +// @8:357 + PCSDrsl_core_Z1_layer1 rsl_inst ( + .serdes_rst_dual_c(serdes_rst_dual_c), + .rx_serdes_rst_c(rx_serdes_rst_c), + .tx_serdes_rst_c(tx_serdes_rst_c), + .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c), + .rx_pcs_rst_c(rx_pcs_rst_c), + .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c), + .tx_pcs_rst_c(tx_pcs_rst_c), + .rsl_disable(rsl_disable), + .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .pll_lol(pll_lol), + .pll_refclki(pll_refclki), + .rx_cdr_lol_s(rx_cdr_lol_s), + .rx_los_low_s(rx_los_low_s), + .rsl_rst(rsl_rst), + .rxrefclk(rxrefclk), + .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c), + .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c) +); +endmodule /* PCSD */ + diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_cck.rpt.db b/gbe/cores/sgmii/PCSD/syn_results/PCSD_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_scck.rpt.db b/gbe/cores/sgmii/PCSD/syn_results/PCSD_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify.lpf new file mode 100644 index 0000000..a0470d8 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify.lpf @@ -0,0 +1,24 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints +#FREQUENCY PORT "pll_refclki" 100.0 MHz; +#FREQUENCY PORT "rxrefclk" 100.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp2.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp4.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp8.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML b/gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML new file mode 100644 index 0000000..c760b6f --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs -top PCSD -hdllog /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/ -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib -v2001 -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -lib work /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/_cmd._cml b/gbe/cores/sgmii/PCSD/syn_results/_cmd._cml new file mode 100644 index 0000000..a2a52c2 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top PCSD -osyn /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/backup/PCSD.srr b/gbe/cores/sgmii/PCSD/syn_results/backup/PCSD.srr new file mode 100644 index 0000000..20082f7 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/backup/PCSD.srr @@ -0,0 +1,1157 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Mon Apr 29 14:56:30 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":30:7:30:10|Top entity is set to PCSD. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Mon Apr 29 14:56:30 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Mon Apr 29 14:56:30 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":30:7:30:10|Top entity is set to PCSD. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":30:7:30:10|Synthesizing work.pcsd.v1. +Post processing for work.pcsd.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Mon Apr 29 14:56:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1051:7:1051:18|Synthesizing module PCSDsll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = PCSDsll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = PCSDrsl_core_Z2_layer1 +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB) + + +Process completed successfully. +# Mon Apr 29 14:56:31 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon Apr 29 14:56:31 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon Apr 29 14:56:31 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Mon Apr 29 14:56:32 2019 + +###########################################################] +Pre-mapping Report + +# Mon Apr 29 14:56:33 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist PCSD + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 76 + +0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59 + +0 - PCSD|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +================================================================================================================ + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Found inferred clock PCSD|pll_refclki which controls 76 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Found inferred clock PCSD|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Mon Apr 29 14:56:33 2019 + +###########################################################] +Map & Optimize Report + +# Mon Apr 29 14:56:33 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1350:0:1350:5|Found counter in view:work.PCSDsll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1304:0:1304:5|Found counter in view:work.PCSDsll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1759:0:1759:5|Found counter in view:work.PCSDsll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.PCSD(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.PCSD(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.PCSD(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.36ns 118 / 186 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.PCSD(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.PCSD(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.PCSD(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 186 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=================================== Non-Gated/Non-Generated Clocks ==================================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 74 rsl_inst.genblk1\.pll_lol_p1 +@K:CKID0002 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +======================================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 146MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 148MB peak: 150MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":150:4:150:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock PCSD|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Mon Apr 29 14:56:37 2019 +# + + +Top view: PCSD +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------ +PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +PCSD|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup +==================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------ +System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths - +PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths - +PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +PCSD|pll_refclki PCSD|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths - +PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +PCSD|tx_pclk_inferred_clock PCSD|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +PCSD|tx_pclk_inferred_clock PCSD|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PCSD|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by PCSD|pll_refclki [rising] on pin CK + The end point is clocked by PCSD|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: PCSD|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[7] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[7] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[8] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[8] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[9] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[11] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170 +=============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by PCSD|rxrefclk [rising] on pin CK + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: PCSD|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 PCSD|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 PCSD|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] PCSD|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] PCSD|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] PCSD|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] PCSD|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] PCSD|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] PCSD|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] PCSD|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] PCSD|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] PCSD|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] PCSD|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +=================================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by PCSD|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by PCSD|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +=================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 9.946 + + Number of logic level(s): 0 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.rlol_p1 / D + The start point is clocked by System [rising] + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 2 +rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 - +=================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 186 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 99 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 60 +FD1S3BX: 10 +FD1S3DX: 96 +GSR: 1 +INV: 3 +ORCALUT4: 116 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 34MB peak: 150MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Mon Apr 29 14:56:37 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/dm/layer0.xdm b/gbe/cores/sgmii/PCSD/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..b88dcd9 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/dm/layer0.xdm @@ -0,0 +1,513 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +SS1SS1SS1S +SF<1kCsOR"b=/lEFCF/#VD0/NH00O8C/HFNlMd8/3_4jG/nc#b$MLCN#/LDH/8PE/bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S> +SF<1kCsOR"b=/lEFC8/NsMHN/0oH/L0s6/#O0bClDCN0/Fbs[0CO/l#oHuH/B/17u7B138PE"=RN"RU"DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/ +"/ +/S<1sFkO>C# +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s 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+SF<1kCsOR"b=/lEFCF/#VD0/NH00O8C/HFNlMd8/3_4jG/nc#b$MLCN#/LDH/FPDoO/#C_lHbCHb#P3#EN"R=""6R"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/ +< +S/k1Fs#OC> + + + +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s u7B1s_#DOCFs__Z4DCN$sP43CDsHFRo"DP="CDsHF>o" +S +S +SRS +SS +S"/ +S +SSuS"/ +S +S +SRSuSS +SS +S"/ +"/ +SuSS +S"/ +"/ +SuS +SRS +SSuSS +SSuSS +S"/ + +SR"/ + +SR"/ +S +SS +SS +SS +S +/S<7>CV +]sC + +@ diff --git a/gbe/cores/sgmii/PCSD/syn_results/run_options.txt b/gbe/cores/sgmii/PCSD/syn_results/run_options.txt new file mode 100644 index 0000000..9fc0ce0 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/run_options.txt @@ -0,0 +1,76 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/run_options.txt +#-- Written on Tue Apr 30 12:09:44 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "PCSD" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./PCSD.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srf" +impl -active "syn_results" diff --git a/gbe/cores/sgmii/PCSD/syn_results/scemi_cfg.txt b/gbe/cores/sgmii/PCSD/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/sgmii/PCSD/syn_results/scratchproject.prs b/gbe/cores/sgmii/PCSD/syn_results/scratchproject.prs new file mode 100644 index 0000000..1a2e57f --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/scratchproject.prs @@ -0,0 +1,74 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "PCSD" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srf" +impl -active "syn_results" diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr new file mode 100644 index 0000000..cd2e67c --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr @@ -0,0 +1,201 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) + + +Process completed successfully. +# Tue Apr 30 12:09:44 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1. +Post processing for work.pcsd.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = PCSDrsl_core_Z1_layer1 +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB) + + +Process completed successfully. +# Tue Apr 30 12:09:45 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:46 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:46 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..64aab840978977f4a582ac1d60aca86e02f0c33d GIT binary patch literal 20480 zcmeHP&2JmW6(=Rqlq|_i(%5dBx*aQ(W5)`~{osd~2B_pXjwBj(EC)Uq!D7iBQClr{ z7qdf3G6WP93N$eK7xdQl-b;~N3-sJ;kv||n?*)n?K-x>+%q&gHN+eO4u@Q6$d!Mx; zx$pO8=FPnKd(RsmHC&3(WA~VMx``g+zL9lXgkEU{bJjtMM|3Gs8yu66M8nq#gGKQ zz%5#g+8x&|-oLf+KEGH|ut~k3?Y0WN`MP0N>xRLFS>AtuJ3-I&+i1rn7!fb{0Q_I0E&nDPG%`OEUX{;o63h1`Wl#g#98^+t~ViXWW7-r0%#UHn+8~7t= z7GCFQ(y|Q?R%eDc7@Fq{zZ;&x>K}fO>v>1E)pemKh^1#%2L(w)m6`m**VI7K1QZa5 zpuh}Q24(G44rN{PsOU8g1%#4>t z7!CH7O`x^&O2AZ?I2aJ4U_xTqVF+hHMTd*^X(jWl%C`p{#OOS8RHIp&QZqDsf6%M2 zKRny)=x(HVXclrDjO25lUgdiT6GzT{;CgL;kDaW>Ic?uK$Mu|+>`|*_u^!5GvvS0v zay`RVG_I~Uvs~9X*}9rSSF>)`p3~Lo+MX2Jp z_bbNP1HnRX%bBn1Ca41!t#nu&{yZ3Ar_j^Hb2IxB@Z7iVu;*6w!E;$OS%i3#x-DFE zT)PwaPSGf6C2O~07Nb2sY}yen0*oR&uNYDILiSuuH^2m3=-U1UhA#jkP`3kdCyoNI z%c3wAS%wiuo!N)D|3yC?BKXYPaGAWsxcN&E(&rEInG3&}`*#xmC-MKcOuQuV|2L*w zlKB6mv|SSaADe+p;{THpze)Um>;zg*;{Ox5gCzcE49K@57n1n@WR8jj{w&Xw#Q$H* zwk7euUQOcv@rmFh{y%m0Vfn8t{(n97k5vBAghuCr@x|32xm8UfVx zyAjaz1h?IY0xjRhe$(653#{b83XKA~Yj0x|bs+~vx1ixd6dnMz&nge%4?|f7CLIhp zCuqzVd{Z<++&{R%;aGCv)Jl-Rt+VSX;0PjLf2`L_pU45Va-C;T-(?w8d9@Wa;Bd53 zU5Ei2=qY18R^CzpqFkyn5JC(nWKpGb*A^3d9k?2xPxOx!7Bie|P%1)g3zt7=3l6&?y%3?PF zVO9sn<`Foo{8AaDYnM4B*%hT_v15QZT2UIuWaCXG7XQy?K2PPf3%BMzo^8*x&Rf%u zr)ci!xj$t848KTTi3Ji1Bo_ECS)lJ!xc6nn*bUvRNJ{wWkcVM>4G1`|ulgZ0OsH zTDttU=-zRM4}y|9Jdy}>%4%SWN>0cGo(85DL;!O~B}`KdOi>70g51clquJ%783(ym zOWA0)4F>ZdD|^xk4yk0;%i3|1R={M@G3Mp33XwXxngQj9BfZ4K>0_2BAccx#gflt^*ZKGD;N7RN8uv9<~1GJ5C$Y-(3 zZ?`aH+``b?6YnE7tP=!P-&P1!+?e$6d$83*9XFJE4n8oP_5JO4l%O4%^(Uj{t+tQ# g7lC$B1=>+RcRX64S6|@RHf}PsFPTh^WRc1L0}i|FPXGV_ literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap new file mode 100644 index 0000000..0168f12 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap @@ -0,0 +1 @@ +./synlog/PCSD_compiler.srr,PCSD_compiler.srr,Compile Log diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr new file mode 100644 index 0000000..da6761e --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr @@ -0,0 +1,537 @@ +# Tue Apr 30 12:09:48 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:00s 5.36ns 63 / 92 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=================================== Non-Gated/Non-Generated Clocks ==================================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +------------------------------------------------------------------------------------------------------- +@K:CKID0001 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18] +@K:CKID0002 pll_refclki port 33 rsl_inst.genblk1\.pll_lol_p1 +======================================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Apr 30 12:09:50 2019 +# + + +Top view: PCSD +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------- +PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup +========================================================================================================================= + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths - +PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths - +PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths - +PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +=========================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PCSD|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by PCSD|pll_refclki [rising] on pin CK + The end point is clocked by PCSD|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: PCSD|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[16] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[17] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +=============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by PCSD|rxrefclk [rising] on pin CK + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946 +DCU0_inst System DCUA CH0_FF_TX_PCLK tx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_EBRD_CLK tx_pclk 10.000 10.000 +DCU0_inst System DCUA CH0_FF_RXI_CLK tx_pclk 10.000 10.000 +================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 9.946 + + Number of logic level(s): 0 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.rlol_p1 / D + The start point is clocked by System [rising] + The end point is clocked by PCSD|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 2 +rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 - +=================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 92 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 37 +DCUA: 1 +FD1P3BX: 4 +FD1P3DX: 42 +FD1S3BX: 10 +FD1S3DX: 36 +GSR: 1 +ORCALUT4: 63 +PFUMX: 2 +PUR: 1 +VHI: 2 +VLO: 2 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Tue Apr 30 12:09:51 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..b2fe294f4efe46b9adcc1481761fbc4514e1da1b GIT binary patch literal 8192 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b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr @@ -0,0 +1,12 @@ +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Apr 30 12:09:47 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr new file mode 100644 index 0000000..fe3b5ab --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr @@ -0,0 +1,70 @@ +# Tue Apr 30 12:09:47 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist PCSD + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +----------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59 + +0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 33 +===================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Apr 30 12:09:48 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr.db 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b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap new file mode 100644 index 0000000..e21637c --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap @@ -0,0 +1 @@ +./synwork/PCSD_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt new file mode 100644 index 0000000..64eb40e --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt @@ -0,0 +1,11 @@ +@N|Running in 64-bit mode +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. +@N|Running in 64-bit mode + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml new file mode 100644 index 0000000..5ab9b80 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml @@ -0,0 +1,41 @@ + + + + + + /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr + Synopsys HDL Compiler + + + Completed + + + + 10 + /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt + + + 50 + /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt + + + 0 + /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_errors.txt + + + - + + + 00h:00m:02s + + + - + + + 1556618986 + + + \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt new file mode 100644 index 0000000..664f602 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt @@ -0,0 +1,51 @@ +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml new file mode 100644 index 0000000..194415f --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_resourceusage.rpt +Resource Usage + + +92 + + +0 + + +0 + + +0 + + +63 + + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt new file mode 100644 index 0000000..b4c4fcb --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt @@ -0,0 +1,11 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..2e79d15 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +2 / 0 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..f5531ea --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +11 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt + + + +3 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt + + + +0h:00m:02s + + +0h:00m:02s + + +148MB + + +1556618991 + + + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..04932ce --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml @@ -0,0 +1,35 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +PCSD|pll_refclki +100.0 MHz +168.9 MHz +4.079 + + +PCSD|rxrefclk +100.0 MHz +170.5 MHz +4.136 + + +System +100.0 MHz +18518.5 MHz +9.946 + + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt new file mode 100644 index 0000000..5df4948 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt @@ -0,0 +1,3 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt new file mode 100644 index 0000000..eed8756 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt @@ -0,0 +1,2 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml new file mode 100644 index 0000000..3302c41 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +2 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt + + + +2 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +143MB + + +1556618988 + + + diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt new file mode 100644 index 0000000..22d5ea5 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt @@ -0,0 +1,2 @@ +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db new file mode 100644 index 0000000000000000000000000000000000000000..3d974e4e3831441084f7ad4e1dd75d9e6311c32e GIT binary patch literal 20480 zcmeI3O>Y}T7{_TOUB3l4lnYU+XOxZS<$3<|-(NO|nH@j=cE?wo zbt4(NirqG@8m4L7Wy~;)CR~@`8kGg8B-f~zqsl3tO{4PH3jzTPWT=}6ddg<>=_a1F;?QOHYtuJ=A zSvl=2-;CPNxTo0AmEOK9KV>0T()T9qp&JbNq&X12iYLuyQG3$xqA=uQN~6-YN1tC@EL1AyaaDWtg2+2)d65`$8T*kq*cqXJXSa7Yn75d0f^u_d5Y#4*PzYlb?M{uHg=M`q&%HG1&ori+ zxtHhgUl1)L0VIF~kN^@u0!RP}AOR$R1dsp{_!k13Z(F34C&jOA6)87pbz!LMGj5+3;luCbHC=k&lSmUK;C+kSf(f3?=u3TTh(~#~C zOdf>$_nItlmAB7h29FJc&4XyjI}O;7C_#2J%hsKzCTEGs`ro9#8}Ne#2_OL^fCP{L y5 +
    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:47 2019
+
+###########################################################]
+
+
     +
    +
+# Tue Apr 30 12:09:47 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+Linked File: PCSD_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist PCSD
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start                Requested     Requested     Clock        Clock                   Clock
+Level     Clock                Frequency     Period        Type         Group                   Load 
+-----------------------------------------------------------------------------------------------------
+0 -       System               100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                     
+0 -       PCSD|rxrefclk        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                     
+0 -       PCSD|pll_refclki     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     33   
+=====================================================================================================
+
+@W:MT529 : PCSD_softlogic.v(412) | Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : PCSD_softlogic.v(567) | Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Apr 30 12:09:48 2019
+
+###########################################################]
+
+
     +
    +
+# Tue Apr 30 12:09:48 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N:MO231 : PCSD_softlogic.v(412) | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:MO231 : PCSD_softlogic.v(778) | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:MO231 : PCSD_softlogic.v(680) | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:00s		     5.36ns		  63 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+ClockId0001        rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+ClockId0002        pll_refclki         port                   33         rsl_inst.genblk1\.pll_lol_p1   
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+@W:MT246 : PCSD.vhd(118) | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W:MT420 :  | Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" 
+@W:MT420 :  | Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Apr 30 12:09:50 2019
+#
+
+
+Top view:               PCSD
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                     Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock       Frequency     Frequency       Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------
+PCSD|pll_refclki     100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+PCSD|rxrefclk        100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+System               100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+=========================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------------------------
+Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------------------------
+System            System            |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System            PCSD|rxrefclk     |  10.000      9.946   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  System            |  10.000      8.385   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  PCSD|pll_refclki  |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     System            |  10.000      8.283   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     PCSD|rxrefclk     |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+===========================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PCSD|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                  Arrival          
+Instance                           Reference            Type        Pin     Net              Time        Slack
+                                   Clock                                                                      
+--------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+==============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                    Required          
+Instance                           Reference            Type        Pin     Net                Time         Slack
+                                   Clock                                                                         
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
+    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: PCSD|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                 Arrival          
+Instance                             Reference         Type        Pin     Net                Time        Slack
+                                     Clock                                                                     
+---------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[16]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[17]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+===============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                   Required          
+Instance                             Reference         Type        Pin     Net                  Time         Slack
+                                     Clock                                                                        
+------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+==================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FF_TX_PCLK     tx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                              Starting                                                       Required           
+Instance                      Reference     Type        Pin                 Net              Time         Slack 
+                              Clock                                                                             
+----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D                   rx_cdr_lol_s     9.946        9.946 
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D                   rx_los_low_s     9.946        9.946 
+DCU0_inst                     System        DCUA        CH0_FF_EBRD_CLK     tx_pclk          10.000       10.000
+DCU0_inst                     System        DCUA        CH0_FF_RXI_CLK      tx_pclk          10.000       10.000
+================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 92 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          37
+DCUA:           1
+FD1P3BX:        4
+FD1P3DX:        42
+FD1S3BX:        10
+FD1S3DX:        36
+GSR:            1
+ORCALUT4:       63
+PFUMX:          2
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Tue Apr 30 12:09:51 2019
+
+###########################################################]
+
+
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    + + + + + + + + + + +
    Project Settings
    Project Name PCSD Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module PCSD
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete10500-00m:02s-4/30/19
    12:09 PM
    (premap)Complete2200m:00s0m:00s143MB4/30/19
    12:09 PM
    (fpga_mapper)Complete11300m:02s0m:02s148MB4/30/19
    12:09 PM
    Multi-srs GeneratorComplete4/30/19
    12:09 PM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 92I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 63

    + + + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    PCSD|pll_refclki100.0 MHz168.9 MHz4.079
    PCSD|rxrefclk100.0 MHz170.5 MHz4.136
    System100.0 MHz18518.5 MHz9.946
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 2 / 0

    +
    +
    + \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer new file mode 100644 index 0000000000000000000000000000000000000000..1106516a728bba57445e931c86cd822e9e0a3dda GIT binary patch literal 457 zcmV;)0XF_0iwFP!0000015#C0RVXORFG)=2L*O z9v+2<{FA`hI0jmdB4H+Qmw|4bJ)6uuF#qJ=DF=uy;av6S>5M z4zY8HP9@#@r67~dOd3g|ArFk4Wzfi!$wS_|!_~XS5<*$>b3`ZR8C&q=!h|75HyIJ6 z2Qh;(W*1?h;7x_p#98L6uU}S`3gJNL`+EOC_fxf3m~LG{m?X`_7H?b!MRufJ zBA+qHwpT5lnrl@-Uou&72C)MszLY|*?TF>+d3?rku{@1!b*--d?G%)qf4Kwup&A>- z=Ra=`&F@Md+VV$Ps%4qco3K{RYs5=7)3a3^9;z?ZUjP6A|NjF3L@?kstpWf5oafvx literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep new file mode 100644 index 0000000..48777ad --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep @@ -0,0 +1,35 @@ +#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 +#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile|-top|work.PCSDrsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile":1556618984 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1556618983 +0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl +1 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" verilog +#Dependency Lists(Uses List) +0 1 +1 -1 +#Dependency Lists(Users Of) +0 -1 +1 0 +#Design Unit to File Association +module work PCSDrsl_core 1 +module work pcsd 0 +arch work pcsd v1 0 diff --git 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+#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 +0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work pcsd v1 0 +module work pcsd 0 + +# Unbound Instances to File Association +inst work pcsd pcsdrsl_core 0 +inst work pcsd dcua 0 + + +# Configuration files used diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig new file mode 100644 index 0000000..41b0e30 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig @@ -0,0 +1,28 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 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zrdU&b3q}b9OS+OIIonM>{RX>830~e8c$K&3j6v9aPkCe>A+qO%)2ZksI24W!OwX7B zEmJi*sg6%%k-?_z;98maK<4EZ3EyGQKRH-kgYPwD?#6rXsj+KL{C{>AKDD)N-fjWz z0nEk)Ft36W2vMIC1E%%G)yL^~rq`czotpxA4ekU&+)6`Y4w)c~Eb2sx|Bundg80^1nc$;P~*%$sP&mzW`bz0>uCT literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg new file mode 100644 index 0000000..52e3197 --- /dev/null +++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg @@ -0,0 +1,96 @@ +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = PCSDrsl_core_Z1_layer1 +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. 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zm-ZA_>zLComh}U@yBNjsywLITsV_w0BdE@_NE_J=@#`UqV`DqUWWdJ1f}jVg3#4W7 zFz(390CXS^h+{qeJs}eQ48#C_*lu6R#QphKJaB0IC}#+GFCqc03f%$-o;WqFLBJam z3Ft@>2Yoye_9Vz|od_(;dq6ETQ(Pek=(f0i5YUcsk05Ld@%pqumMcOst_1El5Xl@7 zQf2BYli$HsTM*TaVFB=mJb65OvBiF#Jnp@` zxqhB}GW76PhabUf^kdS4dvv97_h8bzd$EOndvZ_J#bvC>$l|El`w|Ho_x2dYY*)!?JJcJ=*lyhL9TgU_O_3Id-HRE zSxvc^cWx%KgtC&yRoz-hwn6IT+b>Z+9RB&&%58u!S4CCzsMlQbyXvz0L0wDK54CrO zvu}d4MpOIRk5TUyj;Jr`{Pc~#X|OG?|B@abXGu4&4sM0Pft0cJsZv$n%pnNjrc9669KJku-n}S8P#Jo!#2^Q57F>zV2s74qj89Xcp!i9r! sAj>!;2Lgrzav=6N90!7igK^+LH#ii>pd5(OS~(1*C*>fN*6|Sk1Gjscuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 17, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 0, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA=> "REFCLK", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 1, CLKOS_DIV=> 18, CLKOP_DIV=> 1, CLKFB_DIV=> 4, + CLKI_DIV=> 15, FEEDBK_PATH=> "INT_OS") + port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>CLKFB_t); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33_ngd.asd b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/.recordref b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_CMD_.CML b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_CMD_.CML new file mode 100644 index 0000000..3410943 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs -top pll_in125_out125_out33 -hdllog /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_cmd._cml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_cmd._cml new file mode 100644 index 0000000..63c1e88 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top pll_in125_out125_out33 -osyn /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs \ No newline at end of file diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/backup/pll_in125_out125_out33.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/backup/pll_in125_out125_out33.srr new file mode 100644 index 0000000..febff8d --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/backup/pll_in125_out125_out33.srr @@ -0,0 +1,403 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Thu May 9 10:42:24 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_in125_out125_out33.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":45:4:45:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu May 9 10:42:24 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu May 9 10:42:24 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu May 9 10:42:24 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu May 9 10:42:26 2019 + +###########################################################] +Pre-mapping Report + +# Thu May 9 10:42:26 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in125_out125_out33 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Thu May 9 10:42:26 2019 + +###########################################################] +Map & Optimize Report + +# Thu May 9 10:42:26 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":51:4:51:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Thu May 9 10:42:29 2019 +# + + +Top view: pll_in125_out125_out33 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 +============================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 +=============================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKOP + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - +CLKOP Net - - - - 2 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +EHXPLLL: 1 +GSR: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Thu May 9 10:42:29 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/dm/layer0.xdm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..d3eb144 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/dm/layer0.xdm @@ -0,0 +1,164 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +SS1SS1SS1S +SF<1kCsOR"b=/lEFCF/#VD0/NH00O8C/HFNlMd8/3_4jG/nc#b$MLCN#/LDH/8PE/bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S> 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+SSSS +SqSS +SSR"/ +SSSS +SqSS"/ +SSSS +SSRS +SSRS +SqS +SqS +S)S7<7/]ps10kkO0s +C>@ + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.areasrr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.areasrr new file mode 100644 index 0000000..5d28e26 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.areasrr @@ -0,0 +1,15 @@ +---------------------------------------------------------------------- +Report for cell pll_in125_out125_out33.structure + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + EHXPLLL 1 100.0 + GSR 1 100.0 + PUR 1 100.0 + VHI 1 100.0 + VLO 1 100.0 + + TOTAL 5 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.fse b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.fse new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.htm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.htm new file mode 100644 index 0000000..43c5f13 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.htm @@ -0,0 +1,9 @@ + + + syntmp/pll_in125_out125_out33_srr.htm log file + + + + + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj new file mode 100644 index 0000000..133a2cb --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj @@ -0,0 +1,46 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj +#-- Written on Fri May 10 15:07:25 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" +add_file -constraint {"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc"} + +#-- top module name +set_option -top_module pll_in125_out125_out33 + +#-- set result format/file last +project -result_file "pll_in125_out125_out33.edn" + +#-- error message log file +project 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a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf new file mode 100644 index 0000000..2ad892a --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf @@ -0,0 +1,404 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 15:07:25 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33. +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_in125_out125_out33.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:25 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:26 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:26 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:27 2019 + +###########################################################] +# Fri May 10 15:07:27 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in125_out125_out33 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 15:07:28 2019 + +###########################################################] +# Fri May 10 15:07:28 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 15:07:30 2019 +# + + +Top view: pll_in125_out125_out33 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 +=================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 +================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKINTFB + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - +CLKFB_t Net - - - - 1 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +==================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +EHXPLLL: 1 +GSR: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33. +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_in125_out125_out33.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:25 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:26 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:26 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:27 2019 + +###########################################################] +# Fri May 10 15:07:27 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in125_out125_out33 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 15:07:28 2019 + +###########################################################] +# Fri May 10 15:07:28 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 15:07:30 2019 +# + + +Top view: pll_in125_out125_out33 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 +=================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 +================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKINTFB + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - +CLKFB_t Net - - - - 1 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +==================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + 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a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vhm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vhm new file mode 100644 index 0000000..57f03c8 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vhm @@ -0,0 +1,108 @@ +-- +-- Written by Synplicity +-- Product Version "M-2017.03L-SP1-1" +-- Program "Synplify Pro", Mapper "maplat, Build 1796R" +-- Fri May 10 15:07:29 2019 +-- + +-- +-- Written by Synplify Pro version Build 1796R +-- Fri May 10 15:07:29 2019 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_in125_out125_out33 is +port( + CLKI : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic); +end pll_in125_out125_out33; + +architecture beh of pll_in125_out125_out33 is + signal CLKOS2 : std_logic ; + signal CLKOS3 : std_logic ; + signal INTLOCK : std_logic ; + signal CLKFB_T : std_logic ; + signal REFCLK : std_logic ; + signal GND : std_logic ; + signal VCC : std_logic ; +begin +GND_0: VLO port map ( + Z => GND); +VCC_0: VHI port map ( + Z => VCC); +PUR_INST: PUR port map ( + PUR => VCC); +GSR_INST: GSR port map ( + GSR => VCC); +PLLINST_0: EHXPLLL + generic map( + CLKI_DIV => 15, + CLKFB_DIV => 4, + CLKOP_DIV => 1, + CLKOS_DIV => 18, + CLKOS2_DIV => 1, + CLKOS3_DIV => 1, + CLKOP_ENABLE => "ENABLED", + CLKOS_ENABLE => "ENABLED", + CLKOS2_ENABLE => "DISABLED", + CLKOS3_ENABLE => "DISABLED", + CLKOP_CPHASE => 0, + CLKOS_CPHASE => 17, + CLKOS2_CPHASE => 0, + CLKOS3_CPHASE => 0, + CLKOP_FPHASE => 0, + CLKOS_FPHASE => 0, + CLKOS2_FPHASE => 0, + CLKOS3_FPHASE => 0, + FEEDBK_PATH => "INT_OS", + CLKOP_TRIM_POL => "FALLING", + CLKOP_TRIM_DELAY => 0, + CLKOS_TRIM_POL => "FALLING", + CLKOS_TRIM_DELAY => 0, + OUTDIVIDER_MUXA => "REFCLK", + OUTDIVIDER_MUXB => "DIVB", + OUTDIVIDER_MUXC => "DIVC", + OUTDIVIDER_MUXD => "DIVD", + PLL_LOCK_MODE => 0, + STDBY_ENABLE => "DISABLED", + DPHASE_SOURCE => "DISABLED", + PLLRST_ENA => "DISABLED", + INTFB_WAKE => "DISABLED" + ) + port map ( + CLKI => CLKI, + CLKFB => CLKFB_T, + PHASESEL1 => GND, + PHASESEL0 => GND, + PHASEDIR => GND, + PHASESTEP => GND, + PHASELOADREG => GND, + STDBY => GND, + PLLWAKESYNC => GND, + RST => GND, + ENCLKOP => GND, + ENCLKOS => GND, + ENCLKOS2 => GND, + ENCLKOS3 => GND, + CLKOP => CLKOP, + CLKOS => CLKOS, + CLKOS2 => CLKOS2, + CLKOS3 => CLKOS3, + LOCK => LOCK, + INTLOCK => INTLOCK, + REFCLK => REFCLK, + CLKINTFB => CLKFB_T); +end beh; + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vm new file mode 100644 index 0000000..653411d --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vm @@ -0,0 +1,115 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Fri May 10 15:07:29 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 11 "\/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc " + +`timescale 100 ps/100 ps +(* NGD_DRC_MASK=1 *)module pll_in125_out125_out33 ( + CLKI, + CLKOP, + CLKOS, + LOCK +) +; +input CLKI ; +output CLKOP ; +output CLKOS ; +output LOCK ; +wire CLKI ; +wire CLKOP ; +wire CLKOS ; +wire LOCK ; +wire CLKOS2 ; +wire CLKOS3 ; +wire INTLOCK ; +wire CLKFB_t ; +wire REFCLK ; +wire GND ; +wire VCC ; + VLO GND_0 ( + .Z(GND) +); + VHI VCC_0 ( + .Z(VCC) +); + PUR PUR_INST ( + .PUR(VCC) +); + GSR GSR_INST ( + .GSR(VCC) +); +// @8:52 +(* LPF_RESISTOR="16" , ICP_CURRENT="5" , FREQUENCY_PIN_CLKI="125.000000" , FREQUENCY_PIN_CLKOP="125.000000" , FREQUENCY_PIN_CLKOS="33.333333" *) EHXPLLL PLLInst_0 ( + .CLKI(CLKI), + .CLKFB(CLKFB_t), + .PHASESEL1(GND), + .PHASESEL0(GND), + .PHASEDIR(GND), + .PHASESTEP(GND), + .PHASELOADREG(GND), + .STDBY(GND), + .PLLWAKESYNC(GND), + .RST(GND), + .ENCLKOP(GND), + .ENCLKOS(GND), + .ENCLKOS2(GND), + .ENCLKOS3(GND), + .CLKOP(CLKOP), + .CLKOS(CLKOS), + .CLKOS2(CLKOS2), + .CLKOS3(CLKOS3), + .LOCK(LOCK), + .INTLOCK(INTLOCK), + .REFCLK(REFCLK), + .CLKINTFB(CLKFB_t) +); +defparam PLLInst_0.CLKI_DIV = 15; +defparam PLLInst_0.CLKFB_DIV = 4; +defparam PLLInst_0.CLKOP_DIV = 1; +defparam PLLInst_0.CLKOS_DIV = 18; +defparam PLLInst_0.CLKOS2_DIV = 1; +defparam PLLInst_0.CLKOS3_DIV = 1; +defparam PLLInst_0.CLKOP_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED"; +defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED"; +defparam PLLInst_0.CLKOP_CPHASE = 0; +defparam PLLInst_0.CLKOS_CPHASE = 17; +defparam PLLInst_0.CLKOS2_CPHASE = 0; +defparam PLLInst_0.CLKOS3_CPHASE = 0; +defparam PLLInst_0.CLKOP_FPHASE = 0; +defparam PLLInst_0.CLKOS_FPHASE = 0; +defparam PLLInst_0.CLKOS2_FPHASE = 0; +defparam PLLInst_0.CLKOS3_FPHASE = 0; +defparam PLLInst_0.FEEDBK_PATH = "INT_OS"; +defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING"; +defparam PLLInst_0.CLKOP_TRIM_DELAY = 0; +defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING"; +defparam PLLInst_0.CLKOS_TRIM_DELAY = 0; +defparam PLLInst_0.OUTDIVIDER_MUXA = "REFCLK"; +defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB"; +defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC"; +defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD"; +defparam PLLInst_0.PLL_LOCK_MODE = 0; +defparam PLLInst_0.STDBY_ENABLE = "DISABLED"; +defparam PLLInst_0.DPHASE_SOURCE = "DISABLED"; +defparam PLLInst_0.PLLRST_ENA = "DISABLED"; +defparam PLLInst_0.INTFB_WAKE = "DISABLED"; +endmodule /* pll_in125_out125_out33 */ + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_cck.rpt.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify.lpf new file mode 100644 index 0000000..8e445e1 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify.lpf @@ -0,0 +1,20 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp2.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp4.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp8.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/run_options.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/run_options.txt new file mode 100644 index 0000000..b19e59a --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/run_options.txt @@ -0,0 +1,75 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/run_options.txt +#-- Written on Fri May 10 15:07:25 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "pll_in125_out125_out33" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./pll_in125_out125_out33.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf" +impl -active "syn_results" diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scemi_cfg.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs new file mode 100644 index 0000000..dccd7f3 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs @@ -0,0 +1,73 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "pll_in125_out125_out33" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf" +impl -active "syn_results" diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/layer0.tlg.rptmap new file mode 100644 index 0000000..3910cac --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/layer0.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr new file mode 100644 index 0000000..b343684 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr @@ -0,0 +1,55 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33. +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure. +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. +Post processing for ecp5um.vhi.syn_black_box +Post processing for work.pll_in125_out125_out33.structure +@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:25 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:26 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 15:07:26 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..ab343225f2f286c43a97ab1e792e1494bd36aabf GIT binary patch literal 8192 zcmeH~&2H2%5XZCI(jq}y5JEjbC950&QQ}R~{ZNn)rBqycq3wm!%1Ndhvxyzq&bCE+ z*`5%O!n5!~+?eb~OQo%lP`QAuIAf2;&fmX`4?g^`&kc}csd8pW;M{X+HRlZ>j^iv~ ztz(^)8a5VZ9kf;dcV)qO`Qyt9M%C87I{4UP30MM_fF)oFSOS)SC143y0+xU!U#owxgYWafRw6Ea{bPMO*w85jM_-ZbRW z(dXiq-~wlIVV+la^QF5>&f59v_tnnIx0T1(vBeUw1S|ndz!IHV+a09IX1Lu7x2u=e9v(n02VC^5$g_8j;m@zB8XY3fp9|- z37QCr4aEmQq)9=7#;&nILoC-XyAH{?rCeA;^IZbG|-Gk zG%I5ehC*C4%Y3r!j^7NuMmRS9@bFBGKmWPf{Y4meD~VCY;(j-hr!H<6Dm9BYuO{%v zYASP$noQ1DbAJKVwAoFv@f)3>k~6WbxpW{s#bnFoYYOV9iR-JH{$>(;e%MBGq2IYG z_C%__JO5C)+Nd%%rGn{y9pb%z^z?lty6yi#lHqBh+9Z?o@_Z!NK}kXAd&5J(EXB++ UJO_fOLT07mQV@fOL{GBnC$bxiU;qFB literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.rptmap new file mode 100644 index 0000000..1ce0348 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.rptmap @@ -0,0 +1 @@ +./synlog/pll_in125_out125_out33_compiler.srr,pll_in125_out125_out33_compiler.srr,Compile Log diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr new file mode 100644 index 0000000..2b5185d --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr @@ -0,0 +1,265 @@ +# Fri May 10 15:07:28 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 15:07:30 2019 +# + + +Top view: pll_in125_out125_out33 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 +=================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 +================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKINTFB + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - +CLKFB_t Net - - - - 1 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +==================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) + 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in125_out125_out33 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +===================================================================================== + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 15:07:28 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..e1a8837f299ed545acca0f4cd473ad0ec3834f52 GIT binary patch literal 8192 zcmeI#F;Buk6bJBYV`L(@7$%YzCP;)tC5;J*5eZH>h-?f^X&>c;-jVh+I5*e z*5_;4c6pUIVJ`#(AOHafKmY;|fB*y_009U<;GYW^uT-toymi+^(F8lq_ zpf?`SxOY7q&~CRO6MBmBcpl{^w3KSGueL4wjfGS{npgHssZ7(&=6+=&Dj#-1KmY;| zfB*y_009U<00Izz00bcLSAiG5R4uP3$Nue25Cr|Dju#Yb^~8B0wIWt-&QIFZ=<6(t z>~LN$*o1mz+-YkjpTjgVoP_o$Oj&Whsbcq?f==spd?zz!TIKqIV?#5!?;BGmM~ra|UN1SJGZ>2U0AUiFKv19>LPC~HvJe$D?eZDEYA?B&JH zaQ*-Q0RR8QSZ#0IHWL24`W3xUK;nb7q$6dkQ<@^)p}2IgB<(4xeh3P|w2BxKZ{>pV zx(WK@ZzLzVyVeGJSEnIho1!Vsa9*ByMkh(4%DB)xzNkS39&M?)H6zzTtm2jl$3X^f zxd8t$C!DQmclc@ zR2r|_CZ$D{IWSSAxBrir4ce5kMv@)C>N48VOgH0^ZC4Js2-ZvCfk#lU9TR-ifi&>4 zEwq{Mv=qf^XqDhy$J*4y0hmO=vgob2!K<(KtM~2Aa)mbYZd_P+i~HsJ`xVI_EtZgF zI}DB8*puvH_r-c7?Xp2AWb&@BSd7ruEWAX~C84B#)U^$s$EO%@oL}l^;=R*_u_c zY=s(TA9jQ2LVh~!sj-y4l~OOw?cG1@>rT78&H}P91lz<^qXZsm1tqu9XbO>0^R0+0 z&K%j4d~XF;KE9@F@W4jx$+UOLO*u1k7bXVDruirp_v8^C#hrTiu8kIg5BWw4%oJ%0 z@|12J)Id7j`A*iM(oi-J9SdBrJLN%_mzhE5l&Sq<($_Q2@S$_;PW{@hbGchY^df^M zzUr~)`@HYTR*uVu(cvz+dDk^qy3Z05@kA}|(WRAP5HV-0q5ML1;wg44GM2f~wcw*? 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To preserve this instance, use the syn_noprune synthesis directive. + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml new file mode 100644 index 0000000..c6fedcf --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_resourceusage.rpt +Resource Usage + + +0 + + +0 + + +0 + + +0 + + +0 + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt new file mode 100644 index 0000000..ad96549 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt @@ -0,0 +1,8 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..a39ddc1 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +0 / 0 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..f7bd0c8 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +8 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt + + + +1 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt + + + +0h:00m:02s + + +0h:00m:02s + + +146MB + + +1557493650 + + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..b33a877 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml @@ -0,0 +1,23 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +System +100.0 MHz +NA +10.000 + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt new file mode 100644 index 0000000..61d4bc9 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt @@ -0,0 +1 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt new file mode 100644 index 0000000..eed8756 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt @@ -0,0 +1,2 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml new file mode 100644 index 0000000..503e067 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +2 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +143MB + + +1557493648 + + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap new file mode 100644 index 0000000..dd09adb --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap @@ -0,0 +1 @@ +./pll_in125_out125_out33_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/closed.png b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/closed.png new file mode 100644 index 0000000000000000000000000000000000000000..0d78634f322a904e7bd0c9466498c0a42777589f GIT binary patch literal 3672 zcmeH}={wX77sr2=$PzQiz6{y-jN4KYF_wtIP-F`kBBt#7AfeD8`@T=sp)7-;LX(KG zMk;%mvP`%|gL&rp8=kk%xjyH6uJhu1o$H)eClzjGdX8O~9RPrH=4QsW^a`dY=UFDY zzNFTs(+e}w@P;7(v}Qz8ZL;Y-#M8|71^^^;13(%*Pw1w20|1DL008n+0MJ_p0HM(! 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    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:27 2019
+
+###########################################################]
+
+
     +
    +
+# Fri May 10 15:07:27 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+Linked File: pll_in125_out125_out33_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in125_out125_out33
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 15:07:28 2019
+
+###########################################################]
+
+
     +
    +
+# Fri May 10 15:07:28 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W:MT246 : pll_in125_out125_out33.vhd(52) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 15:07:30 2019
+#
+
+
+Top view:               pll_in125_out125_out33
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 15:07:30 2019
+
+###########################################################]
+
+
     diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_toc.htm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_toc.htm new file mode 100644 index 0000000..0e7c50e --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_toc.htm @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml new file mode 100644 index 0000000..4eb904e --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/statusReport.html b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..c558da4 --- /dev/null +++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/statusReport.html @@ -0,0 +1,112 @@ + + + Project Status Summary Page + + + + + + +
    + + + + + + + + + + +
    Project Settings
    Project Name pll_in125_out125_out33 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module pll_in125_out125_out33
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete910-00m:01s-5/10/19
    3:07 PM
    (premap)Complete2000m:00s0m:00s143MB5/10/19
    3:07 PM
    (fpga_mapper)Complete8100m:02s0m:02s146MB5/10/19
    3:07 PM
    Multi-srs GeneratorComplete5/10/19
    3:07 PM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 0I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 0

    + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    System100.0 MHzNA10.000
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 0 / 0

    +
    +
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pll_in125_out125_out33.CLKI + + + + + pll_in125_out125_out33_CLKOP + pll_in125_out125_out33_CLKOP + + out + + + + pll_in125_out125_out33.CLKOP + + + + + pll_in125_out125_out33_CLKOS + pll_in125_out125_out33_CLKOS + + out + + + + pll_in125_out125_out33.CLKOS + + + + + pll_in125_out125_out33_LOCK + pll_in125_out125_out33_LOCK + + out + + + + pll_in125_out125_out33.LOCK + + + + + sgmii_ecp5_hdinn + sgmii_ecp5_hdinn + + in + + + + sgmii_ecp5.hdinn + + + + + sgmii_ecp5_hdinp + sgmii_ecp5_hdinp + + in + + + + sgmii_ecp5.hdinp + + + + + sgmii_ecp5_hdoutn + sgmii_ecp5_hdoutn + + out + + + + sgmii_ecp5.hdoutn + + + + + sgmii_ecp5_hdoutp + sgmii_ecp5_hdoutp + + out + + + + sgmii_ecp5.hdoutp + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-04-24.09:28:38 AM + 2019-05-10.04:50:40 PM + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + sgmii + 1.0 + + + PCSD + + Lattice Semiconductor Corporation + LEGACY + PCS + 8.2 + + + Diamond_Simulation + simulation + + ./PCSD/PCSD_softlogic.v + verilogSource + + + ./PCSD/PCSD.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./PCSD/PCSD_softlogic.v + verilogSource + + + ./PCSD/PCSD.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + ctc_del_s + ctc_del_s + + out + + + + ctc_ins_s + ctc_ins_s + + out + + + + ctc_orun_s + ctc_orun_s + + out + + + + ctc_urun_s + ctc_urun_s + + out + + + + hdinn + hdinn + + in + + + + true + + + + + hdinp + hdinp + + in + + + + true + + + + + hdoutn + hdoutn + + out + + + + true + + + + + hdoutp + hdoutp + + out + + + + true + + + + + lsm_status_s + lsm_status_s + + out + + + + pll_lol + pll_lol + + in + + + + pll_refclki + pll_refclki + + in + + + + rsl_disable + rsl_disable + + in + + + + rsl_rst + rsl_rst + + in + + + + rst_dual_c + rst_dual_c + + in + + + + rx_cdr_lol_s + rx_cdr_lol_s + + out + + + + rx_los_low_s + rx_los_low_s + + out + + + + rx_pcs_rst_c + rx_pcs_rst_c + + in + + + + rx_pwrup_c + rx_pwrup_c + + in + + + + rx_serdes_rst_c + rx_serdes_rst_c + + in + + + + rxrefclk + rxrefclk + + in + + + + serdes_pdb + serdes_pdb + + in + + + + serdes_rst_dual_c + serdes_rst_dual_c + + in + + + + signal_detect_c + signal_detect_c + + in + + + + tx_pclk + tx_pclk + + out + + + + tx_pcs_rst_c + tx_pcs_rst_c + + in + + + + tx_pwrup_c + tx_pwrup_c + + in + + + + tx_serdes_rst_c + tx_serdes_rst_c + + in + + + + txi_clk + txi_clk + + in + + + + rx_cv_err + rx_cv_err + + out + + 0 + 0 + + + + + rx_disp_err + rx_disp_err + + out + + 0 + 0 + + + + + rx_k + rx_k + + out + + 0 + 0 + + + + + rxdata + rxdata + + out + + 7 + 0 + + + + + tx_disp_correct + tx_disp_correct + + in + + 0 + 0 + + + + + tx_k + tx_k + + in + + 0 + 0 + + + + + txdata + txdata + + in + + 7 + 0 + + + + + xmit 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none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + CLKI + CLKI + + in + + + + CLKOP + CLKOP + + out + + + + CLKOS + CLKOS + + out + + + + LOCK + LOCK + + out + + + + + + synplify + 2019-05-10.04:50:40 PM + + false + false + false + true + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/10/2019 + + + ModuleName + pll_in125_out125_out33 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 15:07:09 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 4 + + + CLKI_DIV + 15 + + + CLKI_FREQ + 125 + + + CLKOP_ACTUAL_FREQ + 125.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 1 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 125 + + + CLKOP_MUXA + ENABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + DISABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + DISABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 100.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + 33.333333 + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 18 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + ENABLED + + + CLKOS_FREQ + 33.3333333333 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.1 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + INT_OS + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 0.955 + + + PLL_LOCK_MODE + ENABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 600.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_in125_out125_out33 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -bypassp -fclkos 33.3333333333 -fclkos_tol 0.1 -phase_cntl STATIC -lock -fb_mode 6 + + + + + + + + sgmii_channel_smi + + Lattice Semiconductor Corporation + LEGACY + SGMII/Gb Ethernet PCS + 4.1 + + + Diamond_Simulation + simulation + + ./sgmii_channel_smi/sgmii_channel_smi.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi.vhd + vhdlSource + + + ./sgmii_channel_smi/sgmii_channel_smi_core_bb.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi.vhd + vhdlSource + + + ./sgmii_channel_smi/sgmii_channel_smi_core_bb.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v + verilogSource + + + + Diamond_Synthesis + synthesis + + ./sgmii_channel_smi/sgmii_channel_smi.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi.vhd + vhdlSource + + + ./sgmii_channel_smi/sgmii_channel_smi_core_bb.v + verilogSource + + + ./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v + verilogSource + + + ./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi_core.ngo + NGO + + + ./sgmii_channel_smi/sgmii_channel_smi.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi.vhd + vhdlSource + + + ./sgmii_channel_smi/sgmii_channel_smi_core_bb.v + verilogSource + + + ./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v + verilogSource + + + ./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v + verilogSource + + + ./sgmii_channel_smi/sgmii_channel_smi_core.ngo + NGO + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + NGDGeneration + none + ${sbp_path}/${instance}/generate_ngd.tcl + GENERATE + + + + + + + an_link_ok + an_link_ok + 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+ + rx_clock_enable_source + rx_clock_enable_source + + out + + + + rx_dv + rx_dv + + out + + + + rx_er + rx_er + + out + + + + rx_pcs_rst_c + rx_pcs_rst_c + + in + + + + rx_serdes_rst_c + rx_serdes_rst_c + + in + + + + rxrefclk + rxrefclk + + in + + + + sci_en + sci_en + + in + + + + sci_en_dual + sci_en_dual + + in + + + + sci_int + sci_int + + out + + + + sci_rd + sci_rd + + in + + + + sci_sel + sci_sel + + in + + + + sci_sel_dual + sci_sel_dual + + in + + + + sci_wrn + sci_wrn + + in + + + + serdes_pdb + serdes_pdb + + out + + + + serdes_rst_dual_c + serdes_rst_dual_c + + out + + + + sgmii_mode + sgmii_mode + + in + + + + sli_rst + sli_rst + + in + + + + true + + + + + tx_clk_125 + tx_clk_125 + + in + + + + tx_clock_enable_sink + tx_clock_enable_sink + + in + + + + tx_clock_enable_source + tx_clock_enable_source + + out + + + + tx_en + tx_en + + in + + + + tx_er + tx_er + + in + + + + tx_pcs_rst_c + tx_pcs_rst_c + + in + + + + tx_pwrup_c + tx_pwrup_c + + out + + + + tx_serdes_rst_c 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+ CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + ctc_del_s + ctc_del_s + + out + + + + ctc_ins_s + ctc_ins_s + + out + + + + ctc_orun_s + ctc_orun_s + + out + + + + ctc_urun_s + ctc_urun_s + + out + + + + cyawstn + cyawstn + + in + + + + hdinn + hdinn + + in + + + + true + + + + + hdinp + hdinp + + in + + + + true + + + + + hdoutn + hdoutn + + out + + + + true + + + + + hdoutp + hdoutp + + out + + + + true + + + + + lsm_status_s + lsm_status_s + + out + + + + pll_lol + pll_lol + + out + + + + pll_refclki + pll_refclki + + in + + + + rsl_disable + rsl_disable + + in + + + + rsl_rst + rsl_rst + + in + + + + rsl_rx_rdy + rsl_rx_rdy + + out + + + + rsl_tx_rdy + rsl_tx_rdy + + out + + + + rst_dual_c + rst_dual_c + + in + + + + rx_cdr_lol_s + rx_cdr_lol_s + + out + + + + rx_los_low_s + rx_los_low_s + + out + + + + rx_pcs_rst_c + rx_pcs_rst_c + + in + + + + rx_pwrup_c + rx_pwrup_c + + in + + + + rx_serdes_rst_c + rx_serdes_rst_c + + in + + + + rxrefclk + rxrefclk + + in + + + + sci_en + sci_en + + in + + + + sci_en_dual + sci_en_dual + + in + + + + sci_int + sci_int + + out + + + + sci_rd + sci_rd + + in + + + + sci_sel + sci_sel + + in + + + + sci_sel_dual + sci_sel_dual + + in + + + + sci_wrn + sci_wrn + + in + + + + serdes_pdb + serdes_pdb + + in + + + + serdes_rst_dual_c + serdes_rst_dual_c + + in + + + + signal_detect_c + signal_detect_c + + in + + + + sli_rst + sli_rst + + in + + + + true + + + + + tx_pclk + tx_pclk + + out + + + + tx_pcs_rst_c + tx_pcs_rst_c + + in + + + + tx_pwrup_c + tx_pwrup_c + + in + + + + tx_serdes_rst_c + tx_serdes_rst_c + + in + + + + txi_clk + txi_clk + + in + + + + rx_cv_err + rx_cv_err + + out + + 0 + 0 + + + + + rx_disp_err + rx_disp_err + + out + + 0 + 0 + + + + + rx_k + rx_k + + out + + 0 + 0 + + + + + rxdata + rxdata + + out + + 7 + 0 + + + + + sci_addr + sci_addr + + in + + 5 + 0 + + + + + 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RXFIFO_ENABLE + Enabled + + + RXINVPOL + Non-invert + + + RXLDR + Off + + + RXLOSTHRESHOLD + 2 + + + RXLSM + Enabled + + + RXSC + K28P5 + + + RXWA + Barrel Shift + + + RX_DATA_WIDTH + 8/10-Bit + + + RX_FICLK_RATE + 125.0000 + + + RX_LINE_RATE + 1.2500 + + + RX_RATE_DIV + Full Rate + + + SCIPORT + Enabled + + + SOFTLOL + Enabled + + + TX8B10B + Enabled + + + TXAMPLITUDE + 1100 + + + TXDEPOST + Disabled + + + TXDEPRE + Disabled + + + TXDIFFTERM + 50 ohms + + + TXFIFO_ENABLE + Enabled + + + TXINVPOL + Non-invert + + + TXLDR + Off + + + TXPLLLOLTHRESHOLD + 0 + + + TXPLLMULT + 10X + + + TX_DATA_WIDTH + 8/10-Bit + + + TX_FICLK_RATE + 125.0000 + + + TX_LINE_RATE + 1.2500 + + + TX_MAX_RATE + 1.25 + + + TX_RATE_DIV + Full Rate + + + VHDL + 1 + + + Verilog + 0 + + + + sgmii_ecp5.pp + pp + + + sgmii_ecp5.sym + sym + + + sgmii_ecp5.tft + tft + + + sgmii_ecp5.txt + pcs_module + + + + + DCUCHANNEL + 1 + + true + false + DCUCHANNEL + + Lane0 + + + + + + + tsmac + + Lattice Semiconductor Corporation + LEGACY + Tri-Speed Ethernet MAC + 4.1 + + + Diamond_Simulation + simulation + + ./tsmac/tsmac_beh.v + verilogSource + + + ./tsmac/tsmac_beh.v + verilogSource + + + + Diamond_Synthesis + synthesis + + ./tsmac/tsmac_bb.v + verilogSource + + + ./tsmac/tsmac.ngo + NGO + + + ./tsmac/tsmac_bb.v + verilogSource + + + ./tsmac/tsmac.ngo + NGO + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + + + + + col + col + + in + + + + cpu_if_gbit_en + cpu_if_gbit_en + + out + + + + crs + crs + + in + + + + hclk + hclk + + in + + + + hcs_n + hcs_n + + in + + + + hdataout_en_n + hdataout_en_n + + out + + + + hread_n + hread_n + + in + + + + hready_n + hready_n + + out + + + + hwrite_n + hwrite_n + + in + + + + ignore_pkt + ignore_pkt + + in + + + + reset_n + reset_n + + in + + + + rx_dv + rx_dv + + in + + + + rx_eof + rx_eof + + out + + + + rx_er + rx_er + + in + + + + rx_error + rx_error + + out + + + + rx_fifo_error + rx_fifo_error + + out + + + + rx_fifo_full + rx_fifo_full + + in + + + + rx_stat_en + rx_stat_en + + out + + + + rx_write + rx_write + + out + + + + rxmac_clk + rxmac_clk + + in + + + + rxmac_clk_en + rxmac_clk_en + + in + + + + tx_discfrm + tx_discfrm + + out + + + + tx_done + tx_done + + out + + + + tx_en + tx_en + + out + + + + tx_er + tx_er + + out + + + + tx_fifoavail + tx_fifoavail + + in + + + + tx_fifoctrl + tx_fifoctrl + + in + + + + tx_fifoempty + tx_fifoempty + + in + + + + tx_fifoeof + tx_fifoeof + + in + + + + tx_macread + tx_macread + + out + + + + tx_sndpausreq + tx_sndpausreq + + in + + + + tx_staten + tx_staten + + out + + + + txmac_clk + txmac_clk + + in + + + + txmac_clk_en + txmac_clk_en + + in + + + + haddr + haddr + + in + + 7 + 0 + + + + + hdatain + hdatain + + in + + 7 + 0 + + + + + hdataout + hdataout + + out + + 7 + 0 + + + + + rx_dbout + rx_dbout + + out + + 7 + 0 + + + + + rx_stat_vector + rx_stat_vector + + out + + 31 + 0 + + + + + rxd + rxd + + in + + 7 + 0 + + + + + tx_fifodata + tx_fifodata + + in + + 7 + 0 + + + + + tx_sndpaustim + tx_sndpaustim + + in + + 15 + 0 + + + + + tx_statvec + tx_statvec + + out + + 30 + 0 + + + + + txd + txd + + out + + 7 + 0 + + + + + + + synplify + 2013-08-08.14:14:33 + 2019-05-10.04:50:40 PM + + false + false + false + false + false + false + false + false + false + IPCFG + PRIMARY + PRIMARY + false + false + + + + + + Family + sa5p00m + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + Tri-Speed Ethernet MAC + + + CoreRevision + 4.1 + + + CoreStatus + Demo + + + CoreType + IPCFG + + + Date + 04/29/2019 + + + ModuleName + tsmac + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 13:44:50 + + + VendorName + Lattice Semiconductor Corporation + + + + ALDC_TOOL + 0 + + + CORE_SYNP + 1 + + + LOOPBACK + NO + + + MIIM + No + + + MODE + SGMII easy connect + + + MODS_TOOL + 1 + + + MULT_WB + NO + + + STAT_REGS + NO + + + + Logical + + + + Misc + + + + Physical + + + + Simulation + + + + Synthesis + + + + + + + + + + + PCSD_sgmii_channel_smi_pll_lol + PCSD_sgmii_channel_smi_pll_lol + PCSD_sgmii_channel_smi_pll_lol + + + pll_lol + DCU + short + + + + + + + PCSD_sgmii_channel_smi_pll_refclki + PCSD_sgmii_channel_smi_pll_refclki + PCSD_sgmii_channel_smi_pll_refclki + + + pll_refclki + DCU + short + + + + + + + PCSD_sgmii_channel_smi_serdes_pdb + PCSD_sgmii_channel_smi_serdes_pdb + PCSD_sgmii_channel_smi_serdes_pdb + + + serdes_pdb + DCU + short + + + + + + + PCSD_hdinn + PCSD_hdinn + + + sys_yes + + + + + + + PCSD_hdinp + PCSD_hdinp + + + sys_yes + + + + + + + PCSD_hdoutn + PCSD_hdoutn + + + sys_yes + + + + + + + PCSD_hdoutp + PCSD_hdoutp + + + sys_yes + + + + + + + pll_in125_out125_out33_CLKI + pll_in125_out125_out33_CLKI + + + + + pll_in125_out125_out33_CLKOP + pll_in125_out125_out33_CLKOP + + + + + pll_in125_out125_out33_CLKOS + pll_in125_out125_out33_CLKOS + + + + + pll_in125_out125_out33_LOCK + pll_in125_out125_out33_LOCK + + + + + sgmii_ecp5_hdinn + sgmii_ecp5_hdinn + + + sys_yes + + + + + + + sgmii_ecp5_hdinp + sgmii_ecp5_hdinp + + + sys_yes + + + + + + + sgmii_ecp5_hdoutn + sgmii_ecp5_hdoutn + + + sys_yes + + + + + + + sgmii_ecp5_hdoutp + sgmii_ecp5_hdoutp + + + sys_yes + + + + + + + + diff --git a/gbe/cores/sgmii/sgmii.vhd b/gbe/cores/sgmii/sgmii.vhd new file mode 100644 index 0000000..e2b5bac --- /dev/null +++ b/gbe/cores/sgmii/sgmii.vhd @@ -0,0 +1,336 @@ + + + + + + + +-- +-- Verific VHDL Description of module sgmii +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity sgmii is + port (PCSD_hdinn: in std_logic; + PCSD_hdinp: in std_logic; + PCSD_hdoutn: out std_logic; + PCSD_hdoutp: out std_logic; + pll_in125_out125_out33_CLKI: in std_logic; + pll_in125_out125_out33_CLKOP: out std_logic; + pll_in125_out125_out33_CLKOS: out std_logic; + pll_in125_out125_out33_LOCK: out std_logic; + sgmii_ecp5_hdinn: in std_logic; + sgmii_ecp5_hdinp: in std_logic; + sgmii_ecp5_hdoutn: out std_logic; + sgmii_ecp5_hdoutp: out std_logic + ); + +end entity sgmii; -- sbp_module=true + +architecture sgmii of sgmii is + component PCSD is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + xmit: in std_logic_vector(0 downto 0); + ctc_del_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_orun_s: out std_logic; + ctc_urun_s: out std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic; + txi_clk: in std_logic + ); + + end component PCSD; -- not_need_bbox=true + + + component pll_in125_out125_out33 is + port (CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic + ); + + end component pll_in125_out125_out33; -- not_need_bbox=true + + + component sgmii_channel_smi is + port (mr_adv_ability: in std_logic_vector(15 downto 0); + mr_lp_adv_ability: out std_logic_vector(15 downto 0); + operational_rate: in std_logic_vector(1 downto 0); + rx_d: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_d: in std_logic_vector(7 downto 0); + an_link_ok: out std_logic; + col: out std_logic; + crs: out std_logic; + cyawstn: in std_logic; + debug_link_timer_short: in std_logic; + force_isolate: in std_logic; + force_loopback: in std_logic; + force_unidir: in std_logic; + gbe_mode: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + mr_an_complete: out std_logic; + mr_an_enable: in std_logic; + mr_main_reset: in std_logic; + mr_page_rx: out std_logic; + mr_power_down: in std_logic; + mr_restart_an: in std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rst_dual_c: in std_logic; + rst_n: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_clk_125: in std_logic; + rx_clock_enable_sink: in std_logic; + rx_clock_enable_source: out std_logic; + rx_dv: out std_logic; + rx_er: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: out std_logic; + serdes_rst_dual_c: out std_logic; + sgmii_mode: in std_logic; + sli_rst: in std_logic; + tx_clk_125: in std_logic; + tx_clock_enable_sink: in std_logic; + tx_clock_enable_source: out std_logic; + tx_en: in std_logic; + tx_er: in std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: out std_logic; + tx_serdes_rst_c: out std_logic + ); + + end component sgmii_channel_smi; -- not_need_bbox=true + + + component sgmii_ecp5 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + xmit: in std_logic_vector(0 downto 0); + ctc_del_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_orun_s: out std_logic; + ctc_urun_s: out std_logic; + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + sli_rst: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic; + txi_clk: in std_logic + ); + + end component sgmii_ecp5; -- not_need_bbox=true + + + component tsmac is + port (haddr: in std_logic_vector(7 downto 0); + hdatain: in std_logic_vector(7 downto 0); + hdataout: out std_logic_vector(7 downto 0); + rx_dbout: out std_logic_vector(7 downto 0); + rx_stat_vector: out std_logic_vector(31 downto 0); + rxd: in std_logic_vector(7 downto 0); + tx_fifodata: in std_logic_vector(7 downto 0); + tx_sndpaustim: in std_logic_vector(15 downto 0); + tx_statvec: out std_logic_vector(30 downto 0); + txd: out std_logic_vector(7 downto 0); + col: in std_logic; + cpu_if_gbit_en: out std_logic; + crs: in std_logic; + hclk: in std_logic; + hcs_n: in std_logic; + hdataout_en_n: out std_logic; + hread_n: in std_logic; + hready_n: out std_logic; + hwrite_n: in std_logic; + ignore_pkt: in std_logic; + reset_n: in std_logic; + rx_dv: in std_logic; + rx_eof: out std_logic; + rx_er: in std_logic; + rx_error: out std_logic; + rx_fifo_error: out std_logic; + rx_fifo_full: in std_logic; + rx_stat_en: out std_logic; + rx_write: out std_logic; + rxmac_clk: in std_logic; + rxmac_clk_en: in std_logic; + tx_discfrm: out std_logic; + tx_done: out std_logic; + tx_en: out std_logic; + tx_er: out std_logic; + tx_fifoavail: in std_logic; + tx_fifoctrl: in std_logic; + tx_fifoempty: in std_logic; + tx_fifoeof: in std_logic; + tx_macread: out std_logic; + tx_sndpausreq: in std_logic; + tx_staten: out std_logic; + txmac_clk: in std_logic; + txmac_clk_en: in std_logic + ); + + end component tsmac; -- not_need_bbox=true + + + component PCSCLKDIV is + port (CLKI: in std_logic; + RST: in std_logic; + SEL2: in std_logic; + SEL1: in std_logic; + SEL0: in std_logic; + CDIV1: out std_logic; + CDIVX: out std_logic + ); + + end component PCSCLKDIV; -- not_need_bbox=true + + + signal PCSD_pll_lol,PCSD_pll_refclki,PCSD_serdes_pdb,sli_rst_wire1,sgmii_channel_smi_inst_serdes_rst_dual_c_sig, + sgmii_channel_smi_inst_tx_serdes_rst_c_sig,sgmii_channel_smi_inst_tx_pwrup_c_sig, + sli_rst_wire2,n1,pwr,pcs_clkdiv0_CDIV1_sig,pcs_clkdiv0_CDIVX_sig, + pcs_clkdiv0_CLKI_sig,pcs_clkdiv0_RST_sig,gnd : std_logic; +begin + sli_rst_wire1 <= sgmii_channel_smi_inst_serdes_rst_dual_c_sig OR sgmii_channel_smi_inst_tx_serdes_rst_c_sig OR (NOT PCSD_serdes_pdb) OR (NOT sgmii_channel_smi_inst_tx_pwrup_c_sig); + PCSD_inst: component PCSD port map (rx_cv_err=>open,rx_disp_err=>open, + rx_k=>open,rxdata=>open,tx_disp_correct=>"0",tx_k=>"0",txdata=>"00000000", + xmit=>"0",ctc_del_s=>open,ctc_ins_s=>open,ctc_orun_s=>open,ctc_urun_s=>open, + hdinn=>PCSD_hdinn,hdinp=>PCSD_hdinp,hdoutn=>PCSD_hdoutn,hdoutp=>PCSD_hdoutp, + lsm_status_s=>open,pll_lol=>PCSD_pll_lol,pll_refclki=>PCSD_pll_refclki, + rsl_disable=>'0',rsl_rst=>'0',rst_dual_c=>'0',rx_cdr_lol_s=>open, + rx_los_low_s=>open,rx_pcs_rst_c=>'0',rx_pwrup_c=>'0',rx_serdes_rst_c=>'0', + rxrefclk=>'0',serdes_pdb=>PCSD_serdes_pdb,serdes_rst_dual_c=>'0', + signal_detect_c=>'0',tx_pclk=>open,tx_pcs_rst_c=>'0',tx_pwrup_c=>'0', + tx_serdes_rst_c=>'0',txi_clk=>'0'); + pll_in125_out125_out33_inst: component pll_in125_out125_out33 port map (CLKI=>pll_in125_out125_out33_CLKI, + CLKOP=>pll_in125_out125_out33_CLKOP,CLKOS=>pll_in125_out125_out33_CLKOS, + LOCK=>pll_in125_out125_out33_LOCK); + sgmii_channel_smi_inst: component sgmii_channel_smi port map (mr_adv_ability=>"0000000000000000", + mr_lp_adv_ability=>open,operational_rate=>"00",rx_d=>open,sci_addr=>"000000", + sci_rddata=>open,sci_wrdata=>"00000000",tx_d=>"00000000",an_link_ok=>open, + col=>open,crs=>open,cyawstn=>'0',debug_link_timer_short=>'0', + force_isolate=>'0',force_loopback=>'0',force_unidir=>'0',gbe_mode=>'0', + hdinn=>'0',hdinp=>'0',hdoutn=>open,hdoutp=>open,mr_an_complete=>open, + mr_an_enable=>'0',mr_main_reset=>'0',mr_page_rx=>open,mr_power_down=>'0', + mr_restart_an=>'0',pll_lol=>PCSD_pll_lol,pll_refclki=>PCSD_pll_refclki, + rst_dual_c=>'0',rst_n=>'0',rx_cdr_lol_s=>open,rx_clk_125=>'0', + rx_clock_enable_sink=>'0',rx_clock_enable_source=>open,rx_dv=>open, + rx_er=>open,rx_pcs_rst_c=>'0',rx_serdes_rst_c=>'0',rxrefclk=>'0', + sci_en=>'0',sci_en_dual=>'0',sci_int=>open,sci_rd=>'0',sci_sel=>'0', + sci_sel_dual=>'0',sci_wrn=>'0',serdes_pdb=>PCSD_serdes_pdb,serdes_rst_dual_c=>sgmii_channel_smi_inst_serdes_rst_dual_c_sig, + sgmii_mode=>'0',sli_rst=>sli_rst_wire1,tx_clk_125=>'0',tx_clock_enable_sink=>'0', + tx_clock_enable_source=>open,tx_en=>'0',tx_er=>'0',tx_pcs_rst_c=>'0', + tx_pwrup_c=>sgmii_channel_smi_inst_tx_pwrup_c_sig,tx_serdes_rst_c=>sgmii_channel_smi_inst_tx_serdes_rst_c_sig); + sgmii_ecp5_inst: component sgmii_ecp5 port map (rx_cv_err=>open,rx_disp_err=>open, + rx_k=>open,rxdata=>open,sci_addr=>"000000",sci_rddata=>open, + sci_wrdata=>"00000000",tx_disp_correct=>"0",tx_k=>"0",txdata=>"00000000", + xmit=>"0",ctc_del_s=>open,ctc_ins_s=>open,ctc_orun_s=>open,ctc_urun_s=>open, + cyawstn=>'0',hdinn=>sgmii_ecp5_hdinn,hdinp=>sgmii_ecp5_hdinp, + hdoutn=>sgmii_ecp5_hdoutn,hdoutp=>sgmii_ecp5_hdoutp,lsm_status_s=>open, + pll_lol=>open,pll_refclki=>'0',rsl_disable=>'0',rsl_rst=>'0', + rsl_rx_rdy=>open,rsl_tx_rdy=>open,rst_dual_c=>'0',rx_cdr_lol_s=>open, + rx_los_low_s=>open,rx_pcs_rst_c=>'0',rx_pwrup_c=>'0',rx_serdes_rst_c=>'0', + rxrefclk=>'0',sci_en=>'0',sci_en_dual=>'0',sci_int=>open,sci_rd=>'0', + sci_sel=>'0',sci_sel_dual=>'0',sci_wrn=>'0',serdes_pdb=>'0', + serdes_rst_dual_c=>'0',signal_detect_c=>'0',sli_rst=>sli_rst_wire2, + tx_pclk=>open,tx_pcs_rst_c=>'0',tx_pwrup_c=>'0',tx_serdes_rst_c=>'0', + txi_clk=>'0'); + tsmac_inst: component tsmac port map (haddr=>"00000000",hdatain=>"00000000", + hdataout=>open,rx_dbout=>open,rx_stat_vector=>open,rxd=>"00000000", + tx_fifodata=>"00000000",tx_sndpaustim=>"0000000000000000",tx_statvec=>open, + txd=>open,col=>'0',cpu_if_gbit_en=>open,crs=>'0',hclk=>'0', + hcs_n=>'0',hdataout_en_n=>open,hread_n=>'0',hready_n=>open,hwrite_n=>'0', + ignore_pkt=>'0',reset_n=>'0',rx_dv=>'0',rx_eof=>open,rx_er=>'0', + rx_error=>open,rx_fifo_error=>open,rx_fifo_full=>'0',rx_stat_en=>open, + rx_write=>open,rxmac_clk=>'0',rxmac_clk_en=>'0',tx_discfrm=>open, + tx_done=>open,tx_en=>open,tx_er=>open,tx_fifoavail=>'0',tx_fifoctrl=>'0', + tx_fifoempty=>'0',tx_fifoeof=>'0',tx_macread=>open,tx_sndpausreq=>'0', + tx_staten=>open,txmac_clk=>'0',txmac_clk_en=>'0'); + pcs_clkdiv0: component PCSCLKDIV port map (CLKI=>pcs_clkdiv0_CLKI_sig,RST=>pcs_clkdiv0_RST_sig, + SEL2=>n1,SEL1=>pwr,SEL0=>n1,CDIV1=>pcs_clkdiv0_CDIV1_sig,CDIVX=>pcs_clkdiv0_CDIVX_sig); + n1 <= '0' ; + pwr <= '1' ; + gnd <= '0' ; + +end architecture sgmii; -- sbp_module=true + diff --git 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+verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v" +verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v" +vhdl_file_list: "/home/soft/lattice/diamond/3.10_x64/cae_library/synthesis/vhdl/ecp5um.vhd" +vhdl_file_list: "../sgmii_channel_smi.vhd" +resource_sharing: false +write_verilog: false +write_vhdl: true +suffix_name: edi +output_file_name: sgmii_channel_smi +write_prf: false +vlog_std_v2001: true +disable_io_insertion: true +force_gsr: false +speed_grade: 8 +frequency: 125.000 +fanout_limit: 100 +retiming: false +pipe: false +fixgatedclocks: 0 +fixgeneratedclocks: 0 diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.fdc b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.fdc new file mode 100644 index 0000000..292bc0f --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU0_CH0} diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.lpc b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.lpc new file mode 100644 index 0000000..34c1f1a --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.lpc @@ -0,0 +1,37 @@ +[Device] +Family=sa5p00m +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=SGMII/Gb Ethernet PCS +CoreRevision=4.1 +CoreStatus=Demo +CoreType=IPCFG +Date=04/29/2019 +ModuleName=sgmii_channel_smi +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=14:09:14 +VendorName=Lattice Semiconductor Corporation +[Parameters] +CH_MODE=Rx and Tx +CORE_SYNP=1 +Channel=CH0 +DCUA=DCU0 +EasyConnect=1 +MAX_RATE=1.250 +NUM_CHS=1 +PROTOCOL=SGMII +REFCLK_RATE=125.0000 +RX_CTC=2 +RX_CTC_HIGH=32 +RX_CTC_LOW=16 +SBP=1 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************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`define SGMII_YES_SINGLE_CLOCK + + +module sgmii_channel_smi ( + +//-----------USERNAME CORE-------------PART PORTS + // Control Interface + rst_n, + gbe_mode, + sgmii_mode, + operational_rate, + debug_link_timer_short, + force_isolate, + force_loopback, + force_unidir, + + an_link_ok, + + // G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + tx_clock_enable_sink , + tx_clock_enable_source , + + rx_clock_enable_sink , + rx_clock_enable_source , + tx_clk_125, + rx_clk_125, +`else + tx_clk_mii , + rx_clk_mii , +`endif + tx_d, + tx_en, + tx_er, + + rx_d, + rx_dv, + rx_er, + col, + crs, + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability, + +//-----------USERNAME PCS-------------PART PORTS + hdoutp, + hdoutn, + hdinp, + hdinn, + + sli_rst, + serdes_rst_dual_c, + tx_serdes_rst_c, + serdes_pdb, + tx_pwrup_c, + + pll_refclki, + rxrefclk, + + sci_wrdata, + sci_addr, + sci_rddata, + sci_en_dual, + sci_sel_dual, + sci_en, + sci_sel, + sci_rd, + sci_wrn, + sci_int, + cyawstn, + rx_cdr_lol_s, + + tx_pcs_rst_c, + rx_pcs_rst_c, + rx_serdes_rst_c, + + rst_dual_c, + pll_lol, + +`ifndef SGMII_YES_SINGLE_CLOCK + clk_125, +`endif + + mr_power_down + ); + +//-----------USERNAME CORE-------------PART PORTS + +// Control Interface +input rst_n ; +input gbe_mode ; +input sgmii_mode ; +input [1:0] operational_rate ; +input debug_link_timer_short ; +input force_isolate ; +input force_loopback ; +input force_unidir ; + +output an_link_ok ; + +// G/MII Interface + +`ifdef SGMII_YES_SINGLE_CLOCK +input tx_clock_enable_sink; +output tx_clock_enable_source; + +input rx_clock_enable_sink; +output rx_clock_enable_source; + +input tx_clk_125; +input rx_clk_125; + +`else +input tx_clk_mii; +input rx_clk_mii; +`endif + +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + + +//-----------USERNAME PCS-------------PART PORTS +output hdoutp; +output hdoutn; +input hdinp; +input hdinn; + +input sli_rst; +output serdes_rst_dual_c; +output tx_serdes_rst_c; +output serdes_pdb; +output tx_pwrup_c; + +input pll_refclki; +input rxrefclk; + +input [7:0]sci_wrdata; +input [5:0]sci_addr; +output [7:0]sci_rddata; +input sci_en_dual; +input sci_sel_dual; +input sci_en; +input sci_sel; +input sci_rd; +input sci_wrn; +output sci_int; +input cyawstn; +output rx_cdr_lol_s; +input tx_pcs_rst_c; +input rx_pcs_rst_c; +input rx_serdes_rst_c; +input rst_dual_c; +output pll_lol; + + +`ifndef SGMII_YES_SINGLE_CLOCK +input clk_125; +`endif + + +input mr_power_down; + +wire link_status; +wire [7:0] data_chan2quad; +wire kcntl_chan2quad; +wire serdes_recovered_clk; +wire [7:0] data_quad2chan; +wire kcntl_quad2chan; +wire disp_err_quad2chan; +wire cv_err_quad2chan; +wire xmit_autoneg; +wire disparity_cntl_chan2quad; + +// SGMII core +sgmii_channel_smi_core u_sgmii_core ( + // Clock and Reset + .rst_n ( rst_n ) , + .signal_detect ( link_status ) , + .gbe_mode ( gbe_mode ) , + .sgmii_mode ( sgmii_mode ) , + .operational_rate ( operational_rate ) , + .debug_link_timer_short ( debug_link_timer_short ) , + .force_isolate ( force_isolate ) , + .force_loopback ( force_loopback ) , + .force_unidir ( force_unidir ) , + + .rx_compensation_err ( ) , + .ctc_drop_flag ( ) , + .ctc_add_flag ( ) , + .an_link_ok ( an_link_ok ) , + +`ifdef SGMII_YES_SINGLE_CLOCK + .tx_clock_enable_sink ( tx_clock_enable_sink ), + .tx_clock_enable_source ( tx_clock_enable_source ), + + .rx_clock_enable_sink ( rx_clock_enable_sink ), + .rx_clock_enable_source ( rx_clock_enable_source ), + .tx_clk_125 ( tx_clk_125 ) , + .rx_clk_125 ( rx_clk_125 ) , +`else + .tx_clk_mii ( tx_clk_mii ), + .rx_clk_mii ( rx_clk_mii ), + .tx_clk_125 ( clk_125 ) , + .rx_clk_125 ( clk_125 ) , +`endif + // GMII TX Inputs + + .tx_d ( tx_d) , + .tx_en ( tx_en) , + .tx_er ( tx_er) , + + // GMII RX Outputs + // To GMII/MAC interface + .rx_d ( rx_d ) , + .rx_dv ( rx_dv ) , + .rx_er ( rx_er ) , + .col ( col ) , + .crs ( crs ) , + + // 8BI TX Outputs + .tx_data ( data_chan2quad) , + .tx_kcntl ( kcntl_chan2quad) , + .tx_disparity_cntl ( disparity_cntl_chan2quad) , + .xmit_autoneg ( xmit_autoneg) , + + // 8BI RX Inputs + .serdes_recovered_clk ( serdes_recovered_clk ) , + .rx_data ( data_quad2chan ) , + .rx_kcntl ( kcntl_quad2chan ) , + .rx_even ( 1'b0 ) , + .rx_disp_err ( disp_err_quad2chan ) , + .rx_cv_err ( cv_err_quad2chan ) , + .rx_err_decode_mode ( 1'b0 ) , + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + +assign serdes_rst_dual_c = ~rst_n; +assign tx_serdes_rst_c = ~rst_n; +assign serdes_pdb = 1'b1; + +assign tx_pwrup_c = ~mr_power_down; + + +sgmii_channel_smi_pcs u_sgmii_pcs ( + +// Global Clocks and Resets + // inputs + .rst_dual_c(rst_dual_c), + .serdes_rst_dual_c(~rst_n), + .pll_refclki(pll_refclki), + .rxrefclk(rxrefclk), + .sli_rst(sli_rst), + +`ifdef SGMII_YES_SINGLE_CLOCK + .txi_clk(tx_clk_125), +`else + .txi_clk(clk_125), +`endif + +// fpga tx datapath signals + // inputs + .tx_pcs_rst_c(tx_pcs_rst_c), + .txdata(data_chan2quad), + .tx_k(kcntl_chan2quad), + .tx_disp_correct(disparity_cntl_chan2quad), + + // outputs + .tx_pclk(), + +// fpga rx datapath signals + // inputs + .rx_pcs_rst_c(rx_pcs_rst_c), + .xmit(xmit_autoneg), + .signal_detect_c(1'b1), + + // outputs + .rx_pclk(serdes_recovered_clk), + .rxdata(data_quad2chan), + .rx_k(kcntl_quad2chan), + .rx_disp_err(disp_err_quad2chan), + .rx_cv_err(cv_err_quad2chan), + .lsm_status_s(link_status), + .rx_cdr_lol_s(rx_cdr_lol_s), + +// serdes signals + // inputs + .rx_serdes_rst_c(rx_serdes_rst_c), + .tx_serdes_rst_c(~rst_n), + + .hdinp(hdinp), + .hdinn(hdinn), + + // outputs + .hdoutp(hdoutp), + .hdoutn(hdoutn), + + //SCI interface + + .cyawstn(cyawstn), + .sci_en(sci_en), + .sci_en_dual(sci_en_dual), + .sci_sel_dual(sci_sel_dual), + .sci_sel(sci_sel), + .sci_wrdata(sci_wrdata), + .sci_addr(sci_addr), + .sci_rddata(sci_rddata), + .sci_rd(sci_rd), + .sci_wrn(sci_wrn), + .sci_int(sci_int), + +// misc control signals + // inputs + .rsl_disable (1'b0), + .rsl_rst (~rst_n), + .tx_pwrup_c(~mr_power_down), // powerup tx channel + .rx_pwrup_c(~mr_power_down), // power up rx channel + .serdes_pdb(1'b1), + + // outputs + .pll_lol(pll_lol) +); + + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.vhd b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.vhd new file mode 100644 index 0000000..a50792f --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.vhd @@ -0,0 +1,359 @@ +--************************************************************************** +-- ************************************************************************* +-- * LATTICE SEMICONDUCTOR CONFIDENTIAL * +-- * PROPRIETARY NOTE * +-- * * +-- * This software contains information confidential and proprietary * +-- * to Lattice Semiconductor Corporation. It shall not be reproduced * +-- * in whole or in part, or transferred to other documents, or disclosed * +-- * to third parties, or used for any purpose other than that for which * +-- * it was obtained, without the prior written consent of Lattice * +-- * Semiconductor Corporation. All rights reserved. * +-- * * +-- ************************************************************************* +--************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity sgmii_channel_smi is port ( + rst_n : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + --rx_compensation_err : out std_logic; + --ctc_drop_flag : out std_logic; + --ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + tx_clk_125 : in std_logic; + rx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0); + + hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + + sli_rst : in std_logic; + serdes_rst_dual_c : out std_logic; + tx_serdes_rst_c : out std_logic; + serdes_pdb : out std_logic; + tx_pwrup_c : out std_logic; + + pll_refclki : in std_logic; + rxrefclk : in std_logic; + + sci_wrdata : in std_logic_vector(7 downto 0); + sci_addr : in std_logic_vector(5 downto 0); + sci_rddata : out std_logic_vector(7 downto 0); + sci_en_dual : in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + + rx_cdr_lol_s: out std_logic; + + tx_pcs_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rx_serdes_rst_c: in std_logic; + + rst_dual_c: in std_logic; + pll_lol: out std_logic; + + + mr_power_down: in std_logic + ); +end entity; + +architecture arch of sgmii_channel_smi is +component sgmii_channel_smi_core port ( + rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + rx_compensation_err : out std_logic; + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + + tx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + xmit_autoneg : out std_logic; + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + +component sgmii_channel_smi_pcs port ( + hdoutp : out std_logic; + hdoutn : out std_logic; + hdinp : in std_logic; + hdinn : in std_logic; + rxrefclk : in std_logic; + txi_clk : in std_logic; + sli_rst : in std_logic; + rx_pclk : out std_logic; + tx_pclk : out std_logic; + txdata : in std_logic_vector(7 downto 0); + tx_k : in std_logic_vector(0 downto 0); + xmit : in std_logic_vector(0 downto 0); + tx_disp_correct : in std_logic_vector(0 downto 0); + rxdata : out std_logic_vector(7 downto 0); + rx_k : out std_logic_vector(0 downto 0); + rx_disp_err : out std_logic_vector(0 downto 0); + rx_cv_err : out std_logic_vector(0 downto 0); + sci_wrdata : in std_logic_vector(7 downto 0); + signal_detect_c : in std_logic; + sci_addr : in std_logic_vector(5 downto 0); + sci_rddata : out std_logic_vector(7 downto 0); + sci_en_dual : in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + lsm_status_s : out std_logic; + rx_cdr_lol_s : out std_logic; + tx_pcs_rst_c : in std_logic; + rx_pcs_rst_c : in std_logic; + rx_serdes_rst_c : in std_logic; + rsl_disable : in std_logic; + rsl_rst : in std_logic; + tx_pwrup_c : in std_logic; + rx_pwrup_c : in std_logic; + rst_dual_c : in std_logic; + serdes_rst_dual_c : in std_logic; + serdes_pdb : in std_logic; + tx_serdes_rst_c : in std_logic; + pll_refclki : in std_logic; + pll_lol : out std_logic + ); +end component; + +-- 8-bit Interface Signals from SGMII channel to QuadPCS/SERDES +signal data_chan2quad : std_logic_vector(7 downto 0); +signal kcntl_chan2quad : std_logic_vector(0 downto 0); +signal disparity_cntl_chan2quad: std_logic_vector(0 downto 0); + +-- 8-bit Interface Signals from QuadPCS/SERDES to SGMII channel +signal data_quad2chan : std_logic_vector(7 downto 0); +signal kcntl_quad2chan : std_logic_vector(0 downto 0); +signal disp_err_quad2chan : std_logic_vector(0 downto 0); +signal cv_err_quad2chan : std_logic_vector(0 downto 0); +signal link_status : std_logic; +signal serdes_recovered_clk : std_logic; +signal xmit_autoneg : std_logic_vector(0 downto 0); +signal reset : std_logic; +signal mr_power_down_inv : std_logic; + +begin + +reset <= not rst_n; +mr_power_down_inv <= not(mr_power_down); +-- Instantiate SGMII IP Core +u_sgmii_core : sgmii_channel_smi_core port map( + -- Clock and Reset + rst_n => rst_n , + signal_detect => link_status , + gbe_mode => gbe_mode , + sgmii_mode => sgmii_mode , + operational_rate => operational_rate , + debug_link_timer_short => debug_link_timer_short , + force_isolate => force_isolate , + force_loopback => force_loopback , + force_unidir => force_unidir , + + rx_compensation_err => open , + ctc_drop_flag => open , + ctc_add_flag => open , + an_link_ok => an_link_ok , + + tx_clock_enable_sink => tx_clock_enable_sink , + tx_clock_enable_source => tx_clock_enable_source , + + rx_clock_enable_sink => rx_clock_enable_sink , + rx_clock_enable_source => rx_clock_enable_source , + tx_clk_125 => tx_clk_125 , + rx_clk_125 => rx_clk_125 , + -- GMII TX Inputs + tx_d => tx_d, + tx_en => tx_en, + tx_er => tx_er, + -- GMII RX Outputs + -- To GMII/MAC interface + rx_d => rx_d , + rx_dv => rx_dv , + rx_er => rx_er , + col => col , + crs => crs , + + -- 8BI TX Outputs + tx_data => data_chan2quad, + tx_kcntl => kcntl_chan2quad(0), + tx_disparity_cntl => disparity_cntl_chan2quad(0), + xmit_autoneg => xmit_autoneg(0), + + -- 8BI RX Inputs + serdes_recovered_clk => serdes_recovered_clk , + rx_data => data_quad2chan , + rx_kcntl => kcntl_quad2chan(0) , + rx_even => '0' , + rx_disp_err => disp_err_quad2chan(0) , + rx_cv_err => cv_err_quad2chan(0) , + rx_err_decode_mode => '0' , + + -- Management Interface I/O + mr_adv_ability => mr_adv_ability, + mr_an_enable => mr_an_enable, + mr_main_reset => mr_main_reset, + mr_restart_an => mr_restart_an, + + mr_an_complete => mr_an_complete, + mr_lp_adv_ability => mr_lp_adv_ability, + mr_page_rx => mr_page_rx + ); + + + serdes_rst_dual_c <= reset; + tx_serdes_rst_c <= reset; + serdes_pdb <= '1'; + tx_pwrup_c <= mr_power_down_inv; + +u_sgmii_pcs : sgmii_channel_smi_pcs port map( +-- Global Clocks and Resets + -- inputs + rst_dual_c => rst_dual_c, + serdes_rst_dual_c => reset, + pll_refclki => pll_refclki, + rxrefclk => rxrefclk, + + txi_clk => tx_clk_125, + + sli_rst => sli_rst, + +-- fpga tx datapath signals + -- inputs + tx_pcs_rst_c => tx_pcs_rst_c, + txdata => data_chan2quad, + tx_k => kcntl_chan2quad, + tx_disp_correct => disparity_cntl_chan2quad, + + -- outputs + tx_pclk => open , + +-- fpga rx datapath signals + -- inputs + rx_pcs_rst_c => rx_pcs_rst_c, + xmit => xmit_autoneg, + + -- outputs + rx_pclk => serdes_recovered_clk, + rxdata => data_quad2chan, + rx_k => kcntl_quad2chan, + rx_disp_err => disp_err_quad2chan, + rx_cv_err => cv_err_quad2chan, + lsm_status_s => link_status, + rx_cdr_lol_s => rx_cdr_lol_s, + +-- serdes signals + -- inputs + rx_serdes_rst_c => rx_serdes_rst_c, + tx_serdes_rst_c => reset, + + hdinp => hdinp, + hdinn => hdinn, + + -- outputs + hdoutp => hdoutp, + hdoutn => hdoutn, + signal_detect_c => '1', + + cyawstn => cyawstn, + sci_en => sci_en, + sci_en_dual => sci_en_dual, + sci_sel_dual => sci_sel_dual, + sci_sel => sci_sel, + sci_wrdata => sci_wrdata, + sci_addr => sci_addr, + sci_rddata => sci_rddata, + sci_rd => sci_rd, + sci_wrn => sci_wrn, + sci_int => sci_int, + +-- misc control signals + -- inputs + rsl_disable => '0', + rsl_rst => reset, + tx_pwrup_c => mr_power_down_inv, -- powerup tx channel + rx_pwrup_c => mr_power_down_inv, -- power up rx channel + serdes_pdb => '1', + + -- outputs + pll_lol => pll_lol +); + +end architecture; + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_bb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_bb.v new file mode 100644 index 0000000..0ab55f4 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_bb.v @@ -0,0 +1,156 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`define SGMII_YES_SINGLE_CLOCK + + +module sgmii_channel_smi ( + +//-----------USERNAME CORE-------------PART PORTS + // Control Interface + rst_n, + gbe_mode, + sgmii_mode, + operational_rate, + debug_link_timer_short, + force_isolate, + force_loopback, + force_unidir, + + an_link_ok, + + // G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + tx_clock_enable_sink , + tx_clock_enable_source , + + rx_clock_enable_sink , + rx_clock_enable_source , + tx_clk_125, + rx_clk_125, +`else + tx_clk_mii , + rx_clk_mii , +`endif + tx_d, + tx_en, + tx_er, + + rx_d, + rx_dv, + rx_er, + col, + crs, + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability, + +//-----------USERNAME PCS-------------PART PORTS + hdoutp, + hdoutn, + hdinp, + hdinn, + + rx_cdr_lol_s, + + tx_pcs_rst_c, + rx_pcs_rst_c, + rx_serdes_rst_c, + + rst_dual_c, + pll_lol, + refclk2fpga, + mr_power_down + + ); + +//-----------USERNAME CORE-------------PART PORTS + +// Control Interface +input rst_n ; +input gbe_mode ; +input sgmii_mode ; +input [1:0] operational_rate ; +input debug_link_timer_short ; +input force_isolate ; +input force_loopback ; +input force_unidir ; + +output an_link_ok ; + +// G/MII Interface + +`ifdef SGMII_YES_SINGLE_CLOCK +input tx_clock_enable_sink; +output tx_clock_enable_source; + +input rx_clock_enable_sink; +output rx_clock_enable_source; + +input tx_clk_125; +input rx_clk_125; + +`else +input tx_clk_mii; +input rx_clk_mii; +`endif + +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + + +//-----------USERNAME PCS-------------PART PORTS +output hdoutp; +output hdoutn; +input hdinp; +input hdinn; +output rx_cdr_lol_s; +input tx_pcs_rst_c; +input rx_pcs_rst_c; +input rx_serdes_rst_c; +input rst_dual_c; +output pll_lol; + +// new added +input refclk2fpga; // new added +input mr_power_down; // new added + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_beh.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_beh.v new file mode 100644 index 0000000..68df57b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_beh.v @@ -0,0 +1,3984 @@ +// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1 +// created on Wed Mar 19 15:39:54 CST 2014 +// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved +// obfuscator_exe version 1.mar0807 +// top +`define SGMII_NO_ENC +`define SGMII_YES_CTC_DYNAMIC +`define SGMII_FIFO_FAMILY_ECP5 +`define SGMII_YES_SINGLE_CLOCK +`timescale 1 ns / 100 ps +module gd2938d (ui49c6d, of4e369, th71b4d, ym8da6f, su6d379, ne69bc9, + vi4de4a, wj6f253, ps7929c, uvc94e2, ld4a714, su538a7, ba9c539, + ale29cb); +input wire [17:0] ui49c6d; +input wire of4e369; +input wire th71b4d; +input wire ym8da6f; +input wire su6d379; +input wire ne69bc9; +input wire vi4de4a; +input wire [9:0] wj6f253; +input wire [9:0] ps7929c; +output wire [17:0] uvc94e2; +output wire ld4a714; +output wire su538a7; +output wire ba9c539; +output wire ale29cb; +wire eaffb08; +wire kdfd840; +wire ldec205; +wire ld6102f; +wire gd817f; +wire dz40bfc; +wire co5fe7; +wire vk2ff39; +wire mr7f9cb; +wire xjfce5c; +wire kde72e7; +wire ux3973c; +wire gocb9e4; +wire ay5cf20; +wire ofe7900; +wire ep3c805; +wire nee402d; +wire vk2016b; +wire gqb5b; +wire aa5ad9; +wire hd2d6c9; +wire fn6b64f; +wire kd5b27e; +wire qtd93f4; +wire qtc9fa5; +wire jp4fd2d; +wire bl7e96e; +wire lqf4b76; +wire pha5bb3; +wire jr2dd9e; +wire rt6ecf6; +wire fa767b7; +wire qib3dbb; +wire zz9edd8; +wire ldf6ec7; +wire jeb763e; +wire yzbb1f3; +wire thd8f9d; +wire ldc7cee; +wire ks3e776; +wire ldf3bb1; +wire ie9dd8e; +wire zkeec70; +wire rg76383; +wire kfb1c1b; +wire hd8e0dd; +wire of706ef; +wire hq8377c; +wire je1bbe3; +wire nrddf1b; +wire meef8de; +wire rg7c6f1; +wire lde378a; +wire ba1bc56; +wire ykde2b3; +wire xwf1598; +wire cb8acc2; +wire ui56614; +wire mgb30a0; +wire uk98501; +wire xjc2809; +wire do1404e; +wire nta0273; +wire vk139f; +wire ph9cfa; +wire al4e7d7; +wire jc73ebd; +wire ux9f5ea; +wire qgfaf54; +wire dzd7aa0; +wire lsbd507; +wire meea83a; +wire sh541d1; +wire dba0e8d; +wire qv746e; +wire do3a375; +wire ead1bab; +wire ou8dd58; +wire th6eac1; +wire wj7560f; +wire uxab07c; +wire zk583e4; +wire icc1f23; +wire qif919; +wire dm7c8c8; +wire fae4643; +wire kf2321b; +wire vx190dc; +wire fnc86e7; +wire su4373e; +wire tw1b9f1; +wire ofdcf8b; +wire wje7c5c; +wire ou3e2e5; +wire psf1729; +wire rv8b94a; +wire kq5ca56; +wire ose52b0; +wire ep29581; +wire hb4ac0d; +wire ic5606e; +wire xlb0370; +wire db81b86; +wire epdc37; +wire rt6e1bd; +wire cz70dee; +wire tw86f75; +wire zz37baa; +wire ribdd56; +wire neeeab3; +wire al7559b; +wire bnaacdc; +wire go566e7; +wire ecb3738; +wire lf9b9c1; +wire czdce0f; +wire ene707c; +wire zz383e4; +wire uic1f26; +wire ief931; +wire rg7c988; +wire nee4c43; +wire sj2621a; +wire ec310d4; +wire ec886a0; +wire kq43500; +wire gq1a801; +wire med4009; +wire hda0049; +wire ym24f; +wire ls1278; +wire nt93c2; +wire ea49e16; +wire rt4f0b1; +wire os7858f; +wire nrc2c78; +wire db163c6; +wire irb1e36; +wire qv8f1b5; +wire go78dad; +wire enc6d69; +wire ir36b4c; +wire ntb5a64; +wire doad327; +wire xw6993b; +wire ww4c9da; +wire fn64ed1; +wire hd2768e; +wire uk3b476; +wire lqda3b1; +wire wwd1d8a; +wire fp8ec50; +wire tu76286; +wire anb1433; +wire an8a19c; +wire ld50ce5; +wire tw8672e; +wire cb33973; +wire pu9cb9c; +wire cme5ce2; +wire gq2e710; +wire rg73880; +wire fc9c402; +wire gbe2013; +wire mg1009c; +wire gd804e1; +wire yz270c; +wire rv13865; +wire tw9c32f; +wire nee197b; +wire tjcbda; +wire gb65ed7; +wire ng2f6bc; +wire xj7b5e2; +wire jcdaf17; +wire nrd78bb; +wire mgbc5df; +wire wje2ef8; +wire qv177c5; +wire irbbe2c; +wire psdf164; +wire enf8b22; +wire nec5915; +wire gd2c8ab; +wire th6455c; +wire tj22ae7; +wire qi1573f; +wire mtab9f9; +wire qg5cfcd; +wire mre7e68; +wire ng3f345; +wire jpf9a2b; +wire dzcd15f; +wire cm68afe; +wire nr457f0; +wire aa2bf86; +wire bl5fc31; +wire zkfe18f; +wire ykf0c7b; +wire ng863d9; +wire ec31ecb; +wire kf8f659; +wire nr7b2cd; +wire ipd966f; +wire cmcb37d; +wire yk59be9; +wire zxcdf48; +wire cz6fa47; +wire os7d23d; +wire nre91e8; +wire zk48f47; +wire by47a3b; +wire lf3d1da; +wire ofe8ed6; +wire dm476b4; +wire co3b5a3; +wire xwdad19; +wire uvd68cb; +wire sjb465d; +wire mga32ec; +wire lf19760; +wire aycbb07; +wire fa5d838; +wire dzec1c2; +wire yx60e17; +wire cb70bc; +wire xl385e5; +wire hbc2f2e; +wire gd17976; +wire iebcbb5; +wire sue5da9; +wire ec2ed48; +wire fa76a41; +wire phb520a; +wire oua9056; +wire ho482b1; +wire kd4158a; +wire coac54; +wire ui562a0; +wire ohb1500; +wire ir8a804; +wire sh54024; +wire dba0125; +wire sw92f; +wire tw4979; +wire aa24bcb; +wire ri25e58; +wire xy2f2c2; +wire xw79612; +wire eacb092; +wire ps58491; +wire jpc248b; +wire an1245f; +wire ie922fc; +wire xl917e0; +wire rv8bf07; +wire nr5f83e; +wire thfc1f7; +wire yke0fbe; +wire cb7df0; +wire qi3ef84; +wire czf7c20; +wire qvbe104; +wire eaf0825; +wire lf84129; +wire ls2094e; +wire ba4a72; +wire ng25393; +wire wl29c9b; +wire qt4e4dc; +wire go726e5; +wire zm93729; +wire db9b94a; +wire qtdca57; +wire kqe52bc; +wire yz295e1; +wire ld4af0d; +wire ps5786e; +wire cobc373; +wire tue1b98; +wire ohdcc2; +wire th6e615; +wire rg730ae; +wire ie98573; +wire fnc2b99; +wire ou15cce; +wire sjae670; +wire jc73384; +wire xy99c23; +wire osce11a; +wire sh708d1; +wire tj8468d; +wire yz2346e; +wire aa1a374; +wire med1ba0; +wire aa8dd00; +wire ld6e801; +wire ld7400f; +wire lfa007e; +wire ec3f7; +reg [17 : 0] hq1fb8; +reg iefdc3; +reg th7ee18; +reg alf70c6; +reg dob8635; +reg czc31aa; +reg wl18d55; +reg [9 : 0] ipc6aac; +reg [9 : 0] ng35564; +reg bnaab22; +reg jp55917; +reg coac8be; +reg nr645f0; +reg xl22f87; +reg yz17c3f; +reg yzbe1fd; +reg qgf0fed; +reg aa87f69; +reg ba3fb48; +reg mrfda42; +reg aled215; +reg zk690ad; +reg rg4856b; +reg lq42b5a; +reg ks15ad2; +reg lsad690; +reg ld6b483; +reg hb5a41e; +reg thd20f6; +reg gd907b6; +reg je83db5; +reg vk1edaa; +reg fnf6d53; +reg mgb6a9e; +reg tjb54f0; +reg xlaa786; +reg ww53c36; +reg jr9e1b1; +reg gof0d8e; +reg zm86c71; +reg ux3638a; +reg irb1c55; +reg rv8e2ad; +reg rt7156f; +reg gd8ab7e; +reg dz55bf4; +reg hqadfa6; +reg al6fd32; +reg bl7e995; +reg lqf4cae; +reg mga6573; +reg lf32b98; +reg kf95cc6; +reg mtae634; +reg ne731a4; +reg co98d23; +reg enc6918; +reg gq348c4; +reg ana4621; +reg wl2310d; +reg mt1886c; +reg eac4364; +reg gq21b20; +reg ohd900; +reg rg6c805; +reg dz6402a; +reg tw20157; +reg qiabb; +reg co55d9; +reg ri2aec8; +reg fa57643; +reg yzbb21a; +reg shd90d5; +reg hbc86ad; +reg ic4356e; +reg qi1ab71; +reg psd5b89; +reg zmadc4a; +reg pf6e252; +reg nr71296; +reg zm894b6; +reg zx4a5b2; +reg by52d97; +reg vk96cbb; +reg ymb65db; +reg ngb2ed9; +reg ym976ca; +reg uxbb650; +reg kqdb285; +reg qtd9428; +reg psca145; +reg bl50a2b; +reg sj8515e; +reg rv28af4; +reg dz457a6; +reg ym2bd36; +reg kd5e9b1; +reg tuf4d8d; +reg yma6c6b; +reg gd36359; +reg anb1acd; +reg co8d66d; +reg xj6b368; +reg ww59b46; +reg jpcda30; +reg cm6d187; +reg os68c39; +reg cm461c8; +reg vk30e41; +reg ou8720b; +reg oh39059; +reg nrc82cc; +reg gb41666; +reg xyb334; +reg kq599a3; +reg qtccd18; +reg ho668c5; +reg ym3462b; +reg iea3158; +reg ep18ac0; +reg tuc5604; +reg wy2b022; +reg ps58110; +reg hoc0883; +reg je441b; +reg xl220da; +reg sw106d6; +reg ba836b1; +reg ng1b58b; +reg nedac5a; +reg shd62d3; +reg yzb169c; +reg lf8b4e4; +reg vv5a727; +reg ald393e; +reg ng9c9f5; +reg nee4faa; +reg tj27d52; +reg qi3ea97; +reg ayf54b8; +reg bnaa5c0; +reg dm52e06; +reg ks97033; +reg lsb8198; +reg nec0cc2; +reg hd6613; +reg kf3309f; +reg ec984fd; +reg zxc27e9; +reg zz13f4f; +reg gd9fa7f; +reg offd3fd; +reg nre9fec; +reg xj4ff66; +reg ip7fb36; +reg qtfd9b4; +reg hbecda5; +reg zk66d2e; +reg oh36973; +reg irb4b9c; +reg rva5ce5; +reg wy2e72e; +reg ps73970; +reg pu9cb82; +reg cme5c12; +reg gq2e090; +reg sh70480; +reg mg82404; +reg yz12021; +reg ux9010c; +reg sj80865; +reg tw432d; +reg wy2196a; +reg ntcb50; +reg kd65a87; +reg vx2d43c; +reg mr6a1e7; +reg pf50f3c; +reg ym879e6; +reg mt3cf30; +reg ale7985; +reg wl3cc2d; +reg dze616d; +reg pu30b6e; +reg ux85b73; +reg lf2db9d; +reg ea6dcee; +reg dz6e770; +reg tu73b86; +reg uk9dc32; +reg rgee190; +reg cz70c82; +reg tw86415; +reg db320ab; +reg cb9055f; +reg co82afd; +reg qi157e8; +reg mtabf41; +reg th5fa0d; +reg offd06f; +reg mre837c; +reg sh41be5; +reg uxdf2d; +reg of6f96d; +reg ho7cb6d; +reg kqe5b6b; +reg vx2db58; +reg go6dac6; +reg qg6d630; +reg zx6b181; +reg ne58c0e; +reg ofc6072; +reg ng30395; +reg bn81caa; +reg nge557; +reg ic72abb; +reg mt955d8; +reg hdaaec5; +reg dm5762f; +reg irbb17a; +reg vvd8bd5; +reg zkc5eae; +reg xy2f573; +reg yx7ab9a; +reg ned5cd4; +reg kfae6a2; +reg xw73514; +reg gd9a8a3; +reg med451d; +reg fca28e9; +reg je1474b; +reg gqa3a5b; +reg sj1d2d9; +reg hbe96cd; +reg en4b66f; +reg qt5b37d; +reg mrd9bec; +reg hbcdf64; +reg of6fb27; +reg go7d93d; +reg fnec9e9; +reg ld64f4e; +reg db27a76; +reg vx3d3b7; +reg rte9dbe; +reg cz4edf6; +reg vi76fb4; +reg lsb7da2; +reg kfbed12; +reg hbf6894; +reg epb44a6; +reg fca2534; +reg gd129a2; +reg lf94d15; +reg swa68ae; +reg ie34571; +reg lsa2b88; +reg ec15c43; +reg qvae218; +reg vv710c4; +reg ks88626; +reg go43130; +reg cb18981; +reg cmc4c0c; +reg wl26061; +reg ls3030c; +reg lf81862; +reg rvc317; +reg nr618be; +reg tjc5f6; +reg ay62fb6; +reg wl17db1; +reg irbed8d; +reg rtf6c6c; +reg ecb6366; +reg kfb1b31; +reg ec8d98d; +reg ps6cc69; +reg lq6634a; +reg aa31a52; +reg co8d291; +reg vi69488; +reg nr4a443; +reg jc5221f; +reg fp910fa; +reg aa887d7; +reg ea43eb8; +reg gq1f5c0; +reg icfae00; +reg rtd7000; +reg pub8006; +reg tuc0032; +reg wy192; +reg ukc90; +reg lf6481; +reg rv3240f; +reg ie9207f; +reg wl903f8; +reg jr81fc5; +reg ymfe2f; +reg qt7f178; +reg gbf8bc5; +reg dmc5e2d; +reg do2f16b; +reg su78b5a; +reg vic5ad1; +reg tj2d68b; +reg xj6b45f; +reg zx5a2fe; +reg [2047:0] ead17f6; +wire [308:0] vx8bfb1; +localparam th5fd8e = 309,nefec77 = 32'hfdffc68b; +localparam [31:0] fnf63ba = nefec77; +localparam tj8eebd = nefec77 & 4'hf; +localparam [11:0] fpbaf71 = 'h7ff; +wire [(1 << tj8eebd) -1:0] jebdc77; +reg [th5fd8e-1:0] fn71dda; +reg [tj8eebd-1:0] ay776be [0:1]; +reg [tj8eebd-1:0] nedaf8d; +reg thd7c6b; +integer kfbe35f; +integer jcf1afd; +AND2 wy8d7eb (.A(ym8da6f), .B(eaffb08), .Z(cobc373)); INV vieb1fc (.A(zz383e4), .Z(eaffb08)); AND2 xy3f896 (.A(su6d379), .B(kdfd840), .Z(thfc1f7)); INV tw965a5 (.A(ene707c), .Z(kdfd840)); OR2 ohb4a93 (.A(ne69bc9), .B(vi4de4a), .Z(uic1f26)); XOR2 ng93bd2 (.A(sue5da9), .B(ec2ed48), .Z(vk2ff39)); XOR2 zxd2605 (.A(ec2ed48), .B(ho482b1), .Z(mr7f9cb)); XOR2 uk5c8b (.A(ho482b1), .B(kd4158a), .Z(xjfce5c)); XOR2 xl8b20f (.A(kd4158a), .B(ir8a804), .Z(kde72e7)); XOR2 swfe75 (.A(ir8a804), .B(sh54024), .Z(ux3973c)); XOR2 cz75178 (.A(sh54024), .B(aa24bcb), .Z(gocb9e4)); XOR2 ic788ba (.A(aa24bcb), .B(ri25e58), .Z(ay5cf20)); XOR2 bnba23c (.A(ri25e58), .B(ps58491), .Z(ofe7900)); XOR2 cb3ce4a (.A(ps58491), .B(jpc248b), .Z(ep3c805)); XOR2 ld4ab24 (.A(jpc248b), .B(irb1e36), .Z(nee402d)); XOR2 ec24d86 (.A(ec31ecb), .B(kf8f659), .Z(pha5bb3)); XOR2 ls8616f (.A(kf8f659), .B(yk59be9), .Z(jr2dd9e)); XOR2 gb6f6ee (.A(yk59be9), .B(zxcdf48), .Z(rt6ecf6)); XOR2 hoee9ce (.A(zxcdf48), .B(zk48f47), .Z(fa767b7)); XOR2 qgce7d5 (.A(zk48f47), .B(by47a3b), .Z(qib3dbb)); XOR2 rgd52a0 (.A(by47a3b), .B(co3b5a3), .Z(zz9edd8)); XOR2 jra0675 (.A(co3b5a3), .B(xwdad19), .Z(ldf6ec7)); XOR2 yx75ff0 (.A(xwdad19), .B(lf19760), .Z(jeb763e)); XOR2 osf0be3 (.A(lf19760), .B(aycbb07), .Z(yzbb1f3)); XOR2 nre335a (.A(aycbb07), .B(tw8672e), .Z(thd8f9d)); defparam dz5adb6.initval = 16'h6996 ; ROM16X1A dz5adb6 (.AD3(fae4643), .AD2(vx190dc), .AD1(su4373e), .AD0(ofdcf8b), .DO0(dm476b4)); defparam ale8012.initval = 16'h6996 ; ROM16X1A ale8012 (.AD3(ou8dd58), .AD2(wj7560f), .AD1(zk583e4), .AD0(qif919), .DO0(ld6102f)); defparam cz70b64.initval = 16'h6996 ; ROM16X1A cz70b64 (.AD3(su4373e), .AD2(ofdcf8b), .AD1(ld6e801), .AD0(ld6e801), .DO0(mga32ec)); defparam fn6e596.initval = 16'h6996 ; ROM16X1A fn6e596 (.AD3(vx190dc), .AD2(su4373e), .AD1(ofdcf8b), .AD0(ld6e801), .DO0(sjb465d)); defparam ou824ce.initval = 16'h6996 ; ROM16X1A ou824ce (.AD3(qif919), .AD2(fae4643), .AD1(vx190dc), .AD0(mga32ec), .DO0(ofe8ed6)); defparam os6247a.initval = 16'h6996 ; ROM16X1A os6247a (.AD3(zk583e4), .AD2(qif919), .AD1(fae4643), .AD0(sjb465d), .DO0(nre91e8)); defparam oh26b57.initval = 16'h6996 ; ROM16X1A oh26b57 (.AD3(wj7560f), .AD2(zk583e4), .AD1(qif919), .AD0(dm476b4), .DO0(os7d23d)); defparam kd5bad2.initval = 16'h6996 ; ROM16X1A kd5bad2 (.AD3(dm476b4), .AD2(ld6102f), .AD1(ld6e801), .AD0(ld6e801), .DO0(cmcb37d)); defparam kd7ade6.initval = 16'h6996 ; ROM16X1A kd7ade6 (.AD3(dm476b4), .AD2(ld6102f), .AD1(do3a375), .AD0(ld6e801), .DO0(ipd966f)); defparam ng2a3cf.initval = 16'h6996 ; ROM16X1A ng2a3cf (.AD3(dm476b4), .AD2(ld6102f), .AD1(dba0e8d), .AD0(do3a375), .DO0(ng863d9)); defparam pha56e0.initval = 16'h6996 ; ROM16X1A pha56e0 (.AD3(meea83a), .AD2(dba0e8d), .AD1(do3a375), .AD0(ld6e801), .DO0(ldec205)); defparam xwc5a2f.initval = 16'h6996 ; ROM16X1A xwc5a2f (.AD3(dm476b4), .AD2(ld6102f), .AD1(ldec205), .AD0(ld6e801), .DO0(ykf0c7b)); defparam mrf8eb2.initval = 16'h6996 ; ROM16X1A mrf8eb2 (.AD3(zz37baa), .AD2(neeeab3), .AD1(bnaacdc), .AD0(ecb3738), .DO0(tw4979)); defparam qt7a8a6.initval = 16'h6996 ; ROM16X1A qt7a8a6 (.AD3(hb4ac0d), .AD2(xlb0370), .AD1(epdc37), .AD0(cz70dee), .DO0(dz40bfc)); defparam xyb445.initval = 16'h6996 ; ROM16X1A xyb445 (.AD3(bnaacdc), .AD2(ecb3738), .AD1(ld6e801), .AD0(ld6e801), .DO0(eacb092)); defparam hof138c.initval = 16'h6996 ; ROM16X1A hof138c (.AD3(neeeab3), .AD2(bnaacdc), .AD1(ecb3738), .AD0(ld6e801), .DO0(xw79612)); defparam qi9de87.initval = 16'h6996 ; ROM16X1A qi9de87 (.AD3(cz70dee), .AD2(zz37baa), .AD1(neeeab3), .AD0(eacb092), .DO0(sw92f)); defparam aa5473.initval = 16'h6996 ; ROM16X1A aa5473 (.AD3(epdc37), .AD2(cz70dee), .AD1(zz37baa), .AD0(xw79612), .DO0(ohb1500)); defparam fc14ece.initval = 16'h6996 ; ROM16X1A fc14ece (.AD3(xlb0370), .AD2(epdc37), .AD1(cz70dee), .AD0(tw4979), .DO0(ui562a0)); defparam xl91848.initval = 16'h6996 ; ROM16X1A xl91848 (.AD3(tw4979), .AD2(dz40bfc), .AD1(ld6e801), .AD0(ld6e801), .DO0(oua9056)); defparam wy97cce.initval = 16'h6996 ; ROM16X1A wy97cce (.AD3(tw4979), .AD2(dz40bfc), .AD1(ose52b0), .AD0(ld6e801), .DO0(phb520a)); defparam mr6f479.initval = 16'h6996 ; ROM16X1A mr6f479 (.AD3(tw4979), .AD2(dz40bfc), .AD1(rv8b94a), .AD0(ose52b0), .DO0(iebcbb5)); defparam ph28aed.initval = 16'h6996 ; ROM16X1A ph28aed (.AD3(ou3e2e5), .AD2(rv8b94a), .AD1(ose52b0), .AD0(ld6e801), .DO0(gd817f)); defparam qvb153b.initval = 16'h6996 ; ROM16X1A qvb153b (.AD3(tw4979), .AD2(dz40bfc), .AD1(gd817f), .AD0(ld6e801), .DO0(gd17976)); XOR2 ie24422 (.A(irb1e36), .B(ecb3738), .Z(xj7b5e2)); XOR2 db22386 (.A(ofdcf8b), .B(tw8672e), .Z(cm68afe)); defparam ri86cbd.initval = 16'h0410 ; ROM16X1A ri86cbd (.AD3(je1bbe3), .AD2(tw8672e), .AD1(ofdcf8b), .AD0(ld6e801), .DO0(yx60e17)); defparam jraa28f.initval = 16'h1004 ; ROM16X1A jraa28f (.AD3(je1bbe3), .AD2(tw8672e), .AD1(ofdcf8b), .AD0(ld6e801), .DO0(dzec1c2)); defparam zmad931.initval = 16'h0140 ; ROM16X1A zmad931 (.AD3(lqf4b76), .AD2(irb1e36), .AD1(ecb3738), .AD0(ld6e801), .DO0(xl917e0)); defparam do9682b.initval = 16'h4001 ; ROM16X1A do9682b (.AD3(lqf4b76), .AD2(irb1e36), .AD1(ecb3738), .AD0(ld6e801), .DO0(ie922fc)); INV the602c (.A(db9b94a), .Z(co5fe7)); AND2 ec5995 (.A(czdce0f), .B(co5fe7), .Z(kqe52bc)); AND2 wl95316 (.A(czdce0f), .B(db9b94a), .Z(yz295e1)); defparam nt16a01.INIT_DATA = "STATIC" ; defparam nt16a01.ASYNC_RESET_RELEASE = "SYNC" ; defparam nt16a01.CSDECODE_B = "0b000" ; defparam nt16a01.CSDECODE_A = "0b000" ; defparam nt16a01.WRITEMODE_B = "NORMAL" ; defparam nt16a01.WRITEMODE_A = "NORMAL" ; defparam nt16a01.GSR = "ENABLED" ; defparam nt16a01.RESETMODE = "ASYNC" ; defparam nt16a01.REGMODE_B = "NOREG" ; defparam nt16a01.REGMODE_A = "NOREG" ; defparam nt16a01.DATA_WIDTH_B = 18 ; defparam nt16a01.DATA_WIDTH_A = 18 ; DP16KD nt16a01 (.DIA17(ui49c6d[17]), .DIA16(ui49c6d[16]), .DIA15(ui49c6d[15]), .DIA14(ui49c6d[14]), .DIA13(ui49c6d[13]), .DIA12(ui49c6d[12]), .DIA11(ui49c6d[11]), .DIA10(ui49c6d[10]), .DIA9(ui49c6d[9]), .DIA8(ui49c6d[8]), .DIA7(ui49c6d[7]), .DIA6(ui49c6d[6]), .DIA5(ui49c6d[5]), .DIA4(ui49c6d[4]), .DIA3(ui49c6d[3]), .DIA2(ui49c6d[2]), .DIA1(ui49c6d[1]), .DIA0(ui49c6d[0]), .ADA13(bl7e96e), .ADA12(jp4fd2d), .ADA11(qtc9fa5), .ADA10(qtd93f4), .ADA9(kd5b27e), .ADA8(fn6b64f), .ADA7(hd2d6c9), .ADA6(aa5ad9), .ADA5(gqb5b), .ADA4(vk2016b), .ADA3(ld6e801), .ADA2(ld6e801), .ADA1(lfa007e), .ADA0(lfa007e), .CEA(cobc373), .OCEA(cobc373), .CLKA(of4e369), .WEA(lfa007e), .CSA2(ld6e801), .CSA1(ld6e801), .CSA0(ld6e801), .RSTA(ne69bc9), .DIB17(ld6e801), .DIB16(ld6e801), .DIB15(ld6e801), .DIB14(ld6e801), .DIB13(ld6e801), .DIB12(ld6e801), .DIB11(ld6e801), .DIB10(ld6e801), .DIB9(ld6e801), .DIB8(ld6e801), .DIB7(ld6e801), .DIB6(ld6e801), .DIB5(ld6e801), .DIB4(ld6e801), .DIB3(ld6e801), .DIB2(ld6e801), .DIB1(ld6e801), .DIB0(ld6e801), .ADB13(hq8377c), .ADB12(of706ef), .ADB11(hd8e0dd), .ADB10(kfb1c1b), .ADB9(rg76383), .ADB8(zkeec70), .ADB7(ie9dd8e), .ADB6(ldf3bb1), .ADB5(ks3e776), .ADB4(ldc7cee), .ADB3(ld6e801), .ADB2(ld6e801), .ADB1(ld6e801), .ADB0(ld6e801), .CEB(thfc1f7), .OCEB(thfc1f7), .CLKB(th71b4d), .WEB(ld6e801), .CSB2(ld6e801), .CSB1(ld6e801), .CSB0(ld6e801), .RSTB(ne69bc9), .DOA17(), .DOA16(), .DOA15(), .DOA14(), .DOA13(), .DOA12(), .DOA11(), .DOA10(), .DOA9(), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB17(uvc94e2[17]), .DOB16(uvc94e2[16]), .DOB15(uvc94e2[15]), .DOB14(uvc94e2[14]), .DOB13(uvc94e2[13]), .DOB12(uvc94e2[12]), .DOB11(uvc94e2[11]), .DOB10(uvc94e2[10]), .DOB9(uvc94e2[9]), .DOB8(uvc94e2[8]), .DOB7(uvc94e2[7]), .DOB6( +uvc94e2[6]), .DOB5(uvc94e2[5]), .DOB4(uvc94e2[4]), .DOB3(uvc94e2[3]), .DOB2(uvc94e2[2]), .DOB1(uvc94e2[1]), .DOB0(uvc94e2[0])) ; FD1P3BX mg77a (.D(ief931), .SP(cobc373), .CK(of4e369), .PD(ne69bc9), .Q(sue5da9)) ; FD1P3DX ng8682a (.D(rg7c988), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ec2ed48)) ; FD1P3DX yz90c12 (.D(sj2621a), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ho482b1)) ; FD1P3DX aaa346f (.D(ec310d4), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(kd4158a)) ; FD1P3DX vic0060 (.D(kq43500), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ir8a804)) ; FD1P3DX uk107ad (.D(gq1a801), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(sh54024)) ; FD1P3DX zx4a65b (.D(hda0049), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(aa24bcb)) ; FD1P3DX ipf866a (.D(ym24f), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ri25e58)) ; FD1P3DX hda5dac (.D(nt93c2), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ps58491)) ; FD1P3DX ie315c2 (.D(ea49e16), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(jpc248b)) ; FD1P3DX ph844b8 (.D(os7858f), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(irb1e36)) ; FD1P3DX oh36a1c (.D(vk2ff39), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(nrddf1b)) ; FD1P3DX yz26632 (.D(mr7f9cb), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(meef8de)) ; FD1P3DX jra5176 (.D(xjfce5c), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(rg7c6f1)) ; FD1P3DX qvbee52 (.D(kde72e7), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(lde378a)) ; FD1P3DX zza50de (.D(ux3973c), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ba1bc56)) ; FD1P3DX zzbf2cc (.D(gocb9e4), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ykde2b3)) ; FD1P3DX qi3e229 (.D(ay5cf20), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(xwf1598)) ; FD1P3DX rt4a3a8 (.D(ofe7900), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(cb8acc2)) ; FD1P3DX cb3cd12 (.D(ep3c805), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(ui56614)) ; FD1P3DX vxaf0ac (.D(nee402d), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(mgb30a0)) ; FD1P3DX je30c02 (.D(irb1e36), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(uk98501)) ; FD1P3DX hd9b52e (.D(sue5da9), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(vk2016b)) ; FD1P3DX qib318b (.D(ec2ed48), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(gqb5b)) ; FD1P3DX zxc8a39 (.D(ho482b1), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(aa5ad9)) ; FD1P3DX hb7ecea (.D(kd4158a), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(hd2d6c9)) ; FD1P3DX twb7049 (.D(ir8a804), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(fn6b64f)) ; FD1P3DX zx5a185 (.D(sh54024), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(kd5b27e)) ; FD1P3DX su726e8 (.D(aa24bcb), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(qtd93f4)) ; FD1P3DX qiafec (.D(ri25e58), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(qtc9fa5)) ; FD1P3DX vx3d7d (.D(ps58491), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(jp4fd2d)) ; FD1P3DX dm733ca (.D(jpc248b), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(bl7e96e)) ; FD1P3DX ux9a698 (.D(irb1e36), .SP(cobc373), .CK(of4e369), .CD(ne69bc9), .Q(lqf4b76)) ; FD1P3BX ec24901 (.D(qv8f1b5), .SP(thfc1f7), .CK(th71b4d), .PD(uic1f26), .Q(ec31ecb)) ; FD1P3DX nr402d4 (.D(go78dad), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(kf8f659)) ; FD1P3DX bn327c0 (.D(ir36b4c), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(yk59be9)) ; FD1P3DX aa3b91d (.D(ntb5a64), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(zxcdf48)) ; FD1P3DX al4476c (.D(xw6993b), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(zk48f47)) ; FD1P3DX pu25916 (.D(ww4c9da), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(by47a3b)) ; FD1P3DX fp94ff2 (.D(hd2768e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(co3b5a3)) ; FD1P3DX ecb34e2 (.D(uk3b476), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(xwdad19)) ; FD1P3DX ng8cae2 (.D(wwd1d8a), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(lf19760)) ; FD1P3DX co9d267 (.D(fp8ec50), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(aycbb07)) ; FD1P3DX tucf245 (.D(anb1433), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(tw8672e)) ; FD1P3DX dz5a8f0 (.D(pha5bb3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(xjc2809)) ; FD1P3DX sj39289 (.D(jr2dd9e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(do1404e)) ; FD1P3DX dz64f59 (.D(rt6ecf6), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(nta0273)) ; FD1P3DX ui77c80 (.D(fa767b7), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(vk139f)) ; FD1P3DX ym5b61 (.D(qib3dbb), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ph9cfa)) ; FD1P3DX mr4e0ff (.D(zz9edd8), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(al4e7d7)) ; FD1P3DX blec445 (.D(ldf6ec7), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(jc73ebd)) ; FD1P3DX su7867a (.D(jeb763e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ux9f5ea)) ; FD1P3DX mt85cea (.D(yzbb1f3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(qgfaf54)) ; FD1P3DX xya844f (.D(thd8f9d), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(dzd7aa0)) ; FD1P3DX sudb6ff (.D(tw8672e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(lsbd507)) ; FD1P3DX fac02cc (.D(ec31ecb), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ldc7cee)) ; FD1P3DX cb12620 (.D(kf8f659), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ks3e776)) ; FD1P3DX db22012 (.D(yk59be9), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ldf3bb1)) ; FD1P3DX kfb196a (.D(zxcdf48), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ie9dd8e)) ; FD1P3DX yzab9ef (.D(zk48f47), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(zkeec70)) ; FD1P3DX gbe8bc8 (.D(by47a3b), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(rg76383)) ; FD1P3DX tj274bd (.D(co3b5a3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(kfb1c1b)) ; FD1P3DX dm73e5a (.D(xwdad19), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(hd8e0dd)) ; FD1P3DX db94c77 (.D(lf19760), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(of706ef)) ; FD1P3DX ayf0385 (.D(aycbb07), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(hq8377c)) ; FD1P3DX ne47766 (.D(tw8672e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(je1bbe3)) ; FD1S3DX qi98d95 (.D(nrddf1b), .CK(th71b4d), .CD(ne69bc9), .Q(sh541d1)) ; FD1S3DX twa8955 (.D(meef8de), .CK(th71b4d), .CD(ne69bc9), .Q(qv746e)) ; FD1S3DX tjaaadf (.D(rg7c6f1), .CK(th71b4d), .CD(ne69bc9), .Q(ead1bab)) ; FD1S3DX cmfff2b (.D(lde378a), .CK(th71b4d), .CD(ne69bc9), .Q(th6eac1)) ; FD1S3DX xw581c8 (.D(ba1bc56), .CK(th71b4d), .CD(ne69bc9), .Q(uxab07c)) ; FD1S3DX ww43766 (.D(ykde2b3), .CK(th71b4d), .CD(ne69bc9), .Q(icc1f23)) ; FD1S3DX qi317b2 (.D(xwf1598), .CK(th71b4d), .CD(ne69bc9), .Q(dm7c8c8)) ; FD1S3DX mt90d7b (.D(cb8acc2), .CK(th71b4d), .CD(ne69bc9), .Q(kf2321b)) ; FD1S3DX uvdc4f6 (.D(ui56614), .CK(th71b4d), .CD(ne69bc9), .Q(fnc86e7)) ; FD1S3DX vxb59fe (.D(mgb30a0), .CK(th71b4d), .CD(ne69bc9), .Q(tw1b9f1)) ; FD1S3DX enf7052 (.D(uk98501), .CK( +th71b4d), .CD(ne69bc9), .Q(wje7c5c)) ; FD1S3DX oh9540b (.D(xjc2809), .CK(of4e369), .CD(uic1f26), .Q(psf1729)) ; FD1S3DX tu5ddf2 (.D(do1404e), .CK(of4e369), .CD(uic1f26), .Q(kq5ca56)) ; FD1S3DX aa9262d (.D(nta0273), .CK(of4e369), .CD(uic1f26), .Q(ep29581)) ; FD1S3DX me6841f (.D(vk139f), .CK(of4e369), .CD(uic1f26), .Q(ic5606e)) ; FD1S3DX nrf9650 (.D(ph9cfa), .CK(of4e369), .CD(uic1f26), .Q(db81b86)) ; FD1S3DX fc8625e (.D(al4e7d7), .CK(of4e369), .CD(uic1f26), .Q(rt6e1bd)) ; FD1S3DX fnf30a4 (.D(jc73ebd), .CK(of4e369), .CD(uic1f26), .Q(tw86f75)) ; FD1S3DX bn27394 (.D(ux9f5ea), .CK(of4e369), .CD(uic1f26), .Q(ribdd56)) ; FD1S3DX mga6a46 (.D(qgfaf54), .CK(of4e369), .CD(uic1f26), .Q(al7559b)) ; FD1S3DX uk31459 (.D(dzd7aa0), .CK(of4e369), .CD(uic1f26), .Q(go566e7)) ; FD1S3DX fnc8b79 (.D(lsbd507), .CK(of4e369), .CD(uic1f26), .Q(lf9b9c1)) ; FD1S3DX facffa3 (.D(sh541d1), .CK(th71b4d), .CD(ne69bc9), .Q(meea83a)) ; FD1S3DX gq1a890 (.D(qv746e), .CK(th71b4d), .CD(ne69bc9), .Q(dba0e8d)) ; FD1S3DX lf812a5 (.D(ead1bab), .CK(th71b4d), .CD(ne69bc9), .Q(do3a375)) ; FD1S3DX qi2eda6 (.D(th6eac1), .CK(th71b4d), .CD(ne69bc9), .Q(ou8dd58)) ; FD1S3DX gq31428 (.D(uxab07c), .CK(th71b4d), .CD(ne69bc9), .Q(wj7560f)) ; FD1S3DX bl40ba7 (.D(icc1f23), .CK(th71b4d), .CD(ne69bc9), .Q(zk583e4)) ; FD1S3DX ls3f27b (.D(dm7c8c8), .CK(th71b4d), .CD(ne69bc9), .Q(qif919)) ; FD1S3DX sudbd7f (.D(kf2321b), .CK(th71b4d), .CD(ne69bc9), .Q(fae4643)) ; FD1S3DX xjf927d (.D(fnc86e7), .CK(th71b4d), .CD(ne69bc9), .Q(vx190dc)) ; FD1S3DX psee871 (.D(tw1b9f1), .CK(th71b4d), .CD(ne69bc9), .Q(su4373e)) ; FD1S3DX lf8bd1e (.D(wje7c5c), .CK(th71b4d), .CD(ne69bc9), .Q(ofdcf8b)) ; FD1S3DX rtf6a8b (.D(psf1729), .CK(of4e369), .CD(uic1f26), .Q(ou3e2e5)) ; FD1S3DX mr5edae (.D(kq5ca56), .CK(of4e369), .CD(uic1f26), .Q(rv8b94a)) ; FD1S3DX gb75c3d (.D(ep29581), .CK(of4e369), .CD(uic1f26), .Q(ose52b0)) ; FD1S3DX kded947 (.D(ic5606e), .CK(of4e369), .CD(uic1f26), .Q(hb4ac0d)) ; FD1S3DX ux3c572 (.D(db81b86), .CK(of4e369), .CD(uic1f26), .Q(xlb0370)) ; FD1S3DX zz94a20 (.D(rt6e1bd), .CK(of4e369), .CD(uic1f26), .Q(epdc37)) ; FD1S3DX tj6fa2 (.D(tw86f75), .CK(of4e369), .CD(uic1f26), .Q(cz70dee)) ; FD1S3DX lf16d13 (.D(ribdd56), .CK(of4e369), .CD(uic1f26), .Q(zz37baa)) ; FD1S3DX ux9f117 (.D(al7559b), .CK(of4e369), .CD(uic1f26), .Q(neeeab3)) ; FD1S3DX mgbca3d (.D(go566e7), .CK(of4e369), .CD(uic1f26), .Q(bnaacdc)) ; FD1S3DX rte9396 (.D(lf9b9c1), .CK(of4e369), .CD(uic1f26), .Q(ecb3738)) ; FD1S3DX zmb7343 (.D(cb33973), .CK(of4e369), .CD(ne69bc9), .Q(ohdcc2)) ; FD1S3DX ls1b389 (.D(cme5ce2), .CK(of4e369), .CD(ne69bc9), .Q(th6e615)) ; FD1S3DX hb4a872 (.D(gq2e710), .CK(of4e369), .CD(ne69bc9), .Q(ie98573)) ; FD1S3DX je96b18 (.D(fc9c402), .CK(of4e369), .CD(ne69bc9), .Q(fnc2b99)) ; FD1S3DX alc3e55 (.D(gbe2013), .CK(of4e369), .CD(ne69bc9), .Q(sjae670)) ; FD1S3DX gqac196 (.D(gd804e1), .CK(of4e369), .CD(ne69bc9), .Q(jc73384)) ; FD1S3DX irb19f2 (.D(yz270c), .CK(of4e369), .CD(ne69bc9), .Q(osce11a)) ; FD1S3DX ir9564c (.D(tw9c32f), .CK(of4e369), .CD(ne69bc9), .Q(sh708d1)) ; FD1S3DX al65869 (.D(nee197b), .CK(of4e369), .CD(ne69bc9), .Q(yz2346e)) ; FD1S3DX ay4cba2 (.D(gb65ed7), .CK(of4e369), .CD(ne69bc9), .Q(aa1a374)) ; FD1S3DX hq11872 (.D(ng2f6bc), .CK(of4e369), .CD(ne69bc9), .Q(aa8dd00)) ; FD1S3DX gq92599 (.D(wje2ef8), .CK(th71b4d), .CD(uic1f26), .Q(cb7df0)) ; FD1S3DX nrc828b (.D(irbbe2c), .CK(th71b4d), .CD(uic1f26), .Q(qi3ef84)) ; FD1S3DX sh5e86e (.D(psdf164), .CK(th71b4d), .CD(uic1f26), .Q(qvbe104)) ; FD1S3DX kd7552f (.D(nec5915), .CK(th71b4d), .CD(uic1f26), .Q(eaf0825)) ; FD1S3DX xw7cf33 (.D(gd2c8ab), .CK(th71b4d), .CD(uic1f26), .Q(ls2094e)) ; FD1S3DX nt9bb75 (.D(tj22ae7), .CK(th71b4d), .CD(uic1f26), .Q(ba4a72)) ; FD1S3DX tjafd3d (.D(qi1573f), .CK(th71b4d), .CD(uic1f26), .Q(wl29c9b)) ; FD1S3DX eaefcdf (.D(qg5cfcd), .CK(th71b4d), .CD(uic1f26), .Q(qt4e4dc)) ; FD1S3DX dzf9ffa (.D(mre7e68), .CK(th71b4d), .CD(uic1f26), .Q(zm93729)) ; FD1S3DX vvd7508 (.D(jpf9a2b), .CK(th71b4d), .CD(uic1f26), .Q(db9b94a)) ; FD1S3DX ic46c6d (.D(dzcd15f), .CK(th71b4d), .CD(uic1f26), .Q(czdce0f)) ; FD1S3BX qg68b49 (.D(cb70bc), .CK(th71b4d), .PD(uic1f26), .Q(ene707c)) ; FD1S3DX ho48fd8 (.D(rv8bf07), .CK(of4e369), .CD(ne69bc9), .Q(zz383e4)) ; FD1S3BX kdc34df (.D(ld4af0d), .CK(th71b4d), .PD(uic1f26), .Q(ba9c539)) ; FD1S3DX yxfd13b (.D(ld7400f), .CK(of4e369), .CD(ne69bc9), .Q(ale29cb)) ; defparam czdc970.INJECT1_1 = "NO" ; defparam czdc970.INJECT1_0 = "NO" ; defparam czdc970.INIT1 = 16'h66AA ; defparam czdc970.INIT0 = 16'h66AA ; CCU2C czdc970 (.A0(ld6e801), .A1(lfa007e), .B0(ld6e801), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(nee4c43)); defparam zm252ac.INJECT1_1 = "NO" ; defparam zm252ac.INJECT1_0 = "NO" ; defparam zm252ac.INIT1 = 16'hAA00 ; defparam zm252ac.INIT0 = 16'hAA00 ; CCU2C zm252ac (.A0(sue5da9), .A1(ec2ed48), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(nee4c43), .S0(ief931), .S1(rg7c988), .COUT(ec886a0)); defparam nt8e731.INJECT1_1 = "NO" ; defparam nt8e731.INJECT1_0 = "NO" ; defparam nt8e731.INIT1 = 16'hAA00 ; defparam nt8e731.INIT0 = 16'hAA00 ; CCU2C nt8e731 (.A0(ho482b1), .A1(kd4158a), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ec886a0), .S0(sj2621a), .S1(ec310d4), .COUT(med4009)); defparam al448cb.INJECT1_1 = "NO" ; defparam al448cb.INJECT1_0 = "NO" ; defparam al448cb.INIT1 = 16'hAA00 ; defparam al448cb.INIT0 = 16'hAA00 ; CCU2C al448cb (.A0(ir8a804), .A1(sh54024), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(med4009), .S0(kq43500), .S1(gq1a801), .COUT(ls1278)); defparam yz12202.INJECT1_1 = "NO" ; defparam yz12202.INJECT1_0 = "NO" ; defparam yz12202.INIT1 = 16'hAA00 ; defparam yz12202.INIT0 = 16'hAA00 ; CCU2C yz12202 (.A0(aa24bcb), .A1(ri25e58), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ls1278), .S0(hda0049), .S1(ym24f), .COUT(rt4f0b1)); defparam gqa9061.INJECT1_1 = "NO" ; defparam gqa9061.INJECT1_0 = "NO" ; defparam gqa9061.INIT1 = 16'hAA00 ; defparam gqa9061.INIT0 = 16'hAA00 ; CCU2C gqa9061 (.A0(ps58491), .A1(jpc248b), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(rt4f0b1), .S0(nt93c2), .S1(ea49e16), .COUT(db163c6)); defparam ng30cac.INJECT1_1 = "NO" ; defparam ng30cac.INJECT1_0 = "NO" ; defparam ng30cac.INIT1 = 16'hAA00 ; defparam ng30cac.INIT0 = 16'hAA00 ; CCU2C ng30cac (.A0(irb1e36), .A1(ld6e801), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(db163c6), .S0(os7858f), .S1(), .COUT(nrc2c78)); defparam by486b9.INJECT1_1 = "NO" ; defparam by486b9.INJECT1_0 = "NO" ; defparam by486b9.INIT1 = 16'h66AA ; defparam by486b9.INIT0 = 16'h66AA ; CCU2C by486b9 (.A0(ld6e801), .A1(lfa007e), .B0(ld6e801), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(enc6d69)); defparam rtec55a.INJECT1_1 = "NO" ; defparam rtec55a.INJECT1_0 = "NO" ; defparam rtec55a.INIT1 = 16'hAA00 ; + defparam rtec55a.INIT0 = 16'hAA00 ; CCU2C rtec55a (.A0(ec31ecb), .A1(kf8f659), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(enc6d69), .S0(qv8f1b5), .S1(go78dad), .COUT(doad327)); defparam ww4ca01.INJECT1_1 = "NO" ; defparam ww4ca01.INJECT1_0 = "NO" ; defparam ww4ca01.INIT1 = 16'hAA00 ; defparam ww4ca01.INIT0 = 16'hAA00 ; CCU2C ww4ca01 (.A0(yk59be9), .A1(zxcdf48), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(doad327), .S0(ir36b4c), .S1(ntb5a64), .COUT(fn64ed1)); defparam wl26283.INJECT1_1 = "NO" ; defparam wl26283.INJECT1_0 = "NO" ; defparam wl26283.INIT1 = 16'hAA00 ; defparam wl26283.INIT0 = 16'hAA00 ; CCU2C wl26283 (.A0(zk48f47), .A1(by47a3b), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(fn64ed1), .S0(xw6993b), .S1(ww4c9da), .COUT(lqda3b1)); defparam an90107.INJECT1_1 = "NO" ; defparam an90107.INJECT1_0 = "NO" ; defparam an90107.INIT1 = 16'hAA00 ; defparam an90107.INIT0 = 16'hAA00 ; CCU2C an90107 (.A0(co3b5a3), .A1(xwdad19), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(lqda3b1), .S0(hd2768e), .S1(uk3b476), .COUT(tu76286)); defparam wwff6b5.INJECT1_1 = "NO" ; defparam wwff6b5.INJECT1_0 = "NO" ; defparam wwff6b5.INIT1 = 16'hAA00 ; defparam wwff6b5.INIT0 = 16'hAA00 ; CCU2C wwff6b5 (.A0(lf19760), .A1(aycbb07), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(tu76286), .S0(wwd1d8a), .S1(fp8ec50), .COUT(ld50ce5)); defparam zxc8c00.INJECT1_1 = "NO" ; defparam zxc8c00.INJECT1_0 = "NO" ; defparam zxc8c00.INIT1 = 16'hAA00 ; defparam zxc8c00.INIT0 = 16'hAA00 ; CCU2C zxc8c00 (.A0(tw8672e), .A1(ld6e801), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ld50ce5), .S0(anb1433), .S1(), .COUT(an8a19c)); defparam ec2b205.INJECT1_1 = "NO" ; defparam ec2b205.INJECT1_0 = "NO" ; defparam ec2b205.INIT1 = 16'h0000 ; defparam ec2b205.INIT0 = 16'h0000 ; CCU2C ec2b205 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(pu9cb9c)); defparam hd8bd85.INJECT1_1 = "NO" ; defparam hd8bd85.INJECT1_0 = "NO" ; defparam hd8bd85.INIT1 = 16'h99AA ; defparam hd8bd85.INIT0 = 16'h99AA ; CCU2C hd8bd85 (.A0(lfa007e), .A1(sue5da9), .B0(ld6e801), .B1(gd17976), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(pu9cb9c), .S0(), .S1(cb33973), .COUT(rg73880)); defparam kf33ad4.INJECT1_1 = "NO" ; defparam kf33ad4.INJECT1_0 = "NO" ; defparam kf33ad4.INIT1 = 16'h99AA ; defparam kf33ad4.INIT0 = 16'h99AA ; CCU2C kf33ad4 (.A0(ec2ed48), .A1(ho482b1), .B0(iebcbb5), .B1(phb520a), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(rg73880), .S0(cme5ce2), .S1(gq2e710), .COUT(mg1009c)); defparam phaa7ab.INJECT1_1 = "NO" ; defparam phaa7ab.INJECT1_0 = "NO" ; defparam phaa7ab.INIT1 = 16'h99AA ; defparam phaa7ab.INIT0 = 16'h99AA ; CCU2C phaa7ab (.A0(kd4158a), .A1(ir8a804), .B0(oua9056), .B1(ui562a0), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(mg1009c), .S0(fc9c402), .S1(gbe2013), .COUT(rv13865)); defparam lq5df1b.INJECT1_1 = "NO" ; defparam lq5df1b.INJECT1_0 = "NO" ; defparam lq5df1b.INIT1 = 16'h99AA ; defparam lq5df1b.INIT0 = 16'h99AA ; CCU2C lq5df1b (.A0(sh54024), .A1(aa24bcb), .B0(ohb1500), .B1(sw92f), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(rv13865), .S0(gd804e1), .S1(yz270c), .COUT(tjcbda)); defparam hd32be5.INJECT1_1 = "NO" ; defparam hd32be5.INJECT1_0 = "NO" ; defparam hd32be5.INIT1 = 16'h99AA ; defparam hd32be5.INIT0 = 16'h99AA ; CCU2C hd32be5 (.A0(ri25e58), .A1(ps58491), .B0(tw4979), .B1(xw79612), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(tjcbda), .S0(tw9c32f), .S1(nee197b), .COUT(jcdaf17)); defparam ne4d155.INJECT1_1 = "NO" ; defparam ne4d155.INJECT1_0 = "NO" ; defparam ne4d155.INIT1 = 16'h99AA ; defparam ne4d155.INIT0 = 16'h99AA ; CCU2C ne4d155 (.A0(jpc248b), .A1(xj7b5e2), .B0(eacb092), .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(jcdaf17), .S0(gb65ed7), .S1(ng2f6bc), .COUT(mgbc5df)); defparam bab845a.INJECT1_1 = "NO" ; defparam bab845a.INJECT1_0 = "NO" ; defparam bab845a.INIT1 = 16'h0000 ; defparam bab845a.INIT0 = 16'h0000 ; CCU2C bab845a (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(mgbc5df), .S0(nrd78bb), .S1(), .COUT()); defparam rgd5621.INJECT1_1 = "NO" ; defparam rgd5621.INJECT1_0 = "NO" ; defparam rgd5621.INIT1 = 16'h0000 ; defparam rgd5621.INIT0 = 16'h0000 ; CCU2C rgd5621 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(qv177c5)); defparam twe316.INJECT1_1 = "NO" ; defparam twe316.INJECT1_0 = "NO" ; defparam twe316.INIT1 = 16'h99AA ; defparam twe316.INIT0 = 16'h99AA ; CCU2C twe316 (.A0(lfa007e), .A1(ykf0c7b), .B0(ld6e801), .B1(ec31ecb), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(qv177c5), .S0(), .S1(wje2ef8), .COUT(enf8b22)); defparam rgee357.INJECT1_1 = "NO" ; defparam rgee357.INJECT1_0 = "NO" ; defparam rgee357.INIT1 = 16'h99AA ; defparam rgee357.INIT0 = 16'h99AA ; CCU2C rgee357 (.A0(ng863d9), .A1(ipd966f), .B0(kf8f659), .B1(yk59be9), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(enf8b22), .S0(irbbe2c), .S1(psdf164), .COUT(th6455c)); defparam ea4991c.INJECT1_1 = "NO" ; defparam ea4991c.INJECT1_0 = "NO" ; defparam ea4991c.INIT1 = 16'h99AA ; defparam ea4991c.INIT0 = 16'h99AA ; CCU2C ea4991c (.A0(cmcb37d), .A1(os7d23d), .B0(zxcdf48), .B1(zk48f47), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(th6455c), .S0(nec5915), .S1(gd2c8ab), .COUT(mtab9f9)); defparam rv9b44d.INJECT1_1 = "NO" ; defparam rv9b44d.INJECT1_0 = "NO" ; defparam rv9b44d.INIT1 = 16'h99AA ; defparam rv9b44d.INIT0 = 16'h99AA ; CCU2C rv9b44d (.A0(nre91e8), .A1(ofe8ed6), .B0(by47a3b), .B1(co3b5a3), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(mtab9f9), .S0(tj22ae7), .S1(qi1573f), .COUT(ng3f345)); defparam bn1c928.INJECT1_1 = "NO" ; defparam bn1c928.INJECT1_0 = "NO" ; defparam bn1c928.INIT1 = 16'h99AA ; defparam bn1c928.INIT0 = 16'h99AA ; CCU2C bn1c928 (.A0(dm476b4), .A1(sjb465d), .B0(xwdad19), .B1(lf19760), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ng3f345), .S0(qg5cfcd), .S1(mre7e68), .COUT(nr457f0)); defparam uie009b.INJECT1_1 = "NO" ; defparam uie009b.INJECT1_0 = "NO" ; defparam uie009b.INIT1 = 16'h99AA ; defparam uie009b.INIT0 = 16'h99AA ; CCU2C uie009b (.A0(mga32ec), .A1(cm68afe), .B0(aycbb07), .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(nr457f0), .S0(jpf9a2b), .S1(dzcd15f), .COUT(bl5fc31)); defparam kdfdc9e.INJECT1_1 = "NO" ; defparam kdfdc9e.INJECT1_0 = "NO" ; defparam kdfdc9e.INIT1 = 16'h0000 ; defparam kdfdc9e.INIT0 = 16'h0000 ; CCU2C kdfdc9e (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(bl5fc31), .S0(aa2bf86), .S1(), .COUT()); defparam jrb58ea.INJECT1_1 = "NO" ; defparam jrb58ea.INJECT1_0 = "NO" ; defparam jrb58ea.INIT1 = 16'h66AA ; defparam jrb58ea.INIT0 = 16'h66AA ; CCU2C jrb58ea (.A0(ld6e801), .A1(thfc1f7), .B0(ld6e801), .B1(thfc1f7), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(zkfe18f)); defparam ym1ffe6.INJECT1_1 = "NO" ; defparam ym1ffe6.INJECT1_0 = "NO" ; defparam ym1ffe6.INIT1 = + 16'h99AA ; defparam ym1ffe6.INIT0 = 16'h99AA ; CCU2C ym1ffe6 (.A0(ec31ecb), .A1(kf8f659), .B0(ykf0c7b), .B1(ng863d9), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(zkfe18f), .S0(), .S1(), .COUT(nr7b2cd)); defparam yz8b23.INJECT1_1 = "NO" ; defparam yz8b23.INJECT1_0 = "NO" ; defparam yz8b23.INIT1 = 16'h99AA ; defparam yz8b23.INIT0 = 16'h99AA ; CCU2C yz8b23 (.A0(yk59be9), .A1(zxcdf48), .B0(ipd966f), .B1(cmcb37d), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(nr7b2cd), .S0(), .S1(), .COUT(cz6fa47)); defparam mr7fe91.INJECT1_1 = "NO" ; defparam mr7fe91.INJECT1_0 = "NO" ; defparam mr7fe91.INIT1 = 16'h99AA ; defparam mr7fe91.INIT0 = 16'h99AA ; CCU2C mr7fe91 (.A0(zk48f47), .A1(by47a3b), .B0(os7d23d), .B1(nre91e8), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(cz6fa47), .S0(), .S1(), .COUT(lf3d1da)); defparam ec1a3b6.INJECT1_1 = "NO" ; defparam ec1a3b6.INJECT1_0 = "NO" ; defparam ec1a3b6.INIT1 = 16'h99AA ; defparam ec1a3b6.INIT0 = 16'h99AA ; CCU2C ec1a3b6 (.A0(co3b5a3), .A1(xwdad19), .B0(ofe8ed6), .B1(dm476b4), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(lf3d1da), .S0(), .S1(), .COUT(uvd68cb)); defparam ldf6be2.INJECT1_1 = "NO" ; defparam ldf6be2.INJECT1_0 = "NO" ; defparam ldf6be2.INIT1 = 16'h99AA ; defparam ldf6be2.INIT0 = 16'h99AA ; CCU2C ldf6be2 (.A0(lf19760), .A1(aycbb07), .B0(sjb465d), .B1(mga32ec), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(uvd68cb), .S0(), .S1(), .COUT(fa5d838)); defparam bn16996.INJECT1_1 = "NO" ; defparam bn16996.INJECT1_0 = "NO" ; defparam bn16996.INIT1 = 16'h99AA ; defparam bn16996.INIT0 = 16'h99AA ; CCU2C bn16996 (.A0(yx60e17), .A1(ld6e801), .B0(dzec1c2), .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(fa5d838), .S0(), .S1(), .COUT(xl385e5)); defparam vi6cfe5.INJECT1_1 = "NO" ; defparam vi6cfe5.INJECT1_0 = "NO" ; defparam vi6cfe5.INIT1 = 16'h0000 ; defparam vi6cfe5.INIT0 = 16'h0000 ; CCU2C vi6cfe5 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(xl385e5), .S0(cb70bc), .S1(), .COUT()); defparam ym82c41.INJECT1_1 = "NO" ; defparam ym82c41.INJECT1_0 = "NO" ; defparam ym82c41.INIT1 = 16'h66AA ; defparam ym82c41.INIT0 = 16'h66AA ; CCU2C ym82c41 (.A0(ld6e801), .A1(cobc373), .B0(ld6e801), .B1(cobc373), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(hbc2f2e)); defparam wl337ff.INJECT1_1 = "NO" ; defparam wl337ff.INJECT1_0 = "NO" ; defparam wl337ff.INIT1 = 16'h99AA ; defparam wl337ff.INIT0 = 16'h99AA ; CCU2C wl337ff (.A0(sue5da9), .A1(ec2ed48), .B0(gd17976), .B1(iebcbb5), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(hbc2f2e), .S0(), .S1(), .COUT(fa76a41)); defparam hbd8c9b.INJECT1_1 = "NO" ; defparam hbd8c9b.INJECT1_0 = "NO" ; defparam hbd8c9b.INIT1 = 16'h99AA ; defparam hbd8c9b.INIT0 = 16'h99AA ; CCU2C hbd8c9b (.A0(ho482b1), .A1(kd4158a), .B0(phb520a), .B1(oua9056), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(fa76a41), .S0(), .S1(), .COUT(coac54)); defparam hq30b38.INJECT1_1 = "NO" ; defparam hq30b38.INJECT1_0 = "NO" ; defparam hq30b38.INIT1 = 16'h99AA ; defparam hq30b38.INIT0 = 16'h99AA ; CCU2C hq30b38 (.A0(ir8a804), .A1(sh54024), .B0(ui562a0), .B1(ohb1500), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(coac54), .S0(), .S1(), .COUT(dba0125)); defparam qi319ee.INJECT1_1 = "NO" ; defparam qi319ee.INJECT1_0 = "NO" ; defparam qi319ee.INIT1 = 16'h99AA ; defparam qi319ee.INIT0 = 16'h99AA ; CCU2C qi319ee (.A0(aa24bcb), .A1(ri25e58), .B0(sw92f), .B1(tw4979), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(dba0125), .S0(), .S1(), .COUT(xy2f2c2)); defparam ose56a6.INJECT1_1 = "NO" ; defparam ose56a6.INJECT1_0 = "NO" ; defparam ose56a6.INIT1 = 16'h99AA ; defparam ose56a6.INIT0 = 16'h99AA ; CCU2C ose56a6 (.A0(ps58491), .A1(jpc248b), .B0(xw79612), .B1(eacb092), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(xy2f2c2), .S0(), .S1(), .COUT(an1245f)); defparam mt904a5.INJECT1_1 = "NO" ; defparam mt904a5.INJECT1_0 = "NO" ; defparam mt904a5.INIT1 = 16'h99AA ; defparam mt904a5.INIT0 = 16'h99AA ; CCU2C mt904a5 (.A0(xl917e0), .A1(ld6e801), .B0(ie922fc), .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(an1245f), .S0(), .S1(), .COUT(nr5f83e)); defparam shd3f61.INJECT1_1 = "NO" ; defparam shd3f61.INJECT1_0 = "NO" ; defparam shd3f61.INIT1 = 16'h0000 ; defparam shd3f61.INIT0 = 16'h0000 ; CCU2C shd3f61 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(nr5f83e), .S0(rv8bf07), .S1(), .COUT()); defparam yx707c8.INJECT1_1 = "NO" ; defparam yx707c8.INJECT1_0 = "NO" ; defparam yx707c8.INIT1 = 16'h66AA ; defparam yx707c8.INIT0 = 16'h66AA ; CCU2C yx707c8 (.A0(ld6e801), .A1(thfc1f7), .B0(ld6e801), .B1(thfc1f7), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(yke0fbe)); defparam vx16390.INJECT1_1 = "NO" ; defparam vx16390.INJECT1_0 = "NO" ; defparam vx16390.INIT1 = 16'h99AA ; defparam vx16390.INIT0 = 16'h99AA ; CCU2C vx16390 (.A0(wj6f253[0]), .A1(wj6f253[1]), .B0(cb7df0), .B1(qi3ef84), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(yke0fbe), .S0(), .S1(), .COUT(czf7c20)); defparam goe0fb3.INJECT1_1 = "NO" ; defparam goe0fb3.INJECT1_0 = "NO" ; defparam goe0fb3.INIT1 = 16'h99AA ; defparam goe0fb3.INIT0 = 16'h99AA ; CCU2C goe0fb3 (.A0(wj6f253[2]), .A1(wj6f253[3]), .B0(qvbe104), .B1(eaf0825), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(czf7c20), .S0(), .S1(), .COUT(lf84129)); defparam xw66d00.INJECT1_1 = "NO" ; defparam xw66d00.INJECT1_0 = "NO" ; defparam xw66d00.INIT1 = 16'h99AA ; defparam xw66d00.INIT0 = 16'h99AA ; CCU2C xw66d00 (.A0(wj6f253[4]), .A1(wj6f253[5]), .B0(ls2094e), .B1(ba4a72), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(lf84129), .S0(), .S1(), .COUT(ng25393)); defparam ukbca9a.INJECT1_1 = "NO" ; defparam ukbca9a.INJECT1_0 = "NO" ; defparam ukbca9a.INIT1 = 16'h99AA ; defparam ukbca9a.INIT0 = 16'h99AA ; CCU2C ukbca9a (.A0(wj6f253[6]), .A1(wj6f253[7]), .B0(wl29c9b), .B1(qt4e4dc), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ng25393), .S0(), .S1(), .COUT(go726e5)); defparam epb10e7.INJECT1_1 = "NO" ; defparam epb10e7.INJECT1_0 = "NO" ; defparam epb10e7.INIT1 = 16'h99AA ; defparam epb10e7.INIT0 = 16'h99AA ; CCU2C epb10e7 (.A0(wj6f253[8]), .A1(wj6f253[9]), .B0(zm93729), .B1(db9b94a), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(go726e5), .S0(), .S1(), .COUT(qtdca57)); defparam vk99feb.INJECT1_1 = "NO" ; defparam vk99feb.INJECT1_0 = "NO" ; defparam vk99feb.INIT1 = 16'h99AA ; defparam vk99feb.INIT0 = 16'h99AA ; CCU2C vk99feb (.A0(yz295e1), .A1(ld6e801), .B0(kqe52bc), .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(qtdca57), .S0(), .S1(), .COUT(ps5786e)); defparam al7f50f.INJECT1_1 = "NO" ; defparam al7f50f.INJECT1_0 = "NO" ; defparam al7f50f.INIT1 = 16'h0000 ; defparam al7f50f.INIT0 = 16'h0000 ; CCU2C al7f50f (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ps5786e), .S0(ld4af0d), .S1(), .COUT()); defparam ksa93bc.INJECT1_1 = "NO" ; defparam ksa93bc.INJECT1_0 = "NO" ; defparam ksa93bc.INIT1 = 16'h66AA ; defparam ksa93bc.INIT0 = 16'h66AA ; CCU2C ksa93bc (.A0(ld6e801), .A1(cobc373), .B0(ld6e801), .B1(cobc373), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1( +lfa007e), .CIN(), .S0(), .S1(), .COUT(tue1b98)); defparam jr28c2a.INJECT1_1 = "NO" ; defparam jr28c2a.INJECT1_0 = "NO" ; defparam jr28c2a.INIT1 = 16'h99AA ; defparam jr28c2a.INIT0 = 16'h99AA ; CCU2C jr28c2a (.A0(ohdcc2), .A1(th6e615), .B0(ps7929c[0]), .B1(ps7929c[1]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(tue1b98), .S0(), .S1(), .COUT(rg730ae)); defparam ld7430e.INJECT1_1 = "NO" ; defparam ld7430e.INJECT1_0 = "NO" ; defparam ld7430e.INIT1 = 16'h99AA ; defparam ld7430e.INIT0 = 16'h99AA ; CCU2C ld7430e (.A0(ie98573), .A1(fnc2b99), .B0(ps7929c[2]), .B1(ps7929c[3]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(rg730ae), .S0(), .S1(), .COUT(ou15cce)); defparam cm59a16.INJECT1_1 = "NO" ; defparam cm59a16.INJECT1_0 = "NO" ; defparam cm59a16.INIT1 = 16'h99AA ; defparam cm59a16.INIT0 = 16'h99AA ; CCU2C cm59a16 (.A0(sjae670), .A1(jc73384), .B0(ps7929c[4]), .B1(ps7929c[5]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ou15cce), .S0(), .S1(), .COUT(xy99c23)); defparam vkbb81.INJECT1_1 = "NO" ; defparam vkbb81.INJECT1_0 = "NO" ; defparam vkbb81.INIT1 = 16'h99AA ; defparam vkbb81.INIT0 = 16'h99AA ; CCU2C vkbb81 (.A0(osce11a), .A1(sh708d1), .B0(ps7929c[6]), .B1(ps7929c[7]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(xy99c23), .S0(), .S1(), .COUT(tj8468d)); defparam oh80b3c.INJECT1_1 = "NO" ; defparam oh80b3c.INJECT1_0 = "NO" ; defparam oh80b3c.INIT1 = 16'h99AA ; defparam oh80b3c.INIT0 = 16'h99AA ; CCU2C oh80b3c (.A0(yz2346e), .A1(aa1a374), .B0(ps7929c[8]), .B1(ps7929c[9]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(tj8468d), .S0(), .S1(), .COUT(med1ba0)); VLO baa2130 (.Z(ld6e801)); defparam vx84c10.INJECT1_1 = "NO" ; defparam vx84c10.INJECT1_0 = "NO" ; defparam vx84c10.INIT1 = 16'h99AA ; defparam vx84c10.INIT0 = 16'h99AA ; CCU2C vx84c10 (.A0(aa8dd00), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(med1ba0), .S0(), .S1(), .COUT(ec3f7)); VHI xjc7664 (.Z(lfa007e)); defparam end9939.INJECT1_1 = "NO" ; defparam end9939.INJECT1_0 = "NO" ; defparam end9939.INIT1 = 16'h0000 ; defparam end9939.INIT0 = 16'h0000 ; CCU2C end9939 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e), .CIN(ec3f7), .S0(ld7400f), .S1(), .COUT()); assign ld4a714 = xl220da; assign su538a7 = sw106d6; +always@* begin hq1fb8<={ui49c6d>>1,vx8bfb1[0]};iefdc3<=vx8bfb1[1];th7ee18<=vx8bfb1[2];alf70c6<=vx8bfb1[3];dob8635<=vx8bfb1[4];czc31aa<=vx8bfb1[5];wl18d55<=vx8bfb1[6];ipc6aac<={wj6f253>>1,vx8bfb1[7]};ng35564<={ps7929c>>1,vx8bfb1[8]};bnaab22<=vx8bfb1[9];jp55917<=vx8bfb1[10];coac8be<=vx8bfb1[11];nr645f0<=vx8bfb1[12];xl22f87<=vx8bfb1[13];yz17c3f<=vx8bfb1[14];yzbe1fd<=vx8bfb1[15];qgf0fed<=vx8bfb1[16];aa87f69<=vx8bfb1[17];ba3fb48<=vx8bfb1[18];mrfda42<=vx8bfb1[19];aled215<=vx8bfb1[20];zk690ad<=vx8bfb1[21];rg4856b<=vx8bfb1[22];lq42b5a<=vx8bfb1[23];ks15ad2<=vx8bfb1[24];lsad690<=vx8bfb1[25];ld6b483<=vx8bfb1[26];hb5a41e<=vx8bfb1[27];thd20f6<=vx8bfb1[28];gd907b6<=vx8bfb1[29];je83db5<=vx8bfb1[30];vk1edaa<=vx8bfb1[31];fnf6d53<=vx8bfb1[32];mgb6a9e<=vx8bfb1[33];tjb54f0<=vx8bfb1[34];xlaa786<=vx8bfb1[35];ww53c36<=vx8bfb1[36];jr9e1b1<=vx8bfb1[37];gof0d8e<=vx8bfb1[38];zm86c71<=vx8bfb1[39];ux3638a<=vx8bfb1[40];irb1c55<=vx8bfb1[41];rv8e2ad<=vx8bfb1[42];rt7156f<=vx8bfb1[43];gd8ab7e<=vx8bfb1[44];dz55bf4<=vx8bfb1[45];hqadfa6<=vx8bfb1[46];al6fd32<=vx8bfb1[47];bl7e995<=vx8bfb1[48];lqf4cae<=vx8bfb1[49];mga6573<=vx8bfb1[50];lf32b98<=vx8bfb1[51];kf95cc6<=vx8bfb1[52];mtae634<=vx8bfb1[53];ne731a4<=vx8bfb1[54];co98d23<=vx8bfb1[55];enc6918<=vx8bfb1[56];gq348c4<=vx8bfb1[57];ana4621<=vx8bfb1[58];wl2310d<=vx8bfb1[59];mt1886c<=vx8bfb1[60];eac4364<=vx8bfb1[61];gq21b20<=vx8bfb1[62];ohd900<=vx8bfb1[63];rg6c805<=vx8bfb1[64];dz6402a<=vx8bfb1[65];tw20157<=vx8bfb1[66];qiabb<=vx8bfb1[67];co55d9<=vx8bfb1[68];ri2aec8<=vx8bfb1[69];fa57643<=vx8bfb1[70];yzbb21a<=vx8bfb1[71];shd90d5<=vx8bfb1[72];hbc86ad<=vx8bfb1[73];ic4356e<=vx8bfb1[74];qi1ab71<=vx8bfb1[75];psd5b89<=vx8bfb1[76];zmadc4a<=vx8bfb1[77];pf6e252<=vx8bfb1[78];nr71296<=vx8bfb1[79];zm894b6<=vx8bfb1[80];zx4a5b2<=vx8bfb1[81];by52d97<=vx8bfb1[82];vk96cbb<=vx8bfb1[83];ymb65db<=vx8bfb1[84];ngb2ed9<=vx8bfb1[85];ym976ca<=vx8bfb1[86];uxbb650<=vx8bfb1[87];kqdb285<=vx8bfb1[88];qtd9428<=vx8bfb1[89];psca145<=vx8bfb1[90];bl50a2b<=vx8bfb1[91];sj8515e<=vx8bfb1[92];rv28af4<=vx8bfb1[93];dz457a6<=vx8bfb1[94];ym2bd36<=vx8bfb1[95];kd5e9b1<=vx8bfb1[96];tuf4d8d<=vx8bfb1[97];yma6c6b<=vx8bfb1[98];gd36359<=vx8bfb1[99];anb1acd<=vx8bfb1[100];co8d66d<=vx8bfb1[101];xj6b368<=vx8bfb1[102];ww59b46<=vx8bfb1[103];jpcda30<=vx8bfb1[104];cm6d187<=vx8bfb1[105];os68c39<=vx8bfb1[106];cm461c8<=vx8bfb1[107];vk30e41<=vx8bfb1[108];ou8720b<=vx8bfb1[109];oh39059<=vx8bfb1[110];nrc82cc<=vx8bfb1[111];gb41666<=vx8bfb1[112];xyb334<=vx8bfb1[113];kq599a3<=vx8bfb1[114];qtccd18<=vx8bfb1[115];ho668c5<=vx8bfb1[116];ym3462b<=vx8bfb1[117];iea3158<=vx8bfb1[118];ep18ac0<=vx8bfb1[119];tuc5604<=vx8bfb1[120];wy2b022<=vx8bfb1[121];ps58110<=vx8bfb1[122];hoc0883<=vx8bfb1[123];je441b<=vx8bfb1[124];xl220da<=vx8bfb1[125];sw106d6<=vx8bfb1[126];ba836b1<=vx8bfb1[127];ng1b58b<=vx8bfb1[128];nedac5a<=vx8bfb1[129];shd62d3<=vx8bfb1[130];yzb169c<=vx8bfb1[131];lf8b4e4<=vx8bfb1[132];vv5a727<=vx8bfb1[133];ald393e<=vx8bfb1[134];ng9c9f5<=vx8bfb1[135];nee4faa<=vx8bfb1[136];tj27d52<=vx8bfb1[137];qi3ea97<=vx8bfb1[138];ayf54b8<=vx8bfb1[139];bnaa5c0<=vx8bfb1[140];dm52e06<=vx8bfb1[141];ks97033<=vx8bfb1[142];lsb8198<=vx8bfb1[143];nec0cc2<=vx8bfb1[144];hd6613<=vx8bfb1[145];kf3309f<=vx8bfb1[146];ec984fd<=vx8bfb1[147];zxc27e9<=vx8bfb1[148];zz13f4f<=vx8bfb1[149];gd9fa7f<=vx8bfb1[150];offd3fd<=vx8bfb1[151];nre9fec<=vx8bfb1[152];xj4ff66<=vx8bfb1[153];ip7fb36<=vx8bfb1[154];qtfd9b4<=vx8bfb1[155];hbecda5<=vx8bfb1[156];zk66d2e<=vx8bfb1[157];oh36973<=vx8bfb1[158];irb4b9c<=vx8bfb1[159];rva5ce5<=vx8bfb1[160];wy2e72e<=vx8bfb1[161];ps73970<=vx8bfb1[162];pu9cb82<=vx8bfb1[163];cme5c12<=vx8bfb1[164];gq2e090<=vx8bfb1[165];sh70480<=vx8bfb1[166];mg82404<=vx8bfb1[167];yz12021<=vx8bfb1[168];ux9010c<=vx8bfb1[169];sj80865<=vx8bfb1[170];tw432d<=vx8bfb1[171];wy2196a<=vx8bfb1[172];ntcb50<=vx8bfb1[173];kd65a87<=vx8bfb1[174];vx2d43c<=vx8bfb1[175];mr6a1e7<=vx8bfb1[176];pf50f3c<=vx8bfb1[177];ym879e6<=vx8bfb1[178];mt3cf30<=vx8bfb1[179];ale7985<=vx8bfb1[180];wl3cc2d<=vx8bfb1[181];dze616d<=vx8bfb1[182];pu30b6e<=vx8bfb1[183];ux85b73<=vx8bfb1[184];lf2db9d<=vx8bfb1[185];ea6dcee<=vx8bfb1[186];dz6e770<=vx8bfb1[187];tu73b86<=vx8bfb1[188];uk9dc32<=vx8bfb1[189];rgee190<=vx8bfb1[190];cz70c82<=vx8bfb1[191];tw86415<=vx8bfb1[192];db320ab<=vx8bfb1[193];cb9055f<=vx8bfb1[194];co82afd<=vx8bfb1[195];qi157e8<=vx8bfb1[196];mtabf41<=vx8bfb1[197];th5fa0d<=vx8bfb1[198];offd06f<=vx8bfb1[199];mre837c<=vx8bfb1[200];sh41be5<=vx8bfb1[201];uxdf2d<=vx8bfb1[202];of6f96d<=vx8bfb1[203];ho7cb6d<=vx8bfb1[204];kqe5b6b<=vx8bfb1[205];vx2db58<=vx8bfb1[206];go6dac6<=vx8bfb1[207];qg6d630<=vx8bfb1[208];zx6b181<=vx8bfb1[209];ne58c0e<=vx8bfb1[210];ofc6072<=vx8bfb1[211];ng30395<=vx8bfb1[212];bn81caa<=vx8bfb1[213];nge557<=vx8bfb1[214];ic72abb<=vx8bfb1[215];mt955d8<=vx8bfb1[216];hdaaec5<=vx8bfb1[217];dm5762f<=vx8bfb1[218];irbb17a<=vx8bfb1[219];vvd8bd5<=vx8bfb1[220];zkc5eae<=vx8bfb1[221];xy2f573<=vx8bfb1[222];yx7ab9a<=vx8bfb1[223];ned5cd4<=vx8bfb1[224];kfae6a2<=vx8bfb1[225];xw73514<=vx8bfb1[226];gd9a8a3<=vx8bfb1[227];med451d<=vx8bfb1[228];fca28e9<=vx8bfb1[229];je1474b<=vx8bfb1[230];gqa3a5b<=vx8bfb1[231];sj1d2d9<=vx8bfb1[232];hbe96cd<=vx8bfb1[233];en4b66f<=vx8bfb1[234];qt5b37d<=vx8bfb1[235];mrd9bec<=vx8bfb1[236];hbcdf64<=vx8bfb1[237];of6fb27<=vx8bfb1[238];go7d93d<=vx8bfb1[239];fnec9e9<=vx8bfb1[240];ld64f4e<=vx8bfb1[241];db27a76<=vx8bfb1[ +242];vx3d3b7<=vx8bfb1[243];rte9dbe<=vx8bfb1[244];cz4edf6<=vx8bfb1[245];vi76fb4<=vx8bfb1[246];lsb7da2<=vx8bfb1[247];kfbed12<=vx8bfb1[248];hbf6894<=vx8bfb1[249];epb44a6<=vx8bfb1[250];fca2534<=vx8bfb1[251];gd129a2<=vx8bfb1[252];lf94d15<=vx8bfb1[253];swa68ae<=vx8bfb1[254];ie34571<=vx8bfb1[255];lsa2b88<=vx8bfb1[256];ec15c43<=vx8bfb1[257];qvae218<=vx8bfb1[258];vv710c4<=vx8bfb1[259];ks88626<=vx8bfb1[260];go43130<=vx8bfb1[261];cb18981<=vx8bfb1[262];cmc4c0c<=vx8bfb1[263];wl26061<=vx8bfb1[264];ls3030c<=vx8bfb1[265];lf81862<=vx8bfb1[266];rvc317<=vx8bfb1[267];nr618be<=vx8bfb1[268];tjc5f6<=vx8bfb1[269];ay62fb6<=vx8bfb1[270];wl17db1<=vx8bfb1[271];irbed8d<=vx8bfb1[272];rtf6c6c<=vx8bfb1[273];ecb6366<=vx8bfb1[274];kfb1b31<=vx8bfb1[275];ec8d98d<=vx8bfb1[276];ps6cc69<=vx8bfb1[277];lq6634a<=vx8bfb1[278];aa31a52<=vx8bfb1[279];co8d291<=vx8bfb1[280];vi69488<=vx8bfb1[281];nr4a443<=vx8bfb1[282];jc5221f<=vx8bfb1[283];fp910fa<=vx8bfb1[284];aa887d7<=vx8bfb1[285];ea43eb8<=vx8bfb1[286];gq1f5c0<=vx8bfb1[287];icfae00<=vx8bfb1[288];rtd7000<=vx8bfb1[289];pub8006<=vx8bfb1[290];tuc0032<=vx8bfb1[291];wy192<=vx8bfb1[292];ukc90<=vx8bfb1[293];lf6481<=vx8bfb1[294];rv3240f<=vx8bfb1[295];ie9207f<=vx8bfb1[296];wl903f8<=vx8bfb1[297];jr81fc5<=vx8bfb1[298];ymfe2f<=vx8bfb1[299];qt7f178<=vx8bfb1[300];gbf8bc5<=vx8bfb1[301];dmc5e2d<=vx8bfb1[302];do2f16b<=vx8bfb1[303];su78b5a<=vx8bfb1[304];vic5ad1<=vx8bfb1[305];tj2d68b<=vx8bfb1[306];xj6b45f<=vx8bfb1[307];zx5a2fe<=vx8bfb1[308];end +always@* begin ead17f6[2047]<=of4e369;ead17f6[2046]<=th71b4d;ead17f6[2044]<=ym8da6f;ead17f6[2043]<=nrd78bb;ead17f6[2040]<=su6d379;ead17f6[2038]<=mgbc5df;ead17f6[2032]<=ne69bc9;ead17f6[2029]<=wje2ef8;ead17f6[2017]<=vi4de4a;ead17f6[2013]<=db81b86;ead17f6[2010]<=qv177c5;ead17f6[2003]<=ld4af0d;ead17f6[1990]<=ec886a0;ead17f6[1987]<=wj6f253[0];ead17f6[1982]<=zm93729;ead17f6[1980]<=ldf3bb1;ead17f6[1979]<=epdc37;ead17f6[1973]<=irbbe2c;ead17f6[1963]<=qtc9fa5;ead17f6[1958]<=ps5786e;ead17f6[1957]<=go566e7;ead17f6[1953]<=fa76a41;ead17f6[1942]<=hd8e0dd;ead17f6[1932]<=kq43500;ead17f6[1929]<=pu9cb9c;ead17f6[1926]<=ps7929c[0];ead17f6[1923]<=lqda3b1;ead17f6[1921]<=ofe7900;ead17f6[1917]<=db9b94a;ead17f6[1914]<=ribdd56;ead17f6[1913]<=ie9dd8e;ead17f6[1911]<=rt6e1bd;ead17f6[1903]<=zz9edd8;ead17f6[1898]<=psdf164;ead17f6[1879]<=jp4fd2d;ead17f6[1876]<=uxab07c;ead17f6[1872]<=cb8acc2;ead17f6[1868]<=cobc373;ead17f6[1866]<=ecb3738;ead17f6[1863]<=jpc248b;ead17f6[1858]<=phb520a;ead17f6[1837]<=of706ef;ead17f6[1816]<=gq1a801;ead17f6[1810]<=cme5ce2;ead17f6[1805]<=eaffb08;ead17f6[1802]<=cb7df0;ead17f6[1799]<=wwd1d8a;ead17f6[1795]<=ep3c805;ead17f6[1786]<=qtdca57;ead17f6[1783]<=thd8f9d;ead17f6[1780]<=neeeab3;ead17f6[1778]<=zkeec70;ead17f6[1775]<=cz70dee;ead17f6[1770]<=ba1bc56;ead17f6[1758]<=ldf6ec7;ead17f6[1748]<=enf8b22;ead17f6[1710]<=bl7e96e;ead17f6[1704]<=zk583e4;ead17f6[1701]<=sjb465d;ead17f6[1699]<=th6455c;ead17f6[1696]<=ui56614;ead17f6[1689]<=tue1b98;ead17f6[1685]<=lf9b9c1;ead17f6[1679]<=vk2ff39;ead17f6[1678]<=an1245f;ead17f6[1668]<=oua9056;ead17f6[1627]<=hq8377c;ead17f6[1624]<=cm68afe;ead17f6[1605]<=ou15cce;ead17f6[1589]<=ofe8ed6;ead17f6[1584]<=med4009;ead17f6[1573]<=gq2e710;ead17f6[1572]<=ng863d9;ead17f6[1567]<=kq5ca56;ead17f6[1562]<=kdfd840;ead17f6[1557]<=go78dad;ead17f6[1556]<=qi3ef84;ead17f6[1551]<=fp8ec50;ead17f6[1548]<=ea49e16;ead17f6[1543]<=nee402d;ead17f6[1524]<=kqe52bc;ead17f6[1521]<=sj2621a;ead17f6[1519]<=ldc7cee;ead17f6[1513]<=al7559b;ead17f6[1512]<=sue5da9;ead17f6[1509]<=rg76383;ead17f6[1504]<=hd2768e;ead17f6[1502]<=tw86f75;ead17f6[1499]<=fa767b7;ead17f6[1493]<=th6eac1;ead17f6[1492]<=ykde2b3;ead17f6[1469]<=jeb763e;ead17f6[1466]<=rg7c6f1;ead17f6[1448]<=nec5915;ead17f6[1421]<=by47a3b;ead17f6[1417]<=zkfe18f;ead17f6[1415]<=psf1729;ead17f6[1404]<=rg7c988;ead17f6[1402]<=gd17976;ead17f6[1400]<=ww4c9da;ead17f6[1398]<=jr2dd9e;ead17f6[1377]<=wje7c5c;ead17f6[1374]<=xl385e5;ead17f6[1373]<=lqf4b76;ead17f6[1361]<=icc1f23;ead17f6[1359]<=tw9c32f;ead17f6[1355]<=meea83a;ead17f6[1354]<=mga32ec;ead17f6[1350]<=tj22ae7;ead17f6[1349]<=dm7c8c8;ead17f6[1344]<=mgb30a0;ead17f6[1343]<=tjcbda;ead17f6[1341]<=ba4a72;ead17f6[1330]<=ohdcc2;ead17f6[1326]<=dba0e8d;ead17f6[1323]<=czdce0f;ead17f6[1322]<=aycbb07;ead17f6[1310]<=mr7f9cb;ead17f6[1308]<=ie922fc;ead17f6[1305]<=mtab9f9;ead17f6[1301]<=kf2321b;ead17f6[1289]<=ho482b1;ead17f6[1286]<=aa1a374;ead17f6[1280]<=xjc2809;ead17f6[1279]<=ng2f6bc;ead17f6[1271]<=wl29c9b;ead17f6[1224]<=rg730ae;ead17f6[1210]<=do3a375;ead17f6[1207]<=je1bbe3;ead17f6[1201]<=nr457f0;ead17f6[1199]<=zz383e4;ead17f6[1195]<=dzec1c2;ead17f6[1193]<=gd804e1;ead17f6[1163]<=cmcb37d;ead17f6[1162]<=sjae670;ead17f6[1155]<=dba0125;ead17f6[1144]<=kde72e7;ead17f6[1136]<=rv8bf07;ead17f6[1130]<=dm476b4;ead17f6[1125]<=mre7e68;ead17f6[1120]<=hda0049;ead17f6[1112]<=cz6fa47;ead17f6[1110]<=fnc86e7;ead17f6[1104]<=osce11a;ead17f6[1098]<=rg73880;ead17f6[1096]<=ec31ecb;ead17f6[1086]<=ose52b0;ead17f6[1076]<=ldec205;ead17f6[1067]<=enc6d69;ead17f6[1065]<=czf7c20;ead17f6[1060]<=coac54;ead17f6[1054]<=tu76286;ead17f6[1053]<=aa24bcb;ead17f6[1051]<=aa8dd00;ead17f6[1048]<=rt4f0b1;ead17f6[1039]<=vk2016b;ead17f6[1026]<=nta0273;ead17f6[1023]<=ui49c6d[0];ead17f6[1021]<=jcdaf17;ead17f6[1006]<=xlb0370;ead17f6[1001]<=yz295e1;ead17f6[995]<=ec310d4;ead17f6[991]<=go726e5;ead17f6[990]<=ks3e776;ead17f6[981]<=qtd93f4;ead17f6[978]<=bnaacdc;ead17f6[976]<=ec2ed48;ead17f6[971]<=kfb1c1b;ead17f6[964]<=cb33973;ead17f6[961]<=uk3b476;ead17f6[960]<=ay5cf20;ead17f6[957]<=zz37baa;ead17f6[951]<=qib3dbb;ead17f6[938]<=wj7560f;ead17f6[936]<=xwf1598;ead17f6[931]<=ps58491;ead17f6[901]<=yke0fbe;ead17f6[891]<=yzbb1f3;ead17f6[885]<=lde378a;ead17f6[850]<=uvd68cb;ead17f6[849]<=gd2c8ab;ead17f6[839]<=co5fe7;ead17f6[812]<=dzcd15f;ead17f6[802]<=fnc2b99;ead17f6[794]<=lf3d1da;ead17f6[786]<=ykf0c7b;ead17f6[783]<=rv8b94a;ead17f6[778]<=qv8f1b5;ead17f6[774]<=nt93c2;ead17f6[760]<=nee4c43;ead17f6[756]<=iebcbb5;ead17f6[752]<=fn64ed1;ead17f6[749]<=rt6ecf6;ead17f6[746]<=ou8dd58;ead17f6[733]<=meef8de;ead17f6[710]<=zk48f47;ead17f6[708]<=bl5fc31;ead17f6[707]<=ou3e2e5;ead17f6[702]<=ief931;ead17f6[701]<=hbc2f2e;ead17f6[700]<=xw6993b;ead17f6[699]<=pha5bb3;ead17f6[688]<=ofdcf8b;ead17f6[687]<=cb70bc;ead17f6[679]<=rv13865;ead17f6[677]<=lsbd507;ead17f6[674]<=qif919;ead17f6[671]<=nee197b;ead17f6[670]<=ls2094e;ead17f6[663]<=sh541d1;ead17f6[661]<=lf19760;ead17f6[652]<=qi1573f;ead17f6[650]<=fae4643;ead17f6[643]<=yz2346e;ead17f6[640]<=uk98501;ead17f6[639]<=gb65ed7;ead17f6[635]<=ng25393;ead17f6[612]<=th6e615;ead17f6[605]<=qv746e;ead17f6[599]<=ene707c;ead17f6[597]<=fa5d838;ead17f6[596]<=mg1009c;ead17f6[581]<=ipd966f;ead17f6[577]<=sh54024;ead17f6[572]<=xjfce5c;ead17f6[568]<=xl917e0;ead17f6[562]<=qg5cfcd;ead17f6[556]<=zxcdf48;ead17f6[555]<=vx190dc;ead17f6[552]<=xy99c23;ead17f6[530]<=kd4158a;ead17f6[526]<=tw4979;ead17f6[525]<=med1ba0;ead17f6[513]<=do1404e;ead17f6[510]<=xj7b5e2;ead17f6[503]<=ic5606e;ead17f6[495]<=qt4e4dc;ead17f6[490]<=kd5b27e;ead17f6[482]<=tw8672e;ead17f6[480]<=gocb9e4;ead17f6[465]<=eacb092;ead17f6[450]<=thfc1f7;ead17f6[438]<=ec3f7;ead17f6[425]<=xwdad19;ead17f6[419]<=dz40bfc;ead17f6[406]<=jpf9a2b;ead17f6[401]<=ie98573;ead17f6[389]<=irb1e36;ead17f6[387]<=ls1278;ead17f6[373]<=ead1bab;ead17f6[366]<=nrddf1b;ead17f6[355]<=nre91e8;ead17f6[354]<=aa2bf86;ead17f6[351]<=uic1f26;ead17f6[350]<=doad327;ead17f6[344]<=tw1b9f1;ead17f6[343]<=yx60e17;ead17f6[339]<=yz270c;ead17f6[338]<=dzd7aa0;ead17f6[335]<=lf84129;ead17f6[321]<=tj8468d;ead17f6[298]<=gbe2013;ead17f6[290]<=nr7b2cd;ead17f6[288]<=ir8a804;ead17f6[278]<=yk59be9;ead17f6[276]<=jc73384;ead17f6[263]<=sw92f;ead17f6[251]<=hb4ac0d;ead17f6[245]<=fn6b64f;ead17f6[241]<=ld50ce5;ead17f6[240]<=ux3973c;ead17f6[232]<=xw79612;ead17f6[225]<=nr5f83e;ead17f6[219]<=lfa007e;ead17f6[212]<=co3b5a3;ead17f6[209]<=gd817f;ead17f6[203]<=ng3f345;ead17f6[194]<=db163c6;ead17f6[193]<=ym24f;ead17f6[177]<=os7d23d;ead17f6[175]<=ntb5a64;ead17f6[172]<=su4373e;ead17f6[169]<=qgfaf54;ead17f6[167]<=eaf0825;ead17f6[160]<=sh708d1;ead17f6[149]<=fc9c402;ead17f6[145]<=kf8f659;ead17f6[144]<=ohb1500;ead17f6[125]<=ep29581;ead17f6[122]<=hd2d6c9;ead17f6[120]<=an8a19c;ead17f6[116]<=xy2f2c2;ead17f6[109]<=ld7400f;ead17f6[104]<=ld6102f;ead17f6[97]<=nrc2c78;ead17f6[87]<=ir36b4c;ead17f6[84]<=ux9f5ea;ead17f6[83]<=qvbe104;ead17f6[72]<=ui562a0;ead17f6[ +61]<=aa5ad9;ead17f6[60]<=anb1433;ead17f6[58]<=ri25e58;ead17f6[54]<=ld6e801;ead17f6[48]<=os7858f;ead17f6[42]<=jc73ebd;ead17f6[30]<=gqb5b;ead17f6[21]<=al4e7d7;ead17f6[10]<=ph9cfa;ead17f6[5]<=vk139f;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[0]};iefdc3<=vx8bfb1[1];th7ee18<=vx8bfb1[2];alf70c6<=vx8bfb1[3];dob8635<=vx8bfb1[4];czc31aa<=vx8bfb1[5];wl18d55<=vx8bfb1[6];ipc6aac<={wj6f253>>1,vx8bfb1[7]};ng35564<={ps7929c>>1,vx8bfb1[8]};bnaab22<=vx8bfb1[9];jp55917<=vx8bfb1[10];coac8be<=vx8bfb1[11];nr645f0<=vx8bfb1[12];xl22f87<=vx8bfb1[13];yz17c3f<=vx8bfb1[14];yzbe1fd<=vx8bfb1[15];qgf0fed<=vx8bfb1[16];aa87f69<=vx8bfb1[17];ba3fb48<=vx8bfb1[18];mrfda42<=vx8bfb1[19];aled215<=vx8bfb1[20];zk690ad<=vx8bfb1[21];rg4856b<=vx8bfb1[22];lq42b5a<=vx8bfb1[23];ks15ad2<=vx8bfb1[24];lsad690<=vx8bfb1[25];ld6b483<=vx8bfb1[26];hb5a41e<=vx8bfb1[27];thd20f6<=vx8bfb1[28];gd907b6<=vx8bfb1[29];je83db5<=vx8bfb1[30];vk1edaa<=vx8bfb1[31];fnf6d53<=vx8bfb1[32];mgb6a9e<=vx8bfb1[33];tjb54f0<=vx8bfb1[34];xlaa786<=vx8bfb1[35];ww53c36<=vx8bfb1[36];jr9e1b1<=vx8bfb1[37];gof0d8e<=vx8bfb1[38];zm86c71<=vx8bfb1[39];ux3638a<=vx8bfb1[40];irb1c55<=vx8bfb1[41];rv8e2ad<=vx8bfb1[42];rt7156f<=vx8bfb1[43];gd8ab7e<=vx8bfb1[44];dz55bf4<=vx8bfb1[45];hqadfa6<=vx8bfb1[46];al6fd32<=vx8bfb1[47];bl7e995<=vx8bfb1[48];lqf4cae<=vx8bfb1[49];mga6573<=vx8bfb1[50];lf32b98<=vx8bfb1[51];kf95cc6<=vx8bfb1[52];mtae634<=vx8bfb1[53];ne731a4<=vx8bfb1[54];co98d23<=vx8bfb1[55];enc6918<=vx8bfb1[56];gq348c4<=vx8bfb1[57];ana4621<=vx8bfb1[58];wl2310d<=vx8bfb1[59];mt1886c<=vx8bfb1[60];eac4364<=vx8bfb1[61];gq21b20<=vx8bfb1[62];ohd900<=vx8bfb1[63];rg6c805<=vx8bfb1[64];dz6402a<=vx8bfb1[65];tw20157<=vx8bfb1[66];qiabb<=vx8bfb1[67];co55d9<=vx8bfb1[68];ri2aec8<=vx8bfb1[69];fa57643<=vx8bfb1[70];yzbb21a<=vx8bfb1[71];shd90d5<=vx8bfb1[72];hbc86ad<=vx8bfb1[73];ic4356e<=vx8bfb1[74];qi1ab71<=vx8bfb1[75];psd5b89<=vx8bfb1[76];zmadc4a<=vx8bfb1[77];pf6e252<=vx8bfb1[78];nr71296<=vx8bfb1[79];zm894b6<=vx8bfb1[80];zx4a5b2<=vx8bfb1[81];by52d97<=vx8bfb1[82];vk96cbb<=vx8bfb1[83];ymb65db<=vx8bfb1[84];ngb2ed9<=vx8bfb1[85];ym976ca<=vx8bfb1[86];uxbb650<=vx8bfb1[87];kqdb285<=vx8bfb1[88];qtd9428<=vx8bfb1[89];psca145<=vx8bfb1[90];bl50a2b<=vx8bfb1[91];sj8515e<=vx8bfb1[92];rv28af4<=vx8bfb1[93];dz457a6<=vx8bfb1[94];ym2bd36<=vx8bfb1[95];kd5e9b1<=vx8bfb1[96];tuf4d8d<=vx8bfb1[97];yma6c6b<=vx8bfb1[98];gd36359<=vx8bfb1[99];anb1acd<=vx8bfb1[100];co8d66d<=vx8bfb1[101];xj6b368<=vx8bfb1[102];ww59b46<=vx8bfb1[103];jpcda30<=vx8bfb1[104];cm6d187<=vx8bfb1[105];os68c39<=vx8bfb1[106];cm461c8<=vx8bfb1[107];vk30e41<=vx8bfb1[108];ou8720b<=vx8bfb1[109];oh39059<=vx8bfb1[110];nrc82cc<=vx8bfb1[111];gb41666<=vx8bfb1[112];xyb334<=vx8bfb1[113];kq599a3<=vx8bfb1[114];qtccd18<=vx8bfb1[115];ho668c5<=vx8bfb1[116];ym3462b<=vx8bfb1[117];iea3158<=vx8bfb1[118];ep18ac0<=vx8bfb1[119];tuc5604<=vx8bfb1[120];wy2b022<=vx8bfb1[121];ps58110<=vx8bfb1[122];hoc0883<=vx8bfb1[123];je441b<=vx8bfb1[124];xl220da<=vx8bfb1[125];sw106d6<=vx8bfb1[126];ba836b1<=vx8bfb1[127];ng1b58b<=vx8bfb1[128];nedac5a<=vx8bfb1[129];shd62d3<=vx8bfb1[130];yzb169c<=vx8bfb1[131];lf8b4e4<=vx8bfb1[132];vv5a727<=vx8bfb1[133];ald393e<=vx8bfb1[134];ng9c9f5<=vx8bfb1[135];nee4faa<=vx8bfb1[136];tj27d52<=vx8bfb1[137];qi3ea97<=vx8bfb1[138];ayf54b8<=vx8bfb1[139];bnaa5c0<=vx8bfb1[140];dm52e06<=vx8bfb1[141];ks97033<=vx8bfb1[142];lsb8198<=vx8bfb1[143];nec0cc2<=vx8bfb1[144];kf3309f<=vx8bfb1[145];hd6613<=vx8bfb1[146];ec984fd<=vx8bfb1[147];zxc27e9<=vx8bfb1[148];zz13f4f<=vx8bfb1[149];gd9fa7f<=vx8bfb1[150];offd3fd<=vx8bfb1[151];nre9fec<=vx8bfb1[152];xj4ff66<=vx8bfb1[153];ip7fb36<=vx8bfb1[154];qtfd9b4<=vx8bfb1[155];hbecda5<=vx8bfb1[156];zk66d2e<=vx8bfb1[157];oh36973<=vx8bfb1[158];irb4b9c<=vx8bfb1[159];rva5ce5<=vx8bfb1[160];wy2e72e<=vx8bfb1[161];ps73970<=vx8bfb1[162];pu9cb82<=vx8bfb1[163];gq2e090<=vx8bfb1[164];cme5c12<=vx8bfb1[165];sh70480<=vx8bfb1[166];yz12021<=vx8bfb1[167];ux9010c<=vx8bfb1[168];sj80865<=vx8bfb1[169];tw432d<=vx8bfb1[170];wy2196a<=vx8bfb1[171];ntcb50<=vx8bfb1[172];kd65a87<=vx8bfb1[173];vx2d43c<=vx8bfb1[174];mr6a1e7<=vx8bfb1[175];pf50f3c<=vx8bfb1[176];ym879e6<=vx8bfb1[177];mt3cf30<=vx8bfb1[178];ale7985<=vx8bfb1[179];wl3cc2d<=vx8bfb1[180];pu30b6e<=vx8bfb1[181];dze616d<=vx8bfb1[182];ux85b73<=vx8bfb1[183];lf2db9d<=vx8bfb1[184];ea6dcee<=vx8bfb1[185];xj6b45f<=vx8bfb1[186];tu73b86<=vx8bfb1[187];uk9dc32<=vx8bfb1[188];rgee190<=vx8bfb1[189];cz70c82<=vx8bfb1[190];tw86415<=vx8bfb1[191];db320ab<=vx8bfb1[192];cb9055f<=vx8bfb1[193];co82afd<=vx8bfb1[194];qi157e8<=vx8bfb1[195];mtabf41<=vx8bfb1[196];th5fa0d<=vx8bfb1[197];offd06f<=vx8bfb1[198];mre837c<=vx8bfb1[199];sh41be5<=vx8bfb1[200];of6f96d<=vx8bfb1[201];uxdf2d<=vx8bfb1[202];ho7cb6d<=vx8bfb1[203];kqe5b6b<=vx8bfb1[204];vx2db58<=vx8bfb1[205];go6dac6<=vx8bfb1[206];qg6d630<=vx8bfb1[207];zx6b181<=vx8bfb1[208];ne58c0e<=vx8bfb1[209];ofc6072<=vx8bfb1[210];ng30395<=vx8bfb1[211];bn81caa<=vx8bfb1[212];nge557<=vx8bfb1[213];ic72abb<=vx8bfb1[214];mt955d8<=vx8bfb1[215];hdaaec5<=vx8bfb1[216];dm5762f<=vx8bfb1[217];irbb17a<=vx8bfb1[218];vvd8bd5<=vx8bfb1[219];zkc5eae<=vx8bfb1[220];xy2f573<=vx8bfb1[221];yx7ab9a<=vx8bfb1[222];ned5cd4<=vx8bfb1[223];kfae6a2<=vx8bfb1[224];xw73514<=vx8bfb1[225];gd9a8a3<=vx8bfb1[226];med451d<=vx8bfb1[227];fca28e9<=vx8bfb1[228];je1474b<=vx8bfb1[229];gqa3a5b<=vx8bfb1[230];sj1d2d9<=vx8bfb1[231];hbe96cd<=vx8bfb1[232];en4b66f<=vx8bfb1[233];qt5b37d<=vx8bfb1[234];mrd9bec<=vx8bfb1[235];hbcdf64<=vx8bfb1[236];of6fb27<=vx8bfb1[237];go7d93d<=vx8bfb1[238];fnec9e9<=vx8bfb1[239];ld64f4e<=vx8bfb1[240];db27a76<=vx8bfb1[241];vx3d3b7<= +vx8bfb1[242];rte9dbe<=vx8bfb1[243];cz4edf6<=vx8bfb1[244];vi76fb4<=vx8bfb1[245];lsb7da2<=vx8bfb1[246];kfbed12<=vx8bfb1[247];hbf6894<=vx8bfb1[248];epb44a6<=vx8bfb1[249];fca2534<=vx8bfb1[250];gd129a2<=vx8bfb1[251];lf94d15<=vx8bfb1[252];swa68ae<=vx8bfb1[253];ie34571<=vx8bfb1[254];lsa2b88<=vx8bfb1[255];ec15c43<=vx8bfb1[256];qvae218<=vx8bfb1[257];vv710c4<=vx8bfb1[258];ks88626<=vx8bfb1[259];go43130<=vx8bfb1[260];cb18981<=vx8bfb1[261];cmc4c0c<=vx8bfb1[262];wl26061<=vx8bfb1[263];ls3030c<=vx8bfb1[264];lf81862<=vx8bfb1[265];rvc317<=vx8bfb1[266];nr618be<=vx8bfb1[267];tjc5f6<=vx8bfb1[268];ay62fb6<=vx8bfb1[269];wl17db1<=vx8bfb1[270];irbed8d<=vx8bfb1[271];rtf6c6c<=vx8bfb1[272];ecb6366<=vx8bfb1[273];kfb1b31<=vx8bfb1[274];ec8d98d<=vx8bfb1[275];ps6cc69<=vx8bfb1[276];lq6634a<=vx8bfb1[277];aa31a52<=vx8bfb1[278];co8d291<=vx8bfb1[279];vi69488<=vx8bfb1[280];nr4a443<=vx8bfb1[281];jc5221f<=vx8bfb1[282];fp910fa<=vx8bfb1[283];aa887d7<=vx8bfb1[284];ea43eb8<=vx8bfb1[285];gq1f5c0<=vx8bfb1[286];icfae00<=vx8bfb1[287];rtd7000<=vx8bfb1[288];pub8006<=vx8bfb1[289];tuc0032<=vx8bfb1[290];wy192<=vx8bfb1[291];ukc90<=vx8bfb1[292];lf6481<=vx8bfb1[293];rv3240f<=vx8bfb1[294];ie9207f<=vx8bfb1[295];wl903f8<=vx8bfb1[296];jr81fc5<=vx8bfb1[297];ymfe2f<=vx8bfb1[298];qt7f178<=vx8bfb1[299];gbf8bc5<=vx8bfb1[300];dmc5e2d<=vx8bfb1[301];do2f16b<=vx8bfb1[302];su78b5a<=vx8bfb1[303];tj2d68b<=vx8bfb1[304];zx5a2fe<=vx8bfb1[305];vic5ad1<=vx8bfb1[306];end +always@* begin ead17f6[2047]<=of4e369;ead17f6[2046]<=th71b4d;ead17f6[2044]<=ym8da6f;ead17f6[2043]<=mgbc5df;ead17f6[2040]<=su6d379;ead17f6[2038]<=wje2ef8;ead17f6[2032]<=ne69bc9;ead17f6[2029]<=lfa007e;ead17f6[2017]<=vi4de4a;ead17f6[2013]<=db81b86;ead17f6[2010]<=irbbe2c;ead17f6[2003]<=ps5786e;ead17f6[1990]<=ec886a0;ead17f6[1987]<=wj6f253[0];ead17f6[1982]<=db9b94a;ead17f6[1980]<=ldf3bb1;ead17f6[1979]<=epdc37;ead17f6[1973]<=psdf164;ead17f6[1963]<=qtc9fa5;ead17f6[1958]<=cobc373;ead17f6[1957]<=go566e7;ead17f6[1953]<=phb520a;ead17f6[1942]<=hd8e0dd;ead17f6[1932]<=kq43500;ead17f6[1929]<=cme5ce2;ead17f6[1926]<=ps7929c[0];ead17f6[1923]<=lqda3b1;ead17f6[1921]<=ofe7900;ead17f6[1917]<=qtdca57;ead17f6[1914]<=ribdd56;ead17f6[1913]<=ie9dd8e;ead17f6[1911]<=rt6e1bd;ead17f6[1903]<=zz9edd8;ead17f6[1898]<=enf8b22;ead17f6[1879]<=jp4fd2d;ead17f6[1876]<=uxab07c;ead17f6[1872]<=cb8acc2;ead17f6[1868]<=tue1b98;ead17f6[1866]<=ecb3738;ead17f6[1863]<=an1245f;ead17f6[1858]<=oua9056;ead17f6[1837]<=of706ef;ead17f6[1816]<=gq1a801;ead17f6[1810]<=gq2e710;ead17f6[1805]<=eaffb08;ead17f6[1802]<=qi3ef84;ead17f6[1799]<=wwd1d8a;ead17f6[1795]<=ep3c805;ead17f6[1786]<=kqe52bc;ead17f6[1783]<=thd8f9d;ead17f6[1780]<=neeeab3;ead17f6[1778]<=zkeec70;ead17f6[1775]<=cz70dee;ead17f6[1770]<=ba1bc56;ead17f6[1758]<=ldf6ec7;ead17f6[1748]<=nec5915;ead17f6[1710]<=bl7e96e;ead17f6[1704]<=zk583e4;ead17f6[1701]<=mga32ec;ead17f6[1699]<=tj22ae7;ead17f6[1696]<=ui56614;ead17f6[1689]<=ohdcc2;ead17f6[1685]<=lf9b9c1;ead17f6[1679]<=vk2ff39;ead17f6[1678]<=ie922fc;ead17f6[1668]<=ho482b1;ead17f6[1627]<=hq8377c;ead17f6[1624]<=cm68afe;ead17f6[1605]<=sjae670;ead17f6[1589]<=dm476b4;ead17f6[1584]<=med4009;ead17f6[1573]<=rg73880;ead17f6[1572]<=ec31ecb;ead17f6[1567]<=kq5ca56;ead17f6[1562]<=kdfd840;ead17f6[1557]<=go78dad;ead17f6[1556]<=czf7c20;ead17f6[1551]<=fp8ec50;ead17f6[1548]<=ea49e16;ead17f6[1543]<=nee402d;ead17f6[1524]<=yz295e1;ead17f6[1521]<=sj2621a;ead17f6[1519]<=ldc7cee;ead17f6[1513]<=al7559b;ead17f6[1512]<=ec2ed48;ead17f6[1509]<=rg76383;ead17f6[1504]<=hd2768e;ead17f6[1502]<=tw86f75;ead17f6[1499]<=fa767b7;ead17f6[1493]<=th6eac1;ead17f6[1492]<=ykde2b3;ead17f6[1469]<=jeb763e;ead17f6[1466]<=rg7c6f1;ead17f6[1448]<=gd2c8ab;ead17f6[1421]<=lf3d1da;ead17f6[1417]<=ykf0c7b;ead17f6[1415]<=psf1729;ead17f6[1404]<=rg7c988;ead17f6[1402]<=iebcbb5;ead17f6[1400]<=ww4c9da;ead17f6[1398]<=jr2dd9e;ead17f6[1377]<=wje7c5c;ead17f6[1374]<=hbc2f2e;ead17f6[1373]<=lqf4b76;ead17f6[1361]<=icc1f23;ead17f6[1359]<=nee197b;ead17f6[1355]<=meea83a;ead17f6[1354]<=lf19760;ead17f6[1350]<=qi1573f;ead17f6[1349]<=dm7c8c8;ead17f6[1344]<=mgb30a0;ead17f6[1343]<=gb65ed7;ead17f6[1341]<=ng25393;ead17f6[1330]<=th6e615;ead17f6[1326]<=dba0e8d;ead17f6[1323]<=czdce0f;ead17f6[1322]<=fa5d838;ead17f6[1310]<=mr7f9cb;ead17f6[1308]<=xl917e0;ead17f6[1305]<=qg5cfcd;ead17f6[1301]<=kf2321b;ead17f6[1289]<=kd4158a;ead17f6[1286]<=med1ba0;ead17f6[1280]<=xjc2809;ead17f6[1279]<=jcdaf17;ead17f6[1271]<=qt4e4dc;ead17f6[1224]<=ie98573;ead17f6[1210]<=do3a375;ead17f6[1207]<=je1bbe3;ead17f6[1201]<=aa2bf86;ead17f6[1199]<=zz383e4;ead17f6[1195]<=yx60e17;ead17f6[1193]<=yz270c;ead17f6[1163]<=yk59be9;ead17f6[1162]<=jc73384;ead17f6[1155]<=sw92f;ead17f6[1144]<=kde72e7;ead17f6[1136]<=nr5f83e;ead17f6[1130]<=co3b5a3;ead17f6[1125]<=ng3f345;ead17f6[1120]<=hda0049;ead17f6[1112]<=os7d23d;ead17f6[1110]<=fnc86e7;ead17f6[1104]<=sh708d1;ead17f6[1098]<=fc9c402;ead17f6[1096]<=kf8f659;ead17f6[1086]<=ose52b0;ead17f6[1076]<=ldec205;ead17f6[1067]<=enc6d69;ead17f6[1065]<=qvbe104;ead17f6[1060]<=ui562a0;ead17f6[1054]<=tu76286;ead17f6[1053]<=ri25e58;ead17f6[1051]<=ld7400f;ead17f6[1048]<=rt4f0b1;ead17f6[1039]<=vk2016b;ead17f6[1026]<=nta0273;ead17f6[1023]<=ui49c6d[0];ead17f6[1021]<=nrd78bb;ead17f6[1006]<=xlb0370;ead17f6[1001]<=ld4af0d;ead17f6[995]<=ec310d4;ead17f6[991]<=zm93729;ead17f6[990]<=ks3e776;ead17f6[981]<=qtd93f4;ead17f6[978]<=bnaacdc;ead17f6[976]<=fa76a41;ead17f6[971]<=kfb1c1b;ead17f6[964]<=cb33973;ead17f6[961]<=uk3b476;ead17f6[960]<=ay5cf20;ead17f6[957]<=zz37baa;ead17f6[951]<=qib3dbb;ead17f6[938]<=wj7560f;ead17f6[936]<=xwf1598;ead17f6[931]<=jpc248b;ead17f6[901]<=cb7df0;ead17f6[891]<=yzbb1f3;ead17f6[885]<=lde378a;ead17f6[850]<=sjb465d;ead17f6[849]<=th6455c;ead17f6[839]<=co5fe7;ead17f6[812]<=nr457f0;ead17f6[802]<=ou15cce;ead17f6[794]<=ofe8ed6;ead17f6[786]<=ng863d9;ead17f6[783]<=rv8b94a;ead17f6[778]<=qv8f1b5;ead17f6[774]<=nt93c2;ead17f6[760]<=nee4c43;ead17f6[756]<=sue5da9;ead17f6[752]<=fn64ed1;ead17f6[749]<=rt6ecf6;ead17f6[746]<=ou8dd58;ead17f6[733]<=meef8de;ead17f6[710]<=by47a3b;ead17f6[708]<=zkfe18f;ead17f6[707]<=ou3e2e5;ead17f6[702]<=ief931;ead17f6[701]<=gd17976;ead17f6[700]<=xw6993b;ead17f6[699]<=pha5bb3;ead17f6[688]<=ofdcf8b;ead17f6[687]<=xl385e5;ead17f6[679]<=tw9c32f;ead17f6[677]<=lsbd507;ead17f6[674]<=qif919;ead17f6[671]<=tjcbda;ead17f6[670]<=ba4a72;ead17f6[663]<=sh541d1;ead17f6[661]<=aycbb07;ead17f6[652]<=mtab9f9;ead17f6[650]<=fae4643;ead17f6[643]<=aa1a374;ead17f6[640]<=uk98501;ead17f6[639]<=ng2f6bc;ead17f6[635]<=wl29c9b;ead17f6[612]<=rg730ae;ead17f6[605]<=qv746e;ead17f6[599]<=ene707c;ead17f6[597]<=dzec1c2;ead17f6[596]<=gd804e1;ead17f6[581]<=cmcb37d;ead17f6[577]<=dba0125;ead17f6[572]<=xjfce5c;ead17f6[568]<=rv8bf07;ead17f6[562]<=mre7e68;ead17f6[556]<=cz6fa47;ead17f6[555]<=vx190dc;ead17f6[552]<=osce11a;ead17f6[530]<=coac54;ead17f6[526]<=aa24bcb;ead17f6[525]<=aa8dd00;ead17f6[513]<=do1404e;ead17f6[510]<=xj7b5e2;ead17f6[503]<=ic5606e;ead17f6[495]<=go726e5;ead17f6[490]<=kd5b27e;ead17f6[482]<=ld50ce5;ead17f6[480]<=gocb9e4;ead17f6[465]<=ps58491;ead17f6[450]<=yke0fbe;ead17f6[425]<=uvd68cb;ead17f6[419]<=dz40bfc;ead17f6[406]<=dzcd15f;ead17f6[401]<=fnc2b99;ead17f6[389]<=db163c6;ead17f6[387]<=ls1278;ead17f6[373]<=ead1bab;ead17f6[366]<=nrddf1b;ead17f6[355]<=zk48f47;ead17f6[354]<=bl5fc31;ead17f6[351]<=uic1f26;ead17f6[350]<=doad327;ead17f6[344]<=tw1b9f1;ead17f6[343]<=cb70bc;ead17f6[339]<=rv13865;ead17f6[338]<=dzd7aa0;ead17f6[335]<=ls2094e;ead17f6[321]<=yz2346e;ead17f6[298]<=mg1009c;ead17f6[290]<=ipd966f;ead17f6[288]<=sh54024;ead17f6[278]<=zxcdf48;ead17f6[276]<=xy99c23;ead17f6[263]<=tw4979;ead17f6[251]<=hb4ac0d;ead17f6[245]<=fn6b64f;ead17f6[241]<=tw8672e;ead17f6[240]<=ux3973c;ead17f6[232]<=eacb092;ead17f6[225]<=thfc1f7;ead17f6[212]<=xwdad19;ead17f6[209]<=gd817f;ead17f6[203]<=jpf9a2b;ead17f6[194]<=irb1e36;ead17f6[193]<=ym24f;ead17f6[177]<=nre91e8;ead17f6[175]<=ntb5a64;ead17f6[172]<=su4373e;ead17f6[169]<=qgfaf54;ead17f6[167]<=lf84129;ead17f6[160]<=tj8468d;ead17f6[149]<=gbe2013;ead17f6[145]<=nr7b2cd;ead17f6[144]<=ir8a804;ead17f6[125]<=ep29581;ead17f6[122]<=hd2d6c9;ead17f6[120]<=an8a19c;ead17f6[116]<=xw79612;ead17f6[109]<=ld6e801;ead17f6[104]<=ld6102f;ead17f6[97]<=nrc2c78;ead17f6[87]<=ir36b4c;ead17f6[84]<=ux9f5ea;ead17f6[83]<=eaf0825;ead17f6[72]<=ohb1500;ead17f6[61]<=aa5ad9;ead17f6[60]<=anb1433; +ead17f6[58]<=xy2f2c2;ead17f6[54]<=ec3f7;ead17f6[48]<=os7858f;ead17f6[42]<=jc73ebd;ead17f6[30]<=gqb5b;ead17f6[21]<=al4e7d7;ead17f6[10]<=ph9cfa;ead17f6[5]<=vk139f;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[1]};zkc0833<=vx8bfb1[2];xy419b<={fc3f1d7>>1,vx8bfb1[3]};do20cda<=vx8bfb1[4];rv66d2<=vx8bfb1[5];mt33697<={thc8030>>1,vx8bfb1[6]};xl9b4bd<={dz40186>>1,vx8bfb1[7]};psda5ee<={ymc36>>1,vx8bfb1[8]};fnd2f72<={rv61b1>>1,vx8bfb1[9]};aa97b97<={ls30d8f>>1,vx8bfb1[10]};ngbdcb9<={ng86c7b>>1,vx8bfb1[11]};hoee5cb<=vx8bfb1[12];yk72e5a<=vx8bfb1[13];ie972d0<=vx8bfb1[14];ukb9680<=vx8bfb1[15];gocb400<={jcdab6f>>1,vx8bfb1[16]};hb5a001<=vx8bfb1[17];rgd000e<=vx8bfb1[18];ux80073<={qg6ded2>>1,vx8bfb1[19]};ec39c<=vx8bfb1[20];hq1ce0<=vx8bfb1[21];jee703<={psda427>>1,vx8bfb1[22]};dm7381b<=vx8bfb1[23];xy9c0da<=vx8bfb1[24];sue06d3<=vx8bfb1[25];lf3699<=vx8bfb1[26];pu1b4cf<=vx8bfb1[27];dmda67a<={end69f2>>1,vx8bfb1[28]};mrd33d2<=vx8bfb1[29];ba99e94<=vx8bfb1[30];vicf4a2<=vx8bfb1[31];wj7a513<=vx8bfb1[32];dzd289d<=vx8bfb1[33];nt944ef<=vx8bfb1[34];nga277f<=vx8bfb1[35];tj13bfa<=vx8bfb1[36];ie9dfd7<=vx8bfb1[37];ykefeb8<={vv64785>>1,vx8bfb1[38]};kd7f5c1<=vx8bfb1[39];icfae0d<=vx8bfb1[40];rtd7068<=vx8bfb1[41];pub8346<=vx8bfb1[42];suc1a32<=vx8bfb1[43];uxd191<=vx8bfb1[44];ic68c8c<=vx8bfb1[45];go46460<=vx8bfb1[46];db32301<=vx8bfb1[47];end +always@* begin ead17f6[2047]<=zke4fc7[0];ead17f6[2046]<=force_isolate;ead17f6[2044]<=fc3f1d7[0];ead17f6[2040]<=wjf8ebb;ead17f6[2032]<=dzc75dd;ead17f6[2017]<=thc8030[0];ead17f6[1987]<=dz40186[0];ead17f6[1926]<=ymc36[0];ead17f6[1805]<=hb6b323;ead17f6[1804]<=rv61b1[0];ead17f6[1803]<=fnd213a;ead17f6[1761]<=shf2b59;ead17f6[1668]<=cb85f51;ead17f6[1562]<=yk5991e;ead17f6[1560]<=ls30d8f[0];ead17f6[1558]<=yz909d6;ead17f6[1550]<=jcdab6f[0];ead17f6[1475]<=oh95acc;ead17f6[1464]<=hqa7cad;ead17f6[1288]<=vk2fa8d;ead17f6[1076]<=yxcc8f0;ead17f6[1072]<=ng86c7b[0];ead17f6[1069]<=vx84eb4;ead17f6[1056]<=eaea358;ead17f6[1052]<=lqd5b7b;ead17f6[1023]<=gbe_mode;ead17f6[902]<=riad664;ead17f6[901]<=psda427[0];ead17f6[880]<=ym3e56b;ead17f6[834]<=qgf0bea;ead17f6[775]<=xj7b56d;ead17f6[732]<=uxb4f95;ead17f6[528]<=kq7d46b;ead17f6[450]<=bl7b484;ead17f6[417]<=hq1e17d;ead17f6[387]<=ir8f6ad;ead17f6[366]<=end69f2[0];ead17f6[225]<=uv6f690;ead17f6[208]<=ir23c2f;ead17f6[193]<=uxb1ed5;ead17f6[183]<=ng3ad3e;ead17f6[128]<=ym8d604;ead17f6[112]<=qg6ded2[0];ead17f6[104]<=vv64785[0];ead17f6[96]<=cb363da;ead17f6[91]<=tj275a7;ead17f6[64]<=cz51ac0;ead17f6[56]<=twadbda;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[2]};do20cda<=vx8bfb1[3];rv66d2<=vx8bfb1[4];gb44b77<=vx8bfb1[5];ba25bbd<=vx8bfb1[6];bn2ddea<={wl2340c>>1,vx8bfb1[7]};mt33697<={thc8030>>1,vx8bfb1[8]};xl9b4bd<={dz40186>>1,vx8bfb1[9]};psda5ee<={ymc36>>1,vx8bfb1[10]};fnd2f72<={rv61b1>>1,vx8bfb1[11]};aa97b97<={ls30d8f>>1,vx8bfb1[12]};ngbdcb9<={ng86c7b>>1,vx8bfb1[13]};hoee5cb<=vx8bfb1[14];yk72e5a<=vx8bfb1[15];ie972d0<=vx8bfb1[16];ukb9680<=vx8bfb1[17];vicf4a2<=vx8bfb1[18];wj7a513<=vx8bfb1[19];xjd76af<=vx8bfb1[20];ie9dfd7<=vx8bfb1[21];ykefeb8<={vv64785>>1,vx8bfb1[22]};kd7f5c1<=vx8bfb1[23];fpafd5a<=vx8bfb1[24];pf7ead7<=vx8bfb1[25];ba99e94<=vx8bfb1[26];gocb400<={jcdab6f>>1,vx8bfb1[27]};rgd000e<=vx8bfb1[28];hb5a001<=vx8bfb1[29];sjbe13f<=vx8bfb1[30];uif09fd<=vx8bfb1[31];dmda67a<={end69f2>>1,vx8bfb1[32]};pu1b4cf<=vx8bfb1[33];lf3699<=vx8bfb1[34];czfd3fa<=vx8bfb1[35];vve9fd4<=vx8bfb1[36];jp4fea6<={me629e2>>1,vx8bfb1[37]};al7f536<=vx8bfb1[38];gofa9b5<=vx8bfb1[39];ykd4da8<=vx8bfb1[40];swa6d40<=vx8bfb1[41];tj13bfa<=vx8bfb1[42];nt944ef<=vx8bfb1[43];xya8066<=vx8bfb1[44];icfae0d<=vx8bfb1[45];rtd7068<=vx8bfb1[46];pub8346<=vx8bfb1[47];suc1a32<=vx8bfb1[48];uxd191<=vx8bfb1[49];ic68c8c<=vx8bfb1[50];go46460<=vx8bfb1[51];db32301<=vx8bfb1[52];end +always@* begin ead17f6[2047]<=force_isolate;ead17f6[2046]<=fc3f1d7[0];ead17f6[2044]<=wjf8ebb;ead17f6[2041]<=dzc75dd;ead17f6[2034]<=ym3111a;ead17f6[2021]<=ie888d0;ead17f6[2017]<=yxcc8f0;ead17f6[1995]<=wl2340c[0];ead17f6[1986]<=vv64785[0];ead17f6[1943]<=thc8030[0];ead17f6[1925]<=ir23c2f;ead17f6[1908]<=ng3ad3e;ead17f6[1864]<=me629e2[0];ead17f6[1855]<=ir8f6ad;ead17f6[1838]<=dz40186[0];ead17f6[1803]<=me43082;ead17f6[1769]<=tj275a7;ead17f6[1680]<=ng14f11;ead17f6[1662]<=xj7b56d;ead17f6[1628]<=ymc36[0];ead17f6[1583]<=eaea358;ead17f6[1559]<=yz18411;ead17f6[1501]<=of6f251;ead17f6[1490]<=mr518a7;ead17f6[1487]<=cb363da;ead17f6[1312]<=jea788a;ead17f6[1276]<=ym3e56b;ead17f6[1209]<=rv61b1[0];ead17f6[1155]<=cze229c;ead17f6[1118]<=cz51ac0;ead17f6[1070]<=hqa7cad;ead17f6[1048]<=ww5391d;ead17f6[1023]<=gbe_mode;ead17f6[1008]<=qi31243;ead17f6[954]<=end69f2[0];ead17f6[932]<=ba8c53c;ead17f6[927]<=uxb1ed5;ead17f6[791]<=kq7d46b;ead17f6[750]<=uk8de4a;ead17f6[743]<=ng86c7b[0];ead17f6[577]<=qv3c453;ead17f6[524]<=riad664;ead17f6[504]<=shf2b59;ead17f6[395]<=vk2fa8d;ead17f6[375]<=lqd5b7b;ead17f6[371]<=ls30d8f[0];ead17f6[262]<=yk5991e;ead17f6[197]<=cb85f51;ead17f6[189]<=ym8d604;ead17f6[187]<=twadbda;ead17f6[98]<=qgf0bea;ead17f6[93]<=jcdab6f[0];ead17f6[49]<=hq1e17d;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[3]};do20cda<=vx8bfb1[4];rv66d2<=vx8bfb1[5];jc58788<={wje7ecc>>1,vx8bfb1[6]};mt33697<={thc8030>>1,vx8bfb1[7]};xl9b4bd<={dz40186>>1,vx8bfb1[8]};psda5ee<={ymc36>>1,vx8bfb1[9]};fnd2f72<={rv61b1>>1,vx8bfb1[10]};aa97b97<={ls30d8f>>1,vx8bfb1[11]};ngbdcb9<={ng86c7b>>1,vx8bfb1[12]};hoee5cb<=vx8bfb1[13];yk72e5a<=vx8bfb1[14];ie972d0<=vx8bfb1[15];ukb9680<=vx8bfb1[16];ykefeb8<={vv64785>>1,vx8bfb1[17]};kd7f5c1<=vx8bfb1[18];fpafd5a<=vx8bfb1[19];ba99e94<=vx8bfb1[20];gocb400<={jcdab6f>>1,vx8bfb1[21]};rgd000e<=vx8bfb1[22];hb5a001<=vx8bfb1[23];icfae0d<=vx8bfb1[24];rtd7068<=vx8bfb1[25];pub8346<=vx8bfb1[26];suc1a32<=vx8bfb1[27];uxd191<=vx8bfb1[28];ic68c8c<=vx8bfb1[29];go46460<=vx8bfb1[30];db32301<=vx8bfb1[31];end +always@* begin ead17f6[2047]<=mr7afdb;ead17f6[2046]<=force_isolate;ead17f6[2044]<=fc3f1d7[0];ead17f6[2040]<=wjf8ebb;ead17f6[2032]<=dzc75dd;ead17f6[2017]<=wje7ecc[0];ead17f6[1987]<=thc8030[0];ead17f6[1926]<=dz40186[0];ead17f6[1804]<=ymc36[0];ead17f6[1803]<=lqd5b7b;ead17f6[1560]<=rv61b1[0];ead17f6[1558]<=hq1e17d;ead17f6[1550]<=xj7b56d;ead17f6[1464]<=cz51ac0;ead17f6[1072]<=ls30d8f[0];ead17f6[1069]<=qgf0bea;ead17f6[1052]<=vv64785[0];ead17f6[1023]<=gbe_mode;ead17f6[901]<=twadbda;ead17f6[880]<=ym8d604;ead17f6[775]<=ir8f6ad;ead17f6[732]<=eaea358;ead17f6[450]<=jcdab6f[0];ead17f6[387]<=uxb1ed5;ead17f6[366]<=kq7d46b;ead17f6[225]<=hqa7cad;ead17f6[193]<=cb363da;ead17f6[183]<=vk2fa8d;ead17f6[112]<=me43082;ead17f6[96]<=ng86c7b[0];ead17f6[91]<=cb85f51;ead17f6[56]<=ir23c2f;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[3]};do20cda<=vx8bfb1[4];rv66d2<=vx8bfb1[5];gb44b77<=vx8bfb1[6];ba25bbd<=vx8bfb1[7];jc58788<={wje7ecc>>1,vx8bfb1[8]};mt33697<={thc8030>>1,vx8bfb1[9]};xl9b4bd<={dz40186>>1,vx8bfb1[10]};psda5ee<={ymc36>>1,vx8bfb1[11]};fnd2f72<={rv61b1>>1,vx8bfb1[12]};aa97b97<={ls30d8f>>1,vx8bfb1[13]};ngbdcb9<={ng86c7b>>1,vx8bfb1[14]};hoee5cb<=vx8bfb1[15];yk72e5a<=vx8bfb1[16];ie972d0<=vx8bfb1[17];ukb9680<=vx8bfb1[18];ykefeb8<={vv64785>>1,vx8bfb1[19]};kd7f5c1<=vx8bfb1[20];fpafd5a<=vx8bfb1[21];ba99e94<=vx8bfb1[22];gocb400<={jcdab6f>>1,vx8bfb1[23]};rgd000e<=vx8bfb1[24];hb5a001<=vx8bfb1[25];sjbe13f<=vx8bfb1[26];uif09fd<=vx8bfb1[27];icfae0d<=vx8bfb1[28];rtd7068<=vx8bfb1[29];pub8346<=vx8bfb1[30];suc1a32<=vx8bfb1[31];uxd191<=vx8bfb1[32];ic68c8c<=vx8bfb1[33];go46460<=vx8bfb1[34];db32301<=vx8bfb1[35];end +always@* begin ead17f6[2047]<=force_isolate;ead17f6[2046]<=mr7afdb;ead17f6[2044]<=fc3f1d7[0];ead17f6[2041]<=wjf8ebb;ead17f6[2035]<=dzc75dd;ead17f6[2022]<=ym3111a;ead17f6[1996]<=ie888d0;ead17f6[1945]<=wje7ecc[0];ead17f6[1922]<=lqd5b7b;ead17f6[1842]<=thc8030[0];ead17f6[1797]<=uk8de4a;ead17f6[1776]<=hqa7cad;ead17f6[1637]<=dz40186[0];ead17f6[1622]<=ng86c7b[0];ead17f6[1546]<=of6f251;ead17f6[1504]<=jcdab6f[0];ead17f6[1468]<=ir23c2f;ead17f6[1391]<=xj7b56d;ead17f6[1312]<=cz51ac0;ead17f6[1226]<=ymc36[0];ead17f6[1197]<=cb363da;ead17f6[1044]<=hq1e17d;ead17f6[1023]<=gbe_mode;ead17f6[961]<=twadbda;ead17f6[888]<=me43082;ead17f6[811]<=ls30d8f[0];ead17f6[734]<=vv64785[0];ead17f6[695]<=ir8f6ad;ead17f6[656]<=eaea358;ead17f6[576]<=ym8d604;ead17f6[405]<=rv61b1[0];ead17f6[347]<=uxb1ed5;ead17f6[328]<=kq7d46b;ead17f6[164]<=vk2fa8d;ead17f6[82]<=cb85f51;ead17f6[41]<=qgf0bea;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[6]};by6978f<=vx8bfb1[7];ip4bc7b<=vx8bfb1[8];sh5e3dc<=vx8bfb1[9];byf1ee4<=vx8bfb1[10];mt8f723<=vx8bfb1[11];dz7b91d<={do1e90d>>1,vx8bfb1[12]};czdc8ee<={psf486b>>1,vx8bfb1[13]};dme4774<={uxa435b>>1,vx8bfb1[14]};ux23ba3<={ym21add>>1,vx8bfb1[15]};an1dd1d<={cbd6e8>>1,vx8bfb1[16]};neee8ec<=vx8bfb1[17];bl74763<=vx8bfb1[18];gqa3b1e<=vx8bfb1[19];sj1d8f1<=vx8bfb1[20];dzec78c<=vx8bfb1[21];xw63c67<=vx8bfb1[22];xy1e33b<={zxf64f7>>1,vx8bfb1[23]};psf19da<=vx8bfb1[24];tw8ced3<={pu93dfb>>1,vx8bfb1[25]};ea6769b<=vx8bfb1[26];wy3b4d8<={gbf7edf>>1,vx8bfb1[27]};byda6c1<={xlbf6fc>>1,vx8bfb1[28]};wjd360a<={jcfb7e7>>1,vx8bfb1[29]};fp9b054<={rgdf9d9>>1,vx8bfb1[30]};dzd82a6<={zxfcecb>>1,vx8bfb1[31]};osc1537<={ale765f>>1,vx8bfb1[32]};iea9b8<={qi3b2fc>>1,vx8bfb1[33]};sh54dc0<={gbd97e1>>1,vx8bfb1[34]};wya6e04<={mecbf0d>>1,vx8bfb1[35]};rv37021<=vx8bfb1[36];jeb810f<=vx8bfb1[37];xwc087a<=vx8bfb1[38];hq43d3<=vx8bfb1[39];ec21e9a<=vx8bfb1[40];wyf4d0<=vx8bfb1[41];en7a681<=vx8bfb1[42];ofd340d<=vx8bfb1[43];sj9a06c<=vx8bfb1[44];byd0364<=vx8bfb1[45];xl81b23<=vx8bfb1[46];ird91f<=vx8bfb1[47];vi6c8fd<=vx8bfb1[48];jp647ea<={czfd4ca>>1,vx8bfb1[49]};qv23f57<=vx8bfb1[50];sw1fabd<=vx8bfb1[51];gbfd5e9<=vx8bfb1[52];ykeaf4c<=vx8bfb1[53];jc57a61<=vx8bfb1[54];hqbd30b<={vxa00d5>>1,vx8bfb1[55]};jpe985a<=vx8bfb1[56];os4c2d6<=vx8bfb1[57];pf616b0<=vx8bfb1[58];lsb587<=vx8bfb1[59];vv5ac3b<={vxaf1ca>>1,vx8bfb1[60]};end61df<=vx8bfb1[61];rvb0efc<=vx8bfb1[62];ie877e7<=vx8bfb1[63];qi3bf39<=vx8bfb1[64];bydf9c8<=vx8bfb1[65];blfce43<={wlb1f10>>1,vx8bfb1[66]};qte721f<=vx8bfb1[67];qv390fc<=vx8bfb1[68];dzc87e4<=vx8bfb1[69];cm43f26<={uk10b14>>1,vx8bfb1[70]};end +always@* begin ead17f6[2047]<=sgmii_mode;ead17f6[2046]<=force_unidir;ead17f6[2044]<=mr_main_reset;ead17f6[2040]<=mr_restart_an;ead17f6[2033]<=mr_an_enable;ead17f6[2019]<=mr_adv_ability[1];ead17f6[1999]<=mecbf0d[0];ead17f6[1991]<=ou2150a;ead17f6[1981]<=ic532a0;ead17f6[1958]<=gq6af;ead17f6[1950]<=ldfc347;ead17f6[1947]<=tj9408c;ead17f6[1934]<=ira1445;ead17f6[1914]<=vk99500;ead17f6[1892]<=rgfe7b2;ead17f6[1868]<=zz3578;ead17f6[1852]<=sjd1f2;ead17f6[1851]<=ym21add[0];ead17f6[1847]<=lfa0467;ead17f6[1820]<=gqa22d;ead17f6[1783]<=do3fa99;ead17f6[1780]<=dmca803;ead17f6[1737]<=pff3d93;ead17f6[1689]<=wy1abc7;ead17f6[1657]<=su68f94;ead17f6[1654]<=cbd6e8[0];ead17f6[1647]<=gd233f;ead17f6[1610]<=vkb27bf;ead17f6[1608]<=hocac7c;ead17f6[1593]<=gb51169;ead17f6[1523]<=qi3b2fc[0];ead17f6[1519]<=czfd4ca[1];ead17f6[1513]<=en5401a;ead17f6[1426]<=rv9ec9e;ead17f6[1404]<=zxfcecb[0];ead17f6[1330]<=lqd5e39;ead17f6[1267]<=jc47ca0;ead17f6[1260]<=xj6b744;ead17f6[1246]<=ba119fd;ead17f6[1225]<=go78e56;ead17f6[1199]<=xlbf6fc[0];ead17f6[1173]<=pu93dfb[0];ead17f6[1169]<=ic563e2;ead17f6[1163]<=ps7c42c;ead17f6[1139]<=ie88b4d;ead17f6[1023]<=gbe_mode;ead17f6[999]<=gbd97e1[0];ead17f6[990]<=suea654;ead17f6[979]<=vxa00d5[0];ead17f6[973]<=mrf2811;ead17f6[946]<=fc3fcf6;ead17f6[925]<=uxa435b[0];ead17f6[891]<=os67f53;ead17f6[805]<=zxf64f7[0];ead17f6[804]<=ux3958f;ead17f6[761]<=ale765f[0];ead17f6[702]<=rgdf9d9[0];ead17f6[612]<=vxaf1ca[1];ead17f6[599]<=gbf7edf[0];ead17f6[581]<=yz8f885;ead17f6[556]<=uk10b14[1];ead17f6[486]<=uk3e502;ead17f6[473]<=hbc7f9e;ead17f6[462]<=psf486b[0];ead17f6[445]<=ri8cfea;ead17f6[402]<=fnc72b1;ead17f6[351]<=jcfb7e7[0];ead17f6[299]<=fp9efdb;ead17f6[290]<=wlb1f10[0];ead17f6[278]<=uve2162;ead17f6[231]<=do1e90d[0];end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[4]};jc4d47a<=vx8bfb1[5];al6a3d2<=vx8bfb1[6];ip4bc7b<=vx8bfb1[7];ep8f4a4<=vx8bfb1[8];qt7a525<={tu69a7f>>1,vx8bfb1[9]};hbd292d<=vx8bfb1[10];tj9496f<=vx8bfb1[11];gda4b7e<=vx8bfb1[12];ng25bf4<={zz3d20b>>1,vx8bfb1[13]};tj2dfa2<={xje905e>>1,vx8bfb1[14]};sh6fd16<={by482f7>>1,vx8bfb1[15]};pf7e8b5<={of417ba>>1,vx8bfb1[16]};tuf45ae<={jebdd4>>1,vx8bfb1[17]};vka2d72<=vx8bfb1[18];jr16b93<=vx8bfb1[19];jrb5c9f<=vx8bfb1[20];yzae4ff<=vx8bfb1[21];ea727fc<=vx8bfb1[22];je93fe1<=vx8bfb1[23];ir9ff0b<=vx8bfb1[24];cmff85d<=vx8bfb1[25];vvfc2e8<=vx8bfb1[26];pse1746<=vx8bfb1[27];lsba33<=vx8bfb1[28];ps5d19a<=vx8bfb1[29];ipe8cd3<=vx8bfb1[30];go4669c<=vx8bfb1[31];cb334e1<=vx8bfb1[32];ux9a70d<=vx8bfb1[33];shd386c<=vx8bfb1[34];ba9c365<=vx8bfb1[35];zke1b2b<=vx8bfb1[36];kfd95a<=vx8bfb1[37];lq6cad5<=vx8bfb1[38];gb656aa<=vx8bfb1[39];qi2b555<=vx8bfb1[40];vv5aaa8<=vx8bfb1[41];dmd5547<={yx54ea5>>1,vx8bfb1[42]};ntaaa3b<={twa752c>>1,vx8bfb1[43]};bl551df<=vx8bfb1[44];vka8eff<=vx8bfb1[45];ho477fa<=vx8bfb1[46];ie3bfd3<=vx8bfb1[47];psdfe98<=vx8bfb1[48];goff4c3<=vx8bfb1[49];cmfa619<=vx8bfb1[50];yxd30c9<=vx8bfb1[51];sw9864c<=vx8bfb1[52];gbc3261<=vx8bfb1[53];db1930d<=vx8bfb1[54];qtc986f<=vx8bfb1[55];go4c37d<=vx8bfb1[56];dz61be8<=vx8bfb1[57];qvdf46<={mg92a74>>1,vx8bfb1[58]};ip6fa35<={gd953a1>>1,vx8bfb1[59]};qte721f<=vx8bfb1[60];qv390fc<=vx8bfb1[61];qg46b44<=vx8bfb1[62];zm35a20<=vx8bfb1[63];vkad103<=vx8bfb1[64];kq6881b<=vx8bfb1[65];icfae0d<=vx8bfb1[66];rtd7068<=vx8bfb1[67];hd3623<={aa3482d>>1,vx8bfb1[68]};end +always@* begin ead17f6[2047]<=sgmii_mode;ead17f6[2046]<=gbe_mode;ead17f6[2044]<=qif9e9;ead17f6[2040]<=rx_data[0];ead17f6[2032]<=rx_kcntl;ead17f6[2016]<=tj3d21d;ead17f6[1985]<=ira1445;ead17f6[1927]<=th74344;ead17f6[1922]<=rx_even;ead17f6[1867]<=shf7515;ead17f6[1807]<=wla1a26;ead17f6[1804]<=an2c486;ead17f6[1797]<=tu69a7f[0];ead17f6[1761]<=ng3a962;ead17f6[1686]<=tjba8ad;ead17f6[1623]<=gb44892;ead17f6[1567]<=mtd134;ead17f6[1561]<=yk62435;ead17f6[1558]<=vi585b7;ead17f6[1547]<=eca3e4a;ead17f6[1542]<=jeb870d;ead17f6[1505]<=yz8f885;ead17f6[1490]<=jebdd4[0];ead17f6[1475]<=cmd4b12;ead17f6[1413]<=jp71616;ead17f6[1409]<=icdee1c;ead17f6[1400]<=mg92a74[0];ead17f6[1324]<=ykd456e;ead17f6[1200]<=wy15b8b;ead17f6[1199]<=aa24495;ead17f6[1086]<=ww689a4;ead17f6[1074]<=cb121a8;ead17f6[1068]<=fnc2dbb;ead17f6[1047]<=aa1f251;ead17f6[1037]<=yxc386a;ead17f6[1023]<=mr_main_reset;ead17f6[963]<=ps7c42c;ead17f6[933]<=al5eea2;ead17f6[902]<=bna5890;ead17f6[880]<=twa752c[0];ead17f6[811]<=lsa8912;ead17f6[779]<=vx8b0b6;ead17f6[771]<=enf70e1;ead17f6[752]<=gd953a1[0];ead17f6[745]<=of417ba[0];ead17f6[706]<=vv6e2c2;ead17f6[704]<=epbbdc3;ead17f6[700]<=ux1254e;ead17f6[600]<=xya2b71;ead17f6[503]<=aa3482d[1];ead17f6[440]<=yx54ea5[0];ead17f6[405]<=vk35122;ead17f6[372]<=by482f7[0];ead17f6[353]<=doadc58;ead17f6[352]<=ngb77b8;ead17f6[350]<=xl224a9;ead17f6[251]<=qgf0bea;ead17f6[220]<=qt6a9d4;ead17f6[202]<=je86a24;ead17f6[186]<=xje905e[0];ead17f6[176]<=swb6ef7;ead17f6[125]<=hq1e17d;ead17f6[110]<=yzd53a;ead17f6[101]<=an90d44;ead17f6[93]<=zz3d20b[0];ead17f6[88]<=rv16dde;ead17f6[55]<=rge1aa7;ead17f6[46]<=uv511a7;ead17f6[27]<=nt1c354;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[2]};jc4d47a<=vx8bfb1[3];al6a3d2<=vx8bfb1[4];sj3c1ea<={vk25ab1>>1,vx8bfb1[5]};qge0f54<={fp2d58a>>1,vx8bfb1[6]};qv7aa0<={of6ac57>>1,vx8bfb1[7]};bn3d504<=vx8bfb1[8];kqea826<=vx8bfb1[9];qte721f<=vx8bfb1[10];qv390fc<=vx8bfb1[11];fc4c6e<=vx8bfb1[12];ux26373<=vx8bfb1[13];uk31b9c<=vx8bfb1[14];gq8dce1<=vx8bfb1[15];hb6e709<=vx8bfb1[16];zk7384e<=vx8bfb1[17];ri9c272<=vx8bfb1[18];xwe1393<={fpa5308>>1,vx8bfb1[19]};end +always@* begin ead17f6[2047]<=signal_detect;ead17f6[2046]<=rx_data[0];ead17f6[2044]<=rx_kcntl;ead17f6[2040]<=tj3d21d;ead17f6[2033]<=vk25ab1[0];ead17f6[2018]<=fp2d58a[0];ead17f6[1988]<=of6ac57[0];ead17f6[1929]<=go562bd;ead17f6[1811]<=gdb15e8;ead17f6[1789]<=wwd4a61;ead17f6[1574]<=yz8f885;ead17f6[1530]<=fpa5308[1];ead17f6[1247]<=gq246a5;ead17f6[1101]<=ps7c42c;ead17f6[1023]<=mr_main_reset;ead17f6[894]<=ec1a94c;ead17f6[623]<=kd448d4;ead17f6[447]<=sj23529;ead17f6[311]<=she891a;ead17f6[155]<=fcbd123;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[4]};vxa0fa9<={oub66fd>>1,vx8bfb1[5]};ep7d4e<=vx8bfb1[6];gq3ea74<=vx8bfb1[7];ykf53a0<={ux17d83>>1,vx8bfb1[8]};iea9d00<={ea67ca6>>1,vx8bfb1[9]};ip4e800<={aa3e531>>1,vx8bfb1[10]};th74004<=vx8bfb1[11];xla0026<=vx8bfb1[12];wy137<={iea6266>>1,vx8bfb1[13]};uk9b8<=vx8bfb1[14];je4dc1<=vx8bfb1[15];an26e0b<={yk4cc03>>1,vx8bfb1[16]};xl3705d<=vx8bfb1[17];fcb82ef<=vx8bfb1[18];qgc177a<=vx8bfb1[19];zmbbd0<=vx8bfb1[20];xw5de82<=vx8bfb1[21];osef412<=vx8bfb1[22];en7a090<=vx8bfb1[23];ned0485<=vx8bfb1[24];mg8242b<=vx8bfb1[25];ba99e94<=vx8bfb1[26];dmda67a<={end69f2>>1,vx8bfb1[27]};oh85664<=vx8bfb1[28];lf3699<=vx8bfb1[29];go59920<=vx8bfb1[30];kdcc900<=vx8bfb1[31];nr64805<=vx8bfb1[32];qi2402e<=vx8bfb1[33];mrd33d2<=vx8bfb1[34];qib8b<=vx8bfb1[35];co5c59<=vx8bfb1[36];uk2e2c9<=vx8bfb1[37];bl71648<=vx8bfb1[38];jr8b246<=vx8bfb1[39];cm59237<=vx8bfb1[40];ipc91b9<=vx8bfb1[41];rg48dcc<={oua96af>>1,vx8bfb1[42]};xl9b4bd<={dz40186>>1,vx8bfb1[43]};psda5ee<={ymc36>>1,vx8bfb1[44]};mgb98c7<={tud5e6f>>1,vx8bfb1[45]};alcc639<={hdaf37a>>1,vx8bfb1[46]};fa631cc<=vx8bfb1[47];gd18e62<=vx8bfb1[48];ldc7314<=vx8bfb1[49];qv398a7<=vx8bfb1[50];hoee5cb<=vx8bfb1[51];ay629ec<=vx8bfb1[52];vk14f61<=vx8bfb1[53];vka7b0a<=vx8bfb1[54];jr3d853<=vx8bfb1[55];dzec29f<=vx8bfb1[56];zx614ff<=vx8bfb1[57];mga7ff<={ks5e8a>>1,vx8bfb1[58]};ay53ff9<={hq2f451>>1,vx8bfb1[59]};icfae0d<=vx8bfb1[60];rtd7068<=vx8bfb1[61];meff268<={kf8a2a9>>1,vx8bfb1[62]};blf9341<={mr5154d>>1,vx8bfb1[63]};mrc9a0e<=vx8bfb1[64];by4d075<=vx8bfb1[65];me683aa<=vx8bfb1[66];sh41d51<=vx8bfb1[67];twea8d<=vx8bfb1[68];cz7546a<=vx8bfb1[69];rvaa354<=vx8bfb1[70];cz51aa6<=vx8bfb1[71];ym8d534<=vx8bfb1[72];qt6a9a0<=vx8bfb1[73];yx54d05<=vx8bfb1[74];swa682c<=vx8bfb1[75];ie34161<={hqade13>>1,vx8bfb1[76]};nta0b08<={al6f09a>>1,vx8bfb1[77]};end +always@* begin ead17f6[2047]<=an_link_ok;ead17f6[2046]<=lqe16b6;ead17f6[2044]<=gbe_mode;ead17f6[2040]<=operational_rate[0];ead17f6[2032]<=oub66fd[0];ead17f6[2018]<=oua96af[0];ead17f6[2017]<=ksb37e9;ead17f6[1989]<=dz40186[0];ead17f6[1987]<=hd9bf49;ead17f6[1931]<=ymc36[0];ead17f6[1927]<=ux17d83[0];ead17f6[1865]<=yk4cc03[0];ead17f6[1859]<=sw3e17a;ead17f6[1844]<=gd9f920;ead17f6[1815]<=tud5e6f[0];ead17f6[1806]<=ea67ca6[0];ead17f6[1682]<=tu66019;ead17f6[1674]<=ks5e8a[0];ead17f6[1671]<=uxb4f95;ead17f6[1640]<=pffc905;ead17f6[1582]<=hdaf37a[0];ead17f6[1565]<=aa3e531[0];ead17f6[1488]<=pfc8f85;ead17f6[1485]<=cb363da;ead17f6[1326]<=hqa7cad;ead17f6[1317]<=ng300ca;ead17f6[1300]<=hq2f451[0];ead17f6[1297]<=dz5536c;ead17f6[1295]<=ir85e89;ead17f6[1233]<=xwe482f;ead17f6[1210]<=nt9b647;ead17f6[1189]<=xw529fb;ead17f6[1172]<=db3294;ead17f6[1124]<=ri86b78;ead17f6[1116]<=zk79bd6;ead17f6[1105]<=qgf0bea;ead17f6[1094]<=nt38610;ead17f6[1092]<=xw4db38;ead17f6[1087]<=cz7a26a;ead17f6[1082]<=ipf2989;ead17f6[1023]<=mr_main_reset;ead17f6[1009]<=gb6aa5a;ead17f6[932]<=pu89980;ead17f6[929]<=zk47c2f;ead17f6[922]<=ecb3f24;ead17f6[837]<=je20bd1;ead17f6[744]<=gbd91f0;ead17f6[742]<=kd7acfc;ead17f6[663]<=pua7ede;ead17f6[648]<=gd8aa6d;ead17f6[605]<=end69f2[0];ead17f6[594]<=faca53f;ead17f6[586]<=an80652;ead17f6[562]<=ou10d6f;ead17f6[552]<=hq1e17d;ead17f6[547]<=ww670c2;ead17f6[546]<=ksa9b67;ead17f6[543]<=ri2f44d;ead17f6[504]<=ne4d54b;ead17f6[466]<=co31330;ead17f6[418]<=sw2417a;ead17f6[400]<=al6f09a[1];ead17f6[372]<=tj275a7;ead17f6[371]<=sh6f59f;ead17f6[331]<=rv94fdb;ead17f6[324]<=mr5154d[0];ead17f6[297]<=fp194a7;ead17f6[281]<=mt18435;ead17f6[273]<=xw6ce18;ead17f6[252]<=hq89aa9;ead17f6[233]<=iea6266[0];ead17f6[200]<=hqade13[1];ead17f6[185]<=blcdeb3;ead17f6[162]<=kf8a2a9[0];ead17f6[140]<=enc3086;ead17f6[136]<=kq6d9c3;ead17f6[126]<=wwd1355;ead17f6[116]<=nt94c4c;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[1]};ep7d4e<=vx8bfb1[2];gq3ea74<=vx8bfb1[3];ykf53a0<={ux17d83>>1,vx8bfb1[4]};iea9d00<={ea67ca6>>1,vx8bfb1[5]};ip4e800<={aa3e531>>1,vx8bfb1[6]};th74004<=vx8bfb1[7];xla0026<=vx8bfb1[8];wy137<={iea6266>>1,vx8bfb1[9]};uk9b8<=vx8bfb1[10];je4dc1<=vx8bfb1[11];an26e0b<={yk4cc03>>1,vx8bfb1[12]};xl3705d<=vx8bfb1[13];fcb82ef<=vx8bfb1[14];qgc177a<=vx8bfb1[15];zmbbd0<=vx8bfb1[16];xw5de82<=vx8bfb1[17];osef412<=vx8bfb1[18];en7a090<=vx8bfb1[19];ned0485<=vx8bfb1[20];mg8242b<=vx8bfb1[21];ba99e94<=vx8bfb1[22];dmda67a<={end69f2>>1,vx8bfb1[23]};oh85664<=vx8bfb1[24];lf3699<=vx8bfb1[25];go59920<=vx8bfb1[26];kdcc900<=vx8bfb1[27];nr64805<=vx8bfb1[28];qi2402e<=vx8bfb1[29];mrd33d2<=vx8bfb1[30];qib8b<=vx8bfb1[31];co5c59<=vx8bfb1[32];uk2e2c9<=vx8bfb1[33];bl71648<=vx8bfb1[34];jr8b246<=vx8bfb1[35];cm59237<=vx8bfb1[36];ipc91b9<=vx8bfb1[37];rg48dcc<={oua96af>>1,vx8bfb1[38]};twea8d<=vx8bfb1[39];cz7546a<=vx8bfb1[40];rvaa354<=vx8bfb1[41];cz51aa6<=vx8bfb1[42];ym8d534<=vx8bfb1[43];qt6a9a0<=vx8bfb1[44];yx54d05<=vx8bfb1[45];swa682c<=vx8bfb1[46];ie34161<={hqade13>>1,vx8bfb1[47]};nta0b08<={al6f09a>>1,vx8bfb1[48]};end +always@* begin ead17f6[2047]<=oub66fd[0];ead17f6[2046]<=ksb37e9;ead17f6[2044]<=hd9bf49;ead17f6[2040]<=ux17d83[0];ead17f6[2033]<=ea67ca6[0];ead17f6[2019]<=aa3e531[0];ead17f6[1991]<=ipf2989;ead17f6[1934]<=nt94c4c;ead17f6[1929]<=hqade13[1];ead17f6[1898]<=an80652;ead17f6[1821]<=iea6266[0];ead17f6[1810]<=al6f09a[1];ead17f6[1749]<=db3294;ead17f6[1707]<=xw529fb;ead17f6[1666]<=zk47c2f;ead17f6[1630]<=ww670c2;ead17f6[1595]<=co31330;ead17f6[1506]<=ou10d6f;ead17f6[1450]<=fp194a7;ead17f6[1440]<=gbd91f0;ead17f6[1384]<=nt9b647;ead17f6[1370]<=hqa7cad;ead17f6[1366]<=rv94fdb;ead17f6[1284]<=sw3e17a;ead17f6[1212]<=nt38610;ead17f6[1142]<=pu89980;ead17f6[1125]<=gb6aa5a;ead17f6[1041]<=ir85e89;ead17f6[1023]<=mr_main_reset;ead17f6[964]<=ri86b78;ead17f6[949]<=ng300ca;ead17f6[853]<=faca53f;ead17f6[833]<=pfc8f85;ead17f6[815]<=xw6ce18;ead17f6[753]<=mt18435;ead17f6[720]<=tj275a7;ead17f6[692]<=end69f2[0];ead17f6[685]<=pua7ede;ead17f6[562]<=ne4d54b;ead17f6[520]<=uxb4f95;ead17f6[474]<=tu66019;ead17f6[407]<=kq6d9c3;ead17f6[376]<=enc3086;ead17f6[281]<=hq89aa9;ead17f6[237]<=yk4cc03[0];ead17f6[203]<=oua96af[0];ead17f6[140]<=wwd1355;ead17f6[70]<=cz7a26a;ead17f6[35]<=ri2f44d;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[1]};ep7d4e<=vx8bfb1[2];gq3ea74<=vx8bfb1[3];ip4e800<={aa3e531>>1,vx8bfb1[4]};th74004<=vx8bfb1[5];xla0026<=vx8bfb1[6];mg8242b<=vx8bfb1[7];ba99e94<=vx8bfb1[8];dmda67a<={end69f2>>1,vx8bfb1[9]};oh85664<=vx8bfb1[10];lf3699<=vx8bfb1[11];go59920<=vx8bfb1[12];kdcc900<=vx8bfb1[13];nr64805<=vx8bfb1[14];mrd33d2<=vx8bfb1[15];co5c59<=vx8bfb1[16];uk2e2c9<=vx8bfb1[17];bl71648<=vx8bfb1[18];jr8b246<=vx8bfb1[19];cm59237<=vx8bfb1[20];ipc91b9<=vx8bfb1[21];twea8d<=vx8bfb1[22];cz7546a<=vx8bfb1[23];rvaa354<=vx8bfb1[24];cz51aa6<=vx8bfb1[25];end +always@* begin ead17f6[2047]<=oub66fd[0];ead17f6[2046]<=ksb37e9;ead17f6[2044]<=hd9bf49;ead17f6[2040]<=aa3e531[0];ead17f6[2033]<=ipf2989;ead17f6[2019]<=nt94c4c;ead17f6[1990]<=pua7ede;ead17f6[1939]<=wwd1355;ead17f6[1933]<=hqa7cad;ead17f6[1831]<=hq89aa9;ead17f6[1819]<=end69f2[0];ead17f6[1778]<=uxb4f95;ead17f6[1615]<=ne4d54b;ead17f6[1591]<=nt9b647;ead17f6[1508]<=ri2f44d;ead17f6[1271]<=ww670c2;ead17f6[1182]<=gb6aa5a;ead17f6[1135]<=tj275a7;ead17f6[1023]<=mr_main_reset;ead17f6[969]<=cz7a26a;ead17f6[889]<=zk47c2f;ead17f6[635]<=xw6ce18;ead17f6[495]<=nt38610;ead17f6[444]<=pfc8f85;ead17f6[317]<=kq6d9c3;ead17f6[222]<=gbd91f0;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[4]};yz3357c<={aa2e5>>1,vx8bfb1[5]};oh9abe5<=vx8bfb1[6];zkd5f2d<=vx8bfb1[7];dbaf96a<={rv28481>>1,vx8bfb1[8]};xw7cb57<=vx8bfb1[9];ice5abb<=vx8bfb1[10];byda6c1<={xlbf6fc>>1,vx8bfb1[11]};wjd360a<={jcfb7e7>>1,vx8bfb1[12]};wy3b4d8<={gbf7edf>>1,vx8bfb1[13]};ohbb1ea<=vx8bfb1[14];rtd8f55<=vx8bfb1[15];vvc7aae<=vx8bfb1[16];ph3d576<={ba2f3a0>>1,vx8bfb1[17]};sueabb6<={dm79d02>>1,vx8bfb1[18]};pf55db1<=vx8bfb1[19];anaed8e<=vx8bfb1[20];zk76c75<=vx8bfb1[21];qte721f<=vx8bfb1[22];qv390fc<=vx8bfb1[23];vx8ea8d<=vx8bfb1[24];sh7546e<=vx8bfb1[25];cm43f26<={uk10b14>>1,vx8bfb1[26]};end +always@* begin ead17f6[2047]<=force_unidir;ead17f6[2046]<=tx_en;ead17f6[2044]<=tx_er;ead17f6[2040]<=en6005c[0];ead17f6[2032]<=aa2e5[0];ead17f6[2017]<=ba1728;ead17f6[1987]<=yk5ca12;ead17f6[1927]<=rv28481[0];ead17f6[1865]<=yke5e74;ead17f6[1806]<=fa4240f;ead17f6[1682]<=ba2f3a0[0];ead17f6[1565]<=ux1207b;ead17f6[1326]<=uk10b14[1];ead17f6[1317]<=dm79d02[0];ead17f6[1189]<=ps7c42c;ead17f6[1172]<=nr74098;ead17f6[1082]<=xlbf6fc[0];ead17f6[1023]<=mr_main_reset;ead17f6[932]<=ipdcbce;ead17f6[663]<=alc6f70;ead17f6[594]<=yz8f885;ead17f6[586]<=eace813;ead17f6[466]<=hb7b979;ead17f6[331]<=ie98dee;ead17f6[297]<=bna04c6;ead17f6[233]<=gbf7edf[0];ead17f6[116]<=jcfb7e7[0];end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[1]};zz9bd9a<=vx8bfb1[2];icdecd7<=vx8bfb1[3];fnf66b9<=vx8bfb1[4];qib35cf<=vx8bfb1[5];cb9ae79<=vx8bfb1[6];jpd73cd<={wj7f18d>>1,vx8bfb1[7]};cob9e6e<=vx8bfb1[8];xwcf371<=vx8bfb1[9];lq79b8b<={ou31b6d>>1,vx8bfb1[10]};thcdc5b<={ks8db69>>1,vx8bfb1[11]};hb6e2df<={kq6db49>>1,vx8bfb1[12]};bl716fe<={ww6da48>>1,vx8bfb1[13]};jr8b7f6<=vx8bfb1[14];en5bfb7<=vx8bfb1[15];xwdfdbd<=vx8bfb1[16];tufedeb<=vx8bfb1[17];blf6f5a<=vx8bfb1[18];hqb7ad6<=vx8bfb1[19];dobd6b2<=vx8bfb1[20];byeb592<=vx8bfb1[21];fn5ac92<=vx8bfb1[22];gbd6497<=vx8bfb1[23];end +always@* begin ead17f6[2047]<=gq10304[0];ead17f6[2046]<=lf81821;ead17f6[2044]<=rvc10f;ead17f6[2040]<=mr6087e;ead17f6[2032]<=je43f4;ead17f6[2016]<=cm62617;ead17f6[1985]<=wj7f18d[0];ead17f6[1922]<=czf8c6d;ead17f6[1796]<=yxc636d;ead17f6[1544]<=ou31b6d[6];ead17f6[1302]<=ho58593;ead17f6[1115]<=fp164de;ead17f6[1105]<=vi48058;ead17f6[1041]<=ks8db69[0];ead17f6[1023]<=hbec4c2;ead17f6[651]<=dob0b2;ead17f6[557]<=xjc2c9b;ead17f6[552]<=cm4900b;ead17f6[325]<=xy1616;ead17f6[276]<=ho69201;ead17f6[162]<=th402c2;ead17f6[138]<=os6d240;ead17f6[69]<=ww6da48[0];ead17f6[34]<=kq6db49[6];end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd>1,vx8bfb1[7]};fa69a8f<={rx_data>>1,vx8bfb1[8]};jc4d47a<=vx8bfb1[9];ep8f4a4<=vx8bfb1[10];ecac00<=vx8bfb1[11];kq56000<=vx8bfb1[12];ntb0000<=vx8bfb1[13];an80006<={tx_d>>1,vx8bfb1[14]};qt7099a<=vx8bfb1[15];db84cd5<=vx8bfb1[16];co5a5e<=vx8bfb1[17];ri14169<=vx8bfb1[18];vxa0b4b<=vx8bfb1[19];qt7a525<={tu69a7f>>1,vx8bfb1[20]};ym387<={xj45a69>>1,vx8bfb1[21]};ls1c38<={jr2d34f>>1,vx8bfb1[22]};al6a3d2<=vx8bfb1[23];al70e1b<={eafa8aa>>1,vx8bfb1[24]};co870dd<=vx8bfb1[25];xl386e9<=vx8bfb1[26];gbc374e<=vx8bfb1[27];ba1ba75<=vx8bfb1[28];bldd3ab<=vx8bfb1[29];ble9d5f<=vx8bfb1[30];en4eafe<=vx8bfb1[31];icfae0d<=vx8bfb1[32];rtd7068<=vx8bfb1[33];pub8346<=vx8bfb1[34];suc1a32<=vx8bfb1[35];uxd191<=vx8bfb1[36];ic68c8c<=vx8bfb1[37];do25e9c<=vx8bfb1[38];pu2f4e2<=vx8bfb1[39];mr7a712<=vx8bfb1[40];ald3895<=vx8bfb1[41];ng9c4ad<=vx8bfb1[42];she256b<=vx8bfb1[43];gd12b5c<=vx8bfb1[44];kf95ae5<={xw52757>>1,vx8bfb1[45]};lsad72c<=vx8bfb1[46];ld6b963<=vx8bfb1[47];ic5cb1f<={kqeae99>>1,vx8bfb1[48]};yke58f8<=vx8bfb1[49];cb2c7c0<=vx8bfb1[50];ps63e05<=vx8bfb1[51];ks1f02b<=vx8bfb1[52];qtf8158<=vx8bfb1[53];byc0ac4<=vx8bfb1[54];mg5623<={jpe3998>>1,vx8bfb1[55]};sw2b118<=vx8bfb1[56];jc588c0<=vx8bfb1[57];goc4602<=vx8bfb1[58];yz23010<=vx8bfb1[59];cb18084<=vx8bfb1[60];end +always@* begin ead17f6[2047]<=sgmii_mode;ead17f6[2046]<=signal_detect;ead17f6[2044]<=debug_link_timer_short;ead17f6[2040]<=force_isolate;ead17f6[2032]<=force_loopback;ead17f6[2017]<=force_unidir;ead17f6[1987]<=operational_rate[0];ead17f6[1926]<=rx_data[0];ead17f6[1805]<=vk2fa8d;ead17f6[1804]<=rx_kcntl;ead17f6[1803]<=tj3d21d;ead17f6[1761]<=hq1e17d;ead17f6[1668]<=cz51293;ead17f6[1562]<=kq7d46b;ead17f6[1560]<=rx_even;ead17f6[1558]<=eafa8aa[0];ead17f6[1550]<=tx_er;ead17f6[1475]<=qgf0bea;ead17f6[1464]<=dob3be;ead17f6[1288]<=do8949d;ead17f6[1242]<=ep331f6;ead17f6[1076]<=eaea358;ead17f6[1072]<=rx_disp_err;ead17f6[1069]<=icd4550;ead17f6[1056]<=xw52757[0];ead17f6[1052]<=mr_an_enable;ead17f6[1028]<=tjba64a;ead17f6[1023]<=gbe_mode;ead17f6[902]<=cb85f51;ead17f6[901]<=jr2d34f[0];ead17f6[880]<=go59df3;ead17f6[874]<=blc7da8;ead17f6[834]<=zkca252;ead17f6[775]<=tx_en;ead17f6[732]<=xl81677;ead17f6[621]<=vve663e;ead17f6[528]<=fn4a4ea;ead17f6[514]<=by574c9;ead17f6[450]<=xj45a69[0];ead17f6[437]<=ie98fb5;ead17f6[417]<=tu7944a;ead17f6[387]<=tx_d[0];ead17f6[366]<=bl502ce;ead17f6[310]<=rv1ccc7;ead17f6[257]<=kqeae99[0];ead17f6[225]<=tu69a7f[0];ead17f6[208]<=do2f289;ead17f6[193]<=rx_err_decode_mode;ead17f6[183]<=hdaa059;ead17f6[155]<=jpe3998[0];ead17f6[128]<=wy9d5d3;ead17f6[112]<=mr_restart_an;ead17f6[104]<=qi5e51;ead17f6[96]<=rx_cv_err;ead17f6[91]<=zma2a81;ead17f6[77]<=ukbc733;ead17f6[64]<=ls93aba;ead17f6[56]<=mr_main_reset;ead17f6[38]<=by578e6;ead17f6[19]<=pu992bc;ead17f6[9]<=end3257;end assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd0mo|GyGHJ*@8$FYaWC-+RmMkWj|M#8huD-YG*2v@cd#1kcoO91T z_uO;ut*)xc=JJKwikhhv@_$v^RkvPw>&Ghs+0GoVuetWlnO9$n%Y2BJ zSKoT=mA79TyM5+O*WPyfl{ZBzq~$RI^7pKHPhbq~u(>fbz;*_Ddjb^|r~WRm_Lc}O zwA3$H7@J%XSY4gO<(P#_V-0l+>t;>=VEB_4*1WGGu;qgZ;MSrAHL?2ESZypEtE;UD zYgEq~op@~!S zWn{rZk=pv!q>9DD5PJt(vduNY9r(BPbj21lX>Ic}3P!#Bf}o=(ZU}f?S;_`sE`MEA zmlT6*o{c*wGh%LItZ{MUf{MT^r$rosHflutm64Q=vbk4Ii@QKHxB1j8Ks$7bVZ`tj zXpHC%)<{^k1(HS;j9$ltj6=bKh<8lNs~9}7CVVsts8R-{ZqdT#1&wpzNmA9FdG$4u zr`sblIj-mnE@8hn?7-zQXFu023W2f5sOEn0VeS1v1)|XEok{rbXMg3jhO45(`^6dqynE1eUbK zWCR&|@p@#uiq|^$`VWU}`NjpYriws&ERIWY$W}X<*ClhJ#vYHH4zvtY)EaX~Ld9Yq zv(Y<4Ix6b#2x=fLj*Tl&4gI5J+mAB>vv<=W^=|vJ)H{s-n45K|*z7I3xsQplUnCr3 znENB|%*tianDn>przuBd2Acn#ZJf@-|{H|GdXsjw<`#N~2M>wG7?ZI1;V z5q9UMf^%8J>r|OW%C~)8p(`w_D&!bk&>Cx!lE+N2tno=NgG{z6I^zyuhtLYVBcnl( z3Y;EQAxW+cf3RJ#OJfT8 zQewky<#%DxDz<`A*zix94J;`lNZ}3tS5OheeZ!wJDuU2&ctNu>1<3lKDud~>VP#51 zxL9n7st7ujJ1=e{sK2d?X0xB`|4>kb2&_`=z`^z12}J_ltbbhv5W4kyqKX6(cl}n? z2D-GqO;v&a>rbcvlViOW8Lnr~t5(s&+~s+@nWFbFle;aXK}_Ng7c^*o>ukts?Dd-7vbWT_Ch2Ik zG|uHL%ta#_M5pf5A@n+T4}_Rkhz%9l!H*<0h#h=?M1$zmWk3`~I`QGG1~JZ)bt(3_ zPM2bD)&_EpCSAWE;#|@x_V-}iftUsZ3Av2Tl|2jkw&qVkM}YFn%NF77noUWEr4Iv& zaO^h7um4X}HHgS;7-L%~Hi5vb-Axj^)1!@u1|nLBITl8oACLz+6n|CPK3 z!JmzLf!N7p_mP_Wbg>prmq6Sl2e&tVBdviPgIysFYN6O;SqV=AdZjPb@+T@28s<5`GVi<_GoV)x;oR9c%i+?OhXlj?vK5R-r3TaB?nIn{&(AAn!;zK-lQ-FaLZS-5SAMs zt#wOcIN`=-UUTEM(`Alq?akYkCdcFySv+^&j5{-hSKf?AQ%hrc3GDp0pw~?0yodi& z<8Mm1IPxD!zd30bK0os2L}ORqa>wlzfnAS8ZTZ?*-GW%-g1XuB8s#?E+(rZ-ohXs5 z3+on^h}g~7@~9Lb$qv`XTIypBVZeyBoWQ)X#ze9LpNiNDH8D98)f6i$4rX<{9o39^ z|LQ5}l1$5@2Hs^`FsErQ&*C8azMl0XIZ=nYNK4x&r1R_QrGTM=PJ{6})>Pi`+S^ea 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b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.v @@ -0,0 +1,230 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`define SGMII_YES_SINGLE_CLOCK + +module sgmii_channel_smi_core ( + + // Control Interface + rst_n, + signal_detect, + gbe_mode, + sgmii_mode, + operational_rate, + debug_link_timer_short, + force_isolate, + force_loopback, + force_unidir, + + rx_compensation_err, + ctc_drop_flag, + ctc_add_flag, + an_link_ok, + + // G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + tx_clock_enable_sink , + tx_clock_enable_source , + + rx_clock_enable_sink , + rx_clock_enable_source , +`else + tx_clk_mii , + rx_clk_mii , +`endif + tx_clk_125, + tx_d, + tx_en, + tx_er, + + rx_clk_125, + rx_d, + rx_dv, + rx_er, + col, + crs, + + // 8-bit Interface + tx_data, + tx_kcntl, + tx_disparity_cntl, + xmit_autoneg, + + serdes_recovered_clk, + rx_data, + rx_kcntl, + rx_even , + rx_disp_err , + rx_cv_err , + rx_err_decode_mode , + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability + ); + + + +// Control Interface +input rst_n ; +input signal_detect ; +input gbe_mode ; +input sgmii_mode ; +input [1:0] operational_rate ; +input debug_link_timer_short ; +input force_isolate ; +input force_loopback ; +input force_unidir ; + +output rx_compensation_err ; +output ctc_drop_flag ; +output ctc_add_flag ; +output an_link_ok ; + +// G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + input tx_clock_enable_sink; + output tx_clock_enable_source; + + input rx_clock_enable_sink; + output rx_clock_enable_source; +`else + input tx_clk_mii; + input rx_clk_mii; +`endif + +input tx_clk_125 ; +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +input rx_clk_125 ; +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// 8-bit Interface +output [7:0] tx_data ; +output tx_kcntl; +output tx_disparity_cntl; +output xmit_autoneg; + +input serdes_recovered_clk ; +input [7:0] rx_data ; +input rx_even ; +input rx_kcntl; +input rx_disp_err ; // Displarity error on "rx_data". +input rx_cv_err ; // Code error on "rx_data". +input rx_err_decode_mode ; + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + + +parameter STATIC_HI_THRESH = 32; +parameter STATIC_LO_THRESH = 16; +parameter LINK_TIMER_SH = 21'h1fff01; + + + +// SGMII PCS +sgmii_pcs_gda_001 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH), .LINK_TIMER_SH(LINK_TIMER_SH)) sgmii_pcs_gda_001 ( + // Clock and Reset + .rst_n ( rst_n ) , + .signal_detect ( signal_detect ) , + .gbe_mode ( gbe_mode ) , + .sgmii_mode ( sgmii_mode ) , + .operational_rate ( operational_rate ) , + .debug_link_timer_short ( debug_link_timer_short ) , + .force_isolate ( force_isolate ) , + .force_loopback ( force_loopback ) , + .force_unidir ( force_unidir ) , + + .rx_compensation_err ( rx_compensation_err ) , + .ctc_drop_flag ( ctc_drop_flag ) , + .ctc_add_flag ( ctc_add_flag ) , + .an_link_ok ( an_link_ok ) , + +`ifdef SGMII_YES_SINGLE_CLOCK + .tx_clock_enable_sink ( tx_clock_enable_sink ), + .tx_clock_enable_source ( tx_clock_enable_source ), + + .rx_clock_enable_sink ( rx_clock_enable_sink ), + .rx_clock_enable_source ( rx_clock_enable_source ), +`else + .tx_clk_mii ( tx_clk_mii ), + .rx_clk_mii ( rx_clk_mii ), +`endif + + // GMII TX Inputs + .tx_clk_125 ( tx_clk_125 ) , + .tx_d ( tx_d) , + .tx_en ( tx_en) , + .tx_er ( tx_er) , + + // GMII RX Outputs + // To GMII/MAC interface + .rx_clk_125 ( rx_clk_125 ) , + .rx_d ( rx_d ) , + .rx_dv ( rx_dv ) , + .rx_er ( rx_er ) , + .col ( col ) , + .crs ( crs ) , + + // 8BI TX Outputs + .tx_data ( tx_data) , + .tx_kcntl ( tx_kcntl) , + .tx_disparity_cntl ( tx_disparity_cntl) , + .xmit_autoneg ( xmit_autoneg) , + + // 8BI RX Inputs + .serdes_recovered_clk ( serdes_recovered_clk ) , + .rx_data ( rx_data ) , + .rx_kcntl ( rx_kcntl ) , + .rx_even ( rx_even ) , + .rx_disp_err ( rx_disp_err ) , + .rx_cv_err ( rx_cv_err ) , + .rx_err_decode_mode ( rx_err_decode_mode ) , + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core_bb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core_bb.v new file mode 100644 index 0000000..553fb71 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core_bb.v @@ -0,0 +1,152 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`define SGMII_YES_SINGLE_CLOCK + +module sgmii_channel_smi_core ( + + // Control Interface + rst_n, + signal_detect, + gbe_mode, + sgmii_mode, + operational_rate, + debug_link_timer_short, + force_isolate, + force_loopback, + force_unidir, + + rx_compensation_err, + ctc_drop_flag, + ctc_add_flag, + an_link_ok, + + // G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + tx_clock_enable_sink , + tx_clock_enable_source , + + rx_clock_enable_sink , + rx_clock_enable_source , +`else + tx_clk_mii , + rx_clk_mii , +`endif + tx_clk_125, + tx_d, + tx_en, + tx_er, + + rx_clk_125, + rx_d, + rx_dv, + rx_er, + col, + crs, + + // 8-bit Interface + tx_data, + tx_kcntl, + tx_disparity_cntl, + xmit_autoneg, + + serdes_recovered_clk, + rx_data, + rx_kcntl, + rx_even , + rx_disp_err , + rx_cv_err , + rx_err_decode_mode , + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability + ); + + + +// Control Interface +input rst_n ; +input signal_detect ; +input gbe_mode ; +input sgmii_mode ; +input [1:0] operational_rate ; +input debug_link_timer_short ; +input force_isolate ; +input force_loopback ; +input force_unidir ; + +output rx_compensation_err ; +output ctc_drop_flag ; +output ctc_add_flag ; +output an_link_ok ; + +// G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + input tx_clock_enable_sink; + output tx_clock_enable_source; + + input rx_clock_enable_sink; + output rx_clock_enable_source; +`else + input tx_clk_mii; + input rx_clk_mii; +`endif + +input tx_clk_125 ; +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +input rx_clk_125 ; +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// 8-bit Interface +output [7:0] tx_data ; +output tx_kcntl; +output tx_disparity_cntl; +output xmit_autoneg; + +input serdes_recovered_clk ; +input [7:0] rx_data ; +input rx_even ; +input rx_kcntl; +input rx_disp_err ; // Displarity error on "rx_data". +input rx_cv_err ; // Code error on "rx_data". +input rx_err_decode_mode ; + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_ngd.asd b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_ngd.asd new file mode 100644 index 0000000..02edbf1 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_ngd.asd @@ -0,0 +1,2 @@ +[ActiveSupport NGD] +IP_1 = LSC_IP_SC_HT_SGMII diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs.v new file mode 100644 index 0000000..32eab38 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs.v @@ -0,0 +1,476 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 +// Netlist written on Tue Apr 30 12:09:53 2019 +// +// Verilog Description of module sgmii_channel_smi_pcs +// + +`timescale 1ns/1ps +module sgmii_channel_smi_pcs (hdoutp, hdoutn, hdinp, + hdinn, rxrefclk, rx_pclk, txi_clk, tx_pclk, txdata, + tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, + rx_cv_err, signal_detect_c, lsm_status_s, rx_cdr_lol_s, + sli_rst, tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, + sci_rddata, sci_en_dual, sci_sel_dual, sci_en, sci_sel, + sci_rd, sci_wrn, sci_int, cyawstn, serdes_pdb, pll_refclki, + rsl_disable, rsl_rst, serdes_rst_dual_c, rst_dual_c, tx_serdes_rst_c, + tx_pcs_rst_c, pll_lol, rx_serdes_rst_c, rx_pcs_rst_c); + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output rx_pclk; + input txi_clk; + output tx_pclk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + input signal_detect_c; + output lsm_status_s; + output rx_cdr_lol_s; + input sli_rst; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input serdes_pdb; + input pll_refclki; + input rsl_disable; + input rsl_rst; + input serdes_rst_dual_c; + input rst_dual_c; + input tx_serdes_rst_c; + input tx_pcs_rst_c; + output pll_lol; + input rx_serdes_rst_c; + input rx_pcs_rst_c; + + + wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, + n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, + n22, n23, n24, n25, n26, n27, n28, n29, rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c, rsl_rx_serdes_rst_c, rsl_rst_dual_c, rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c, n30, n31, n32, n33, n34, n35, n36, + n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, + n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, + n57, n60, n61, n62, n63, n64, n65, n66, n67, n68, + n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, + n99, n100, n101, n102, n103, n104, n105, n116, n117, + n118, n119, n120, n121, n122, n123, n124, n125, n126, + _Z; + + DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), + .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), + .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(rx_pclk), .CH1_FF_RXI_CLK(1'b1), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(1'b1), + .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), + .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), + .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0), + .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), + .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), + .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), + .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), + .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), + .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), + .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), + .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), + .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), + .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), + .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), + .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), + .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0), + .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0), + .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0), + .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0), + .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0), + .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0), + .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0), + .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0), + .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), + .D_FFC_DUAL_RST(rsl_rst_dual_c), .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(1'b0), .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), + .D_SCAN_IN_0(1'b0), .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), + .D_SCAN_IN_4(1'b0), .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), + .D_SCAN_MODE(1'b0), .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), + .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), + .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), + .D_CIN10(1'b0), .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n61), + .CH0_HDOUTN(hdoutn), .CH1_HDOUTN(n62), .D_TXBIT_CLKP_TO_ND(n1), + .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), + .CH0_FF_RX_F_CLK(n5), .CH1_FF_RX_F_CLK(n63), .CH0_FF_RX_H_CLK(n6), + .CH1_FF_RX_H_CLK(n64), .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n65), + .CH0_FF_TX_H_CLK(n8), .CH1_FF_TX_H_CLK(n66), .CH0_FF_RX_PCLK(rx_pclk), + .CH1_FF_RX_PCLK(n67), .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n68), + .CH0_FF_RX_D_0(rxdata[0]), .CH1_FF_RX_D_0(n69), .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n70), .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n71), + .CH0_FF_RX_D_3(rxdata[3]), .CH1_FF_RX_D_3(n72), .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n73), .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n74), + .CH0_FF_RX_D_6(rxdata[6]), .CH1_FF_RX_D_6(n75), .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n76), .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n77), + .CH0_FF_RX_D_9(rx_disp_err[0]), .CH1_FF_RX_D_9(n78), .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n79), .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n80), + .CH0_FF_RX_D_12(n10), .CH1_FF_RX_D_12(n81), .CH0_FF_RX_D_13(n11), + .CH1_FF_RX_D_13(n82), .CH0_FF_RX_D_14(n12), .CH1_FF_RX_D_14(n83), + .CH0_FF_RX_D_15(n13), .CH1_FF_RX_D_15(n84), .CH0_FF_RX_D_16(n14), + .CH1_FF_RX_D_16(n85), .CH0_FF_RX_D_17(n15), .CH1_FF_RX_D_17(n86), + .CH0_FF_RX_D_18(n16), .CH1_FF_RX_D_18(n87), .CH0_FF_RX_D_19(n17), + .CH1_FF_RX_D_19(n88), .CH0_FF_RX_D_20(n18), .CH1_FF_RX_D_20(n89), + .CH0_FF_RX_D_21(n19), .CH1_FF_RX_D_21(n90), .CH0_FF_RX_D_22(n20), + .CH1_FF_RX_D_22(n91), .CH0_FF_RX_D_23(n21), .CH1_FF_RX_D_23(n92), + .CH0_FFS_PCIE_DONE(n22), .CH1_FFS_PCIE_DONE(n93), .CH0_FFS_PCIE_CON(n23), + .CH1_FFS_PCIE_CON(n94), .CH0_FFS_RLOS(n95), .CH1_FFS_RLOS(n96), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), .CH1_FFS_LS_SYNC_STATUS(n97), + .CH0_FFS_CC_UNDERRUN(n24), .CH1_FFS_CC_UNDERRUN(n98), .CH0_FFS_CC_OVERRUN(n25), + .CH1_FFS_CC_OVERRUN(n99), .CH0_FFS_RXFBFIFO_ERROR(n26), .CH1_FFS_RXFBFIFO_ERROR(n100), + .CH0_FFS_TXFBFIFO_ERROR(n27), .CH1_FFS_TXFBFIFO_ERROR(n101), .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n102), .CH0_FFS_SKP_ADDED(n28), .CH1_FFS_SKP_ADDED(n103), + .CH0_FFS_SKP_DELETED(n29), .CH1_FFS_SKP_DELETED(n104), .CH0_LDR_RX2CORE(n105), + .CH1_LDR_RX2CORE(n116), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), .D_SCAN_OUT_0(n30), .D_SCAN_OUT_1(n31), .D_SCAN_OUT_2(n32), + .D_SCAN_OUT_3(n33), .D_SCAN_OUT_4(n34), .D_SCAN_OUT_5(n35), .D_SCAN_OUT_6(n36), + .D_SCAN_OUT_7(n37), .D_COUT0(n38), .D_COUT1(n39), .D_COUT2(n40), + .D_COUT3(n41), .D_COUT4(n42), .D_COUT5(n43), .D_COUT6(n44), + .D_COUT7(n45), .D_COUT8(n46), .D_COUT9(n47), .D_COUT10(n48), + .D_COUT11(n49), .D_COUT12(n50), .D_COUT13(n51), .D_COUT14(n52), + .D_COUT15(n53), .D_COUT16(n54), .D_COUT17(n55), .D_COUT18(n56), + .D_COUT19(n57), .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n60)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; + defparam DCU0_inst.D_MACROPDB = "0b1"; + defparam DCU0_inst.D_IB_PWDNB = "0b1"; + defparam DCU0_inst.D_XGE_MODE = "0b0"; + defparam DCU0_inst.D_LOW_MARK = "0d4"; + defparam DCU0_inst.D_HIGH_MARK = "0d12"; + defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; + defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; + defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; + defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; + defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; + defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; + defparam DCU0_inst.CH0_UC_MODE = "0b0"; + defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; + defparam DCU0_inst.CH0_RIO_MODE = "0b0"; + defparam DCU0_inst.CH0_WA_MODE = "0b0"; + defparam DCU0_inst.CH0_INVERT_RX = "0b0"; + defparam DCU0_inst.CH0_INVERT_TX = "0b0"; + defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; + defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b1"; + defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; + defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; + defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; + defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; + defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; + defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; + defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_CTC_BYPASS = "0b1"; + defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; + defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b0"; + defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; + defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; + defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_3 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_4 = "0x000"; + defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; + defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; + defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; + defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b000"; + defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; + defparam DCU0_inst.CH0_TPWDNB = "0b1"; + defparam DCU0_inst.CH0_RATE_MODE_TX = "0b1"; + defparam DCU0_inst.CH0_RTERM_TX = "0d19"; + defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; + defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b011"; + defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; + defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; + defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; + defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH0_RPWDNB = "0b1"; + defparam DCU0_inst.CH0_RATE_MODE_RX = "0b1"; + defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b1"; + defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; + defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; + defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; + defparam DCU0_inst.CH0_REQ_LVL_SET = "0b01"; + defparam DCU0_inst.CH0_REQ_EN = "0b1"; + defparam DCU0_inst.CH0_RTERM_RX = "0d22"; + defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; + defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; + defparam DCU0_inst.CH0_RXIN_CM = "0b11"; + defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; + defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; + defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; + defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010"; + defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; + defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; + defparam DCU0_inst.CH0_RX_LOS_EN = "0b0"; + defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; + defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; + defparam DCU0_inst.D_TX_MAX_RATE = "2.5"; + defparam DCU0_inst.CH0_CDR_MAX_RATE = "2.5"; + defparam DCU0_inst.CH0_TXAMPLITUDE = "0d6"; + defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; + defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; + defparam DCU0_inst.CH0_PROTOCOL = "SGMII"; + defparam DCU0_inst.D_ISETLOS = "0d0"; + defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; + defparam DCU0_inst.D_SETICONST_AUX = "0b00"; + defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; + defparam DCU0_inst.D_SETICONST_CH = "0b00"; + defparam DCU0_inst.D_REQ_ISET = "0b000"; + defparam DCU0_inst.D_PD_ISET = "0b00"; + defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; + defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; + defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; + defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; + defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; + defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; + defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; + defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; + defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; + defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; + defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; + defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; + defparam DCU0_inst.CH0_DCOITUNE = "0b00"; + defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; + defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; + defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; + defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; + defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; + defparam DCU0_inst.CH0_DCOSTEP = "0b00"; + defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; + defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; + defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; + defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; + defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; + defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; + defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; + defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; + defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; + defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; + defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; + defparam DCU0_inst.D_CMUSETZGM = "0b000"; + defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; + defparam DCU0_inst.D_CMUSETP1GM = "0b000"; + defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; + defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; + defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; + defparam DCU0_inst.D_CMUSETICP4P = "0b01"; + defparam DCU0_inst.D_CMUSETBIASI = "0b00"; + defparam DCU0_inst.D_SETPLLRC = "0d1"; + defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; + defparam DCU0_inst.D_REFCK_MODE = "0b000"; + defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000"; + defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; + defparam DCU0_inst.D_RG_EN = "0b0"; + defparam DCU0_inst.D_RG_SET = "0b00"; + assign n1 = 1'bz; + assign n2 = 1'bz; + assign n3 = 1'bz; + assign n4 = 1'bz; + assign n5 = 1'bz; + assign n6 = 1'bz; + assign n7 = 1'bz; + assign n8 = 1'bz; + assign n9 = 1'bz; + assign n10 = 1'bz; + assign n11 = 1'bz; + assign n12 = 1'bz; + assign n13 = 1'bz; + assign n14 = 1'bz; + assign n15 = 1'bz; + assign n16 = 1'bz; + assign n17 = 1'bz; + assign n18 = 1'bz; + assign n19 = 1'bz; + assign n20 = 1'bz; + assign n21 = 1'bz; + assign n22 = 1'bz; + assign n23 = 1'bz; + assign n24 = 1'bz; + assign n25 = 1'bz; + assign n26 = 1'bz; + assign n27 = 1'bz; + assign n28 = 1'bz; + assign n29 = 1'bz; + assign n30 = 1'bz; + assign n31 = 1'bz; + assign n32 = 1'bz; + assign n33 = 1'bz; + assign n34 = 1'bz; + assign n35 = 1'bz; + assign n36 = 1'bz; + assign n37 = 1'bz; + assign n38 = 1'bz; + assign n39 = 1'bz; + assign n40 = 1'bz; + assign n41 = 1'bz; + assign n42 = 1'bz; + assign n43 = 1'bz; + assign n44 = 1'bz; + assign n45 = 1'bz; + assign n46 = 1'bz; + assign n47 = 1'bz; + assign n48 = 1'bz; + assign n49 = 1'bz; + assign n50 = 1'bz; + assign n51 = 1'bz; + assign n52 = 1'bz; + assign n53 = 1'bz; + assign n54 = 1'bz; + assign n55 = 1'bz; + assign n56 = 1'bz; + assign n57 = 1'bz; + assign n60 = 1'bz; + assign n61 = 1'bz; + assign n62 = 1'bz; + assign n63 = 1'bz; + assign n64 = 1'bz; + assign n65 = 1'bz; + assign n66 = 1'bz; + assign n67 = 1'bz; + assign n68 = 1'bz; + assign n69 = 1'bz; + assign n70 = 1'bz; + assign n71 = 1'bz; + assign n72 = 1'bz; + assign n73 = 1'bz; + assign n74 = 1'bz; + assign n75 = 1'bz; + assign n76 = 1'bz; + assign n77 = 1'bz; + assign n78 = 1'bz; + assign n79 = 1'bz; + assign n80 = 1'bz; + assign n81 = 1'bz; + assign n82 = 1'bz; + assign n83 = 1'bz; + assign n84 = 1'bz; + assign n85 = 1'bz; + assign n86 = 1'bz; + assign n87 = 1'bz; + assign n88 = 1'bz; + assign n89 = 1'bz; + assign n90 = 1'bz; + assign n91 = 1'bz; + assign n92 = 1'bz; + assign n93 = 1'bz; + assign n94 = 1'bz; + assign n95 = 1'bz; + assign n96 = 1'bz; + assign n97 = 1'bz; + assign n98 = 1'bz; + assign n99 = 1'bz; + assign n100 = 1'bz; + assign n101 = 1'bz; + assign n102 = 1'bz; + assign n103 = 1'bz; + assign n104 = 1'bz; + assign n105 = 1'bz; + assign n116 = 1'bz; + sgmii_channel_smi_pcsrsl_core rsl_inst (.rui_rst(rsl_rst), .rui_serdes_rst_dual_c(serdes_rst_dual_c), + .rui_rst_dual_c(rst_dual_c), .rui_rsl_disable(rsl_disable), + .rui_tx_ref_clk(pll_refclki), .rui_tx_serdes_rst_c(tx_serdes_rst_c), + .rui_tx_pcs_rst_c({3'b000, tx_pcs_rst_c}), .rdi_pll_lol(pll_lol), + .rui_rx_ref_clk(rxrefclk), .rui_rx_serdes_rst_c({3'b000, rx_serdes_rst_c}), + .rui_rx_pcs_rst_c({3'b000, rx_pcs_rst_c}), .rdi_rx_los_low_s({4'b0000}), + .rdi_rx_cdr_lol_s({3'b000, rx_cdr_lol_s}), .rdo_serdes_rst_dual_c(rsl_serdes_rst_dual_c), + .rdo_rst_dual_c(rsl_rst_dual_c), .ruo_tx_rdy(n117), .rdo_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rdo_tx_pcs_rst_c({n118, n119, n120, rsl_tx_pcs_rst_c}), + .ruo_rx_rdy(n121), .rdo_rx_serdes_rst_c({n122, n123, n124, + rsl_rx_serdes_rst_c}), .rdo_rx_pcs_rst_c({n125, n126, _Z, + rsl_rx_pcs_rst_c})); + defparam rsl_inst.pnum_channels = 1; + defparam rsl_inst.pprotocol = "SGMII"; + defparam rsl_inst.pserdes_mode = "RX AND TX"; + defparam rsl_inst.pport_tx_rdy = "DISABLED"; + defparam rsl_inst.pwait_tx_rdy = 3000; + defparam rsl_inst.pport_rx_rdy = "DISABLED"; + defparam rsl_inst.pwait_rx_rdy = 3000; + assign n117 = 1'bz; + assign n118 = 1'bz; + assign n119 = 1'bz; + assign n120 = 1'bz; + assign n121 = 1'bz; + assign n122 = 1'bz; + assign n123 = 1'bz; + assign n124 = 1'bz; + assign n125 = 1'bz; + assign n126 = 1'bz; + assign _Z = 1'bz; + sgmii_channel_smi_pcssll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), + .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), + .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), + .slo_plol(pll_lol)); + defparam sll_inst.PPROTOCOL = "SGMII"; + defparam sll_inst.PLOL_SETTING = 0; + defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; + defparam sll_inst.PPCIE_MAX_RATE = "2.5"; + defparam sll_inst.PDIFF_VAL_LOCK = 19; + defparam sll_inst.PDIFF_VAL_UNLOCK = 39; + defparam sll_inst.PPCLK_TC = 65536; + defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; + defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; + defparam sll_inst.PPCLK_DIV11_TC = 0; + +endmodule + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v new file mode 100644 index 0000000..eb97d6c --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v @@ -0,0 +1,57 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.22, Attr. rev. 2.25 +// Netlist written on Mon Mar 10 15:35:03 2014 +// +// Verilog Description of module pcs_serdes +// + +`timescale 1ns/1ps +module sgmii_channel_smi_pcs (hdoutp, hdoutn, hdinp, hdinn, + rxrefclk, rx_pclk, tx_pclk, txdata, tx_k, xmit, tx_disp_correct, + rxdata, rx_k, rx_disp_err, rx_cv_err, lsm_status_s, rx_cdr_lol_s, + tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, tx_pwrup_c, + rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata, sci_en_dual, + sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn, sci_int, + cyawstn,rst_dual_c, serdes_rst_dual_c, serdes_pdb, tx_serdes_rst_c, + pll_refclki, pll_lol) /*synthesis syn_black_box black_box_pad_pin="hdoutp,hdoutn,hdinp,hdinn"*/; + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output rx_pclk; + output tx_pclk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + output lsm_status_s; + output rx_cdr_lol_s; + input tx_pcs_rst_c; + input rx_pcs_rst_c; + input rx_serdes_rst_c; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input rst_dual_c; + input serdes_rst_dual_c; + input serdes_pdb; + input tx_serdes_rst_c; + input pll_refclki; + output pll_lol; + + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_defines.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_defines.v new file mode 100644 index 0000000..ef2ca4e --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_defines.v @@ -0,0 +1,4 @@ +`define SGMII_NO_ENC +`define SGMII_YES_CTC_DYNAMIC +`define SGMII_YES_SINGLE_CLOCK +`define SGMII_FIFO_FAMILY_ECP5 diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.lpc b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.lpc new file mode 100644 index 0000000..40438e0 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.lpc @@ -0,0 +1,97 @@ +[Device] +Family=sa5p00m +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=PCS +CoreRevision=4.1 +ModuleName=sgmii_channel_smi_pcs +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/30/2019 +Time=12:09:53 + +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=2.5 +CDR_MULT=20X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=SGMII +LEQ=1 +LOOPBACK=Disabled +LOSPORT=Disabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=SGMII +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1100000101 +RXCOMMAB=0011111010 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Disabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=0 00H +RXCTCBYTEN3=0 00H +RXCTCMATCHPATTERN=M1-S1 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=2 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Div2 Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=6 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=20X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=2.5 +TX_RATE_DIV=Div2 Rate +VHDL=0 +Verilog=1 + +[SYSTEMPNR] +LN0=DCU0_CH0 + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v new file mode 100644 index 0000000..32eab38 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v @@ -0,0 +1,476 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 +// Netlist written on Tue Apr 30 12:09:53 2019 +// +// Verilog Description of module sgmii_channel_smi_pcs +// + +`timescale 1ns/1ps +module sgmii_channel_smi_pcs (hdoutp, hdoutn, hdinp, + hdinn, rxrefclk, rx_pclk, txi_clk, tx_pclk, txdata, + tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, + rx_cv_err, signal_detect_c, lsm_status_s, rx_cdr_lol_s, + sli_rst, tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, + sci_rddata, sci_en_dual, sci_sel_dual, sci_en, sci_sel, + sci_rd, sci_wrn, sci_int, cyawstn, serdes_pdb, pll_refclki, + rsl_disable, rsl_rst, serdes_rst_dual_c, rst_dual_c, tx_serdes_rst_c, + tx_pcs_rst_c, pll_lol, rx_serdes_rst_c, rx_pcs_rst_c); + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output rx_pclk; + input txi_clk; + output tx_pclk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + input signal_detect_c; + output lsm_status_s; + output rx_cdr_lol_s; + input sli_rst; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input serdes_pdb; + input pll_refclki; + input rsl_disable; + input rsl_rst; + input serdes_rst_dual_c; + input rst_dual_c; + input tx_serdes_rst_c; + input tx_pcs_rst_c; + output pll_lol; + input rx_serdes_rst_c; + input rx_pcs_rst_c; + + + wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, + n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, + n22, n23, n24, n25, n26, n27, n28, n29, rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c, rsl_rx_serdes_rst_c, rsl_rst_dual_c, rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c, n30, n31, n32, n33, n34, n35, n36, + n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, + n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, + n57, n60, n61, n62, n63, n64, n65, n66, n67, n68, + n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, + n99, n100, n101, n102, n103, n104, n105, n116, n117, + n118, n119, n120, n121, n122, n123, n124, n125, n126, + _Z; + + DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), + .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), + .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(rx_pclk), .CH1_FF_RXI_CLK(1'b1), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(1'b1), + .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), + .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), + .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0), + .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), + .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), + .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), + .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), + .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), + .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), + .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), + .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), + .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), + .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), + .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), + .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), + .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0), + .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0), + .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0), + .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0), + .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0), + .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0), + .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0), + .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0), + .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), + .D_FFC_DUAL_RST(rsl_rst_dual_c), .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(1'b0), .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), + .D_SCAN_IN_0(1'b0), .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), + .D_SCAN_IN_4(1'b0), .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), + .D_SCAN_MODE(1'b0), .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), + .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), + .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), + .D_CIN10(1'b0), .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n61), + .CH0_HDOUTN(hdoutn), .CH1_HDOUTN(n62), .D_TXBIT_CLKP_TO_ND(n1), + .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), + .CH0_FF_RX_F_CLK(n5), .CH1_FF_RX_F_CLK(n63), .CH0_FF_RX_H_CLK(n6), + .CH1_FF_RX_H_CLK(n64), .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n65), + .CH0_FF_TX_H_CLK(n8), .CH1_FF_TX_H_CLK(n66), .CH0_FF_RX_PCLK(rx_pclk), + .CH1_FF_RX_PCLK(n67), .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n68), + .CH0_FF_RX_D_0(rxdata[0]), .CH1_FF_RX_D_0(n69), .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n70), .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n71), + .CH0_FF_RX_D_3(rxdata[3]), .CH1_FF_RX_D_3(n72), .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n73), .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n74), + .CH0_FF_RX_D_6(rxdata[6]), .CH1_FF_RX_D_6(n75), .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n76), .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n77), + .CH0_FF_RX_D_9(rx_disp_err[0]), .CH1_FF_RX_D_9(n78), .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n79), .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n80), + .CH0_FF_RX_D_12(n10), .CH1_FF_RX_D_12(n81), .CH0_FF_RX_D_13(n11), + .CH1_FF_RX_D_13(n82), .CH0_FF_RX_D_14(n12), .CH1_FF_RX_D_14(n83), + .CH0_FF_RX_D_15(n13), .CH1_FF_RX_D_15(n84), .CH0_FF_RX_D_16(n14), + .CH1_FF_RX_D_16(n85), .CH0_FF_RX_D_17(n15), .CH1_FF_RX_D_17(n86), + .CH0_FF_RX_D_18(n16), .CH1_FF_RX_D_18(n87), .CH0_FF_RX_D_19(n17), + .CH1_FF_RX_D_19(n88), .CH0_FF_RX_D_20(n18), .CH1_FF_RX_D_20(n89), + .CH0_FF_RX_D_21(n19), .CH1_FF_RX_D_21(n90), .CH0_FF_RX_D_22(n20), + .CH1_FF_RX_D_22(n91), .CH0_FF_RX_D_23(n21), .CH1_FF_RX_D_23(n92), + .CH0_FFS_PCIE_DONE(n22), .CH1_FFS_PCIE_DONE(n93), .CH0_FFS_PCIE_CON(n23), + .CH1_FFS_PCIE_CON(n94), .CH0_FFS_RLOS(n95), .CH1_FFS_RLOS(n96), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), .CH1_FFS_LS_SYNC_STATUS(n97), + .CH0_FFS_CC_UNDERRUN(n24), .CH1_FFS_CC_UNDERRUN(n98), .CH0_FFS_CC_OVERRUN(n25), + .CH1_FFS_CC_OVERRUN(n99), .CH0_FFS_RXFBFIFO_ERROR(n26), .CH1_FFS_RXFBFIFO_ERROR(n100), + .CH0_FFS_TXFBFIFO_ERROR(n27), .CH1_FFS_TXFBFIFO_ERROR(n101), .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n102), .CH0_FFS_SKP_ADDED(n28), .CH1_FFS_SKP_ADDED(n103), + .CH0_FFS_SKP_DELETED(n29), .CH1_FFS_SKP_DELETED(n104), .CH0_LDR_RX2CORE(n105), + .CH1_LDR_RX2CORE(n116), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), .D_SCAN_OUT_0(n30), .D_SCAN_OUT_1(n31), .D_SCAN_OUT_2(n32), + .D_SCAN_OUT_3(n33), .D_SCAN_OUT_4(n34), .D_SCAN_OUT_5(n35), .D_SCAN_OUT_6(n36), + .D_SCAN_OUT_7(n37), .D_COUT0(n38), .D_COUT1(n39), .D_COUT2(n40), + .D_COUT3(n41), .D_COUT4(n42), .D_COUT5(n43), .D_COUT6(n44), + .D_COUT7(n45), .D_COUT8(n46), .D_COUT9(n47), .D_COUT10(n48), + .D_COUT11(n49), .D_COUT12(n50), .D_COUT13(n51), .D_COUT14(n52), + .D_COUT15(n53), .D_COUT16(n54), .D_COUT17(n55), .D_COUT18(n56), + .D_COUT19(n57), .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n60)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; + defparam DCU0_inst.D_MACROPDB = "0b1"; + defparam DCU0_inst.D_IB_PWDNB = "0b1"; + defparam DCU0_inst.D_XGE_MODE = "0b0"; + defparam DCU0_inst.D_LOW_MARK = "0d4"; + defparam DCU0_inst.D_HIGH_MARK = "0d12"; + defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; + defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; + defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; + defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; + defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; + defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; + defparam DCU0_inst.CH0_UC_MODE = "0b0"; + defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; + defparam DCU0_inst.CH0_RIO_MODE = "0b0"; + defparam DCU0_inst.CH0_WA_MODE = "0b0"; + defparam DCU0_inst.CH0_INVERT_RX = "0b0"; + defparam DCU0_inst.CH0_INVERT_TX = "0b0"; + defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; + defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b1"; + defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; + defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; + defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; + defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; + defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; + defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; + defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_CTC_BYPASS = "0b1"; + defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; + defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b0"; + defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; + defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; + defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_3 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_4 = "0x000"; + defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; + defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; + defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; + defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b000"; + defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; + defparam DCU0_inst.CH0_TPWDNB = "0b1"; + defparam DCU0_inst.CH0_RATE_MODE_TX = "0b1"; + defparam DCU0_inst.CH0_RTERM_TX = "0d19"; + defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; + defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b011"; + defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; + defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; + defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; + defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH0_RPWDNB = "0b1"; + defparam DCU0_inst.CH0_RATE_MODE_RX = "0b1"; + defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b1"; + defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; + defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; + defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; + defparam DCU0_inst.CH0_REQ_LVL_SET = "0b01"; + defparam DCU0_inst.CH0_REQ_EN = "0b1"; + defparam DCU0_inst.CH0_RTERM_RX = "0d22"; + defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; + defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; + defparam DCU0_inst.CH0_RXIN_CM = "0b11"; + defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; + defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; + defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; + defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010"; + defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; + defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; + defparam DCU0_inst.CH0_RX_LOS_EN = "0b0"; + defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; + defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; + defparam DCU0_inst.D_TX_MAX_RATE = "2.5"; + defparam DCU0_inst.CH0_CDR_MAX_RATE = "2.5"; + defparam DCU0_inst.CH0_TXAMPLITUDE = "0d6"; + defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; + defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; + defparam DCU0_inst.CH0_PROTOCOL = "SGMII"; + defparam DCU0_inst.D_ISETLOS = "0d0"; + defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; + defparam DCU0_inst.D_SETICONST_AUX = "0b00"; + defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; + defparam DCU0_inst.D_SETICONST_CH = "0b00"; + defparam DCU0_inst.D_REQ_ISET = "0b000"; + defparam DCU0_inst.D_PD_ISET = "0b00"; + defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; + defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; + defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; + defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; + defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; + defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; + defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; + defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; + defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; + defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; + defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; + defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; + defparam DCU0_inst.CH0_DCOITUNE = "0b00"; + defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; + defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; + defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; + defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; + defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; + defparam DCU0_inst.CH0_DCOSTEP = "0b00"; + defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; + defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; + defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; + defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; + defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; + defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; + defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; + defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; + defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; + defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; + defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; + defparam DCU0_inst.D_CMUSETZGM = "0b000"; + defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; + defparam DCU0_inst.D_CMUSETP1GM = "0b000"; + defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; + defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; + defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; + defparam DCU0_inst.D_CMUSETICP4P = "0b01"; + defparam DCU0_inst.D_CMUSETBIASI = "0b00"; + defparam DCU0_inst.D_SETPLLRC = "0d1"; + defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; + defparam DCU0_inst.D_REFCK_MODE = "0b000"; + defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000"; + defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; + defparam DCU0_inst.D_RG_EN = "0b0"; + defparam DCU0_inst.D_RG_SET = "0b00"; + assign n1 = 1'bz; + assign n2 = 1'bz; + assign n3 = 1'bz; + assign n4 = 1'bz; + assign n5 = 1'bz; + assign n6 = 1'bz; + assign n7 = 1'bz; + assign n8 = 1'bz; + assign n9 = 1'bz; + assign n10 = 1'bz; + assign n11 = 1'bz; + assign n12 = 1'bz; + assign n13 = 1'bz; + assign n14 = 1'bz; + assign n15 = 1'bz; + assign n16 = 1'bz; + assign n17 = 1'bz; + assign n18 = 1'bz; + assign n19 = 1'bz; + assign n20 = 1'bz; + assign n21 = 1'bz; + assign n22 = 1'bz; + assign n23 = 1'bz; + assign n24 = 1'bz; + assign n25 = 1'bz; + assign n26 = 1'bz; + assign n27 = 1'bz; + assign n28 = 1'bz; + assign n29 = 1'bz; + assign n30 = 1'bz; + assign n31 = 1'bz; + assign n32 = 1'bz; + assign n33 = 1'bz; + assign n34 = 1'bz; + assign n35 = 1'bz; + assign n36 = 1'bz; + assign n37 = 1'bz; + assign n38 = 1'bz; + assign n39 = 1'bz; + assign n40 = 1'bz; + assign n41 = 1'bz; + assign n42 = 1'bz; + assign n43 = 1'bz; + assign n44 = 1'bz; + assign n45 = 1'bz; + assign n46 = 1'bz; + assign n47 = 1'bz; + assign n48 = 1'bz; + assign n49 = 1'bz; + assign n50 = 1'bz; + assign n51 = 1'bz; + assign n52 = 1'bz; + assign n53 = 1'bz; + assign n54 = 1'bz; + assign n55 = 1'bz; + assign n56 = 1'bz; + assign n57 = 1'bz; + assign n60 = 1'bz; + assign n61 = 1'bz; + assign n62 = 1'bz; + assign n63 = 1'bz; + assign n64 = 1'bz; + assign n65 = 1'bz; + assign n66 = 1'bz; + assign n67 = 1'bz; + assign n68 = 1'bz; + assign n69 = 1'bz; + assign n70 = 1'bz; + assign n71 = 1'bz; + assign n72 = 1'bz; + assign n73 = 1'bz; + assign n74 = 1'bz; + assign n75 = 1'bz; + assign n76 = 1'bz; + assign n77 = 1'bz; + assign n78 = 1'bz; + assign n79 = 1'bz; + assign n80 = 1'bz; + assign n81 = 1'bz; + assign n82 = 1'bz; + assign n83 = 1'bz; + assign n84 = 1'bz; + assign n85 = 1'bz; + assign n86 = 1'bz; + assign n87 = 1'bz; + assign n88 = 1'bz; + assign n89 = 1'bz; + assign n90 = 1'bz; + assign n91 = 1'bz; + assign n92 = 1'bz; + assign n93 = 1'bz; + assign n94 = 1'bz; + assign n95 = 1'bz; + assign n96 = 1'bz; + assign n97 = 1'bz; + assign n98 = 1'bz; + assign n99 = 1'bz; + assign n100 = 1'bz; + assign n101 = 1'bz; + assign n102 = 1'bz; + assign n103 = 1'bz; + assign n104 = 1'bz; + assign n105 = 1'bz; + assign n116 = 1'bz; + sgmii_channel_smi_pcsrsl_core rsl_inst (.rui_rst(rsl_rst), .rui_serdes_rst_dual_c(serdes_rst_dual_c), + .rui_rst_dual_c(rst_dual_c), .rui_rsl_disable(rsl_disable), + .rui_tx_ref_clk(pll_refclki), .rui_tx_serdes_rst_c(tx_serdes_rst_c), + .rui_tx_pcs_rst_c({3'b000, tx_pcs_rst_c}), .rdi_pll_lol(pll_lol), + .rui_rx_ref_clk(rxrefclk), .rui_rx_serdes_rst_c({3'b000, rx_serdes_rst_c}), + .rui_rx_pcs_rst_c({3'b000, rx_pcs_rst_c}), .rdi_rx_los_low_s({4'b0000}), + .rdi_rx_cdr_lol_s({3'b000, rx_cdr_lol_s}), .rdo_serdes_rst_dual_c(rsl_serdes_rst_dual_c), + .rdo_rst_dual_c(rsl_rst_dual_c), .ruo_tx_rdy(n117), .rdo_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rdo_tx_pcs_rst_c({n118, n119, n120, rsl_tx_pcs_rst_c}), + .ruo_rx_rdy(n121), .rdo_rx_serdes_rst_c({n122, n123, n124, + rsl_rx_serdes_rst_c}), .rdo_rx_pcs_rst_c({n125, n126, _Z, + rsl_rx_pcs_rst_c})); + defparam rsl_inst.pnum_channels = 1; + defparam rsl_inst.pprotocol = "SGMII"; + defparam rsl_inst.pserdes_mode = "RX AND TX"; + defparam rsl_inst.pport_tx_rdy = "DISABLED"; + defparam rsl_inst.pwait_tx_rdy = 3000; + defparam rsl_inst.pport_rx_rdy = "DISABLED"; + defparam rsl_inst.pwait_rx_rdy = 3000; + assign n117 = 1'bz; + assign n118 = 1'bz; + assign n119 = 1'bz; + assign n120 = 1'bz; + assign n121 = 1'bz; + assign n122 = 1'bz; + assign n123 = 1'bz; + assign n124 = 1'bz; + assign n125 = 1'bz; + assign n126 = 1'bz; + assign _Z = 1'bz; + sgmii_channel_smi_pcssll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), + .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), + .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), + .slo_plol(pll_lol)); + defparam sll_inst.PPROTOCOL = "SGMII"; + defparam sll_inst.PLOL_SETTING = 0; + defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; + defparam sll_inst.PPCIE_MAX_RATE = "2.5"; + defparam sll_inst.PDIFF_VAL_LOCK = 19; + defparam sll_inst.PDIFF_VAL_UNLOCK = 39; + defparam sll_inst.PPCLK_TC = 65536; + defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; + defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; + defparam sll_inst.PPCLK_DIV11_TC = 0; + +endmodule + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v new file mode 100644 index 0000000..37a1f5b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module sgmii_channel_smi_pcsrsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_channel_smi_pcssll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v new file mode 100644 index 0000000..01ea781 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v @@ -0,0 +1,629 @@ +// -------------------------------------------------------------------- +// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// -------------------------------------------------------------------- +// Copyright (c) 2005-2010 by Lattice Semiconductor Corporation +// -------------------------------------------------------------------- +// +// +// Lattice Semiconductor Corporation +// 5555 NE Foore Court +// Hillsboro, OR 97214 +// U.S.A. +// +// TEL: 1-800-Lattice (USA and Canada) +// 1-408-826-6000 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// +// Simulation Library File for FIFO Dual Clock PMI Block +// +// Parameter Definition +//Name Value Default +/* +------------------------------------------------------------------------------ +pmi_data_width_w 18 +pmi_data_width_r 18 +pmi_data_depth_w 256 +pmi_data_depth_r 256 +pmi_full_flag 256 +pmi_empty_flag 0 +pmi_almost_full_flag 252 +pmi_almost_empty_flag 4 +pmi_regmode "reg"|"noreg"|"outreg"|"outreg_rden" "reg" +pmi_resetmode "async"|"sync" "async" +pmi_family "EC"|"XP"|"XP2"|"SC"|"SCM"|"ECP"|"ECP2"|"ECP2M"|"ECP3"|"XO"|"XO2"|"LPTM" "EC" +pmi_implementation "EBR"|"LUT" "EBR" +------------------------------------------------------------------------------ +WARNING: Do not change the default parameters in this model. Parameter +redefinition must be done using defparam or in-line (#) paramater +redefinition in a top level file that instantiates this model. + +NOTE: The purpose of RPReset (Read Point Reset) is to indicate a retransmit, +and it is more commonly used in "packetized" communications. In this +application, the user must keep careful track of when the packet is written +into or read from fifo. + +RPReset does not affect the write port, nor any data that has been written +into the fifo. However, using RPReset imposes two restrictions on the write +operation: + + - Packet size must not exceed the maximum FIFO depth. + + - The write pointer should be reset (using Reset) before writing each new + packet to replace the previous one. + + +These restrictions prevent the read and write pointers from recirculating +around the address space and back to location 0 at any time during packet +storage. Such a pointer wraparound would lose the packet's original starting +point from which to retransmit. These restrictions are only required when +using the retransmit function. + +*/ +// fpga\verilog\pkg\versclibs\data\pmi\pmi_fifo_dc.v 1.26 07-NOV-2012 18:51:50 PYAO + +`timescale 1ns / 1ps +module pmi_fifo_dc #( + parameter pmi_data_width_w = 18, + parameter pmi_data_width_r = 18, + parameter pmi_data_depth_w = 256, + parameter pmi_data_depth_r = 256, + parameter pmi_full_flag = 256, + parameter pmi_empty_flag = 0, + parameter pmi_almost_full_flag = 252, + parameter pmi_almost_empty_flag = 4, + parameter pmi_regmode = "reg", + parameter pmi_resetmode = "async", + parameter pmi_family = "EC" , + parameter module_type = "pmi_fifo_dc", + parameter pmi_implementation = "EBR" + ) + + (input [pmi_data_width_w-1:0] Data, + input WrClock, + input RdClock, + input WrEn, + input RdEn, + input Reset, + input RPReset, + output reg [pmi_data_width_r-1:0] Q = 0, + output Empty, + output Full, + output AlmostEmpty, + output AlmostFull)/*synthesis syn_black_box */; + +//pragma translate_off + localparam pmi_array_size_w = pmi_data_width_w * pmi_data_depth_w; + localparam pmi_array_size_r = pmi_data_width_r * pmi_data_depth_r; + + localparam r_w_ratio = pmi_data_width_w/pmi_data_width_r; + localparam w_r_ratio = pmi_data_width_r/pmi_data_width_w; + +// tri1 GSR_sig = GSR_INST.GSRNET; +// tri1 PUR_sig = PUR_INST.PURNET; +// reg SRN; + wire RST_sig, RPRST_sig; + + reg [pmi_array_size_w-1:0] fifo_mem = {pmi_array_size_w{1'b0}}; + + reg [pmi_data_width_w-1:0] Data_reg = 0; + reg [pmi_data_width_w-1:0] Data_reg_sync = 0; + reg [pmi_data_width_w-1:0] Data_reg_async = 0; + reg [pmi_data_width_r-1:0] Q_reg = 0; + reg [pmi_data_width_r-1:0] Q_reg_sync = 0; + reg [pmi_data_width_r-1:0] Q_reg_async = 0; + reg [pmi_data_width_r-1:0] Q_node = 0; + reg [pmi_data_width_r-1:0] Q_int = 0; + + localparam pmi_addr_width_w = + (pmi_data_depth_w == 2) ? 1 : (pmi_data_depth_w == 4) ? 2 : (pmi_data_depth_w == 8) ? 3 : + (pmi_data_depth_w == 16) ? 4 : (pmi_data_depth_w == 32) ? 5 : (pmi_data_depth_w == 64) ? 6 : + (pmi_data_depth_w == 128) ? 7 : (pmi_data_depth_w == 256) ? 8 : (pmi_data_depth_w == 512) ? 9 : + (pmi_data_depth_w == 1024) ? 10 : (pmi_data_depth_w == 2048) ? 11 : (pmi_data_depth_w == 4096) ? 12 : + (pmi_data_depth_w == 8192) ? 13 : (pmi_data_depth_w == 16384) ? 14 : (pmi_data_depth_w == 32768) ? 15 : + (pmi_data_depth_w == 65536) ? 16 : 17 ; + + localparam pmi_addr_width_r = + (pmi_data_depth_r == 2) ? 1 : (pmi_data_depth_r == 4) ? 2 : (pmi_data_depth_r == 8) ? 3 : + (pmi_data_depth_r == 16) ? 4 : (pmi_data_depth_r == 32) ? 5 : (pmi_data_depth_r == 64) ? 6 : + (pmi_data_depth_r == 128) ? 7 : (pmi_data_depth_r == 256) ? 8 : (pmi_data_depth_r == 512) ? 9 : + (pmi_data_depth_r == 1024) ? 10 : (pmi_data_depth_r == 2048) ? 11 : (pmi_data_depth_r == 4096) ? 12 : + (pmi_data_depth_r == 8192) ? 13 : (pmi_data_depth_r == 16384) ? 14 : (pmi_data_depth_r == 32768) ? 15 : + (pmi_data_depth_r == 65536) ? 16 : 17 ; + + localparam bit_ptr_extra_width_w = + (pmi_data_width_w == 1) ? 0 : (pmi_data_width_w == 2) ? 1 : (pmi_data_width_w <= 4) ? 2 : + (pmi_data_width_w <= 8) ? 3: (pmi_data_width_w <= 16) ? 4 : (pmi_data_width_w <= 32) ? 5 : + (pmi_data_width_w <= 64) ? 6 : (pmi_data_width_w <= 128) ? 7 : 8; + + localparam bit_ptr_width = pmi_addr_width_w + bit_ptr_extra_width_w; + + reg [pmi_addr_width_w:0] wr_pointer = {(pmi_addr_width_w+1){1'b1}}; + reg [pmi_addr_width_r:0] rd_pointer = {(pmi_addr_width_r+1){1'b1}}; + reg [pmi_addr_width_w:0] wr_pointer_sync = {(pmi_addr_width_w+1){1'b1}}; + reg [pmi_addr_width_r:0] rd_pointer_sync = {(pmi_addr_width_r+1){1'b1}}; + reg [pmi_addr_width_w:0] wr_pointer_sync1 = {(pmi_addr_width_w+1){1'b1}}, wr_pointer_sync2 = {(pmi_addr_width_w+1){1'b1}}; + reg [pmi_addr_width_r:0] rd_pointer_sync1 = {(pmi_addr_width_r+1){1'b1}}, rd_pointer_sync2 = {(pmi_addr_width_r+1){1'b1}}; + + reg [bit_ptr_width:0] wr_pointer_lsb = 0, rd_pointer_lsb = 0; + reg [bit_ptr_width:0] wr_pointer_bit = 0, wr_pointer_sync_bit = 0; + reg [bit_ptr_width:0] rd_pointer_bit = 0, rd_pointer_sync_bit = 0; + + wire [pmi_addr_width_w:0] wr_pointer_1 = wr_pointer + 1; + wire [pmi_addr_width_r:0] rd_pointer_1 = rd_pointer + 1; + + reg [pmi_addr_width_w:0] wr_pointer_var, wr_pointer_sync_var; + reg [pmi_addr_width_r:0] rd_pointer_var, rd_pointer_sync_var; + + wire [bit_ptr_width:0] fifo_words_used_syncr, fifo_words_used_syncw; + wire [bit_ptr_width:0] ae_ptr, empty_ptr, af_ptr, full_ptr; + + integer i, j; + + reg RPRST_reg1 = 0; + + +//For SC/M +//Task to check if proper fifo depth is set. + task sc_depth_check (input integer depth_w, depth_r); + begin + if ((depth_w != 2) && (depth_w != 4) && (depth_w != 8) && (depth_w != 16) && (depth_w != 32) && (depth_w != 64)&& (depth_w != 128) && (depth_w != 256) && (depth_w!= 512) && (depth_w != 1024) && (depth_w != 2048) && (depth_w != 4096) && (depth_w != 8192) && (depth_w != 16384) && (depth_w != 32768) && (depth_w != 65536) && (depth_w != 131072)) + begin + $display("\nError! Invalid Write Port Depth!"); + $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072."); + $stop; + end + + if ((depth_r != 2) && (depth_r != 4) && (depth_r != 8) && (depth_r != 16) && (depth_r != 32) && (depth_r != 64)&& (depth_r != 128) && (depth_r != 256) && (depth_r!= 512) && (depth_r != 1024) && (depth_r != 2048) && (depth_r != 4096) && (depth_r != 8192) && (depth_r != 16384) && (depth_r != 32768) && (depth_r != 65536) && (depth_r != 131072)) + begin + $display("\nError! Invalid Read Port Depth!"); + $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072."); + $stop; + end + end + endtask // sc_depth_check + +//For XO +//Task to check if proper fifo depth is set. + task xo_depth_check (input integer depth_w, depth_r); + begin + if ((depth_w != 2) && (depth_w != 4) && (depth_w != 8) && (depth_w != 16) && (depth_w != 32) && (depth_w != 64)&& (depth_w != 128) && (depth_w != 256) && (depth_w!= 512) && (depth_w != 1024) && (depth_w != 2048) && (depth_w != 4096) && (depth_w != 8192) && (depth_w != 16384)) + begin + $display("\nError! Invalid Write Port Depth!"); + $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384."); + $stop; + end + + if ((depth_r != 2) && (depth_r != 4) && (depth_r != 8) && (depth_r != 16) && (depth_r != 32) && (depth_r != 64)&& (depth_r != 128) && (depth_r != 256) && (depth_r!= 512) && (depth_r != 1024) && (depth_r != 2048) && (depth_r != 4096) && (depth_r != 8192) && (depth_r != 16384)) + begin + $display("\nError! Invalid Read Port Depth!"); + $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384."); + $stop; + end + end + endtask // xo_depth_check + +//Task to check if Depth * Width are same for read and write ports + task sc_array_check (input integer array_w, array_r); + begin + if (array_w != array_r) + begin + $display("\nError! Total value of (Depth * Width) must be the same for read set and write set ports."); + $stop; + end + end + endtask // sc_array_check + + +//For All Other families +//Task to check if proper fifo depth is set. + task ec_depth_check (input integer depth_w, depth_r, width_w, width_r); + begin + if (depth_w > 8192 && pmi_implementation == "LUT") + begin + $display("\nError! Fifo depth is too large! Maximum Fifo depth can be 8192."); + $stop; + end + else if (depth_w > 65536 && (pmi_family == "EC" || pmi_family == "XP" || pmi_family == "ECP")) + begin + $display("\nError! Fifo depth is too large! Maximum Fifo depth can be 65536."); + $stop; + end + else if (depth_w > 131072) + begin + $display("\nError! Fifo depth is too large! Maximum Fifo depth can be 131072."); + $stop; + end + + if ((depth_w != 2) && (depth_w != 4) && (depth_w != 8) && (depth_w != 16) && (depth_w != 32) && (depth_w != 64)&& (depth_w != 128) && (depth_w != 256) && (depth_w!= 512) && (depth_w != 1024) && (depth_w != 2048) && (depth_w != 4096) && (depth_w != 8192) && (depth_w != 16384) && (depth_w != 32768) && (depth_w != 65536) && (depth_w != 131072)/* && (depth_w != 262144) && (depth_w != 524288)*/) + begin + $display("\nError! Fifo depth can only be power of 2!"); + $stop; + end + end + endtask // ec_depth_check + +// Error Checks + initial begin + if (pmi_empty_flag != 0) + begin + $display("\nError! Empty Flag must be set to 0!"); + $stop; + end + + if (pmi_full_flag !== pmi_data_depth_w) + begin + $display("\nError! Full Flag must equal the total depth of the FIFO!"); + $stop; + end + + if ( ( ((pmi_family != "SC") && (pmi_family != "SCM") && + (pmi_family != "XO") && (pmi_family != "XO2") && (pmi_family != "LPTM")) || + (pmi_implementation == "LUT") ) && (pmi_resetmode == "sync") ) + begin + $display("\nError! Synchronous Reset is not supported for this family or implementation!"); + $stop; + end + + if ( ((pmi_family == "SC") || (pmi_family == "SCM") || + (pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) && + (pmi_implementation == "EBR") ) begin + sc_array_check(pmi_array_size_w, pmi_array_size_r); + end + + if ( ((pmi_family == "SC") || (pmi_family == "SCM")) && + (pmi_implementation == "EBR") ) begin + sc_depth_check(pmi_data_depth_w, pmi_data_depth_r); + end + + if ( ((pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) && + (pmi_implementation == "EBR") ) begin + xo_depth_check(pmi_data_depth_w, pmi_data_depth_r); + end + + if ( ((pmi_family != "SC") && (pmi_family != "SCM") && + (pmi_family != "XO") && (pmi_family != "XO2") && (pmi_family != "LPTM")) || + (pmi_implementation == "LUT") ) begin + ec_depth_check(pmi_data_depth_w, pmi_data_depth_r, pmi_data_width_w, pmi_data_width_r); + end + + end // initial begin + +//Following commented out code for pmi_gsr is for future compatibility +/* always @ (GSR_sig or PUR_sig ) begin + if (pmi_gsr == "enable") begin + SRN = GSR_sig & PUR_sig ; + end + else if (pmi_gsr == "disable") + SRN = PUR_sig; + end + + not INST0 (SR1, SRN); + or INST1 (RST_sig, Reset, SR1); + or INST2 (RPRST_sig, RPReset, SR1); + + always @(SR1 or Data) + begin + if (SR1 == 1) + begin + assign Data_reg = 0; + assign Q_reg = 0; + end + else + begin + deassign Data_reg; + deassign Q_reg; + end + end // always @ (SR1 or Data) +*/ + buf INST1 (RST_sig, Reset); + buf INST2 (RPRST_sig, RPReset); + + always @(posedge WrClock) + begin + RPRST_reg1 <= RPRST_sig; + end + + always @(RST_sig or RPRST_sig or RPRST_reg1) + begin + if (RST_sig == 1) + begin + assign wr_pointer = {(pmi_addr_width_w+1){1'b1}}; + assign wr_pointer_sync = {(pmi_addr_width_w+1){1'b1}}; + assign wr_pointer_sync1 = {(pmi_addr_width_w+1){1'b1}}; + assign wr_pointer_sync2 = {(pmi_addr_width_w+1){1'b1}}; + assign wr_pointer_lsb = 0; + assign wr_pointer_bit = 0; + assign wr_pointer_sync_bit = 0; + end + else + begin + deassign wr_pointer; + deassign wr_pointer_sync; + deassign wr_pointer_sync1; + deassign wr_pointer_sync2; + deassign wr_pointer_lsb; + deassign wr_pointer_bit; + deassign wr_pointer_sync_bit; + end // else: !if(RST_sig == 1) + + if (RST_sig == 1 || RPRST_sig == 1) + begin + assign rd_pointer = {(pmi_addr_width_r+1){1'b1}}; + assign rd_pointer_lsb = 0; + assign rd_pointer_bit = 0; + end + else + begin + deassign rd_pointer; + deassign rd_pointer_lsb; + deassign rd_pointer_bit; + end // else: !if(RPRST_sig == 1 || RST_sig == 1) + + if (RPRST_reg1 == 1 || RST_sig == 1) + begin + assign rd_pointer_sync = {(pmi_addr_width_r+1){1'b1}}; + assign rd_pointer_sync1 = {(pmi_addr_width_r+1){1'b1}}; + assign rd_pointer_sync2 = {(pmi_addr_width_r+1){1'b1}}; + assign rd_pointer_sync_bit = 0; + end + else + begin + deassign rd_pointer_sync; + deassign rd_pointer_sync1; + deassign rd_pointer_sync2; + deassign rd_pointer_sync_bit; + end + end + + //Additional Warning checks for RPRST Usage +/* + always @(RPRST_sig) + begin + if (wr_pointer > pmi_data_depth_w) + begin + $display("\nWarning! Illegal Operation! RPReset is being asserted when the packet size has exceeded fifo depth!"); + $display("\nSimulation mismatches are possible at time: %d !", $time); + $display("\nPlease refer to the header information of pmi_fifo_dc.v model for proper RPReset usage."); + end + end // always @ (RPRST_sig) +*/ + +//Asynchronous Reset + always @(posedge RST_sig or posedge WrClock) + begin + if (RST_sig == 1) + begin + Data_reg_async <= 0; + end + else + begin + if (WrEn == 1 && Full != 1) + Data_reg_async <= Data; + end + end + +//Synchronous Reset + always @(posedge WrClock) + begin + if (RST_sig == 1) + begin + Data_reg_sync <= 0; + end + else + begin + if (WrEn == 1 && Full != 1) + Data_reg_sync <= Data; + end + end + +//Choice between Async and Sync Reset + always @(Data_reg_sync or Data_reg_async) + begin + if (pmi_resetmode == "async") + Data_reg = Data_reg_async; + else + Data_reg = Data_reg_sync; + end + +//Write and Read Pointers + +always @(posedge WrClock) + begin + if (WrEn == 1) + begin + if (Full != 1) + begin + wr_pointer <= wr_pointer_1; + wr_pointer_lsb <= (wr_pointer_1 % pmi_data_depth_w) * pmi_data_width_w; + end + end + end + +always @(posedge RdClock) + begin + if (RdEn == 1) + begin + if (Empty != 1) + begin + rd_pointer <= rd_pointer_1; + rd_pointer_lsb <= (rd_pointer_1 % pmi_data_depth_r) * pmi_data_width_r; + end // if (Empty != 1) + end // if (RdEn == 1) + end // always @ (posedge RdClock) + + +//Synchronization Logic + +//Sync Write Pointer to Rd Clock +//Delayed by 2 clock cycles for EC based families + always @(posedge RdClock) + if ( ((pmi_family == "SC") || (pmi_family == "SCM") || + (pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) && + (pmi_implementation == "EBR") ) + begin + wr_pointer_sync <= wr_pointer; + end + else begin + wr_pointer_sync1 <= wr_pointer; + wr_pointer_sync2 <= wr_pointer_sync1; + wr_pointer_sync <= wr_pointer_sync2; + end + +//Sync Read Pointer to Wr Clock +//Delayed by 2 clock cycles for EC based families. +//For SC and XO, rd_pointer_sync depends on the adjusted rd_pointer +//which depends on pmi_data_depth_w and pmi_data_depth_r + + always @(posedge WrClock) + if ( ((pmi_family == "SC") || (pmi_family == "SCM") || + (pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) && + (pmi_implementation == "EBR") ) + begin + rd_pointer_sync <= rd_pointer; + end + else begin + rd_pointer_sync1 <= rd_pointer; + rd_pointer_sync2 <= rd_pointer_sync1; + rd_pointer_sync <= rd_pointer_sync2; + end + + //Write Data into FIFO + always @(Data_reg, wr_pointer, wr_pointer_lsb) + begin + for (i = 0; i < pmi_data_width_w; i = i + 1) + fifo_mem[wr_pointer_lsb + i] = Data_reg[i]; + end + + //Read from FIFO + always @(rd_pointer, rd_pointer_lsb, posedge RST_sig, posedge RPRST_sig) begin + if (RST_sig == 1'b1 || RPRST_sig == 1'b1) + Q_node = 0; + else if (RST_sig == 0 && RPRST_sig == 0) begin + for (j = 0; j < pmi_data_width_r; j = j + 1) + Q_node[j] = fifo_mem[rd_pointer_lsb + j]; + end // if (RST_sig == 0 && RPRST_sig == 0) + end // always @ (rd_pointer, posedge RST_sig, posedge RPRST_sig) + + +//Asynchronous Reset + always @(posedge RST_sig or posedge RPRST_sig or posedge RdClock) + begin + if (RST_sig == 1 || RPRST_sig == 1) + begin + Q_reg_async <= 0; + end + else + begin + if (pmi_regmode == "outreg_rden") + begin + if (RdEn == 1) //cr45303 + Q_reg_async <= Q_node; + end + else + begin + Q_reg_async <= Q_node; + end + end + end + +//Synchronous Reset + always @(posedge RdClock) + begin + if (RST_sig == 1 || RPRST_sig == 1) + begin + Q_reg_sync <= 0; + end + else + begin + if (pmi_regmode == "outreg_rden") + begin + if (RdEn == 1) //cr45303 + Q_reg_sync <= Q_node; + end + else + begin + Q_reg_sync <= Q_node; + end + end + end + +//Choice between Async and Sync Reset + always @(Q_reg_sync or Q_reg_async) + begin + if (pmi_resetmode == "async") + Q_reg = Q_reg_async; + else + Q_reg = Q_reg_sync; + end + + always @(Q_reg or Q_node) + begin + if (pmi_regmode == "noreg") + begin + Q_int = Q_node; + end + else + begin + Q_int = Q_reg; + end + end + + always @(Q_int) + begin + Q = Q_int ; + end + + +//Flag Generation + + always @(wr_pointer) + begin + wr_pointer_var = wr_pointer + 1; + wr_pointer_bit <= wr_pointer_var * pmi_data_width_w; + end + + always @(wr_pointer_sync, posedge RPRST_sig, posedge RdClock) + begin + if (RPRST_sig == 1) + wr_pointer_sync_bit <= 0; + else + begin + wr_pointer_sync_var = wr_pointer_sync + 1; + wr_pointer_sync_bit <= wr_pointer_sync_var * pmi_data_width_w; + end + end + + always @(rd_pointer) + begin + rd_pointer_var = rd_pointer + 1; + rd_pointer_bit <= rd_pointer_var * pmi_data_width_r; + end + + always @(rd_pointer_sync) + begin + rd_pointer_sync_var = rd_pointer_sync + 1; + rd_pointer_sync_bit <= rd_pointer_sync_var * pmi_data_width_r; + end + + assign fifo_words_used_syncr = (wr_pointer_sync_bit < pmi_array_size_w) && (rd_pointer_bit >= pmi_array_size_w) ? + (wr_pointer_sync_bit + pmi_array_size_w) - (rd_pointer_bit - pmi_array_size_w) : wr_pointer_sync_bit - rd_pointer_bit; + assign fifo_words_used_syncw = (wr_pointer_bit < pmi_array_size_w) && (rd_pointer_sync_bit >= pmi_array_size_w) ? + (wr_pointer_bit + pmi_array_size_w) - (rd_pointer_sync_bit - pmi_array_size_w) : wr_pointer_bit - rd_pointer_sync_bit; + + assign ae_ptr = (pmi_almost_empty_flag * pmi_data_width_r) + (pmi_data_width_r - 1); + assign empty_ptr = pmi_data_width_r - 1; + assign af_ptr = (pmi_almost_full_flag * pmi_data_width_w) - (pmi_data_width_w - 1); + assign full_ptr = pmi_array_size_w - (pmi_data_width_w - 1); + + assign Empty = (fifo_words_used_syncr <= empty_ptr); + assign AlmostEmpty = (fifo_words_used_syncr <= ae_ptr); + assign AlmostFull = (fifo_words_used_syncw >= af_ptr); + assign Full = (fifo_words_used_syncw >= full_ptr); +//pragma translate_on + +endmodule + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/readme.htm b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/readme.htm new file mode 100644 index 0000000..479a87e --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/readme.htm @@ -0,0 +1,1314 @@ + + + + + + + + + + + + + +SGMII/Gb Ethernet PCS Readme + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    + +
    + +

    SGMII/Gb +Ethernet PCS ReadMe

    + +

     

    + +

    General Information

    + +
    + +


    +    Copyright Notice

    + + + + + +
    +

    Copyright + 2000-2014© Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This + confidential and proprietary software may be used only as authorized by a licensing + agreement from Lattice Semiconductor Corporation. The entire notice above + must be reproduced on all authorized copies and copies may only be made to + the extent permitted by a licensing agreement from Lattice Semiconductor + Corporation.

    +
    + +
    + +


    +    Contacting Lattice

    + +
    + +

     

    + + + + + + + + + + + + + + + + + + + + + + + +
    +

    Mail:

    +     		+

    Lattice + Semiconductor Corporation
    +5555 NE Moore Court
    +Hillsboro, OR +  97124
    +U.S.A.

    +
    +

    Telephone:

    +     		+

    1-800-Lattice + (USA and Canada)

    +
    +

     

    +     		+

    1-503-268-8001 + (other locations)

    +
    +

    Website:

    +     		+

    http://www.latticesemi.com

    +
    +

    E-mail:

    +     		+

    techsupport@latticesemi.com

    +
    + +

     

    + +
    + +

    IP Module Information

    + +
    + +


    +    About this Module

    + + + + + + + + + + + + + + + + + + + +
    +

    IP Name:

    +     		+

    SGMII/Gb + Ethernet PCS

    +
    +

    IP + Version:

    +     		+

    4.1

    +
    +

    IP + Release Date:

    +     		+

    June + 2015

    +
    +

    Target + Technology:

    +     		+

    LatticeECP3,ECP5UM

    +
    + +


    +    Software Requirements

    + + + + + + + + + + + + + + + +
    +

    Synthesis Tools + Supported:

    +     		+

    Synplify Pro I-2014.03L-SP1
    + Lattice Synthesis Engine (ECP5UM only)
    + Precision RTL Synthesis 2010a_Update2.254(ECP3/Windows only)

    +
    +

    Simulation + Tools Supported:

    +     		+

    Active-HDL + 9.3SP1(Windows only)
    + ModelSim SE 10.2c

    +
    +

    Lattice + Tool Supported:

    +     		+

    Diamond + 3.5

    +
    + +

     

    + +
    + +

    Implementing the IP Module Using +Diamond SW

    + +
    + +


    +    Instantiating the Core

    + + + + + +
    +

    The + generated SGMII core package includes black-box (<user_name>_bb.v) and + instance (<username>_inst.v) templates that can be used to instantiate + the core in a top-level design.

    +

    An + example RTL top-level reference source file(top_smi.v[vhd]) that can be used + as an instantiation template for the IP core is provided in <project_dir>\sgmii_pcs_eval\<username>\src\rtl\top\[device]. + Users may also use this top-level reference as the starting template for the + top-level for their complete design.

    +
    + +


    +    Hardware Evaluation

    + + + + + +
    +

    Lattice's IP hardware evaluation capability makes it + possible to create IP cores that operate in hardware for a limited period of + time (approximately four hours) without requiring the purchase on an IP + license. The hardware evaluation capability is enabled by default. It can be + disabled by right clicking on "Build Database" in the "Process + for current sources" window of the Project Navigator. The setting is + called "Hardware Evaluation" and the options are "Enable" + or "Disable".
    +   
    + When the Hardware Evaluation feature is enabled in the design, it will + generate a programming file that may be downloaded into the device. After + initialization, the IP core will be operational for approximately four hours. + After four hours, the device will stop working and it will be necessary to + reprogram the device to re-enable operation. This hardware evaluation + capability is only enabled if the core has not been licensed. During + implementation, a license check is performed. If the hardware evaluation + feature is disabled, a pop-up window will be displayed indicating a license + failure. Click"OK" in the window and the + bitstream will not be generated. If a license is detected, no pop-up window + is displayed and core generation is completed with no restrictions.

    +

     

    +
    + +


    +    Implementing the core only design in a Top-Level Design

    + + + + + + + + +
    +

    As + described previously, the top-level file top_pcs_core_only.v + provided in <project_dir>\sgmii_pcs_eval\<username>\src\rtl\top\[device] supports the ability to implement + just the SGMII IP core.

    +

    Push-button + top-level implementation of this top-level is supported via the Diamond + project file <username>_core_only_eval.ldf + located in <project_dir>\sgmii_pcs_eval\<username>\impl\core_only\[vendor].

    +

    This + design is intended only to provide an accurate indication of the device + utilization associated with the core itself and should not be used as an actual + implementation example.

    +
    +


    + To use the + project file:

    +
      +
    • Select File->Open->Project + in Lattice Diamond.
      • +
    • Browse to <project_dir>\sgmii_pcs_eval\<username>\impl\core_only\[vendor] + in the Open Project dialog box.
      • +
    • Select and + open <username>_core_only_eval.ldf.At + this point, all of the files needed to support top-level synthesis and + implementation will be imported to the project.
      • +
    • Implement + the complete design via the standard Lattice Diamond GUI flow.
      • +
    +

     

    +
    + +

     

    + +

    Implementing the reference design in a Top-Level +Design

    + + + + + + + + +
    +

    Push-button + top-level implementation of a sample reference design is also supported via + the Diamond project file <username>_reference_eval.ldf + located in <project_dir>\sgmii_pcs_eval\<username>\impl\reference\[vendor]. +

    +
    +


    + To use the + project file:

    +
      +
    • Select + File->Open->Project in Lattice Diamond.
      • +
    • Browse to <project_dir>\sgmii_pcs_eval\<username>\impl\reference\[vendor] in the Open Project + dialog box.
      • +
    • Select and + open <username>_reference_eval.ldf.At + this point, all of the files needed to support top-level synthesis and + implementation will be imported to the project.
      • +
    • Implement + the complete design via the standard Lattice Diamond GUI flow.
      • +
    +

     

    +
    + +


    +    Running Functional and Post + Route Timing Simulation

    + + + + + + + + +
    +

    The + functional simulation includes a configuration-specific behavioral model of + the SGMII, which is instantiated in an FPGA top level along with some + test logic (PLLs, and registers with Read/Write Interface). This FPGA top is + instantiated in an eval testbench that configures FPGA test logic registers + and SGMII IP core registers. The testbench files can be found in <project_dir>\sgmii_pcs_eval\testbench.

    +
    +

    Functional + Simulation
    + The + generated IP core package includes the configuration-specific behavior model + (<username>_beh.v) for functional simulation. ModelSim simulation is + supported via testbench files provided in <project_dir>\sgmii_pcs_eval\testbench. + Models required for simulation are provided in the <project_dir>\sgmii_pcs_eval\models\[device] folder.
    + Users may run the eval simulation by doing the following with     ModelSim + SE:

    +
      +
    • Open + ModelSim.
      • +
    • Under the File + tab, select Change Directory
      • +
    • Set the + directory to <project_dir>\sgmii_pcs_eval\<username>\sim\modelsim.
      • +
    • Select OK. +
      • +
    • Under the + Tools tab, select TCL, then select Execute Macro.
      • +
    • Select file + <username>_reference_eval_se.do for ModelSim SE.
      • +
    +

    Users + may run the eval simulation by doing the following with Active-HDL:

    +
      +
    • Open + Active-HDL.
      • +
    • Under the tools + tab, select Execute Macro...
      • +
    • Select file + <project_dir>\sgmii_pcs_eval\<username>\sim\aldec\<username>_reference_eval.do
      • +
    +

    Post Route Timing Simulation

    +

    No post route + timing simulation is supported in this version.

    +
    + +

     

    + +


    +    Reference Information
    +
    +The following documents provide more information on +implementing this core:

    + + + +

     

    + +
    + + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.ldf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.ldf new file mode 100644 index 0000000..bb391d4 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.ldf @@ -0,0 +1,12 @@ + + + + + + + + + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.lpf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.lpf new file mode 100644 index 0000000..1310d50 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.lpf @@ -0,0 +1,5 @@ +block RESETPATHS; +block ASYNCPATHS; +FREQUENCY NET "tx_clk_125_c" 125.0 MHz PAR_ADJ 25; +FREQUENCY NET "rx_clk_125_c" 125.0 MHz PAR_ADJ 25; +FREQUENCY NET "serdes_recovered_clk_c" 125.0 MHz PAR_ADJ 25; diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.sty b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.sty new file mode 100644 index 0000000..b7c8175 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.sty @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.ldf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.ldf new file mode 100644 index 0000000..2218a5e --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.ldf @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.lpf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.lpf new file mode 100644 index 0000000..c34d25a --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.lpf @@ -0,0 +1,9 @@ +block RESETPATHS; +block ASYNCPATHS; +# +FREQUENCY NET "in_clk_125_c" 125.0 MHz PAR_ADJ 25; +FREQUENCY NET "out_clk_125_c" 125.0 MHz PAR_ADJ 25; +FREQUENCY NET "hclk_c" 50.0 MHz PAR_ADJ 25; +FREQUENCY NET "*serdes_recovered_clk" 125.0 MHz PAR_ADJ 25; +# +# diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.sty b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.sty new file mode 100644 index 0000000..97aabce --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.sty @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/sim/modelsim/sgmii_channel_smi_reference_eval_se.do b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/sim/modelsim/sgmii_channel_smi_reference_eval_se.do new file mode 100644 index 0000000..9991117 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/sim/modelsim/sgmii_channel_smi_reference_eval_se.do @@ -0,0 +1,76 @@ +if {!0} { + vlib work +} +vmap work work +vmap ecp5u_black_boxes "/home/soft/lattice/diamond/3.10_x64/cae_library/simulation/blackbox/ecp5u_black_boxes" + +# compile the IP core ############### +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../../sgmii_channel_smi_beh.v +vcom ../../../../sgmii_channel_smi.vhd + +# compile components of an sgmii channel ############### +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../src/rtl/template/ecp5um/register_interface_hb.v +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../src/rtl/template/ecp5um/rate_resolution.v + +# compile top level hardware components ############### +vlog +define+RSL_SIM_MODE -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v + +# compile top level wrapper ############### +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../src/rtl/top/ecp5um/top_hb.v + +# compile testbench components of sgmii_node ############### +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/sgmii_node.v + +# compile testbench components of mii monitor ############### +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/port_parser_mii.v +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/port_monitor.v +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/mii_monitor.v + +# compile the testbench ############### +vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/tb_hb.v + + +#start the simulator +vsim -novopt -t ps -L ecp5u_black_boxes tb -l testcase.log + + +# list waves +view wave +onerror {resume} +add wave -divider {Control Signals} +add wave -format Logic -radix hexadecimal sim:/tb/top/rst_n +add wave -format Logic -radix hexadecimal sim:/tb/top/sgmii_mode +add wave -divider {Host Bus Signals} +add wave -format Logic -radix hexadecimal sim:/tb/top/hcs_n +add wave -format Logic -radix hexadecimal sim:/tb/top/hwrite_n +add wave -format Logic -radix hexadecimal sim:/tb/top/haddr +add wave -format Logic -radix hexadecimal sim:/tb/top/hdatain +add wave -format Logic -radix hexadecimal sim:/tb/top/hdataout +add wave -format Logic -radix hexadecimal sim:/tb/top/hready_n +add wave -divider {(G)MII Inbound Signals} +add wave -format Logic -radix hexadecimal sim:/tb/top/in_ce_source +add wave -format Logic -radix hexadecimal sim:/tb/top/in_ce_sink +add wave -format Logic -radix hexadecimal sim:/tb/top/en_in_mii +add wave -format Literal -radix hexadecimal sim:/tb/top/data_in_mii +add wave -format Logic -radix hexadecimal sim:/tb/top/err_in_mii +add wave -divider {(G)MII Outbound Signals} +add wave -format Logic -radix hexadecimal sim:/tb/top/out_ce_source +add wave -format Logic -radix hexadecimal sim:/tb/top/out_ce_sink +add wave -format Logic -radix hexadecimal sim:/tb/top/dv_out_mii +add wave -format Literal -radix hexadecimal sim:/tb/top/data_out_mii +add wave -format Logic -radix hexadecimal sim:/tb/top/err_out_mii +add wave -format Logic -radix hexadecimal sim:/tb/top/col_out_mii +add wave -format Logic -radix hexadecimal sim:/tb/top/crs_out_mii +add wave -divider {SERDES Outbound Signals} +add wave -format Logic -radix hexadecimal sim:/tb/top/hdoutp0 +add wave -format Logic -radix hexadecimal sim:/tb/top/hdoutn0 +add wave -divider {SERDES Inbound Signals} +add wave -format Logic -radix hexadecimal sim:/tb/top/hdinp0 +add wave -format Logic -radix hexadecimal sim:/tb/top/hdinn0 + + +# run simulation cycles +run -all + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/rate_resolution.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/rate_resolution.v new file mode 100644 index 0000000..b9edbef --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/rate_resolution.v @@ -0,0 +1,66 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module rate_resolution ( + gbe_mode, + sgmii_mode, + an_enable, + advertised_rate, + link_partner_rate, + non_an_rate, + + operational_rate +); + +input gbe_mode; +input sgmii_mode; +input an_enable; +input [1:0] advertised_rate; // 00=10Mbps 01=100Mbps 10=1Gbps +input [1:0] link_partner_rate; +input [1:0] non_an_rate; + +output [1:0] operational_rate; +reg [1:0] operational_rate; + + + +always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin + if (gbe_mode) begin + operational_rate <= 2'b10; // 1Gbps + end + else begin + if (an_enable) begin + if (sgmii_mode) begin + // PHY Mode + operational_rate <= advertised_rate; + end + else begin + // MAC Mode + operational_rate <= link_partner_rate; + end + end + else begin + // If auto-negotiation disabled, then this becomes active rate + operational_rate <= non_an_rate; + end + end +end + + + +endmodule + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/register_interface_hb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/register_interface_hb.v new file mode 100644 index 0000000..028d806 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/register_interface_hb.v @@ -0,0 +1,1393 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module register_interface_hb ( + + // Control Signals + rst_n, + hclk, + gbe_mode, + sgmii_mode, + + // Host Bus + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + // Register Inputs + mr_stat_1000base_x_fd, + mr_stat_1000base_x_hd, + mr_stat_1000base_t_fd, + mr_stat_1000base_t_hd, + + mr_stat_100base_t4, + mr_stat_100base_x_fd, + mr_stat_100base_x_hd, + mr_stat_10mbps_fd, + mr_stat_10mbps_hd, + mr_stat_100base_t2_fd, + mr_stat_100base_t2_hd, + + mr_stat_extended_stat, + mr_stat_unidir_able, + mr_stat_preamb_supr, + mr_stat_an_complete, + mr_stat_remote_fault, + mr_stat_an_able, + mr_stat_link_stat, + mr_stat_jab_det, + mr_stat_extended_cap, + + mr_page_rx, + mr_lp_adv_ability, + + // Register Outputs + mr_main_reset, + mr_loopback_enable, + mr_speed_selection, + mr_an_enable, + mr_power_down, + mr_isolate, + mr_restart_an, + mr_duplex_mode, + mr_col_test, + mr_unidir_enable, + mr_adv_ability + ); + + +input rst_n ; +input hclk ; +input gbe_mode ; +input sgmii_mode ; + +input hcs_n; +input hwrite_n; +input [5:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input mr_stat_1000base_x_fd; +input mr_stat_1000base_x_hd; +input mr_stat_1000base_t_fd; +input mr_stat_1000base_t_hd; + +input mr_stat_100base_t4; +input mr_stat_100base_x_fd; +input mr_stat_100base_x_hd; +input mr_stat_10mbps_fd; +input mr_stat_10mbps_hd; +input mr_stat_100base_t2_fd; +input mr_stat_100base_t2_hd; + +input mr_stat_extended_stat; +input mr_stat_unidir_able; +input mr_stat_preamb_supr; +input mr_stat_an_complete; +input mr_stat_remote_fault; +input mr_stat_an_able; +input mr_stat_link_stat; +input mr_stat_jab_det; +input mr_stat_extended_cap; + +input mr_page_rx; +input [15:0] mr_lp_adv_ability; + +output mr_main_reset; +output mr_loopback_enable; +output [1:0] mr_speed_selection; +output mr_an_enable; +output mr_power_down; +output mr_isolate; +output mr_restart_an; +output mr_duplex_mode; +output mr_col_test; +output mr_unidir_enable; +output [15:0] mr_adv_ability; + +regs_hb regs ( + .rst_n (rst_n), + .hclk (hclk), + + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + + .hcs_n (hcs_n), + .hwrite_n (hwrite_n), + .haddr (haddr), + .hdatain (hdatain), + + .hdataout (hdataout), + .hready_n (hready_n), + + .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd), + .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd), + .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd), + .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd), + + .mr_stat_100base_t4 (mr_stat_100base_t4), + .mr_stat_100base_x_fd (mr_stat_100base_x_fd), + .mr_stat_100base_x_hd (mr_stat_100base_x_hd), + .mr_stat_10mbps_fd (mr_stat_10mbps_fd), + .mr_stat_10mbps_hd (mr_stat_10mbps_hd), + .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd), + .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd), + + .mr_stat_extended_stat (mr_stat_extended_stat), + .mr_stat_unidir_able (mr_stat_unidir_able), + .mr_stat_preamb_supr (mr_stat_preamb_supr), + .mr_stat_an_complete (mr_stat_an_complete), + .mr_stat_remote_fault (mr_stat_remote_fault), + .mr_stat_an_able (mr_stat_an_able), + .mr_stat_link_stat (mr_stat_link_stat), + .mr_stat_jab_det (mr_stat_jab_det), + .mr_stat_extended_cap (mr_stat_extended_cap), + + .mr_page_rx (mr_page_rx), + .mr_lp_adv_ability (mr_lp_adv_ability), + + .mr_main_reset (mr_main_reset), + .mr_loopback_enable (mr_loopback_enable), + .mr_speed_selection (mr_speed_selection), + .mr_an_enable (mr_an_enable), + .mr_power_down (mr_power_down), + .mr_isolate (mr_isolate), + .mr_restart_an (mr_restart_an), + .mr_duplex_mode (mr_duplex_mode), + .mr_col_test (mr_col_test), + .mr_unidir_enable (mr_unidir_enable), + + .mr_adv_ability (mr_adv_ability) +); +endmodule + + + + + + +module register_0_hb ( + rst_n, + clk, + gbe_mode, + cs_0, + cs_1, + write, + ready, + data_in, + + data_out, + mr_main_reset, + mr_loopback_enable, + mr_speed_selection, + mr_an_enable, + mr_power_down, + mr_isolate, + mr_restart_an, + mr_duplex_mode, + mr_col_test, + mr_unidir_enable +); + +input rst_n; +input clk; +input gbe_mode; +input cs_0; +input cs_1; +input write; +input ready; +input [15:0] data_in; + +output [15:0] data_out; +output mr_main_reset; // bit D15 // R/W // Self Clearing +output mr_loopback_enable; // bit D14 // R/W +output [1:0] mr_speed_selection; // bit D13 LSB bit D6 MSB // R/W +output mr_an_enable; // bit D12 // R/W +output mr_power_down; // bit D11 // R/W +output mr_isolate; // bit D10 // R/W +output mr_restart_an; // bit D09 // R/W // Self Clearing +output mr_duplex_mode; // bit D08 // STUCK HIGH +output mr_col_test; // bit D08 // STUCK LOW +output mr_unidir_enable; // bit D05 // STUCK LOW + +reg [15:0] data_out; +reg mr_main_reset; +reg mr_loopback_enable; +reg [1:0] mr_speed_selection; +reg mr_an_enable; +reg mr_power_down = 1'b0; +reg mr_isolate; +reg mr_restart_an; +reg mr_duplex_mode; +reg mr_col_test; +reg mr_unidir_enable; +reg m_m_r; +reg m_r_a; +reg gbe_mode_d1; +reg gbe_mode_d2; + + + +// Deboggle +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + gbe_mode_d1 <= 0; + gbe_mode_d2 <= 0; + end + else begin + gbe_mode_d1 <= gbe_mode; + gbe_mode_d2 <= gbe_mode_d1; + end +end + + + +// Write Operations + + // Low Portion of Register[D7:D0] has no + // implemented bits. Therefore, no write + // operations here. + + // High Portion of Register[D15:D8] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_main_reset <= 1'b0; + mr_loopback_enable <= 1'b0; + mr_speed_selection <= 2'b10; + mr_an_enable <= 1'b1; + mr_power_down <= 1'b0; + mr_isolate <= 1'b0; + mr_restart_an <= 1'b0; + mr_duplex_mode <= 1'b1; + mr_col_test <= 1'b0; + mr_unidir_enable <= 1'b0; + m_m_r <= 0; + m_r_a <= 0; + end + else begin + + // defaults + mr_duplex_mode <= 1'b1; // STUCK HIGH + mr_col_test <= 1'b0; // STUCK LOW + + // Do the Writes + if (cs_1 && ready && write) begin + mr_main_reset <= data_in[15]; + mr_loopback_enable <= data_in[14]; + mr_an_enable <= data_in[12]; + mr_power_down <= data_in[11]; + mr_isolate <= data_in[10]; + mr_restart_an <= data_in[9]; + end + + + // Manage Writes to Speed Selection Based on GBE MODE + if (gbe_mode_d2) begin + mr_speed_selection[1:0] <= 2'b10; // STUCK AT 1GBPS + end + else begin + if (cs_1 && ready && write) begin + mr_speed_selection[0] <= data_in[13]; + end + if (cs_0 && ready && write) begin + mr_speed_selection[1] <= data_in[6]; + mr_unidir_enable <= data_in[5]; + end + end + + + + // Delay the Self Clearing Register Bits + m_m_r <= mr_main_reset; + m_r_a <= mr_restart_an; + + // Do the Self Clearing + if (m_m_r) + mr_main_reset <= 0; + + if (m_r_a) + mr_restart_an <= 0; + end + end + + + + + +// Read Operations + always @(*) begin + data_out[7] <= mr_col_test; + data_out[6] <= mr_speed_selection[1]; + data_out[5] <= mr_unidir_enable; + data_out[4] <= 1'b0; + data_out[3] <= 1'b0; + data_out[2] <= 1'b0; + data_out[1] <= 1'b0; + data_out[0] <= 1'b0; + + data_out[15] <= mr_main_reset; + data_out[14] <= mr_loopback_enable; + data_out[13] <= mr_speed_selection[0]; + data_out[12] <= mr_an_enable; + data_out[11] <= mr_power_down; + data_out[10] <= mr_isolate; + data_out[9] <= mr_restart_an; + data_out[8] <= mr_duplex_mode; + end +endmodule + +module register_1_hb ( + rst_n, + clk, + cs_0, + cs_1, + write, + ready, + + + mr_stat_100base_t4, + mr_stat_100base_x_fd, + mr_stat_100base_x_hd, + mr_stat_10mbps_fd, + mr_stat_10mbps_hd, + mr_stat_100base_t2_fd, + mr_stat_100base_t2_hd, + + mr_stat_extended_stat, + mr_stat_unidir_able, + mr_stat_preamb_supr, + mr_stat_an_complete, + mr_stat_remote_fault, + mr_stat_an_able, + mr_stat_link_stat, + mr_stat_jab_det, + mr_stat_extended_cap, + + data_out +); + +input rst_n; +input clk; +input cs_0; +input cs_1; +input write; +input ready; +input mr_stat_100base_t4; // bit D15 // Read-Only +input mr_stat_100base_x_fd; // bit D14 // Read-Only +input mr_stat_100base_x_hd; // bit D13 // Read-Only +input mr_stat_10mbps_fd; // bit D12 // Read-Only +input mr_stat_10mbps_hd; // bit D11 // Read-Only +input mr_stat_100base_t2_fd; // bit D10 // Read-Only +input mr_stat_100base_t2_hd; // bit D9 // Read-Only + +input mr_stat_extended_stat; // bit D8 // Read-Only +input mr_stat_unidir_able; // bit D7 // Read-Only +input mr_stat_preamb_supr; // bit D6 // Read-Only +input mr_stat_an_complete; // bit D5 // Read-Only +input mr_stat_remote_fault; // bit D4 // Read-Only +input mr_stat_an_able; // bit D3 // Read-Only +input mr_stat_link_stat; // bit D2 // Read-Only // Latch-On-Zero // Clear-On-Read +input mr_stat_jab_det; // bit D1 // Read-Only +input mr_stat_extended_cap; // bit D0 // Read-Only + +output [15:0] data_out; + +reg [15:0] data_out; + +reg link_stat_d1; +reg link_stat_d2; +reg clear_on_read; +reg read_detect; +reg rd_d1; +reg rd_d2; +reg allow_link_stat; +reg link_ok_status; +// metastability filter + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + link_stat_d1 <= 1'b0; + link_stat_d2 <= 1'b0; + end + else begin + link_stat_d1 <= mr_stat_link_stat; + link_stat_d2 <= link_stat_d1; + end + end + +// generate clear-on-read signal + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + clear_on_read <= 1'b0; + read_detect <= 1'b0; + rd_d1 <= 1'b0; + rd_d2 <= 1'b0; + end + else begin + if (!write && ready && cs_0) + read_detect <= 1'b1; + else + read_detect <= 1'b0; + + rd_d1 <= read_detect; + rd_d2 <= rd_d1; + + // assert on falling edge of rd_d2 + clear_on_read <= !rd_d1 & rd_d2; + end + end + + +// Latch and Clear + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + allow_link_stat <= 1'b0; + link_ok_status <= 1'b0; + end + else begin + + case (allow_link_stat) + 1'b0: begin + if (clear_on_read) begin + allow_link_stat<= 1'b1; + end + end + + 1'b1: begin + if (!link_stat_d2) begin + allow_link_stat <= 1'b0; + end + end + endcase + + + if (allow_link_stat) begin + // allow status shoot-thru after clear-on-read + link_ok_status <= link_stat_d2; + end + else begin + // force status low when link IS NOT_OKAY + link_ok_status <= 1'b0; + end + + end + end + + +// Read Operations + + always @(*) begin + data_out[7] <= mr_stat_unidir_able; + data_out[6] <= mr_stat_preamb_supr; + data_out[5] <= mr_stat_an_complete; + data_out[4] <= mr_stat_remote_fault; + data_out[3] <= mr_stat_an_able; + data_out[2] <= link_ok_status; + data_out[1] <= mr_stat_jab_det; + data_out[0] <= mr_stat_extended_cap; + + data_out[15] <= mr_stat_100base_t4; + data_out[14] <= mr_stat_100base_x_fd; + data_out[13] <= mr_stat_100base_x_hd; + data_out[12] <= mr_stat_10mbps_fd; + data_out[11] <= mr_stat_10mbps_hd; + data_out[10] <= mr_stat_100base_t2_fd; + data_out[9] <= mr_stat_100base_t2_hd; + data_out[8] <= mr_stat_extended_stat; + end +endmodule + +module register_4_hb ( + rst_n, + clk, + gbe_mode, + sgmii_mode, + cs_0, + cs_1, + write, + ready, + data_in, + + data_out, + mr_adv_ability +); + +parameter [15:0] initval_gbe = 16'h0020; +parameter [15:0] initval_phy = 16'hd801; +parameter [15:0] initval_mac = 16'h4001; + +input rst_n; +input clk; +input gbe_mode; +input sgmii_mode; +input cs_0; +input cs_1; +input write; +input ready; +input [15:0] data_in; + +output [15:0] data_out; +output [15:0] mr_adv_ability; // When sgmii_mode == 1 == PHY + // all bits D15-D0 are R/W, + /////////////////////////////////// + // D15 = Link Status (1=up, 0=down) + // D14 = Can be written but has no effect + // on autonegotiation. Instead + // the autonegotiation state machine + // controls the utilization of this bit. + // D12 = Duplex Mode (1=full, 0=half) + // D11:10 = Speed (11=reserved) + // (10=1000Mbps) + // (01=100 Mbps) + // (00=10 Mbps) + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + //When sgmii_mode == 0 = MAC + // all bits D15-D0 are R/W, + // D14 = Can be written but has no effect + // on autonegotiation. Instead + // the autonegotiation state machine + // controls the utilization of this bit. + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + + +reg [15:0] data_out; +reg [15:0] mr_adv_ability; +reg rst_d1; +reg rst_d2; +reg rst_d3; +reg rst_d4; +reg rst_d5; +reg rst_d6; +reg rst_d7; +reg rst_d8; +reg sync_reset; +reg sgmii_mode_d1; +reg sgmii_mode_d2; +reg sgmii_mode_d3; +reg sgmii_mode_d4; +reg sgmii_mode_change; +reg gbe_mode_d1; +reg gbe_mode_d2; +reg gbe_mode_d3; +reg gbe_mode_d4; +reg gbe_mode_change; + +// generate a synchronous reset signal +// note: this method is used so that +// an initval can be applied during +// device run-time, instead of at compile time +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + rst_d1 <= 0; + rst_d2 <= 0; + rst_d3 <= 0; + rst_d4 <= 0; + rst_d5 <= 0; + rst_d6 <= 0; + rst_d7 <= 0; + rst_d8 <= 0; + sync_reset <= 0; + end + else begin + rst_d1 <= 1; + rst_d2 <= rst_d1; + rst_d3 <= rst_d2; + rst_d4 <= rst_d3; + rst_d5 <= rst_d4; + rst_d6 <= rst_d5; + rst_d7 <= rst_d6; + rst_d8 <= rst_d7; + + // asserts on rising edge of rst_d8 + sync_reset <= !rst_d8 & rst_d7; + end +end + + +// Detect change in sgmii_mode +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + sgmii_mode_d1 <= 0; + sgmii_mode_d2 <= 0; + sgmii_mode_d3 <= 0; + sgmii_mode_d4 <= 0; + sgmii_mode_change <= 0; + end + else begin + + // deboggle + sgmii_mode_d1 <= sgmii_mode; + sgmii_mode_d2 <= sgmii_mode_d1; + + // delay + sgmii_mode_d3 <= sgmii_mode_d2; + sgmii_mode_d4 <= sgmii_mode_d3; + + // detect change + if (sgmii_mode_d3 != sgmii_mode_d4) + sgmii_mode_change <= 1; + else + sgmii_mode_change <= 0; + end +end + + +// Detect change in gbe_mode +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + gbe_mode_d1 <= 0; + gbe_mode_d2 <= 0; + gbe_mode_d3 <= 0; + gbe_mode_d4 <= 0; + gbe_mode_change <= 0; + end + else begin + + // deboggle + gbe_mode_d1 <= gbe_mode; + gbe_mode_d2 <= gbe_mode_d1; + + // delay + gbe_mode_d3 <= gbe_mode_d2; + gbe_mode_d4 <= gbe_mode_d3; + + // detect change + if (gbe_mode_d3 != gbe_mode_d4) + gbe_mode_change <= 1; + else + gbe_mode_change <= 0; + end +end + + +// Write Operations + // Low Portion of Register[D7:D0] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_adv_ability[7:0] <= 8'h01; + end + else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin + if (gbe_mode_d4) + mr_adv_ability[7:0] <= initval_gbe[7:0]; + else if (sgmii_mode) + mr_adv_ability[7:0] <= initval_phy[7:0]; + else + mr_adv_ability[7:0] <= initval_mac[7:0]; + end + else begin + if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin + mr_adv_ability[7:0] <= data_in[7:0]; + end + end + end + + + // High Portion of Register[D15:D8] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_adv_ability[15:8] <= 8'h40; // default + end + else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin + if (gbe_mode_d4) + mr_adv_ability[15:8] <= initval_gbe[15:8]; + else if (sgmii_mode) + mr_adv_ability[15:8] <= initval_phy[15:8]; + else + mr_adv_ability[15:8] <= initval_mac[15:8]; + end + else begin + if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin + mr_adv_ability[15:8] <= data_in[15:8]; + end + end + end + + + + + + + + + +// Read Operations + + always @(*) begin + data_out[7:0] <= mr_adv_ability[7:0]; + data_out[15:8] <= mr_adv_ability[15:8]; + end + +endmodule + + + + + + +module register_5_hb ( + rst_n, + mr_lp_adv_ability, + cs_0, + cs_1, + ready, + + data_out +); + +input rst_n; +input cs_0; +input cs_1; +input ready; +input [15:0] mr_lp_adv_ability; + // This entire register is read-only + /////////////////////////////////// + // When sgmii_mode == 0 == MAC + /////////////////////////////////// + // D15 = PHY Link Status (1=up, 0=down) + // D14 = PHY Autonegotiation Handshake + // D12 = PHY Duplex Mode (1=full, 0=half) + // D11:10 = PHY Speed (11=reserved) + // (10=1000Mbps) + // (01=100 Mbps) + // (00=10 Mbps) + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + //When sgmii_mode == 1 = PHY + // D14 = MAC Autonegotiation Handshake + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// +output [15:0] data_out; + +reg [15:0] data_out; + +// Read Operations + + always @(*) begin + data_out[7:0] <= mr_lp_adv_ability[7:0]; + data_out[15:8] <= mr_lp_adv_ability[15:8]; + end +endmodule + +module register_6_hb ( + rst_n, + clk, + mr_page_rx, + cs_0, + cs_1, + write, + ready, + + data_out +); + +input rst_n; +input clk; +input cs_0; +input cs_1; +input write; +input ready; +input mr_page_rx; +output [15:0] data_out; + +reg [15:0] data_out; +reg mr_page_rx_latched; +reg clear_on_read; +reg read_detect; +reg rd_d1; +reg rd_d2; + +// generate clear-on-read signal + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + clear_on_read <= 0; + read_detect <= 0; + rd_d1 <= 0; + rd_d2 <= 0; + end + else begin + if (!write && ready && cs_0) + read_detect <= 1; + else + read_detect <= 0; + + rd_d1 <= read_detect; + rd_d2 <= rd_d1; + + // assert on falling edge of rd_d2 + clear_on_read <= !rd_d1 & rd_d2; + end + end + + +// Latch and Clear + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_page_rx_latched <= 0; + end + else begin + if (clear_on_read) + mr_page_rx_latched <= 0; + else if (mr_page_rx) + mr_page_rx_latched <= 1; + end + end + + +// Read Operations + + always @(*) begin + data_out[15:2] <= 14'd0; + data_out[1] <= mr_page_rx_latched; + data_out[0] <= 0; + end +endmodule + + +module register_f_hb ( + rst_n, + cs_0, + cs_1, + + mr_stat_1000base_x_fd, + mr_stat_1000base_x_hd, + mr_stat_1000base_t_fd, + mr_stat_1000base_t_hd, + + data_out +); + +input rst_n; +input cs_0; +input cs_1; + +input mr_stat_1000base_x_fd; // bit D15 // Read-Only +input mr_stat_1000base_x_hd; // bit D14 // Read-Only +input mr_stat_1000base_t_fd; // bit D13 // Read-Only +input mr_stat_1000base_t_hd; // bit D12 // Read-Only + +output [15:0] data_out; + +reg [15:0] data_out; + + +// Read Operations + + always @(*) begin + data_out[7] <= 1'b0; + data_out[6] <= 1'b0; + data_out[5] <= 1'b0; + data_out[4] <= 1'b0; + data_out[3] <= 1'b0; + data_out[2] <= 1'b0; + data_out[1] <= 1'b0; + data_out[0] <= 1'b0; + + data_out[15] <= mr_stat_1000base_x_fd; + data_out[14] <= mr_stat_1000base_x_hd; + data_out[13] <= mr_stat_1000base_t_fd; + data_out[12] <= mr_stat_1000base_t_hd; + data_out[11] <= 1'b0; + data_out[10] <= 1'b0; + data_out[9] <= 1'b0; + data_out[8] <= 1'b0; + end +endmodule + + +module regs_hb ( + rst_n, + hclk, + gbe_mode, + sgmii_mode, + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + mr_stat_1000base_x_fd, + mr_stat_1000base_x_hd, + mr_stat_1000base_t_fd, + mr_stat_1000base_t_hd, + + mr_stat_100base_t4, + mr_stat_100base_x_fd, + mr_stat_100base_x_hd, + mr_stat_10mbps_fd, + mr_stat_10mbps_hd, + mr_stat_100base_t2_fd, + mr_stat_100base_t2_hd, + + mr_stat_extended_stat, + mr_stat_unidir_able, + mr_stat_preamb_supr, + mr_stat_an_complete, + mr_stat_remote_fault, + mr_stat_an_able, + mr_stat_link_stat, + mr_stat_jab_det, + mr_stat_extended_cap, + + mr_page_rx, + mr_lp_adv_ability, + + mr_main_reset, + mr_loopback_enable, + mr_speed_selection, + mr_an_enable, + mr_power_down, + mr_isolate, + mr_restart_an, + mr_duplex_mode, + mr_col_test, + mr_unidir_enable, + mr_adv_ability +); + +input rst_n; +input hclk; +input gbe_mode; +input sgmii_mode; +input hcs_n; +input hwrite_n; +input [5:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input mr_stat_1000base_x_fd; +input mr_stat_1000base_x_hd; +input mr_stat_1000base_t_fd; +input mr_stat_1000base_t_hd; + +input mr_stat_100base_t4; +input mr_stat_100base_x_fd; +input mr_stat_100base_x_hd; +input mr_stat_10mbps_fd; +input mr_stat_10mbps_hd; +input mr_stat_100base_t2_fd; +input mr_stat_100base_t2_hd; + +input mr_stat_extended_stat; +input mr_stat_unidir_able; +input mr_stat_preamb_supr; +input mr_stat_an_complete; +input mr_stat_remote_fault; +input mr_stat_an_able; +input mr_stat_link_stat; +input mr_stat_jab_det; +input mr_stat_extended_cap; + +input mr_page_rx; +input [15:0] mr_lp_adv_ability; + +output mr_main_reset; +output mr_loopback_enable; +output [1:0] mr_speed_selection; +output mr_an_enable; +output mr_power_down; +output mr_isolate; +output mr_restart_an; +output mr_duplex_mode; +output mr_col_test; +output mr_unidir_enable; +output [15:0] mr_adv_ability; + +/////////////////////////////////// + + + +reg [7:0] hdataout; +reg hr; +reg hready_n; + +reg hcs_n_delayed; + +wire reg0_cs_0; +wire reg0_cs_1; + +wire reg1_cs_0; +wire reg1_cs_1; + +wire reg4_cs_0; +wire reg4_cs_1; + +wire reg5_cs_0; +wire reg5_cs_1; + +wire reg6_cs_0; +wire reg6_cs_1; + +wire regf_cs_0; +wire regf_cs_1; + +wire [15:0] data_out_reg_0; +wire [15:0] data_out_reg_1; +wire [15:0] data_out_reg_4; +wire [15:0] data_out_reg_5; +wire [15:0] data_out_reg_6; +wire [15:0] data_out_reg_f; + + + +register_addr_decoder ad_dec ( + .rst_n(rst_n), + .addr(haddr), + .cs_in(~hcs_n), + + .reg0_cs_0 (reg0_cs_0), + .reg0_cs_1 (reg0_cs_1), + .reg1_cs_0 (reg1_cs_0), + .reg1_cs_1 (reg1_cs_1), + .reg4_cs_0 (reg4_cs_0), + .reg4_cs_1 (reg4_cs_1), + .reg5_cs_0 (reg5_cs_0), + .reg5_cs_1 (reg5_cs_1), + .reg6_cs_0 (reg6_cs_0), + .reg6_cs_1 (reg6_cs_1), + .regf_cs_0 (regf_cs_0), + .regf_cs_1 (regf_cs_1) +); + + +register_0_hb register_0 ( + .rst_n (rst_n), + .clk (hclk), + .gbe_mode (gbe_mode), + .cs_0 (reg0_cs_0), + .cs_1 (reg0_cs_1), + .write (~hwrite_n), + .ready (1'b1), + .data_in ({hdatain, hdatain}), + + .data_out (data_out_reg_0), + .mr_main_reset (mr_main_reset), + .mr_loopback_enable (mr_loopback_enable), + .mr_speed_selection (mr_speed_selection), + .mr_an_enable (mr_an_enable), + .mr_power_down (mr_power_down), + .mr_isolate (mr_isolate), + .mr_restart_an (mr_restart_an), + .mr_duplex_mode (mr_duplex_mode), + .mr_col_test (mr_col_test), + .mr_unidir_enable (mr_unidir_enable) +); + + +register_1_hb register_1 ( + .rst_n (rst_n), + .clk (hclk), + .cs_0 (reg1_cs_0), + .cs_1 (reg1_cs_1), + .write (~hwrite_n), + .ready (1'b1), + + .mr_stat_100base_t4 (mr_stat_100base_t4), + .mr_stat_100base_x_fd (mr_stat_100base_x_fd), + .mr_stat_100base_x_hd (mr_stat_100base_x_hd), + .mr_stat_10mbps_fd (mr_stat_10mbps_fd), + .mr_stat_10mbps_hd (mr_stat_10mbps_hd), + .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd), + .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd), + + .mr_stat_extended_stat (mr_stat_extended_stat), + .mr_stat_unidir_able (mr_stat_unidir_able), + .mr_stat_preamb_supr (mr_stat_preamb_supr), + .mr_stat_an_complete (mr_stat_an_complete), + .mr_stat_remote_fault (mr_stat_remote_fault), + .mr_stat_an_able (mr_stat_an_able), + .mr_stat_link_stat (mr_stat_link_stat), + .mr_stat_jab_det (mr_stat_jab_det), + .mr_stat_extended_cap (mr_stat_extended_cap), + + .data_out (data_out_reg_1) +); + + +register_4_hb register_4 ( + .rst_n (rst_n), + .clk (hclk), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .cs_0 (reg4_cs_0), + .cs_1 (reg4_cs_1), + .write (~hwrite_n), + .ready (1'b1), + .data_in ({hdatain, hdatain}), + + .data_out (data_out_reg_4), + .mr_adv_ability (mr_adv_ability) +); + + +register_5_hb register_5 ( + .rst_n (rst_n), + .mr_lp_adv_ability (mr_lp_adv_ability), + .cs_0 (reg5_cs_0), + .cs_1 (reg5_cs_1), + .ready (1'b1), + + .data_out (data_out_reg_5) +); + + +register_6_hb register_6 ( + .rst_n (rst_n), + .clk (hclk), + .mr_page_rx (mr_page_rx), + .cs_0 (reg6_cs_0), + .cs_1 (reg6_cs_1), + .write (~hwrite_n), + .ready (1'b1), + + .data_out (data_out_reg_6) +); + + + +register_f_hb register_f ( + .rst_n (rst_n), + .cs_0 (regf_cs_0), + .cs_1 (regf_cs_1), + + .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd), + .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd), + .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd), + .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd), + + .data_out (data_out_reg_f) +); + + +// generate an ack +always @(posedge hclk or negedge rst_n) begin + if (rst_n == 1'b0) begin + hcs_n_delayed <= 1'b1; + hr <= 1'b1; + hready_n <= 1'b1; + end + else begin + hcs_n_delayed <= hcs_n; + + //assert on falling edge of delayed chip select + hr <= ~hcs_n & hcs_n_delayed; + hready_n <= ~hr; + end +end + + + +// Mux Register Read-Data Outputs +always @(posedge hclk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + hdataout <= 8'd0; + end + else begin + case (haddr[5:0]) + + 6'd0: + begin + hdataout <= data_out_reg_0[7:0]; + end + + + 6'd1: + begin + hdataout <= data_out_reg_0[15:8]; + end + + ///////////////////////////////////////////// + + 6'd2: + begin + hdataout <= data_out_reg_1[7:0]; + end + + + 6'd3: + begin + hdataout <= data_out_reg_1[15:8]; + end + + ///////////////////////////////////////////// + + 6'd8: + begin + hdataout <= data_out_reg_4[7:0]; + end + + + 6'd9: + begin + hdataout <= data_out_reg_4[15:8]; + end + + ///////////////////////////////////////////// + + 6'd10: + begin + hdataout <= data_out_reg_5[7:0]; + end + + + 6'd11: + begin + hdataout <= data_out_reg_5[15:8]; + end + + ///////////////////////////////////////////// + + 6'd12: + begin + hdataout <= data_out_reg_6[7:0]; + end + + + 6'd13: + begin + hdataout <= data_out_reg_6[15:8]; + end + + ///////////////////////////////////////////// + + 6'd30: + begin + hdataout <= data_out_reg_f[7:0]; + end + + + 6'd31: + begin + hdataout <= data_out_reg_f[15:8]; + end + + ///////////////////////////////////////////// + + default: + begin + hdataout <= 8'd0; + end + endcase + end +end + +endmodule + +module register_addr_decoder ( + rst_n, + addr, + cs_in, + + reg0_cs_0, + reg0_cs_1, + + reg1_cs_0, + reg1_cs_1, + + reg4_cs_0, + reg4_cs_1, + + reg5_cs_0, + reg5_cs_1, + + reg6_cs_0, + reg6_cs_1, + + regf_cs_0, + regf_cs_1 +); + +input rst_n; +input cs_in; +input [5:0] addr; + +output reg0_cs_0; +output reg0_cs_1; + +output reg1_cs_0; +output reg1_cs_1; + +output reg4_cs_0; +output reg4_cs_1; + +output reg5_cs_0; +output reg5_cs_1; + +output reg6_cs_0; +output reg6_cs_1; + +output regf_cs_0; +output regf_cs_1; + +////////////////////////// + +wire reg0_cs_0; +wire reg0_cs_1; + +wire reg1_cs_0; +wire reg1_cs_1; + +wire reg4_cs_0; +wire reg4_cs_1; + +wire reg5_cs_0; +wire reg5_cs_1; + +wire reg6_cs_0; +wire reg6_cs_1; + +wire regf_cs_0; +wire regf_cs_1; + +////////////////////////// + +assign reg0_cs_0 = (addr == 6'h00) ? cs_in : 1'b0; +assign reg0_cs_1 = (addr == 6'h01) ? cs_in : 1'b0; + +assign reg1_cs_0 = (addr == 6'h02) ? cs_in : 1'b0; +assign reg1_cs_1 = (addr == 6'h03) ? cs_in : 1'b0; + +assign reg4_cs_0 = (addr == 6'h08) ? cs_in : 1'b0; +assign reg4_cs_1 = (addr == 6'h09) ? cs_in : 1'b0; + +assign reg5_cs_0 = (addr == 6'h0a) ? cs_in : 1'b0; +assign reg5_cs_1 = (addr == 6'h0b) ? cs_in : 1'b0; + +assign reg6_cs_0 = (addr == 6'h0c) ? cs_in : 1'b0; +assign reg6_cs_1 = (addr == 6'h0d) ? cs_in : 1'b0; + +assign regf_cs_0 = (addr == 6'h1e) ? cs_in : 1'b0; +assign regf_cs_1 = (addr == 6'h1f) ? cs_in : 1'b0; + + +endmodule + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/sgmii_channel_smi.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/sgmii_channel_smi.v new file mode 100644 index 0000000..54ee87a --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/sgmii_channel_smi.v @@ -0,0 +1,280 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module sgmii_channel_smi ( + + // Control Interface + rst_n, + gbe_mode, + sgmii_mode, + signal_detect, + debug_link_timer_short, + rx_compensation_err, + + // G/MII Interface + in_clk_gmii, + in_clk_mii, + data_in_mii, + en_in_mii, + err_in_mii, + + out_clk_gmii, + out_clk_mii, + data_out_mii, + dv_out_mii, + err_out_mii, + col_out_mii, + crs_out_mii, + + // 8-bit Interface + data_out_8bi, + kcntl_out_8bi, + disparity_cntl_out_8bi, + + serdes_recovered_clk, + data_in_8bi, + kcntl_in_8bi, + even_in_8bi, + disp_err_in_8bi, + cv_err_in_8bi, + err_decode_mode_8bi, + + // MDIO Port + mdc, + mdio, + port_id + ); + + + +// I/O Declarations +input rst_n ; // System Reset, Active Low +input signal_detect ; +input gbe_mode ; // GBE Mode (0=SGMII 1=GBE) +input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY) +input debug_link_timer_short ; // (0=NORMAL 1=SHORT) +output rx_compensation_err; // Active high pulse indicating RX_CTC_FIFO either underflowed or overflowed + +input in_clk_mii ; // G/MII Transmit clock 2.5Mhz/25Mhz/125Mhz +input [7:0] data_in_mii ; // G/MII Tx data +input en_in_mii ; // G/MII data valid +input err_in_mii ; // G/MII Tx error + +input out_clk_mii ; // G/MII Receice clock 2.5Mhz/25Mhz/125MHz +output [7:0] data_out_mii ; // G/MII Rx data +output dv_out_mii ; // G/MII Rx data valid +output err_out_mii ; // G/MII Rx error +output col_out_mii ; // G/MII collision detect +output crs_out_mii ; // G/MII carrier sense detect + +output [7:0] data_out_8bi ; // 8BI Tx Data +output kcntl_out_8bi ; // 8BI Tx Kcntl +output disparity_cntl_out_8bi ; // 8BI Tx Kcntl + +input serdes_recovered_clk ; +input [7:0] data_in_8bi ; // 8BI Rx Data +input kcntl_in_8bi ; // 8BI Rx Kcntl +input even_in_8bi ; // 8BI Rx Even +input disp_err_in_8bi ; // 8BI Rx Disparity Error +input cv_err_in_8bi ; // 8BI Rx Coding Violation Error +input err_decode_mode_8bi ; // 8BI Error Decode Mode (0=NORMAL, 1=DECODE_MODE) + +input in_clk_gmii ; // GMII Transmit clock 125Mhz +input out_clk_gmii ; // GMII Receive clock 125Mhz + +input mdc; +inout mdio; +input [4:0] port_id; + + +wire mdin; +wire mdout; +wire mdout_en; + +// Internal Signals + +wire mr_an_complete; +wire mr_page_rx; +wire [15:0] mr_lp_adv_ability; + +wire mr_main_reset; +wire mr_an_enable; +wire mr_restart_an; +wire [15:0] mr_adv_ability; +wire mr_loopback_enable; +wire [1:0] mr_speed_selection; +wire mr_power_down; +wire mr_isolate; +wire mr_duplex_mode; +wire mr_col_test; +wire mr_unidir_enable; +wire an_link_ok; + +wire [1:0] operational_rate; + + + + + + + + +// SGMII PCS +USER_NAME USER_NAME_U ( + // Clock and Reset + .rst_n (rst_n ), + .signal_detect (signal_detect), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .debug_link_timer_short (debug_link_timer_short), + .force_isolate (mr_isolate), + .force_loopback (mr_loopback_enable), + .force_unidir (mr_unidir_enable), + .operational_rate (operational_rate), + .rx_compensation_err (rx_compensation_err), + .ctc_drop_flag (), + .ctc_add_flag (), + .an_link_ok (an_link_ok), + .tx_clk_125 (in_clk_gmii), + .serdes_recovered_clk (serdes_recovered_clk), + .rx_clk_125 (out_clk_gmii), + + // Control + + + // (G)MII TX Port + .tx_clk_mii (in_clk_mii), + .tx_d (data_in_mii), + .tx_en (en_in_mii), + .tx_er (err_in_mii), + + // (G)MII RX Port + .rx_clk_mii (out_clk_mii), + .rx_d (data_out_mii), + .rx_dv (dv_out_mii), + .rx_er (err_out_mii), + .col (col_out_mii), + .crs (crs_out_mii), + + // 8BI TX Port + .tx_data (data_out_8bi), + .tx_kcntl (kcntl_out_8bi), + .tx_disparity_cntl (disparity_cntl_out_8bi), + .xmit_autoneg (), + + // 8BI RX Port + .rx_data (data_in_8bi), + .rx_kcntl (kcntl_in_8bi), + .rx_even (even_in_8bi), + .rx_disp_err (disp_err_in_8bi), + .rx_cv_err (cv_err_in_8bi), + .rx_err_decode_mode (err_decode_mode_8bi), + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + + + +// SMI Register Interface for SGMII IP Core +register_interface_smi ri ( + + // Control Signals + .rst_n (rst_n), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + + // MDIO Port + .mdc (mdc), + .mdin (mdin), + .mdout (mdout), + .mdout_en (mdout_en), + .port_id (port_id), + + // Register Outputs + .mr_main_reset (mr_main_reset), + .mr_loopback_enable (mr_loopback_enable), + .mr_speed_selection (mr_speed_selection), + .mr_an_enable (mr_an_enable), + .mr_power_down (mr_power_down), + .mr_isolate (mr_isolate), + .mr_restart_an (mr_restart_an), + .mr_duplex_mode (mr_duplex_mode), + .mr_col_test (mr_col_test), + .mr_unidir_enable (mr_unidir_enable), + + .mr_adv_ability (mr_adv_ability), + + // Register Inputs + .mr_stat_1000base_x_fd (1'b1), // SUPPORTED + .mr_stat_1000base_x_hd (1'b0), + .mr_stat_1000base_t_fd (1'b0), + .mr_stat_1000base_t_hd (1'b0), + + .mr_stat_100base_t4 (1'b0), + .mr_stat_100base_x_fd (1'b0), + .mr_stat_100base_x_hd (1'b0), + .mr_stat_10mbps_fd (1'b0), + .mr_stat_10mbps_hd (1'b0), + .mr_stat_100base_t2_fd (1'b0), + .mr_stat_100base_t2_hd (1'b0), + + .mr_stat_extended_stat (1'b1), // SUPPORTED + .mr_stat_unidir_able (mr_unidir_enable), + .mr_stat_preamb_supr (1'b0), + .mr_stat_an_complete (mr_an_complete), + .mr_stat_remote_fault (1'b0), + .mr_stat_an_able (1'b1), // SUPPORTED + .mr_stat_link_stat (an_link_ok), + .mr_stat_jab_det (1'b0), + .mr_stat_extended_cap (1'b0), + + .mr_page_rx (mr_page_rx), + .mr_lp_adv_ability (mr_lp_adv_ability) + ); + + + +// (G)MII Rate Resolution for SGMII IP Core +rate_resolution rate_resolution ( + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .an_enable (mr_an_enable), + .advertised_rate (mr_adv_ability[11:10]), + .link_partner_rate (mr_lp_adv_ability[11:10]), + .non_an_rate (mr_speed_selection), // speed selected when auto-negotiation disabled + + .operational_rate (operational_rate) +); + + + + + +// Bidirectional Assignments +assign mdio = mdout_en ? mdout : 1'bz; // MDIO Output +assign mdin = mdio; // MDIO Input + +endmodule + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_hb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_hb.v new file mode 100644 index 0000000..cba77f6 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_hb.v @@ -0,0 +1,404 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module top_hb ( + + // G/MII Interface + data_in_mii, + en_in_mii, + err_in_mii, + + data_out_mii, + dv_out_mii, + err_out_mii, + col_out_mii, + crs_out_mii, + + // GB Timing References + in_clk_125, + in_ce_sink, + in_ce_source, + out_clk_125, + out_ce_sink, + out_ce_source, + + // SERIAL GMII Interface + refclkp, + refclkn, + hdinp0, + hdinn0, + hdoutp0, + hdoutn0, + + // Control Interface + gbe_mode, + sgmii_mode, + rst_n, + + // Host Bus + hclk, + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + //Debug Port + debug_link_timer_short, + mr_an_complete + ); + + + +// I/O Declarations +input rst_n; // System Reset, Active Low +input hclk; +input gbe_mode ; // GBE Mode (0=SGMII 1=GBE) +input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY) + +input in_clk_125 ; // GMII Input Data Path clock 125Mhz +input in_ce_sink ; +output in_ce_source ; +input [7:0] data_in_mii; // G/MII Incoming Data +input en_in_mii; // G/MII Incoming Data Valid +input err_in_mii; // G/MII Incoming Error + +input out_clk_125 ; // GMII Output Data Path clock 125Mhz +input out_ce_sink ; +output out_ce_source ; +output [7:0] data_out_mii; // G/MII Outgoing Data +output dv_out_mii; // G/MII Outgoing Data Valid +output err_out_mii; // G/MII Outgoing Error +output col_out_mii; // G/MII Collision Detect +output crs_out_mii; // G/MII Carrier Sense Detect + +input refclkp; +input refclkn; +// exemplar attribute refclkp NOPAD true +// exemplar attribute refclkn NOPAD true + +input hdinp0; // Incoming SGMII (on SERDES) +input hdinn0; // Incoming SGMII (on SERDES) +// exemplar attribute hdinp0 NOPAD true +// exemplar attribute hdinn0 NOPAD true + +output hdoutp0; // Outgoing SGMII (on SERDES) +output hdoutn0; // Outgoing SGMII (on SERDES) +// exemplar attribute hdoutp0 NOPAD true +// exemplar attribute hdoutn0 NOPAD true + +input hcs_n; +input hwrite_n; +input [5:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input debug_link_timer_short; +output mr_an_complete; + +// Primary G/MII Outputs -- Latched Before Leaving FPGA +reg [7:0] data_out_mii; +reg dv_out_mii; +reg err_out_mii; +reg col_out_mii; +reg crs_out_mii; + +// G/MII Signals from input latches to SGMII channel +reg [7:0] data_buf2chan; +reg en_buf2chan; +reg err_buf2chan; + +// G/MII Signals from SGMII channel to output latches +wire [7:0] data_chan2buf; +wire dv_chan2buf; +wire err_chan2buf; +wire col_chan2buf; +wire crs_chan2buf; + +// 8-bit Interface Signals from SGMII channel to QuadPCS/SERDES +//wire [7:0] data_chan2quad; +//wire kcntl_chan2quad; +//wire disparity_cntl_chan2quad; +//wire xmit_autoneg; + +// 8-bit Interface Signals from QuadPCS/SERDES to SGMII channel +//wire [7:0] data_quad2chan; +//wire kcntl_quad2chan; +//wire disp_err_quad2chan; +//wire cv_err_quad2chan; +//wire link_status; +//wire serdes_recovered_clk; +wire clk_125; + +// Misc Signals +wire mdin; +wire mdout; +wire mdout_en; + +wire mr_an_enable; +wire mr_restart_an; +wire [15:0] mr_adv_ability; + +wire mr_an_complete; +wire mr_page_rx; +wire [15:0] mr_lp_adv_ability; +wire mr_main_reset; +wire mr_loopback_enable; +wire [1:0] mr_speed_selection; +wire mr_power_down; +wire mr_isolate; +wire mr_duplex_mode; +wire mr_col_test; +wire mr_unidir_enable; +wire an_link_ok; + +wire debug_link_timer_short; +wire [1:0] operational_rate; + +wire tx_pll_lol; +wire rx_cdr_lol; +wire quad_rst; +wire tx_pcs_rst; +wire rx_pcs_rst; +wire rx_serdes_rst; + +wire nc_1; +wire nc_2; +wire nc_3; + +wire sli_rst; +wire serdes_rst_dual_c; +wire tx_serdes_rst_c; +wire serdes_pdb; +wire tx_pwrup_c; + +assign sli_rst = serdes_rst_dual_c || tx_serdes_rst_c || (!serdes_pdb) || (!tx_pwrup_c); + + +// Active High Reset +wire rst; +assign rst = ~rst_n; + +// Instantiate Global Reset Controller +GSR GSR_INST (.GSR(rst_n)); +PUR PUR_INST (.PUR(1'b1)); + +// Buffer Incoming MII Data at Primary I/O +always @(posedge in_clk_125 or negedge rst_n) +begin + if (rst_n == 1'b0) begin + data_buf2chan <= 8'd0; + en_buf2chan <= 0; + err_buf2chan <= 0; + end + else begin + data_buf2chan <= data_in_mii; + en_buf2chan <= en_in_mii; + err_buf2chan <= err_in_mii; + end +end + +// Buffer Outgoing MII Data at Primary I/O +always @(posedge out_clk_125 or negedge rst_n) +begin + if (rst_n == 1'b0) begin + data_out_mii <= 8'd0; + dv_out_mii <= 0; + err_out_mii <= 0; + col_out_mii <= 0; + crs_out_mii <= 0; + end + else begin + data_out_mii <= data_chan2buf; + dv_out_mii <= dv_chan2buf; + err_out_mii <= err_chan2buf; + col_out_mii <= col_chan2buf; + crs_out_mii <= crs_chan2buf; + end +end + + +// Host Bus Register Interface for SGMII IP Core +register_interface_hb ri ( + + // Control Signals + .rst_n (rst_n), + .hclk (hclk), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + + // Host Bus + .hcs_n (hcs_n), + .hwrite_n (hwrite_n), + .haddr (haddr), + .hdatain (hdatain), + + .hdataout (hdataout), + .hready_n (hready_n), + + // Register Outputs + .mr_main_reset (mr_main_reset), + .mr_loopback_enable (mr_loopback_enable), + .mr_speed_selection (mr_speed_selection), + .mr_an_enable (mr_an_enable), + .mr_power_down (mr_power_down), + .mr_isolate (mr_isolate), + .mr_restart_an (mr_restart_an), + .mr_duplex_mode (mr_duplex_mode), + .mr_col_test (mr_col_test), + .mr_unidir_enable (mr_unidir_enable), + + .mr_adv_ability (mr_adv_ability), + + // Register Inputs + .mr_stat_1000base_x_fd (1'b1), // SUPPORTED + .mr_stat_1000base_x_hd (1'b0), + .mr_stat_1000base_t_fd (1'b0), + .mr_stat_1000base_t_hd (1'b0), + + .mr_stat_100base_t4 (1'b0), + .mr_stat_100base_x_fd (1'b0), + .mr_stat_100base_x_hd (1'b0), + .mr_stat_10mbps_fd (1'b0), + .mr_stat_10mbps_hd (1'b0), + .mr_stat_100base_t2_fd (1'b0), + .mr_stat_100base_t2_hd (1'b0), + + .mr_stat_extended_stat (1'b1), // SUPPORTED + .mr_stat_unidir_able (mr_unidir_enable), + .mr_stat_preamb_supr (1'b0), + .mr_stat_an_complete (mr_an_complete), + .mr_stat_remote_fault (1'b0), + .mr_stat_an_able (1'b1), // SUPPORTED + .mr_stat_link_stat (an_link_ok), + .mr_stat_jab_det (1'b0), + .mr_stat_extended_cap (1'b0), + + .mr_page_rx (mr_page_rx), + .mr_lp_adv_ability (mr_lp_adv_ability) + ); + + + +// (G)MII Rate Resolution for SGMII IP Core +rate_resolution rate_resolution ( + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .an_enable (mr_an_enable), + .advertised_rate (mr_adv_ability[11:10]), + .link_partner_rate (mr_lp_adv_ability[11:10]), + .non_an_rate (mr_speed_selection), // speed selected when auto-negotiation disabled + + .operational_rate (operational_rate) +); + +ILVDS ILVDS_X ( + .A (refclkp), + .AN(refclkn), + .Z (clk_125)); + +sgmii_channel_smi u_sgmii( + +//-----------USERNAME CORE-------------PART PORTS + // Control Interface + .rst_n (rst_n), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .operational_rate (operational_rate), + .debug_link_timer_short (debug_link_timer_short), + .force_isolate (mr_isolate), + .force_loopback (mr_loopback_enable), + .force_unidir (mr_unidir_enable), + .tx_clock_enable_sink (in_ce_sink), + .tx_clock_enable_source (in_ce_source), + .rx_clock_enable_sink (out_ce_sink), + .rx_clock_enable_source (out_ce_source), + + + .an_link_ok (an_link_ok), + + // G/MII Interface + .tx_d(data_buf2chan), + .tx_en (en_buf2chan), + .tx_er (err_buf2chan), + .tx_clk_125(in_clk_125), + .rx_clk_125(out_clk_125), + .rx_d (data_chan2buf), + .rx_dv (dv_chan2buf), + .rx_er (err_chan2buf), + .col (col_chan2buf), + .crs (crs_chan2buf), + + // Managment Control Outputs + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx), + + // Managment Control Inputs + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + +//-----------USERNAME PCS-------------PART PORTS + .hdinp(hdinp0), + .hdinn(hdinn0), + // outputs + .hdoutp(hdoutp0), + .hdoutn(hdoutn0), + + .sli_rst (sli_rst), + .serdes_rst_dual_c (serdes_rst_dual_c), + .tx_serdes_rst_c (tx_serdes_rst_c), + .serdes_pdb (serdes_pdb), + .tx_pwrup_c (tx_pwrup_c), + + + .pll_refclki (clk_125), + .rxrefclk (clk_125), + + //SCI interface + .cyawstn (1'b0), + .sci_en (1'b0), + .sci_en_dual (1'b0), + .sci_sel_dual (1'b0), + .sci_sel (1'b0), + .sci_wrdata (8'd0), + .sci_addr (6'd0), + .sci_rddata (), + .sci_rd (1'b0), + .sci_wrn (1'b1), + .sci_int (), + + .rx_cdr_lol_s (rx_cdr_lol), + + .tx_pcs_rst_c (1'b0), + .rx_pcs_rst_c (1'b0), + .rx_serdes_rst_c (1'b0), + + .rst_dual_c (~rst_n), + .pll_lol (tx_pll_lol), + + //New added + .mr_power_down(mr_power_down) +); +endmodule + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_pcs_core_only.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_pcs_core_only.v new file mode 100644 index 0000000..df7a705 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_pcs_core_only.v @@ -0,0 +1,203 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +module top_pcs_core_only ( + + // Control Interface + rst_n, + signal_detect, + gbe_mode, + sgmii_mode, + force_isolate, + force_loopback, + force_unidir, + operational_rate, + + rx_compensation_err, + ctc_drop_flag, + ctc_add_flag, + an_link_ok, + + // G/MII Interface + tx_clk_125, + tx_clock_enable_source, + tx_clock_enable_sink, + tx_d, + tx_en, + tx_er, + + rx_clk_125, + rx_clock_enable_source, + rx_clock_enable_sink, + rx_d, + rx_dv, + rx_er, + col, + crs, + + // 8-bit Interface + tx_data, + tx_kcntl, + tx_disparity_cntl, + xmit_autoneg, + + serdes_recovered_clk, + rx_data, + rx_kcntl, + rx_disp_err , + rx_cv_err , + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability + ); + + + +// Control Interface +input rst_n ; +input signal_detect ; +input gbe_mode ; +input sgmii_mode ; +input force_isolate ; +input force_loopback ; +input force_unidir ; +input [1:0] operational_rate ; + +output rx_compensation_err ; +output ctc_drop_flag ; +output ctc_add_flag ; +output an_link_ok ; + +// G/MII Interface +input tx_clk_125 ; +output tx_clock_enable_source ; +input tx_clock_enable_sink ; +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +input rx_clk_125 ; +output rx_clock_enable_source ; +input rx_clock_enable_sink ; +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// 8-bit Interface +output [7:0] tx_data ; +output tx_kcntl; +output tx_disparity_cntl; +output xmit_autoneg; + +input serdes_recovered_clk ; +input [7:0] rx_data ; +input rx_kcntl; +input rx_disp_err ; // Displarity error on "rx_data". +input rx_cv_err ; // Code error on "rx_data". + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + + + +// Instantiate Global Reset Controller +GSR GSR_INST (.GSR(rst_n)); +PUR PUR_INST (.PUR(1'b1)); + + +// SGMII PCS +sgmii_channel_smi_core sgmii_channel_smi_core ( + // Clock and Reset + .rst_n ( rst_n ) , + .signal_detect ( signal_detect ) , + .gbe_mode ( gbe_mode ) , + .sgmii_mode ( sgmii_mode ) , + .force_isolate ( force_isolate ) , + .force_loopback ( force_loopback ) , + .force_unidir ( force_unidir ) , + .operational_rate ( operational_rate ) , + .debug_link_timer_short ( 1'b0 ) , + + .rx_compensation_err ( rx_compensation_err ) , + .ctc_drop_flag ( ctc_drop_flag ) , + .ctc_add_flag ( ctc_add_flag ) , + .an_link_ok ( an_link_ok ) , + + .tx_clk_125 ( tx_clk_125 ) , + .tx_clock_enable_source ( tx_clock_enable_source ) , + .tx_clock_enable_sink ( tx_clock_enable_sink ) , + .serdes_recovered_clk ( serdes_recovered_clk ) , + .rx_clk_125 ( rx_clk_125 ) , + .rx_clock_enable_source ( rx_clock_enable_source ) , + .rx_clock_enable_sink ( rx_clock_enable_sink ) , + + // GMII TX Inputs + .tx_d ( tx_d) , + .tx_en ( tx_en) , + .tx_er ( tx_er) , + + // GMII RX Outputs + // To GMII/MAC interface + .rx_d ( rx_d ) , + .rx_dv ( rx_dv ) , + .rx_er ( rx_er ) , + .col ( col ) , + .crs ( crs ) , + + // 8BI TX Outputs + .tx_data ( tx_data) , + .tx_kcntl ( tx_kcntl) , + .tx_disparity_cntl ( tx_disparity_cntl) , + .xmit_autoneg ( xmit_autoneg) , + + // 8BI RX Inputs + .rx_data ( rx_data ) , + .rx_kcntl ( rx_kcntl ) , + .rx_even ( 1'b0 ) , + .rx_disp_err ( rx_disp_err ) , + .rx_cv_err ( rx_cv_err ) , + .rx_err_decode_mode ( 1'b0 ) , + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/mii_monitor.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/mii_monitor.v new file mode 100644 index 0000000..bc0e2a7 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/mii_monitor.v @@ -0,0 +1,118 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +//`timescale 1ns/100ps +`timescale 1ps/1ps + +module mii_monitor ( + rst_n, + clk, + GBspeed, + + data_in_ref, + dv_in_ref, + err_in_ref, + + data_in_dut, + dv_in_dut, + err_in_dut +); + +input rst_n; +input clk; +input GBspeed; + +input [7:0] data_in_ref; +input dv_in_ref; +input err_in_ref; + +input [7:0] data_in_dut; +input dv_in_dut; +input err_in_dut; + + + +wire [16:0] len_ref_pp; +wire len_write_ref_pp; + +wire [7:0] data_ref_pp; +wire err_ref_pp; +wire data_write_ref_pp; + +wire [16:0] len_dut_pp; +wire len_write_dut_pp; + +wire [7:0] data_dut_pp; +wire err_dut_pp; +wire data_write_dut_pp; + +wire dv_in_dut; +wire [7:0] data_in_dut; +wire err_in_dut; + + +port_parser_mii pp_ref ( + .rst_n (rst_n), + .clk (clk), + .GBspeed (GBspeed), + .enable_in (dv_in_ref), + .data_in (data_in_ref), + .err_in (err_in_ref), + + .err_out (err_ref_pp), + .data_out (data_ref_pp), + .length_out (len_ref_pp), + .dat_wr (data_write_ref_pp), + .len_wr (len_write_ref_pp) +); + +port_parser_mii pp_dut ( + .rst_n (rst_n), + .clk (clk), + .GBspeed (GBspeed), + .enable_in (dv_in_dut), + .data_in (data_in_dut), + .err_in (err_in_dut), + + .err_out (err_dut_pp), + .data_out (data_dut_pp), + .length_out (len_dut_pp), + .dat_wr (data_write_dut_pp), + .len_wr (len_write_dut_pp) +); + + + + +port_monitor port_monitor ( + .rst_n (rst_n), + .clk (clk), + + .len_in_ref (len_ref_pp), + .len_write_en_ref (len_write_ref_pp), + + .data_in_ref (data_ref_pp), + .data_write_en_ref (data_write_ref_pp), + .err_in_ref (err_ref_pp), + + .len_in_dut (len_dut_pp), + .len_write_en_dut (len_write_dut_pp), + + .data_in_dut (data_dut_pp), + .data_write_en_dut (data_write_dut_pp), + .err_in_dut (err_dut_pp) +); + +endmodule diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_monitor.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_monitor.v new file mode 100644 index 0000000..53e1391 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_monitor.v @@ -0,0 +1,827 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +//`timescale 1ns/100ps +`timescale 1ps/1ps + +module port_monitor ( + rst_n, + clk, + + len_in_ref, + len_write_en_ref, + + data_in_ref, + data_write_en_ref, + err_in_ref, + + len_in_dut, + len_write_en_dut, + + data_in_dut, + data_write_en_dut, + err_in_dut +); + +input rst_n; +input clk; + +input [16:0] len_in_ref; +input len_write_en_ref; + +input [7:0] data_in_ref; +input data_write_en_ref; +input err_in_ref; + +input [16:0] len_in_dut; +input len_write_en_dut; + +input [7:0] data_in_dut; +input data_write_en_dut; +input err_in_dut; + +///////////////////////// + +parameter + READY = 4'd0, + CHECK_DUT_LEN = 4'd1, + PREAMBLE_REF = 4'd2, + PREAMBLE_DUT = 4'd3, + DEST_ADD = 4'd4, + SRC_ADD = 4'd5, + LEN = 4'd6, + SEQ_NUM = 4'd7, + PAYLD = 4'd8, + CHECK_FCS = 4'd9, + CHECK_CAR_EXT = 4'd10, + SUMMARY = 4'd11; +reg [3:0] fsm; + +integer i; +integer preamb_count_ref; +integer preamb_count_dut; + +reg [15:0] payld_count_ref; +reg [15:0] payld_count_dut; + +reg [47:0] dest_add_ref; +reg [47:0] dest_add_dut; + +reg [47:0] src_add_ref; +reg [47:0] src_add_dut; + +reg [15:0] fr_len_ref; +reg [15:0] fr_len_dut; + +reg [7:0] seq_num_ref; +reg [7:0] seq_num_dut; + +reg [31:0] fcs_dut; + +reg [31:0] FCS_d0_ref; +reg [31:0] FCS_d1_ref; +reg [31:0] FCS_d2_ref; +reg [31:0] FCS_d3_ref; +reg [31:0] FCS_d4_ref; + +reg [31:0] FCS_d0_dut; +reg [31:0] FCS_d1_dut; +reg [31:0] FCS_d2_dut; +reg [31:0] FCS_d3_dut; +reg [31:0] FCS_d4_dut; + +reg [7:0] data_in_ref_d1; +reg [7:0] data_in_ref_d2; +reg [7:0] data_in_ref_d3; +reg [7:0] data_in_ref_d4; + +reg [16:0] len_ref_fifo [0:2560]; +reg [7:0] data_ref_fifo [0:256000]; +reg err_ref_fifo [0:256000]; + +reg [16:0] len_dut_fifo [0:2560]; +reg [7:0] data_dut_fifo [0:256000]; +reg err_dut_fifo [0:256000]; + +integer hr, tr; // head for ref fifo, tail for ref fifo +integer hd, td; // head for dut fifo, tail for dut fifo + +integer l_hr, l_tr; // head for ref length fifo, tail for ref length fifo +integer l_hd, l_td; // head for dut length fifo, tail for dut length fifo + +integer words_available_ref; +integer words_available_dut; +integer len_words_available_ref; +integer len_words_available_dut; + +reg data_read_en_ref; +reg data_read_en_dut; +reg len_read_en_ref; +reg len_read_en_dut; +reg [16:0] total_len_ref; +reg [16:0] total_len_dut; + +reg [16:0] total_count_ref; +reg [16:0] total_count_dut; + +wire [16:0] len_ref_fifo_out; +wire [7:0] data_ref_fifo_out; +wire err_ref_fifo_out; + +wire [16:0] len_dut_fifo_out; +wire [7:0] data_dut_fifo_out; +wire err_dut_fifo_out; +wire read_inhibit_ref; +wire read_inhibit_dut; +reg data_mismatch; +reg capt_first_mismatch; +reg [7:0] data_capt_ref; +reg [7:0] data_capt_dut; +reg [15:0] mismatch_byte_num; + +reg fcs_fail_ref; +reg fcs_fail_dut; + +reg dest_add_fail; +reg src_add_fail; +reg fr_len_fail; +reg seq_num_fail; +reg car_ext_dut; + + + +// capture incoming data +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + hr <= 0; // head for ref fifo + tr <= 0; // tail for ref fifo + + hd <= 0; // head for dut fifo + td <= 0; // tail for dut fifo + + l_hr <= 0; // head for ref length fifo + l_tr <= 0; // tail for ref length fifo + + l_hd <= 0; // head for dut length fifo + l_td <= 0; // tail for dut length fifo + + words_available_ref <= 0; + words_available_dut <= 0; + len_words_available_ref <= 0; + len_words_available_dut <= 0; + end + + else begin + + // defaults + words_available_ref <= hr - tr; + words_available_dut <= hd - td; + len_words_available_ref <= l_hr - l_tr; + len_words_available_dut <= l_hd - l_td; + + //////////////////////// + // FIFO WRITES + //////////////////////// + + // capture reference data + if (data_write_en_ref) begin + data_ref_fifo[hr] <= data_in_ref; + err_ref_fifo[hr] <= err_in_ref; + if (hr == 256000) begin + hr <= 0; + end + else begin + hr <= hr + 1; + end + end + + // capture dut data + if (data_write_en_dut) begin + data_dut_fifo[hd] <= data_in_dut; + err_dut_fifo[hd] <= err_in_dut; + if (hd == 256000) begin + hd <= 0; + end + else begin + hd <= hd + 1; + end + end + + // capture reference lengths + if (len_write_en_ref) begin + len_ref_fifo[l_hr] <= len_in_ref; + if (l_hr == 2560) begin + l_hr <= 0; + end + else begin + l_hr <= l_hr + 1; + end + end + + // capture dut lengths + if (len_write_en_dut) begin + len_dut_fifo[l_hd] <= len_in_dut; + if (l_hd == 2560) begin + l_hd <= 0; + end + else begin + l_hd <= l_hd + 1; + end + end + + ///////////////////////////// + // FIFO READ ADDRESS CONTROL + ///////////////////////////// + if (data_read_en_ref) begin + if (tr == 256000) begin + tr <= 0; + end + else begin + tr <= tr + 1; + end + end + if (data_read_en_dut) begin + if (td == 256000) begin + td <= 0; + end + else begin + td <= td + 1; + end + end + if (len_read_en_ref) begin + if (l_tr == 2560) begin + l_tr <= 0; + end + else begin + l_tr <= l_tr + 1; + end + end + if (len_read_en_dut) begin + if (l_td == 2560) begin + l_td <= 0; + end + else begin + l_td <= l_td + 1; + end + end + + + + + end +end + + +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + fsm <= READY; + i <= 0; + preamb_count_ref <= 0; + preamb_count_dut <= 0; + + payld_count_ref <= 0; + payld_count_dut <= 0; + + dest_add_ref <= 0; + dest_add_dut <= 0; + + src_add_ref <= 0; + src_add_dut <= 0; + + fr_len_ref <= 0; + fr_len_dut <= 0; + + seq_num_ref <= 0; + seq_num_dut <= 0; + + fcs_dut <= 0; + + FCS_d0_ref <= 0; + FCS_d1_ref <= 0; + FCS_d2_ref <= 0; + FCS_d3_ref <= 0; + FCS_d4_ref <= 0; + + FCS_d0_dut <= 0; + FCS_d1_dut <= 0; + FCS_d2_dut <= 0; + FCS_d3_dut <= 0; + FCS_d4_dut <= 0; + + data_in_ref_d1 <= 0; + data_in_ref_d2 <= 0; + data_in_ref_d3 <= 0; + data_in_ref_d4 <= 0; + + data_read_en_ref <= 0; + data_read_en_dut <= 0; + len_read_en_ref <= 0; + len_read_en_dut <= 0; + + total_len_ref <= 0; + total_len_dut <= 0; + + total_count_ref <= 0; + total_count_dut <= 0; + + data_mismatch <= 0; + capt_first_mismatch <= 0; + data_capt_ref <= 0; + data_capt_dut <= 0; + mismatch_byte_num <= 0; + + fcs_fail_ref <= 0; + fcs_fail_dut <= 0; + + car_ext_dut <= 0; + + end + else begin + + // defaults + FCS_d1_ref <= FCS_d0_ref; + FCS_d2_ref <= FCS_d1_ref; + FCS_d3_ref <= FCS_d2_ref; + FCS_d4_ref <= FCS_d3_ref; + + FCS_d1_dut <= FCS_d0_dut; + FCS_d2_dut <= FCS_d1_dut; + FCS_d3_dut <= FCS_d2_dut; + FCS_d4_dut <= FCS_d3_dut; + + data_in_ref_d1 <= data_in_ref; + data_in_ref_d2 <= data_in_ref_d1; + data_in_ref_d3 <= data_in_ref_d2; + data_in_ref_d4 <= data_in_ref_d3; + + data_read_en_ref <= 0; + data_read_en_dut <= 0; + len_read_en_ref <= 0; + len_read_en_dut <= 0; + + data_mismatch <= 0; + + case(fsm) + READY: + begin + preamb_count_ref <= 0; + preamb_count_dut <= 0; + + payld_count_ref <= 0; + payld_count_dut <= 0; + + dest_add_ref <= 0; + dest_add_dut <= 0; + + src_add_ref <= 0; + src_add_dut <= 0; + + fr_len_ref <= 0; + fr_len_dut <= 0; + + seq_num_ref <= 0; + seq_num_dut <= 0; + + fcs_dut <= 0; + + FCS_d0_ref <= 0; + FCS_d0_dut <= 0; + + total_count_ref <= 0; + total_count_dut <= 0; + + data_mismatch <= 0; + capt_first_mismatch <= 0; + data_capt_ref <= 0; + data_capt_dut <= 0; + mismatch_byte_num <= 0; + + fcs_fail_ref <= 0; + fcs_fail_dut <= 0; + + car_ext_dut <= 0; + + if (len_words_available_ref > 0) begin + len_read_en_ref <= 1; + total_len_ref <= len_ref_fifo_out; + fsm <= CHECK_DUT_LEN; + end + end + + CHECK_DUT_LEN: + begin + + if (len_words_available_dut > 0) begin + len_read_en_dut <= 1; + total_len_dut <= len_dut_fifo_out; + + data_read_en_ref <= 1; + + fsm <= PREAMBLE_REF; + end + + end + + PREAMBLE_REF: + begin + total_count_ref <= total_count_ref + 1; + + if (data_ref_fifo_out == 8'hd5) begin + data_read_en_ref <= 0; + data_read_en_dut <= 1; + fsm <= PREAMBLE_DUT; + end + else begin + data_read_en_ref <= 1; + preamb_count_ref <= preamb_count_ref + 1; + end + end + + + PREAMBLE_DUT: + begin + total_count_dut <= total_count_dut + 1; + data_read_en_dut <= 1; + + if (data_dut_fifo_out == 8'hd5) begin + data_read_en_ref <= 1; + i <= 1; + fsm <= DEST_ADD; + end + else begin + preamb_count_dut <= preamb_count_dut + 1; + end + end + + + + DEST_ADD: + begin + data_read_en_ref <= ~read_inhibit_ref; + data_read_en_dut <= ~read_inhibit_dut; + + if (!read_inhibit_ref) begin + total_count_ref <= total_count_ref + 1; + end + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + i <= i + 1; + case (i) + 1: begin dest_add_ref[47:40] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 2: begin dest_add_ref[39:32] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 3: begin dest_add_ref[31:24] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 4: begin dest_add_ref[23:16] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 5: begin dest_add_ref[15:8] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 6: begin dest_add_ref[7:0] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + default: dest_add_ref<= dest_add_ref; + endcase + case (i) + 1: begin dest_add_dut[47:40] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 2: begin dest_add_dut[39:32] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 3: begin dest_add_dut[31:24] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 4: begin dest_add_dut[23:16] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 5: begin dest_add_dut[15:8] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 6: begin dest_add_dut[7:0] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + default: dest_add_dut<= dest_add_dut; + endcase + + if (i == 6) begin + i <= 1; + fsm <= SRC_ADD; + end + end + + SRC_ADD: + begin + data_read_en_ref <= ~read_inhibit_ref; + data_read_en_dut <= ~read_inhibit_dut; + + if (!read_inhibit_ref) begin + total_count_ref <= total_count_ref + 1; + end + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + i <= i + 1; + case (i) + 1: begin src_add_ref[47:40] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 2: begin src_add_ref[39:32] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 3: begin src_add_ref[31:24] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 4: begin src_add_ref[23:16] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 5: begin src_add_ref[15:8] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 6: begin src_add_ref[7:0] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + default: src_add_ref<= src_add_ref; + endcase + case (i) + 1: begin src_add_dut[47:40] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 2: begin src_add_dut[39:32] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 3: begin src_add_dut[31:24] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 4: begin src_add_dut[23:16] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 5: begin src_add_dut[15:8] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 6: begin src_add_dut[7:0] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + default: src_add_dut<= src_add_dut; + endcase + if (i == 6) begin + i <= 1; + fsm <= LEN; + end + end + + LEN: + begin + data_read_en_ref <= ~read_inhibit_ref; + data_read_en_dut <= ~read_inhibit_dut; + + if (!read_inhibit_ref) begin + total_count_ref <= total_count_ref + 1; + end + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + i <= i + 1; + case (i) + 1: begin fr_len_ref[15:8] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + 2: begin fr_len_ref[7:0] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end + default: fr_len_ref <= fr_len_ref; + endcase + case (i) + 1: begin fr_len_dut[15:8] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + 2: begin fr_len_dut[7:0] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end + default: fr_len_dut <= fr_len_dut; + endcase + if (i == 2) begin + i <= 1; + fsm <= SEQ_NUM; + end + end + + SEQ_NUM: + begin + data_read_en_ref <= ~read_inhibit_ref; + data_read_en_dut <= ~read_inhibit_dut; + + if (!read_inhibit_ref) begin + total_count_ref <= total_count_ref + 1; + end + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + seq_num_ref <= data_ref_fifo_out; + FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; + payld_count_ref <= 2; + + seq_num_dut <= data_dut_fifo_out; + FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; + payld_count_dut <= 2; + + fsm <= PAYLD; + end + + PAYLD: + begin + data_read_en_ref <= ~read_inhibit_ref; + data_read_en_dut <= ~read_inhibit_dut; + + if (!read_inhibit_ref) begin + total_count_ref <= total_count_ref + 1; + end + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; + FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; + + //if (total_count_ref >= (total_len_ref - 5)) begin + if (payld_count_ref == (fr_len_ref)) begin + i <= 1; + fsm <= CHECK_FCS; + end + else begin + payld_count_ref <= payld_count_ref + 1; + payld_count_dut <= payld_count_dut + 1; + end + + if (data_ref_fifo_out != data_dut_fifo_out) begin + + if (!capt_first_mismatch) begin + capt_first_mismatch <= 1; + data_capt_ref <= data_ref_fifo_out; + data_capt_dut <= data_dut_fifo_out; + mismatch_byte_num <= payld_count_ref; + end + + data_mismatch <= 1; + end + + end + + CHECK_FCS: + begin + if ((i >= 1) && (i <= 3)) begin + data_read_en_ref <= ~read_inhibit_ref; + data_read_en_dut <= ~read_inhibit_dut; + end + + if (!read_inhibit_ref) begin + total_count_ref <= total_count_ref + 1; + end + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + case (i) + 1: begin if (FCS_d0_ref[31:24] != data_ref_fifo_out) fcs_fail_ref <= 1; end + 2: begin if (FCS_d0_ref[23:16] != data_ref_fifo_out) fcs_fail_ref <= 1; end + 3: begin if (FCS_d0_ref[15:8] != data_ref_fifo_out) fcs_fail_ref <= 1; end + 4: begin if (FCS_d0_ref[7:0] != data_ref_fifo_out) fcs_fail_ref <= 1; end + default: fcs_fail_ref <= fcs_fail_ref; + endcase + case (i) + 1: begin fcs_dut[31:24] <= data_dut_fifo_out; if (FCS_d0_dut[31:24] != data_dut_fifo_out) fcs_fail_dut <= 1; end + 2: begin fcs_dut[23:16] <= data_dut_fifo_out; if (FCS_d0_dut[23:16] != data_dut_fifo_out) fcs_fail_dut <= 1; end + 3: begin fcs_dut[15:8] <= data_dut_fifo_out; if (FCS_d0_dut[15:8] != data_dut_fifo_out) fcs_fail_dut <= 1; end + 4: begin fcs_dut[7:0] <= data_dut_fifo_out; if (FCS_d0_dut[7:0] != data_dut_fifo_out) fcs_fail_dut <= 1; end + default: fcs_fail_dut <= fcs_fail_dut; + endcase + + i <= i + 1; + + if (i == 4) begin + if ((total_len_dut - total_count_dut) > 1) begin + data_read_en_dut <= 1; + fsm <= CHECK_CAR_EXT; + end + else begin + fsm <= SUMMARY; + end + end + end + + CHECK_CAR_EXT: + begin + + if (!read_inhibit_dut) begin + total_count_dut <= total_count_dut + 1; + end + + if ((data_dut_fifo_out == 8'h0f) && (err_dut_fifo_out == 1'b1)) begin + car_ext_dut <= 1; + end + + + if ((total_len_dut - total_count_dut) > 1) begin + data_read_en_dut <= 1; + end + else begin + fsm <= SUMMARY; + end + + end + + SUMMARY: + begin + if (dest_add_fail || src_add_fail || fr_len_fail || seq_num_fail || capt_first_mismatch || fcs_fail_dut) begin + $display("PORT MONITOR: recvd frame : ***** FAILED ***** @ %t", $time); + if (dest_add_fail) begin + $display(" expected_dest_addr 0x%0h : actual_dest_addr 0x%0h", dest_add_ref, dest_add_dut); + end + if (src_add_fail) begin + $display(" expected_src_addr 0x%0h : actual_src_addr 0x%0h", src_add_ref, src_add_dut); + end + if (fr_len_fail) begin + $display(" expected_frame_length 0x%0h : actual_frame_length 0x%0h", fr_len_ref, fr_len_dut); + end + if (seq_num_fail) begin + $display(" expected_sequence_number 0x%0h : actual_sequence_number 0x%0h", seq_num_ref, seq_num_dut); + end + if (capt_first_mismatch) begin + $display(" expected_data 0x%0h : actual_data 0x%0h @ byte_number %d", data_capt_ref, data_capt_dut, mismatch_byte_num); + end + if (fcs_fail_dut) begin + $display(" expected_FCS 0x%0h : actual_FCS 0x%0h", FCS_d0_ref, fcs_dut); + end + end + else if (car_ext_dut) begin + $display("\tPORT MONITOR: recvd frame : GOOD ---- CARRIER EXTENSION PRESENT ---- @ %t", $time); + end + + else begin + $display("\tPORT MONITOR: recvd frame : GOOD @ %t", $time); + end + + //$display("--------------------------------------------------"); + $display(" preamble_size %0d", preamb_count_dut); + $display(" dest_addr 0x%0h : src_addr 0x%0h", dest_add_dut, src_add_dut); + $display(" sequence_num %0d : payload_len %0d : FCS 0x%0h ", seq_num_dut, payld_count_dut, FCS_d0_dut); + $display(" "); + + fsm <= READY; + end + + + + default : + begin + fsm <= READY; + end + endcase + end +end + +always @(*) begin + + if (dest_add_ref == dest_add_dut) + dest_add_fail <= 0; + else + dest_add_fail <= 1; + + + if (src_add_ref == src_add_dut) + src_add_fail <= 0; + else + src_add_fail <= 1; + + + if (fr_len_ref == fr_len_dut) + fr_len_fail <= 0; + else + fr_len_fail <= 1; + + + if (seq_num_ref == seq_num_dut) + seq_num_fail <= 0; + else + seq_num_fail <= 1; + + +end + + +// assign FIFO data out +assign len_ref_fifo_out = len_ref_fifo[l_tr]; +assign data_ref_fifo_out = data_ref_fifo [tr]; +assign err_ref_fifo_out = err_ref_fifo [tr]; + +assign len_dut_fifo_out = len_dut_fifo[l_td]; +assign data_dut_fifo_out = data_dut_fifo [td]; +assign err_dut_fifo_out = err_dut_fifo [td]; + +// continuous assignments +assign read_inhibit_ref = (total_count_ref <= total_len_ref) ? 0 : 1; +assign read_inhibit_dut = (total_count_dut <= total_len_dut) ? 0 : 1; + + +// synopsys translate_off +reg [(22*8):1] fsm_monitor; +always @(*) begin + case (fsm) + READY : fsm_monitor = "READY"; + CHECK_DUT_LEN : fsm_monitor = "CHECK_DUT_LEN"; + PREAMBLE_REF : fsm_monitor = "PREAMBLE_REF"; + PREAMBLE_DUT : fsm_monitor = "PREAMBLE_DUT"; + DEST_ADD : fsm_monitor = "DEST_ADD"; + SRC_ADD : fsm_monitor = "SRC_ADD"; + LEN : fsm_monitor = "LEN"; + SEQ_NUM : fsm_monitor = "SEQ_NUM"; + PAYLD : fsm_monitor = "PAYLD"; + CHECK_FCS : fsm_monitor = "CHECK_FCS"; + CHECK_CAR_EXT : fsm_monitor = "CHECK_CAR_EXT"; + SUMMARY : fsm_monitor = "SUMMARY"; + + default : fsm_monitor = "***ERROR***"; + endcase +end +// synopsys translate_on + + +endmodule +// ============================================================================= + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_parser_mii.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_parser_mii.v new file mode 100644 index 0000000..972508c --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_parser_mii.v @@ -0,0 +1,237 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +//`timescale 1ns/100ps +`timescale 1ps/1ps + +module port_parser_mii ( + rst_n, + clk, + enable_in, + data_in, + err_in, + GBspeed, + + err_out, + data_out, + length_out, + dat_wr, + len_wr +); + +input rst_n; +input clk; +input enable_in; +input err_in; +input [7:0] data_in; +input GBspeed; + +output err_out; +output [7:0] data_out; +output [16:0] length_out; +output dat_wr; +output len_wr; + +reg err_out; +reg [7:0] data_out; +reg dat_wr; +reg len_wr; + +reg [16:0] count; + +parameter + SEEK_EN = 3'd0, + DO_WRITE_LO = 3'd1, + DO_WRITE_HI = 3'd2, + CAR_EXT_LO = 3'd3, + CAR_EXT_HI = 3'd4, + DO_WRITE_GB = 3'd5, + CAR_EXT_GB = 3'd6; +reg [2:0] cfsm; + + + +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + cfsm <= SEEK_EN; + count <= 17'd0; + data_out <= 8'd0; + err_out <= 1'b0; + dat_wr <= 1'b0; + len_wr <= 1'b0; + end + else begin + // defaults + //data_out <= data_in; + err_out <= err_in; + dat_wr <= 1'b0; + len_wr <= 1'b0; + + case(cfsm) + SEEK_EN: + begin + count <= 17'd1; + if (enable_in) begin + if (GBspeed) begin + // 1GBPS Mode + dat_wr <= 1'b1; + data_out <= data_in; + cfsm <= DO_WRITE_GB; + end + else begin + // 100MBPS or 10MBPS Mode + data_out[3:0] <= data_in[3:0]; + cfsm <= DO_WRITE_HI; + end + end + end + + + + + + DO_WRITE_LO: + begin + data_out[3:0] <= data_in[3:0]; + + if (enable_in) begin + count <= count + 1; + cfsm <= DO_WRITE_HI; + end + else begin + if (err_in) begin + count <= count + 1; + cfsm <= CAR_EXT_HI; + end + else begin + cfsm <= DO_WRITE_HI; + end + end + end + DO_WRITE_HI: + begin + if (enable_in) begin + dat_wr <= 1'b1; + data_out[7:4] <= data_in[3:0]; + cfsm <= DO_WRITE_LO; + end + else begin + if (err_in) begin + dat_wr <= 1'b1; + cfsm <= CAR_EXT_LO; + end + else begin + len_wr <= 1'b1; + cfsm <= SEEK_EN; + end + end + end + + + + CAR_EXT_LO: + begin + if (err_in) begin + count <= count + 1; + end + data_out[3:0] <= data_in[3:0]; + cfsm <= CAR_EXT_HI; + end + CAR_EXT_HI: + begin + if (err_in) begin + dat_wr <= 1'b1; + data_out[7:4] <= data_in[3:0]; + cfsm <= CAR_EXT_LO; + end + else begin + len_wr <= 1'b1; + cfsm <= SEEK_EN; + end + end + + + DO_WRITE_GB: + begin + data_out <= data_in; + if (enable_in) begin + dat_wr <= 1'b1; + count <= count + 1; + end + else begin + if (err_in) begin + dat_wr <= 1'b1; + count <= count + 1; + cfsm <= CAR_EXT_GB; + end + else begin + len_wr <= 1'b1; + cfsm <= SEEK_EN; + end + end + end + CAR_EXT_GB: + begin + data_out <= data_in; + if (err_in) begin + dat_wr <= 1'b1; + count <= count + 1; + cfsm <= CAR_EXT_GB; + end + else begin + len_wr <= 1'b1; + cfsm <= SEEK_EN; + end + end + + + + + default : + begin + cfsm <= SEEK_EN; + end + endcase + end +end + + +assign length_out = count; + + + +// synopsys translate_off +reg [(22*8):1] cfsm_monitor; +always @(*) begin + case (cfsm) + SEEK_EN : cfsm_monitor = "SEEK_EN"; + DO_WRITE_LO : cfsm_monitor = "DO_WRITE_LO"; + DO_WRITE_HI : cfsm_monitor = "DO_WRITE_HI"; + CAR_EXT_LO : cfsm_monitor = "CAR_EXT_LO"; + CAR_EXT_HI : cfsm_monitor = "CAR_EXT_HI"; + DO_WRITE_GB : cfsm_monitor = "DO_WRITE_GB"; + CAR_EXT_GB : cfsm_monitor = "CAR_EXT_GB"; + + default : cfsm_monitor = "***ERROR***"; + endcase +end +// synopsys translate_on + +endmodule +// ============================================================================= + + + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/sgmii_node.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/sgmii_node.v new file mode 100644 index 0000000..914fafc --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/sgmii_node.v @@ -0,0 +1,302 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module sgmii_node ( + // Control Interface + gbe_mode, + sgmii_mode, + force_loopback, + rst_n, + phy_speed, + + // G/MII Interface + data_in_mii, + en_in_mii, + err_in_mii, + + data_out_mii, + dv_out_mii, + err_out_mii, + + // GMII Timing References + tx_clk_125, + tx_ce_sink, + tx_ce_source, + + rx_clk_125, + rx_ce_sink, + rx_ce_source, + + // SERIAL GMII Interface + refclkp, + refclkn, + hdinp0, + hdinn0, + hdoutp0, + hdoutn0 + ); + + + +// I/O Declarations +input rst_n; // System Reset, Active Low +input gbe_mode ; // GBE Mode (0=SGMII 1=GBE) +input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY) +input force_loopback ; +input [1:0] phy_speed; + +input refclkp, refclkn ; +input tx_clk_125 ; // GMII Transmit clock 125Mhz +input tx_ce_sink ; +output tx_ce_source ; + +input [7:0] data_in_mii; // G/MII Incoming Data +input en_in_mii; // G/MII Incoming Data Valid +input err_in_mii; // G/MII Incoming Error + +input rx_clk_125 ; // GMII Receive clock 125Mhz +input rx_ce_sink ; +output rx_ce_source ; + +output [7:0] data_out_mii; // G/MII Outgoing Data +output dv_out_mii; // G/MII Outgoing Data Valid +output err_out_mii; // G/MII Outgoing Error + +input hdinp0; // Incoming SGMII (on SERDES) +input hdinn0; // Incoming SGMII (on SERDES) + +output hdoutp0; // Outgoing SGMII (on SERDES) +output hdoutn0; // Outgoing SGMII (on SERDES) + + + +// 8-bit Interface Signals from SGMII channel to QuadPCS/SERDES +wire [7:0] data_chan2quad; +wire kcntl_chan2quad; +wire disparity_cntl_chan2quad; + +// 8-bit Interface Signals from QuadPCS/SERDES to SGMII channel +wire [7:0] data_quad2chan; +wire kcntl_quad2chan; +wire disp_err_quad2chan; +wire cv_err_quad2chan; +wire link_status; +wire serdes_recovered_clk; +wire refclk2fpga; +wire xmit_autoneg; + +wire adv_link_status; +wire adv_duplex_mode; +wire [1:0] adv_link_speed; + +// Active High Reset +wire rst; +assign rst = ~rst_n; + + +wire debug_link_timer_short; +wire [1:0] operational_rate; +wire [15:0] mr_lp_adv_ability; +wire mr_an_complete; + + +wire sli_rst; +assign sli_rst = ~rst_n; + + +// Control Advertised Ability +// When in PHY mode, choose appropriate values +// When in MAC mode, always set to zeros +assign adv_link_status = gbe_mode ? 1'b0 : sgmii_mode ? 1'b1 : 1'b0; +assign adv_duplex_mode = gbe_mode ? 1'b0 : sgmii_mode ? 1'b1 : 1'b0; +assign adv_link_speed = gbe_mode ? 2'd0 : sgmii_mode ? phy_speed : 2'd0; +wire [7:0] gbe_bits; +assign gbe_bits = gbe_mode ? 8'h20 : 8'h01; + +assign debug_link_timer_short = 1'b0; //0= normal operation + // when running simulation + // will override this value to 1'b1 + // so that autonegotion completes + +// Instantiate Global Reset Controller +GSR GSR_INST (.GSR(rst_n)); +PUR PUR_INST (.PUR(1'b1)); + +// Instantiate SGMII IP Core +sgmii_channel_smi_core u_sgmii_core ( + // Clock and Reset + .rst_n (rst_n ), + .tx_clk_125 (tx_clk_125), + .tx_clock_enable_sink (tx_ce_sink), + .tx_clock_enable_source (tx_ce_source), + .rx_clk_125 (rx_clk_125), + .rx_clock_enable_sink (rx_ce_sink), + .rx_clock_enable_source (rx_ce_source), + + // Control + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .debug_link_timer_short (debug_link_timer_short), + .force_isolate (1'b0), + .force_loopback (force_loopback), + .force_unidir (1'b0), + .operational_rate (operational_rate), + .rx_compensation_err (), + .ctc_drop_flag (), + .ctc_add_flag (), + .an_link_ok (), + + + // (G)MII TX Port + .tx_d (data_in_mii), + .tx_en (en_in_mii), + .tx_er (err_in_mii), + + // (G)MII RX Port + .rx_d (data_out_mii), + .rx_dv (dv_out_mii), + .rx_er (err_out_mii), + .col (), + .crs (), + + // 8BI TX Port + .tx_data (data_chan2quad), + .tx_kcntl (kcntl_chan2quad), + .tx_disparity_cntl (disparity_cntl_chan2quad), + + // 8BI RX Port + .signal_detect (link_status), + .serdes_recovered_clk (serdes_recovered_clk), + .rx_data (data_quad2chan), + .rx_kcntl (kcntl_quad2chan), + .rx_even (1'b0), // Signal Not Used in Normal Mode + .rx_disp_err (disp_err_quad2chan), + .rx_cv_err (cv_err_quad2chan), + .rx_err_decode_mode (1'b0), // 0= Normal Mode, always tie low for SC Familiy + .xmit_autoneg (xmit_autoneg), + + // Management Interface I/O + .mr_adv_ability ({adv_link_status, 2'd0, adv_duplex_mode, adv_link_speed, 2'd0, gbe_bits}), + .mr_an_enable (1'b1), + .mr_main_reset (1'b0), + .mr_restart_an (1'b0), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx () + ); + + +// (G)MII Rate Resolution for SGMII IP Core +rate_resolution rate_resolution ( + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .an_enable (1'b1), + .advertised_rate (phy_speed), + .link_partner_rate (mr_lp_adv_ability[11:10]), + .non_an_rate (2'b10), // 1Gbps is rate when auto-negotiation disabled + + .operational_rate (operational_rate) +); + +wire refclk; +ILVDS ILVDS_X ( + .A (refclkp), + .AN(refclkn), + .Z (refclk)); + +assign refclk2fpga = refclk; + +// QUAD ASB 8B10B + SERDES + +sgmii_channel_smi_pcs u_sgmii_pcs ( + +// Global Clocks and Resets + // inputs + .rst_dual_c(~rst_n), + .serdes_rst_dual_c(~rst_n), + .pll_refclki(refclk), + .rxrefclk(refclk), + .sli_rst(sli_rst), + +// fpga tx datapath signals + // inputs + .tx_pcs_rst_c(1'b0), + .txdata(data_chan2quad), + .tx_k(kcntl_chan2quad), + .tx_disp_correct(disparity_cntl_chan2quad), + + .txi_clk(tx_clk_125), + + // outputs + .tx_pclk(), + +// fpga rx datapath signals + // inputs + .rx_pcs_rst_c(1'b0), + .xmit(xmit_autoneg), + .signal_detect_c(1'b1), + + // outputs + .rx_pclk(serdes_recovered_clk), + .rxdata(data_quad2chan), + .rx_k(kcntl_quad2chan), + .rx_disp_err(disp_err_quad2chan), + .rx_cv_err(cv_err_quad2chan), + .lsm_status_s(link_status), + .rx_cdr_lol_s(rx_cdr_lol), + +// serdes signals + // inputs + .rx_serdes_rst_c(1'b0), + .tx_serdes_rst_c(~rst_n), + + .hdinp(hdinp0), + .hdinn(hdinn0), + + // outputs + .hdoutp(hdoutp0), + .hdoutn(hdoutn0), + + //SCI interface + .cyawstn (1'b0), + .sci_en (1'b0), + .sci_en_dual (1'b0), + .sci_sel_dual (1'b0), + .sci_sel (1'b0), + .sci_wrdata (8'd0), + .sci_addr (6'd0), + .sci_rddata (), + .sci_rd (1'b0), + .sci_wrn (1'b1), + .sci_int (), + +// misc control signals + // inputs + .rsl_disable (1'b0), + .rsl_rst (~rst_n), + .tx_pwrup_c (1'b1), // powerup tx channel + .rx_pwrup_c (1'b1), // power up rx channel + .serdes_pdb (1'b1), + + // outputs + .pll_lol() +); + + +endmodule + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/tb_hb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/tb_hb.v new file mode 100644 index 0000000..fc6aae5 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/tb_hb.v @@ -0,0 +1,924 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ps/1ps + +module tb ; + +reg clk_125 ; +reg hclk ; +wire hready_n; +wire [7:0] hdataout; +reg [9:0] haddr; +reg [7:0] hdatain; +reg hcs_n; +reg hread_n; +reg hwrite_n; +reg hdataout_en_n; + +reg rst_n ; +reg rst_tb_n; + +reg clk_25; +reg clk_12_5; +reg clk_2_5; +reg clk_1_25; +reg [3:0] clk_count; +reg [5:0] sclk_count; + +/////////////////////// + +reg [7:0] drv_data; +reg drv_en; +reg drv_er; + +wire [7:0] local_tx_d; +wire local_tx_en; +wire local_tx_er; + +wire [7:0] mn_data; +wire mn_dv; +wire mn_er; + +wire [7:0] mon_data; +wire mon_dv; +wire mon_er; + +/////////////////////// + +wire [7:0] local_rx_d; +wire local_rx_dv; +wire local_rx_er; + +reg clk_mii; +reg clk_drvmon; +reg [1:0] adv_speed; +reg [1:0] mii_speed; +reg dut_sgmii_mode; +reg dut_gbe_mode; +reg GBspeed_drvmon; +reg force_loopback; + + +////////////////////////////////////////////////////////////////////////////// + +initial +begin + clk_125 = 1'b0 ; + hclk = 1'b0 ; + $timeformat (-9 ,1 , "ns", 10); +end + +// 125 Mhz clock Generation +always #4000 clk_125 = ~clk_125 ; + +// HCLK Clock Generation +always #10000 hclk = ~hclk ; + +// 25Mhz Clock Generation +always @(posedge clk_125 or negedge rst_tb_n) +begin + if (rst_tb_n == 1'b0) begin + clk_count <= 4'd0; + clk_25 <= 1'd0; + clk_12_5 <= 1'd0; + end + else begin + + // These statements implement a "divide by 5" + if (clk_count == 4'd4) + clk_count <= 4'd0; + else + clk_count <= clk_count + 1; + + + if ((clk_count==4'd1) || (clk_count==4'd4)) + clk_25 <= ~clk_25; + + if ((clk_25 == 1'd0) && (clk_count == 4'd1)) + clk_12_5 <= ~clk_12_5; + + + end +end + + + +// 2.5Mhz Clock Generation +always @(posedge clk_125 or negedge rst_tb_n) +begin + if (rst_tb_n == 1'b0) begin + sclk_count <= 0; + clk_2_5 <= 0; + clk_1_25 <= 0; + end + else begin + + // These statements implement a "divide by 50" + if (sclk_count == 49) + sclk_count <= 0; + else + sclk_count <= sclk_count + 1; + + + if ((sclk_count==24) || (sclk_count==49)) + clk_2_5 <= ~clk_2_5; + + if ((clk_2_5 == 0) && (sclk_count == 1)) + clk_1_25 <= ~clk_1_25; + + end +end + + +// choose mii clock based on DUT_MII_SPEED +always @(*) +begin + if (mii_speed == 2'b01) + clk_mii = 1'b1; + else if (mii_speed == 2'b00) + clk_mii = 1'b1; + else + clk_mii = 1'b1; +end + +// choose driver and monitor clock +always @(*) +begin + if (mii_speed == 2'b01) + clk_drvmon = clk_12_5; + else if (mii_speed == 2'b00) + clk_drvmon = clk_1_25; + else + clk_drvmon = clk_125; +end + + +GSR GSR_INST (.GSR(rst_n)); +PUR PUR_INST (.PUR(1'b1)); +OLVDS O_CLK_BUF (.A(clk_125), .Z(clk_125_p), .ZN(clk_125_n)); + +////////////////////////////////////////////////////////////////////////////// + +// Device Under Test (DUT) +top_hb top ( + .rst_n ( rst_n ) , + .gbe_mode ( dut_gbe_mode ) , + .sgmii_mode ( dut_sgmii_mode ) , + + .hclk (hclk), + .hcs_n (hcs_n), + .hwrite_n (hwrite_n), + .haddr (haddr[5:0]), + .hdatain (hdatain), + + .hdataout (hdataout), + .hready_n (hready_n), + + // G/MII Interface + .data_in_mii ( {local_tx_d} ) , + .en_in_mii ( local_tx_en ) , + .err_in_mii ( local_tx_er ) , + + .data_out_mii ( local_rx_d ) , + .dv_out_mii ( local_rx_dv ) , + .err_out_mii ( local_rx_er ) , + .col_out_mii ( ) , + .crs_out_mii ( ) , + + .debug_link_timer_short(1'b1), + .mr_an_complete(mr_an_complete), + + // GMII Clocks + .in_clk_125 ( clk_125 ) , + .in_ce_sink ( clock_enable ) , + .in_ce_source ( clock_enable ) , + .out_clk_125 ( clk_125 ) , + .out_ce_sink ( clock_enable ) , + .out_ce_source ( ) , + + // SERDES Interface + .refclkp ( clk_125_p ) , + .refclkn ( clk_125_n ) , + .hdoutp0 ( local_serdes_p ) , + .hdoutn0 ( local_serdes_n ) , + .hdinp0 ( remote_serdes_p ), + .hdinn0 ( remote_serdes_n ) + ); + + +// Loopback DUT (G)MII Interface +assign local_tx_d = local_rx_d; +assign local_tx_en = local_rx_dv; +assign local_tx_er = local_rx_er; + + +// Testbench SGMII Channel +sgmii_node sgmii_node ( + // Control Interface + .rst_n (rst_n) , + .gbe_mode (dut_gbe_mode) , + .sgmii_mode (~dut_sgmii_mode) , + .force_loopback (force_loopback) , + .phy_speed (adv_speed) , + + // G/MII Interface + .data_in_mii (drv_data), + .en_in_mii (drv_en), + .err_in_mii (drv_er), + + .data_out_mii (mon_data), + .dv_out_mii (mon_dv), + .err_out_mii (mon_er), + + // GB Timing References + .tx_clk_125 (clk_125) , + .tx_ce_source () , + .tx_ce_sink (clock_enable) , + + .rx_clk_125 (clk_125) , + .rx_ce_source () , + .rx_ce_sink (clock_enable) , + + // SERDES Interface + .refclkp (clk_125_p) , + .refclkn (clk_125_n) , + .hdoutp0 (remote_serdes_p) , + .hdoutn0 (remote_serdes_n) , + .hdinp0 (local_serdes_p ), + .hdinn0 (local_serdes_n ) +); + + + + + + +// Compare MII In/Out Ports of DUT +mii_monitor mii_monitor ( + .rst_n (rst_n), + .clk (clk_drvmon), + .GBspeed (GBspeed_drvmon) , + + .data_in_ref (drv_data), + .dv_in_ref (drv_en), + .err_in_ref (drv_er), + + .data_in_dut (mon_data), + .dv_in_dut (mon_dv), + .err_in_dut (mon_er) +); + + + +////////////////////////////////////////////////////////////////////////////// + +// THIS BLOCK CONTROLS TEST SCRIPT FLOW +initial +begin + rst_tb_n = 1'b0 ; + rst_n = 0; + + haddr = 10'd0; + hdatain = 8'd0; + hcs_n = 1'b1; + hread_n = 1'b1; + hwrite_n = 1'b1; + hdataout_en_n = 1'b1; + + drv_data = 8'd0; + drv_en = 1'd0; + drv_er = 1'd0; + + force_loopback = 1'b0; + + // the following lines allow short autonegotiation timer to operate + force sgmii_node.debug_link_timer_short = 1'b1 ; + + // For the Soft LOL and RSL logic in simulation + @(posedge clk_125); + force tb.top.u_sgmii.u_sgmii_pcs.sll_inst.LRCLK_TC_w = 16'd100; + force tb.top.u_sgmii.u_sgmii_pcs.sll_inst.rcount_tc = 22'd100; + force tb.sgmii_node.u_sgmii_pcs.sll_inst.LRCLK_TC_w = 16'd100; + force tb.sgmii_node.u_sgmii_pcs.sll_inst.rcount_tc = 22'd100; + +/////// SET SGMII MODE == 1GB Rate ///////////////////////////////////////////////////////////////////// + + GBspeed_drvmon = 1; + mii_speed = 2'b10; // 1GB + adv_speed = 2'b10; // 1GB + dut_sgmii_mode = 1'b0; // MAC + dut_gbe_mode = 1'b0; // SGMII + + #1000000 // Wait for 100 nanoseconds + $display(" ") ; + $display(" !!!!!!!!!! Starting SGMII Tests !!!!!!!!!!"); + $display(" ") ; + $display(" ") ; + $display(" ") ; + $display(" ") ; + $display(" MII operating @ 1Gbps in SGMII Mode") ; + $display(" ") ; + $display(" Device Under Test operating in SGMII MAC mode") ; + $display(" ") ; + + + // release testbench reset + #1000000 // Wait for 100 nanoseconds + rst_tb_n <= 1'b1 ; + + // Perform Device Resets + #1000000 // Wait for 1 microsecond + rst_n = 0; // Apply reset + #1000000 // Wait for 1 microsecond + rst_n = 1; // Release reset + #1000000 // Wait for 1 microsecond + + +//////////////////// + + #1000000 // Wait for 1 microsecond + + @(posedge hclk); +// Quick Check of SGMII Management Registers + $display(" TEST#1 of 3 : Check SGMII Management Registers before Autonegotiaion Completes "); + + hb_read (10'h000, 8'h00, 8'h00); // Reg 0 + hb_read (10'h001, 8'h00, 8'h00); + $display(" ") ; + + hb_read (10'h002, 8'h00, 8'h00); // Reg 1 + hb_read (10'h003, 8'h00, 8'h00); + $display(" ") ; + + hb_read (10'h008, 8'h00, 8'h00); // Reg 4 + hb_read (10'h009, 8'h00, 8'h00); + $display(" ") ; + + hb_read (10'h00A, 8'h00, 8'h00); // Reg 5 + hb_read (10'h00B, 8'h00, 8'h00); + $display(" ") ; + + hb_read (10'h00C, 8'h00, 8'h00); // Reg 6 + hb_read (10'h00D, 8'h00, 8'h00); + $display(" ") ; + + +// Wait for Auto Negotiation to Complete + wait (mr_an_complete) + + @(posedge hclk); +// Quick Check of SGMII Management Registers + #2000000 // Wait for 2.00 microseconds + $display(" TEST#2 of 3 : Check SGMII Management Registers after Autonegotiaion Completes "); + + hb_read (10'h000, 8'h40, 8'hFF); // Reg 0 + hb_read (10'h001, 8'h11, 8'hFF); + $display(" ") ; + + hb_read (10'h002, 8'h2C, 8'h00); // Reg 1 + hb_read (10'h003, 8'h00, 8'h00); + + hb_read (10'h002, 8'h2C, 8'hFF); // Reg 1 Re-Read + hb_read (10'h003, 8'h01, 8'hFF); + $display(" ") ; + + hb_read (10'h008, 8'h01, 8'hFF); // Reg 4 + hb_read (10'h009, 8'h40, 8'hFF); + $display(" ") ; + + hb_read (10'h00A, 8'h01, 8'hFF); // Reg 5 + hb_read (10'h00B, 8'hD8, 8'hFF); + $display(" ") ; + + hb_read (10'h00C, 8'h02, 8'hFF); // Reg 6 + hb_read (10'h00D, 8'h00, 8'hFF); + + hb_read (10'h01E, 8'h00, 8'hFF); // Reg F + hb_read (10'h01F, 8'h80, 8'hFF); + $display(" ") ; + + + #10000000 // Wait for 10.00 microseconds + + + @(posedge clk_drvmon ); +// Send 4 Ethernet Frames + $display(" TEST#3 of 3 : Send 4 ethernet frames"); + //send_local_gmii_frame (preamble size, dest addr, src addr, payload len, sequence number); + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 0); + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 1); + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 2); + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 3); + + repeat (2000) @(posedge clk_drvmon ); + + + + $display("\n\n\n\n") ; + $display(" TEST#4 : Test Loopback Function"); + force_loopback = 1'b1; + repeat (500) @(posedge clk_drvmon ); + + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 4); + repeat (500) @(posedge clk_drvmon ); + + force_loopback = 1'b0; + repeat (500) @(posedge clk_drvmon ); + + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 5); + repeat (1000) @(posedge clk_drvmon ); + + + + + + + $display("\n\n\n\n") ; + $display(" TEST#5 : Test Isolate Function"); + hb_write (10'h001, 8'h15); + hb_read (10'h000, 8'h40, 8'hFF); + hb_read (10'h001, 8'h15, 8'hFF); + + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 6); + repeat (500) @(posedge clk_drvmon ); + + hb_write (10'h001, 8'h11); + hb_read (10'h000, 8'h40, 8'hFF); + hb_read (10'h001, 8'h11, 8'hFF); + + repeat (500) @(posedge clk_drvmon ); + + send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 7); + repeat (1000) @(posedge clk_drvmon ); + $display("**** Expected Frame Mismatch Failure, Due to Isolate Function****"); + + + + + + $display("\n\n\n\n") ; + $display(" !!!!!!!!!! Testbench Done. All Tests Completed !!!!!!!!!!"); + $stop ; +end + +// END OF TEST SCRIPT FLOW //////////////////////////////////////////////////////////// + + + + + + + + + + + +////////////////////////////////////////////////////////////////////////////// +task send_mii_frame ; +input [7:0] preamble_len; // Total number of bytes +input [47:0] dest_add; +input [47:0] src_add; +input [15:0] payld_len; +input [15:0] sequence_num; + +integer i; +reg[31:0] j; +reg [31:0] FCS; + +begin + +// Put Preamble /////////////////// +for(i = 0; i < preamble_len; i = i+1) begin + if (GBspeed_drvmon) begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 8'h55; + FCS = #1 32'd0; + @(posedge clk_drvmon); + end + else begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 8'h05; + FCS = #1 32'd0; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 8'h05; + FCS = #1 32'd0; + @(posedge clk_drvmon); + end +end + +// Put SFD //////////////////////// + if (GBspeed_drvmon) begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 8'hd5; + @(posedge clk_drvmon); + end + else begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 8'h05; // low nibble + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 8'h0d; // high nibble + @(posedge clk_drvmon); + end + +// Put Destination Address /////////////////////// +for(i = 0; i < 6; i = i+1) begin + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + + if (GBspeed_drvmon) begin + case (i) + 0: begin drv_data = #1 dest_add[47:40]; FCS = #1 (FCS + dest_add[47:40]); @(posedge clk_drvmon); end + 1: begin drv_data = #1 dest_add[39:32]; FCS = #1 (FCS + dest_add[39:32]); @(posedge clk_drvmon); end + 2: begin drv_data = #1 dest_add[31:24]; FCS = #1 (FCS + dest_add[31:24]); @(posedge clk_drvmon); end + 3: begin drv_data = #1 dest_add[23:16]; FCS = #1 (FCS + dest_add[23:16]); @(posedge clk_drvmon); end + 4: begin drv_data = #1 dest_add[15:8]; FCS = #1 (FCS + dest_add[15:8]); @(posedge clk_drvmon); end + 5: begin drv_data = #1 dest_add[7:0]; FCS = #1 (FCS + dest_add[7:0]); @(posedge clk_drvmon); end + endcase + + end + else begin + case (i) + 0: begin + drv_data = #1 {4'd0, dest_add[43:40]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, dest_add[47:44]}; FCS = #1 (FCS + dest_add[47:40]); + @(posedge clk_drvmon); + end + + 1: begin + drv_data = #1 {4'd0, dest_add[35:32]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, dest_add[39:36]}; FCS = #1 (FCS + dest_add[39:32]); + @(posedge clk_drvmon); + end + + 2: begin + drv_data = #1 {4'd0, dest_add[27:24]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, dest_add[31:28]}; FCS = #1 (FCS + dest_add[31:24]); + @(posedge clk_drvmon); + end + + 3: begin + drv_data = #1 {4'd0, dest_add[19:16]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, dest_add[23:20]}; FCS = #1 (FCS + dest_add[23:16]); + @(posedge clk_drvmon); + end + + 4: begin + drv_data = #1 {4'd0, dest_add[11:8]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, dest_add[15:12]}; FCS = #1 (FCS + dest_add[15:8]); + @(posedge clk_drvmon); + end + + 5: begin + drv_data = #1 {4'd0, dest_add[3:0]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, dest_add[7:4]}; FCS = #1 (FCS + dest_add[7:0]); + @(posedge clk_drvmon); + end + endcase + end +end + +// Put Source Address /////////////////////// +for(i = 0; i < 6; i = i+1) begin + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + + if (GBspeed_drvmon) begin + case (i) + 0: begin drv_data = #1 src_add[47:40]; FCS = #1 (FCS + src_add[47:40]); @(posedge clk_drvmon); end + 1: begin drv_data = #1 src_add[39:32]; FCS = #1 (FCS + src_add[39:32]); @(posedge clk_drvmon); end + 2: begin drv_data = #1 src_add[31:24]; FCS = #1 (FCS + src_add[31:24]); @(posedge clk_drvmon); end + 3: begin drv_data = #1 src_add[23:16]; FCS = #1 (FCS + src_add[23:16]); @(posedge clk_drvmon); end + 4: begin drv_data = #1 src_add[15:8]; FCS = #1 (FCS + src_add[15:8]); @(posedge clk_drvmon); end + 5: begin drv_data = #1 src_add[7:0]; FCS = #1 (FCS + src_add[7:0]); @(posedge clk_drvmon); end + endcase + + end + else begin + case (i) + 0: begin + drv_data = #1 {4'd0, src_add[43:40]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, src_add[47:44]}; FCS = #1 (FCS + src_add[47:40]); + @(posedge clk_drvmon); + end + + 1: begin + drv_data = #1 {4'd0, src_add[35:32]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, src_add[39:36]}; FCS = #1 (FCS + src_add[39:32]); + @(posedge clk_drvmon); + end + + 2: begin + drv_data = #1 {4'd0, src_add[27:24]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, src_add[31:28]}; FCS = #1 (FCS + src_add[31:24]); + @(posedge clk_drvmon); + end + + 3: begin + drv_data = #1 {4'd0, src_add[19:16]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, src_add[23:20]}; FCS = #1 (FCS + src_add[23:16]); + @(posedge clk_drvmon); + end + + 4: begin + drv_data = #1 {4'd0, src_add[11:8]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, src_add[15:12]}; FCS = #1 (FCS + src_add[15:8]); + @(posedge clk_drvmon); + end + + 5: begin + drv_data = #1 {4'd0, src_add[3:0]}; + @(posedge clk_drvmon); + drv_data = #1 {4'd0, src_add[7:4]}; FCS = #1 (FCS + src_add[7:0]); + @(posedge clk_drvmon); + end + endcase + end +end + +// Put Length //////////////////////// + if (GBspeed_drvmon) begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 payld_len[15:8]; + FCS = #1 FCS + payld_len[15:8]; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 payld_len[7:0]; + FCS = #1 FCS + payld_len[7:0]; + @(posedge clk_drvmon); + end + else begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, payld_len[11:8]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, payld_len[15:12]}; + FCS = #1 FCS + payld_len[15:8]; + @(posedge clk_drvmon); + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, payld_len[3:0]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, payld_len[7:4]}; + FCS = #1 FCS + payld_len[7:0]; + @(posedge clk_drvmon); + end + +// Put Sequence Num (part of the payload) //// + if (GBspeed_drvmon) begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 sequence_num[7:0]; + FCS = #1 FCS + sequence_num[7:0]; + @(posedge clk_drvmon); + end + else begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, sequence_num[3:0]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, sequence_num[7:4]}; + FCS = #1 FCS + sequence_num[7:0]; + @(posedge clk_drvmon); + end + +// Put Payload /////////////////////// +for(j = 1; j < payld_len; j = j+1) begin + if (GBspeed_drvmon) begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 j; + FCS = #1 FCS + j[7:0]; + @(posedge clk_drvmon); + end + else begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, j[3:0]}; // low nibble + @(posedge clk_drvmon); + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, j[7:4]}; // high nibble + FCS = #1 FCS + j[7:0]; + @(posedge clk_drvmon); + end +end + +// Put FCS /////////////////////// + if (GBspeed_drvmon) begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 FCS[31:24]; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 FCS[23:16]; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 FCS[15:8]; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 FCS[7:0]; + @(posedge clk_drvmon); + end + else begin + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[27:24]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[31:28]}; + @(posedge clk_drvmon); + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[19:16]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[23:20]}; + @(posedge clk_drvmon); + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[11:8]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[15:12]}; + @(posedge clk_drvmon); + + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[3:0]}; + @(posedge clk_drvmon); + drv_en = #1 1'b1; + drv_er = #1 1'b0; + drv_data = #1 {4'd0, FCS[7:4]}; + @(posedge clk_drvmon); + end + +// Put Carrier Extension /////////////////////// +// +// +//////////////////////////////////////////////// + +// Put Inter packet gap /////////// +for(i = 1; i <= 12; i = i+1) begin + drv_en = #1 1'b0; + drv_er = #1 1'b0; + @(posedge clk_drvmon); +end + + + +end +endtask + + + + + +task hb_write; + +input [9:0] address; +input [7:0] data; + +begin + @(posedge hclk); + + #1 + haddr[9:0] = address[9:0]; + hdatain[7:0] = data[7:0]; + + hcs_n = 1'b0; // assert + hread_n = 1'b1; + hwrite_n = 1'b0; // assert + hdataout_en_n = 1'b1; + + // wait for an acknowledge + @ (negedge hready_n); + + @(posedge hclk); + #1 + hcs_n = 1'b1; + hread_n = 1'b1; + hwrite_n = 1'b1; + hdataout_en_n = 1'b1; + + @(posedge hclk); + #1 + hcs_n = 1'b1; + hread_n = 1'b1; + hwrite_n = 1'b1; + hdataout_en_n = 1'b1; +end + +endtask + + + + + +task hb_read; + +input [9:0] address; +input [7:0] expected_data; +input [7:0] mask; + +reg [7:0] read_data; + +begin + @(posedge hclk); + + #1 + haddr[9:0] = address[9:0]; + + hcs_n = 1'b0; // assert + hread_n = 1'b0; + hwrite_n = 1'b1; + hdataout_en_n = 1'b0; // assert + + // wait for an acknowledge + @ (negedge hready_n); + + @(posedge hclk); + #1 + read_data[7:0] = hdataout[7:0]; + hcs_n = 1'b1; + hread_n = 1'b1; + hwrite_n = 1'b1; + hdataout_en_n = 1'b1; + + if ((read_data & mask) != (expected_data & mask)) begin + $display ("ERROR : Read-data mismatch at address %h", address) ; + $display (" : Expected Data : %h. Read Data : %h.", (expected_data & mask), read_data ) ; + end + else begin + $display (" INFO : Read Check Passed at address %h", address) ; + end + + + @(posedge hclk); + #1 + hcs_n = 1'b1; + hread_n = 1'b1; + hwrite_n = 1'b1; + hdataout_en_n = 1'b1; +end + +endtask + + + + + +endmodule +// ============================================================================= + diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.1 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.1 new file mode 100644 index 0000000..2960279 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.1 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Mon Apr 29 14:09:33 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch syn_results/sgmii_channel_smi.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr" +Running: syn_results in foreground + +Running sgmii_channel_smi|syn_results + +Running: compile (Compile) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:33 2019 + +Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:33 2019 + +Running: compiler (Compile Input) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:33 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs + +compiler completed +# Mon Apr 29 14:09:36 2019 + +Return Code: 0 +Run Time:00h:00m:03s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:36 2019 + +multi_srs_gen completed +# Mon Apr 29 14:09:36 2019 + +Return Code: 0 +Run Time:00h:00m:00s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Compile Process on sgmii_channel_smi|syn_results + +Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:36 2019 + +premap completed with warnings +# Mon Apr 29 14:09:37 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_channel_smi|syn_results + +Running: map (Map) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:37 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:09:37 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm + +fpga_mapper completed with warnings +# Mon Apr 29 14:09:40 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_channel_smi|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Logic Synthesis on sgmii_channel_smi|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.2 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.2 new file mode 100644 index 0000000..1ac7cca --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.2 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Mon Apr 29 14:08:39 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch syn_results/sgmii_channel_smi.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr" +Running: syn_results in foreground + +Running sgmii_channel_smi|syn_results + +Running: compile (Compile) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:39 2019 + +Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:39 2019 + +Running: compiler (Compile Input) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:39 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs + +compiler completed +# Mon Apr 29 14:08:41 2019 + +Return Code: 0 +Run Time:00h:00m:02s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:41 2019 + +multi_srs_gen completed +# Mon Apr 29 14:08:42 2019 + +Return Code: 0 +Run Time:00h:00m:01s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Compile Process on sgmii_channel_smi|syn_results + +Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:42 2019 + +premap completed with warnings +# Mon Apr 29 14:08:43 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_channel_smi|syn_results + +Running: map (Map) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:43 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:43 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm + +fpga_mapper completed with warnings +# Mon Apr 29 14:08:46 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_channel_smi|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Logic Synthesis on sgmii_channel_smi|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.3 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.3 new file mode 100644 index 0000000..1ac7cca --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.3 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Mon Apr 29 14:08:39 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch syn_results/sgmii_channel_smi.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr" +Running: syn_results in foreground + +Running sgmii_channel_smi|syn_results + +Running: compile (Compile) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:39 2019 + +Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:39 2019 + +Running: compiler (Compile Input) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:39 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs + +compiler completed +# Mon Apr 29 14:08:41 2019 + +Return Code: 0 +Run Time:00h:00m:02s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:41 2019 + +multi_srs_gen completed +# Mon Apr 29 14:08:42 2019 + +Return Code: 0 +Run Time:00h:00m:01s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Compile Process on sgmii_channel_smi|syn_results + +Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:42 2019 + +premap completed with warnings +# Mon Apr 29 14:08:43 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_channel_smi|syn_results + +Running: map (Map) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:43 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results +# Mon Apr 29 14:08:43 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm + +fpga_mapper completed with warnings +# Mon Apr 29 14:08:46 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_channel_smi|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Logic Synthesis on sgmii_channel_smi|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.4 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.4 new file mode 100644 index 0000000..a285c50 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.4 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Mon Apr 29 13:36:21 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch syn_results/sgmii_channel_smi.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr" +Running: syn_results in foreground + +Running sgmii_channel_smi|syn_results + +Running: compile (Compile) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:21 2019 + +Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:21 2019 + +Running: compiler (Compile Input) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:21 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs + +compiler completed +# Mon Apr 29 13:36:24 2019 + +Return Code: 0 +Run Time:00h:00m:03s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:24 2019 + +multi_srs_gen completed +# Mon Apr 29 13:36:24 2019 + +Return Code: 0 +Run Time:00h:00m:00s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Compile Process on sgmii_channel_smi|syn_results + +Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:24 2019 + +premap completed with warnings +# Mon Apr 29 13:36:25 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_channel_smi|syn_results + +Running: map (Map) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:25 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:25 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm + +fpga_mapper completed with warnings +# Mon Apr 29 13:36:28 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_channel_smi|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Logic Synthesis on sgmii_channel_smi|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.5 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.5 new file mode 100644 index 0000000..a285c50 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.5 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Mon Apr 29 13:36:21 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch syn_results/sgmii_channel_smi.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr" +Running: syn_results in foreground + +Running sgmii_channel_smi|syn_results + +Running: compile (Compile) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:21 2019 + +Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:21 2019 + +Running: compiler (Compile Input) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:21 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs + +compiler completed +# Mon Apr 29 13:36:24 2019 + +Return Code: 0 +Run Time:00h:00m:03s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:24 2019 + +multi_srs_gen completed +# Mon Apr 29 13:36:24 2019 + +Return Code: 0 +Run Time:00h:00m:00s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Compile Process on sgmii_channel_smi|syn_results + +Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:24 2019 + +premap completed with warnings +# Mon Apr 29 13:36:25 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_channel_smi|syn_results + +Running: map (Map) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:25 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results +# Mon Apr 29 13:36:25 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm + +fpga_mapper completed with warnings +# Mon Apr 29 13:36:28 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_channel_smi|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf +Complete: Logic Synthesis on sgmii_channel_smi|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cmd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cmd new file mode 100644 index 0000000..438b319 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cmd @@ -0,0 +1,18 @@ +PROJECT: sgmii_ecp5 + working_path: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results" + module: sgmii_ecp5 + verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" + vlog_std_v2001: true + constraint_file_name: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc" + suffix_name: edn + output_file_name: sgmii_ecp5 + write_prf: true + disable_io_insertion: true + force_gsr: false + frequency: 100 + fanout_limit: 50 + retiming: false + pipe: false + part: LFE5UM-85F + speed_grade: 8 + diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cst b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cst new file mode 100644 index 0000000..571fc3a --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cst @@ -0,0 +1,3 @@ +Date=05/10/2019 +Time=09:02:05 + diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.fdc b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.fdc new file mode 100644 index 0000000..5424a21 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU1_CH1} diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.lpc b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.lpc new file mode 100644 index 0000000..24a8719 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=05/10/2019 +ModuleName=sgmii_ecp5 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=09:02:05 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=10X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=2 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=1100 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +sgmii_ecp5.pp=pp +sgmii_ecp5.sym=sym +sgmii_ecp5.tft=tft +sgmii_ecp5.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH1 diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngd new file mode 100644 index 0000000000000000000000000000000000000000..fd4d8d5da678c0ab3119ebd0ef13c875454df15b GIT binary patch literal 393974 zcma%EcVJXi_MREA>x#YWU`0_(Lbt4>0nw1eB%p{o6N)Y?B_yC=!3424?22vdU9oq? zu3P!7Yh886vc_FYW-`y-e&;*)-uG^siTt7Oedjypo_p`P=a%>8W%ZhDt|C@GGRFTl zi1*GJL|5_7W9QDEotibHePk^DX=)8YiO#l>?PXRP%zI*r@v=Gw~E+Ei=Zq}rC&%1KSJc(7*|1XYvk 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Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5rsl_core +-- + +-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5sll_core +-- + +-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity sgmii_ecp5 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + tx_pclk: out std_logic; + txi_clk: in std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + xmit: in std_logic_vector(0 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + ctc_urun_s: out std_logic; + ctc_orun_s: out std_logic; + rx_cdr_lol_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_del_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity sgmii_ecp5; + +architecture v1 of sgmii_ecp5 is + component sgmii_ecp5rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "GBE"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component sgmii_ecp5rsl_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component sgmii_ecp5sll_core is + generic (PPROTOCOL: string := "GBE"; + PLOL_SETTING: integer := 0; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 39; + PDIFF_VAL_UNLOCK: integer := 78; + PPCLK_TC: integer := 131072; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component sgmii_ecp5sll_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11, + n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25, + n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39, + n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53, + n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67, + n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81, + n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95, + n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121, + n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd, + pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU1_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU1_inst : label is "CH1"; +begin + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103, + CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103, + CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103, + CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103, + CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103, + CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103, + CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103, + CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103, + D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2), + D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5), + D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0), + D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3), + D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual, + D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103, + CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn, + D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103, + CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44, + D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44, + D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44, + D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44, + D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44, + CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6, + CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8, + CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c, + CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1), + CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3), + CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5), + CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7), + CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0), + CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66, + CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69, + CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73, + CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77, + CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81, + CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85, + CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89, + CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91, + CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c, + CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94, + CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s, + CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97, + CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c, + CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100, + CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19, + D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23, + D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29, + D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35, + D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40, + D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n103 <= '0' ; + n102 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n112 <= 'Z' ; + rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122, + rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122, + rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122, + rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116, + rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n111 <= '1' ; + n110 <= '0' ; + n122 <= '0' ; + n121 <= '1' ; + n113 <= 'Z' ; + n114 <= 'Z' ; + n115 <= 'Z' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n124 <= '1' ; + n123 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_ngd.asd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v new file mode 100644 index 0000000..69a023d --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module sgmii_ecp5rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_ecp5sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.1 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.1 new file mode 100644 index 0000000..085fe8a --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.1 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Tue May 7 17:10:00 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr" +Running: syn_results in foreground + +Running sgmii_ecp5|syn_results + +Running: compile (Compile) on sgmii_ecp5|syn_results +# Tue May 7 17:10:01 2019 + +Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results +# Tue May 7 17:10:01 2019 + +Running: compiler (Compile Input) on sgmii_ecp5|syn_results +# Tue May 7 17:10:01 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs + +compiler completed +# Tue May 7 17:10:03 2019 + +Return Code: 0 +Run Time:00h:00m:02s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results +# Tue May 7 17:10:03 2019 + +multi_srs_gen completed +# Tue May 7 17:10:04 2019 + +Return Code: 0 +Run Time:00h:00m:01s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Compile Process on sgmii_ecp5|syn_results + +Running: premap (Pre-mapping) on sgmii_ecp5|syn_results +# Tue May 7 17:10:04 2019 + +premap completed with warnings +# Tue May 7 17:10:04 2019 + +Return Code: 1 +Run Time:00h:00m:00s +Complete: Compile on sgmii_ecp5|syn_results + +Running: map (Map) on sgmii_ecp5|syn_results +# Tue May 7 17:10:04 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results +# Tue May 7 17:10:04 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm + +fpga_mapper completed with warnings +# Tue May 7 17:10:08 2019 + +Return Code: 1 +Run Time:00h:00m:04s +Complete: Map on sgmii_ecp5|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Logic Synthesis on sgmii_ecp5|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.2 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.2 new file mode 100644 index 0000000..b9b8215 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.2 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Tue May 7 16:13:41 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr" +Running: syn_results in foreground + +Running sgmii_ecp5|syn_results + +Running: compile (Compile) on sgmii_ecp5|syn_results +# Tue May 7 16:13:41 2019 + +Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results +# Tue May 7 16:13:41 2019 + +Running: compiler (Compile Input) on sgmii_ecp5|syn_results +# Tue May 7 16:13:41 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs + +compiler completed +# Tue May 7 16:13:44 2019 + +Return Code: 0 +Run Time:00h:00m:03s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results +# Tue May 7 16:13:44 2019 + +multi_srs_gen completed +# Tue May 7 16:13:44 2019 + +Return Code: 0 +Run Time:00h:00m:00s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Compile Process on sgmii_ecp5|syn_results + +Running: premap (Pre-mapping) on sgmii_ecp5|syn_results +# Tue May 7 16:13:44 2019 + +premap completed with warnings +# Tue May 7 16:13:45 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_ecp5|syn_results + +Running: map (Map) on sgmii_ecp5|syn_results +# Tue May 7 16:13:45 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results +# Tue May 7 16:13:45 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm + +fpga_mapper completed with warnings +# Tue May 7 16:13:48 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_ecp5|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Logic Synthesis on sgmii_ecp5|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.3 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.3 new file mode 100644 index 0000000..c1fc835 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.3 @@ -0,0 +1,76 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Mon Apr 29 16:13:15 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj +ProductType: synplify_pro + + + + +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr" +Running: syn_results in foreground + +Running sgmii_ecp5|syn_results + +Running: compile (Compile) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:16 2019 + +Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:16 2019 + +Running: compiler (Compile Input) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:16 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs + +compiler completed +# Mon Apr 29 16:13:18 2019 + +Return Code: 0 +Run Time:00h:00m:02s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:18 2019 + +multi_srs_gen completed +# Mon Apr 29 16:13:18 2019 + +Return Code: 0 +Run Time:00h:00m:00s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Compile Process on sgmii_ecp5|syn_results + +Running: premap (Pre-mapping) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:18 2019 + +premap completed with warnings +# Mon Apr 29 16:13:19 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_ecp5|syn_results + +Running: map (Map) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:19 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results +# Mon Apr 29 16:13:19 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm + +fpga_mapper completed with warnings +# Mon Apr 29 16:13:22 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_ecp5|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Logic Synthesis on sgmii_ecp5|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.4 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.4 new file mode 100644 index 0000000..ebf331c --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.4 @@ -0,0 +1,75 @@ +Running in Lattice mode + +Starting: /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch +Install: /home/soft/lattice/diamond/3.10_x64/synpbase +Hostname: lxhadeb07 +Date: Wed Apr 24 09:44:47 2019 +Version: M-2017.03L-SP1-1 + +Arguments: -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj +ProductType: synplify_pro + + + + +log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr" +Running: syn_results in foreground + +Running sgmii_ecp5|syn_results + +Running: compile (Compile) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:47 2019 + +Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:47 2019 + +Running: compiler (Compile Input) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:47 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs + +compiler completed +# Wed Apr 24 09:44:50 2019 + +Return Code: 0 +Run Time:00h:00m:03s + +Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:50 2019 + +multi_srs_gen completed +# Wed Apr 24 09:44:50 2019 + +Return Code: 0 +Run Time:00h:00m:00s +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Compile Process on sgmii_ecp5|syn_results + +Running: premap (Pre-mapping) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:50 2019 + +premap completed with warnings +# Wed Apr 24 09:44:51 2019 + +Return Code: 1 +Run Time:00h:00m:01s +Complete: Compile on sgmii_ecp5|syn_results + +Running: map (Map) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:51 2019 +License granted for 4 parallel jobs + +Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results +# Wed Apr 24 09:44:51 2019 +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm + +fpga_mapper completed with warnings +# Wed Apr 24 09:44:54 2019 + +Return Code: 1 +Run Time:00h:00m:03s +Complete: Map on sgmii_ecp5|syn_results +Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf +Complete: Logic Synthesis on sgmii_ecp5|syn_results +exit status=0 +exit status=0 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/.recordref b/gbe/cores/sgmii/sgmii_ecp5/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/_CMD_.CML b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_CMD_.CML new file mode 100644 index 0000000..87a778c --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs -top sgmii_ecp5 -hdllog /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/ -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib -v2001 -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -lib work /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/_cmd._cml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_cmd._cml new file mode 100644 index 0000000..225b64d --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top sgmii_ecp5 -osyn /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs \ No newline at end of file diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr new file mode 100644 index 0000000..f6086bf --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr @@ -0,0 +1,1157 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Wed Apr 24 09:44:47 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Wed Apr 24 09:44:48 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Wed Apr 24 09:44:48 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Wed Apr 24 09:44:48 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB) + + +Process completed successfully. +# Wed Apr 24 09:44:49 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Wed Apr 24 09:44:49 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Wed Apr 24 09:44:49 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Wed Apr 24 09:44:50 2019 + +###########################################################] +Pre-mapping Report + +# Wed Apr 24 09:44:50 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 76 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 76 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Wed Apr 24 09:44:51 2019 + +###########################################################] +Map & Optimize Report + +# Wed Apr 24 09:44:51 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.36ns 118 / 186 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 186 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=================================== Non-Gated/Non-Generated Clocks ==================================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 74 rsl_inst.genblk1\.pll_lol_p1 +@K:CKID0002 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +======================================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 146MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":150:4:150:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Wed Apr 24 09:44:54 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------------ +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup +========================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[7] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[8] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170 +===================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +======================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +=================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 9.946 + + Number of logic level(s): 0 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.rlol_p1 / D + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 2 +rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 - +=================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 186 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 99 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 60 +FD1S3BX: 10 +FD1S3DX: 96 +GSR: 1 +INV: 3 +ORCALUT4: 116 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 34MB peak: 150MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Wed Apr 24 09:44:54 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/dm/layer0.xdm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..96ecede --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/dm/layer0.xdm @@ -0,0 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b/gbe/cores/sgmii/sgmii_ecp5/syn_results/run_options.txt new file mode 100644 index 0000000..5110194 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/run_options.txt @@ -0,0 +1,76 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/run_options.txt +#-- Written on Fri May 10 09:02:09 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "sgmii_ecp5" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./sgmii_ecp5.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf" +impl -active "syn_results" diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/scemi_cfg.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/scratchproject.prs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scratchproject.prs new file mode 100644 index 0000000..1406dc9 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scratchproject.prs @@ -0,0 +1,74 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "sgmii_ecp5" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf" +impl -active "syn_results" diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr new file mode 100644 index 0000000..c3d63b8 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr @@ -0,0 +1,97 @@ +---------------------------------------------------------------------- +Report for cell sgmii_ecp5.v1 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + CCU2C 113 100.0 + DCUA 1 100.0 + FD1P3BX 20 100.0 + FD1P3DX 92 100.0 + FD1S3BX 12 100.0 + FD1S3DX 97 100.0 + GSR 1 100.0 + INV 3 100.0 + ORCALUT4 154 100.0 + PFUMX 2 100.0 + PUR 1 100.0 + VHI 6 100.0 + VLO 6 100.0 +SUB MODULES + sgmii_ecp5rsl_core_Z2_layer1 1 100.0 + sgmii_ecp5sll_core_Z1_layer1 1 100.0 + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 513 +---------------------------------------------------------------------- +Report for cell sgmii_ecp5rsl_core_Z2_layer1.netlist + Instance path: rsl_inst + Cell usage: + cell count Res Usage(%) + CCU2C 51 45.1 + FD1P3BX 4 20.0 + FD1P3DX 74 80.4 + FD1S3BX 12 100.0 + FD1S3DX 37 38.1 + ORCALUT4 100 64.9 + PFUMX 2 100.0 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 282 +---------------------------------------------------------------------- +Report for cell sgmii_ecp5sll_core_Z1_layer1.netlist + Instance path: sll_inst + Cell usage: + cell count Res Usage(%) + CCU2C 62 54.9 + FD1P3BX 16 80.0 + FD1P3DX 18 19.6 + FD1S3DX 60 61.9 + INV 3 100.0 + ORCALUT4 54 35.1 + VHI 4 66.7 + VLO 4 66.7 +SUB MODULES + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 224 +---------------------------------------------------------------------- +Report for cell sync_0s_0.netlist + Original Cell name sync_0s + Instance path: sll_inst.pdiff_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s_6.netlist + Original Cell name sync_0s + Instance path: sll_inst.rtc_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s.netlist + Original Cell name sync_0s + Instance path: sll_inst.phb_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.fse b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.fse new file mode 100644 index 0000000..cc147f0 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.fse @@ -0,0 +1,12 @@ + +fsm_encoding {61801018011} sequential + +fsm_state_encoding {61801018011} LPLL_LOSS_ST {00} + +fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01} + +fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10} + +fsm_state_encoding {61801018011} LPLL_LOCK_ST {11} + +fsm_registers {61801018011} {sll_state[1]} {sll_state[0]} diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.htm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.htm new file mode 100644 index 0000000..31d89ed --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.htm @@ -0,0 +1,9 @@ + + + syntmp/sgmii_ecp5_srr.htm log file + + + + + + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj new file mode 100644 index 0000000..7f5b1db --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj @@ -0,0 +1,47 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj +#-- Written on Fri May 10 09:02:08 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -constraint {"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc"} + +#-- top module name +set_option -top_module sgmii_ecp5 + +#-- set result format/file last +project -result_file "sgmii_ecp5.edn" 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/home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 09:02:09 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:02:09 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:11 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:12 2019 + +###########################################################] +# Fri May 10 09:02:12 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 09:02:13 2019 + +###########################################################] +# Fri May 10 09:02:13 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 4.90ns 155 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 09:02:16 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.043 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.902 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.043 + + Number of logic level(s): 11 + Starting point: rsl_inst.genblk2\.rxs_rst / Q + Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - +rxs_rst Net - - - - 6 +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - +rsl_rx_serdes_rst_c Net - - - - 3 +rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - +rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - +dual_or_rserd_rst Net - - - - 9 +rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - +rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - +rx_any_rst Net - - - - 2 +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - +rxr_wt_cnt9 Net - - - - 14 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - +rxr_wt_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - +rxr_wt_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - +rxr_wt_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - +rxr_wt_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - +rxr_wt_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - +rxr_wt_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - +rxr_wt_cnt_s[11] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - +================================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 154 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 09:02:16 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm new file mode 100644 index 0000000000000000000000000000000000000000..fc1b683f7a7268ddd47c206610aeb4ffe8cce108 GIT binary patch literal 31307 zcmYg%byQSe^sj<~k_u8%A__=%4JiT=f{1i?cMLEvh)75(NHYxG-Q5h$kiyVC^Z)}4 zLq5O1-&=3J``6uT@4e1Bd+mL9oX=&9eDdIb9^5ZlT3T#uLp(~KxPvB&-ksQ`h!q)< zl>f)Pzdr~-xh#m1?I5=+o*m#MxHgCrGUcX6<2WF^j9%3ryNXKa}}j?w`SWyu^zUqAW+0)CgeZvjtunz-X6YLVPQ0` zXmQ|&#EkS+tH3t;Y~!Atl1D3|V+Vi|wT$Ni zQDz;ZhN#9LL!N@$^AL$+J<=N!H5>NOU7VpVOw``d>=OfuTt9{?0;^r0<>yPKJ~m$J9)|UVeUTAsa5;y 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/home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 09:02:09 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:02:09 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:11 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:11 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:12 2019 + +###########################################################] +# Fri May 10 09:02:12 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 09:02:13 2019 + +###########################################################] +# Fri May 10 09:02:13 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 4.90ns 155 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 09:02:16 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.043 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.902 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.043 + + Number of logic level(s): 11 + Starting point: rsl_inst.genblk2\.rxs_rst / Q + Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - +rxs_rst Net - - - - 6 +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - +rsl_rx_serdes_rst_c Net - - - - 3 +rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - +rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - +dual_or_rserd_rst Net - - - - 9 +rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - +rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - +rx_any_rst Net - - - - 2 +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - +rxr_wt_cnt9 Net - - - - 14 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - +rxr_wt_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - +rxr_wt_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - +rxr_wt_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - +rxr_wt_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - +rxr_wt_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - +rxr_wt_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - +rxr_wt_cnt_s[11] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - +================================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 154 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 09:02:16 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..8868cb218988b1713b4046aedbde725a2fe5b4bc GIT binary patch literal 36864 zcmeHQTX5Uhd8R~Nty{LX>pE-ip1PZ?)Yv2df)q*bZX#9h}h=u9sUo#{hf`qF0dmT9LmolGC{(9Yy#r`_qyJ~Y!dowjM( zm;V0&uU^TPRyb?8A;-p{NB}(F|DSX4-_PpxtA~F|cHm0G@@EEt>O)f>Aniw|{&(uXrhYQ@I1aL+$ z$&%qGeYcSIw4_ffj;Z=I>A3bis`*K;R56U;s8G#Gcf3_RyXc#C$JEGn8^ag?fM+S~m2AD{%z-si=V!If9*v8d!lJSYwibwIj1YsZ9Fra59g z7BQ?Gng6pVkXB!P)wx-6cn*Z?_P7OD7KNRRrNrsYm0fB;~GlE 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zz=H>sp5ur!($1soou1WH`ttj01Jf4gstFelV~_3)srFlckly%zB#HRX$MbtfzAes? zBY$q}IPQQBL*Q@mJsugBbUGe*90a)db{NOvxf?wnVpY;~>H1C>Uoms$ z&BSvv1Pka~1`DrZT2}}f^I~)MFoR&}fFC;UmC0fcW;2>E?#&?$Z)F$HUSr?97S9Sa zdbiwR;!K%lYaa8ru^V&EbwlTtwS^An)BdZ_;rvzTklvgBN{2k|$%PKpst)OU3nv|N zSPC7A_tJ$9`SRku134TN@5rCNXV6+ca<9}Ll;33_9HnnI3`*Bx9^C^)JE7;2LMLQ1 zo^w@Ae%; zh33~~Q+{{9|2Eh8%^%|14(0d8+)NjIU|tvBO?bS{_$`08p$X?3=-8+Kar%xzS)V7~ zd3K*4JLjSBBbDz1%+z5o9K00960;&M>n0ssI2|NjF3$_Z7m HuxtSULWJ~L literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vhm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vhm new file mode 100644 index 0000000..bbff63b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vhm @@ -0,0 +1,6445 @@ +-- +-- Written by Synplicity +-- Product Version "M-2017.03L-SP1-1" +-- Program "Synplify Pro", Mapper "maplat, Build 1796R" +-- Fri May 10 09:02:16 2019 +-- + +-- +-- Written by Synplify Pro version Build 1796R +-- Fri May 10 09:02:16 2019 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_0 is +port( + ppul_sync : in std_logic; + pdiff_sync : out std_logic; + sli_rst : in std_logic; + pll_refclki : in std_logic); +end sync_0s_0; + +architecture beh of sync_0s_0 is + signal DATA_P1 : std_logic ; + signal DATA_P2_QN_1 : std_logic ; + signal VCC : std_logic ; + signal DATA_P1_QN_1 : std_logic ; + signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => pll_refclki, + CD => sli_rst, + Q => pdiff_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => ppul_sync, + CK => pll_refclki, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_6 is +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic); +end sync_0s_6; + +architecture beh of sync_0s_6 is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => tx_pclk, + CD => sli_rst, + Q => ppul_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => rtc_pul, + CK => tx_pclk, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s is +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic); +end sync_0s; + +architecture beh of sync_0s is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN_0 : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN_0 : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( +D => DATA_P1, +CK => pll_refclki, +CD => sli_rst, +Q => rhb_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( +D => phb, +CK => pll_refclki, +CD => sli_rst, +Q => DATA_P1); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5rsl_core_Z2_layer1 is +port( +rx_pcs_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +tx_serdes_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rsl_disable : in std_logic; +rx_serdes_rst_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rst_dual_c : in std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic); +end sgmii_ecp5rsl_core_Z2_layer1; + +architecture beh of sgmii_ecp5rsl_core_Z2_layer1 is +signal RXS_CNT : std_logic_vector(1 downto 0); +signal RXS_CNT_3 : std_logic_vector(1 downto 0); +signal RXPR_APPD_RNO : std_logic_vector(0 to 0); +signal PLOL0_CNT : std_logic_vector(2 downto 0); +signal PLOL0_CNT_3 : std_logic_vector(2 downto 0); +signal RXSR_APPD : std_logic_vector(0 to 0); +signal RXS_CNT_QN : std_logic_vector(1 downto 0); +signal RLOS_DB_CNT : std_logic_vector(3 downto 0); +signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOLS0_CNT_S : std_logic_vector(17 downto 0); +signal RLOLS0_CNT : std_logic_vector(17 downto 0); +signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0); +signal RLOL_DB_CNT : std_logic_vector(3 downto 0); +signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOL1_CNT_S : std_logic_vector(18 downto 0); +signal RLOL1_CNT : std_logic_vector(18 downto 0); +signal RLOL1_CNT_QN : std_logic_vector(18 downto 0); +signal RXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal RXR_WT_CNT : std_logic_vector(11 downto 0); +signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal RXSR_APPD_QN : std_logic_vector(0 to 0); +signal RXPR_APPD : std_logic_vector(0 to 0); +signal RXPR_APPD_QN : std_logic_vector(0 to 0); +signal TXS_CNT : std_logic_vector(1 downto 0); +signal TXS_CNT_QN : std_logic_vector(1 downto 0); +signal TXS_CNT_RNO : std_logic_vector(1 to 1); +signal TXP_CNT : std_logic_vector(1 downto 0); +signal TXP_CNT_QN : std_logic_vector(1 downto 0); +signal TXP_CNT_RNO : std_logic_vector(1 to 1); +signal PLOL_CNT_S : std_logic_vector(19 downto 0); +signal PLOL_CNT : std_logic_vector(19 downto 0); +signal PLOL_CNT_QN : std_logic_vector(19 downto 0); +signal PLOL0_CNT_QN : std_logic_vector(2 downto 0); +signal TXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal TXR_WT_CNT : std_logic_vector(11 downto 0); +signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal TXPR_APPD : std_logic_vector(0 to 0); +signal TXPR_APPD_QN : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17); +signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal PLOL_CNT_CRY : std_logic_vector(18 downto 0); +signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19); +signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19); +signal RXS_RST : std_logic ; +signal VCC : std_logic ; +signal DUAL_OR_RSERD_RST : std_logic ; +signal PLOL0_CNT9 : std_logic ; +signal WAITA_PLOL0 : std_logic ; +signal RLOS_DB_P1 : std_logic ; +signal RLOS_DB : std_logic ; +signal RXP_RST25 : std_logic ; +signal RLOL_DB : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ; +signal RX_ALL_WELL : std_logic ; +signal RSL_RX_PCS_RST_C_10 : std_logic ; +signal UN3_RX_ALL_WELL_2 : std_logic ; +signal UN17_RXR_WT_TC : std_logic ; +signal UN3_RX_ALL_WELL_1 : std_logic ; +signal RX_ANY_RST : std_logic ; +signal RXR_WT_CNT9 : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_I : std_logic ; +signal RLOL1_CNT_TC_1 : std_logic ; +signal \RLOL1_CNT_\ : std_logic ; +signal RXR_WT_EN : std_logic ; +signal RXR_WT_CNTE : std_logic ; +signal RLOLS0_CNT_TC_1 : std_logic ; +signal UN2_RLOS_REDGE_1_I : std_logic ; +signal UN18_TXR_WT_TC : std_logic ; +signal TX_ANY_RST : std_logic ; +signal PLL_LOL_P2 : std_logic ; +signal UN2_PLOL_FEDGE_5_I : std_logic ; +signal N_2124_0 : std_logic ; +signal WAITA_RLOLS06 : std_logic ; +signal UN1_RLOLS0_CNT_TC : std_logic ; +signal WAITA_RLOLS0 : std_logic ; +signal WAITA_RLOLS0_QN : std_logic ; +signal WAIT_CALIB_RNO : std_logic ; +signal UN1_RLOS_FEDGE_1 : std_logic ; +signal WAIT_CALIB : std_logic ; +signal WAIT_CALIB_QN : std_logic ; +signal RXS_RST6 : std_logic ; +signal UN1_RXS_CNT_TC : std_logic ; +signal RXS_RST_QN : std_logic ; +signal RXP_RST2 : std_logic ; +signal RXP_RST2_QN : std_logic ; +signal RLOS_P1 : std_logic ; +signal RLOS_P2 : std_logic ; +signal RLOS_P2_QN : std_logic ; +signal RLOS_P1_QN : std_logic ; +signal RLOS_DB_P1_QN : std_logic ; +signal RLOS_DB_CNT_AXB_0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOS_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOS_DB_CNT_MAX : std_logic ; +signal RLOS_DB_QN : std_logic ; +signal RLOLS0_CNTE : std_logic ; +signal RLOL_P1 : std_logic ; +signal RLOL_P2 : std_logic ; +signal RLOL_P2_QN : std_logic ; +signal RLOL_P1_QN : std_logic ; +signal RLOL_DB_P1 : std_logic ; +signal RLOL_DB_P1_QN : std_logic ; +signal RLOL_DB_CNT_AXB_0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOL_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOL_DB_CNT_MAX : std_logic ; +signal RLOL_DB_QN : std_logic ; +signal RLOL1_CNTE : std_logic ; +signal RXSDR_APPD_2 : std_logic ; +signal RXSDR_APPD : std_logic ; +signal RXSDR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ; +signal RXR_WT_EN_QN : std_logic ; +signal RXDPR_APPD : std_logic ; +signal RXDPR_APPD_QN : std_logic ; +signal RSL_RX_RDY_9 : std_logic ; +signal RUO_RX_RDYR_QN : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ; +signal PLOL_FEDGE : std_logic ; +signal UN1_PLOL0_CNT_TC_1_I : std_logic ; +signal WAITA_PLOL0_QN : std_logic ; +signal UN1_PLOL_CNT_TC : std_logic ; +signal UN2_PLOL_CNT_TC : std_logic ; +signal TXS_RST : std_logic ; +signal TXS_RST_QN : std_logic ; +signal N_10_I : std_logic ; +signal UN9_PLOL0_CNT_TC : std_logic ; +signal UN1_PLOL0_CNT_TC_1 : std_logic ; +signal TXP_RST : std_logic ; +signal TXP_RST_QN : std_logic ; +signal N_11_I : std_logic ; +signal PLL_LOL_P3 : std_logic ; +signal PLL_LOL_P3_QN : std_logic ; +signal PLL_LOL_P1 : std_logic ; +signal PLL_LOL_P2_QN : std_logic ; +signal PLL_LOL_P1_QN : std_logic ; +signal TXSR_APPD_2 : std_logic ; +signal TXSR_APPD : std_logic ; +signal TXSR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ; +signal TXR_WT_EN : std_logic ; +signal TXR_WT_EN_QN : std_logic ; +signal TXR_WT_CNTE : std_logic ; +signal UN2_PLOL_FEDGE_2 : std_logic ; +signal UN2_PLOL_FEDGE_3_I : std_logic ; +signal TXDPR_APPD : std_logic ; +signal TXDPR_APPD_QN : std_logic ; +signal UN2_PLOL_FEDGE_5_1 : std_logic ; +signal RSL_TX_RDY_8 : std_logic ; +signal RUO_TX_RDYR_QN : std_logic ; +signal UN2_PLOL_FEDGE_8_I : std_logic ; +signal RLOS_REDGE : std_logic ; +signal RLOLS0_CNT11_0 : std_logic ; +signal RSL_TX_SERDES_RST_C_7 : std_logic ; +signal \PLOL_CNT_\ : std_logic ; +signal \RLOLS0_CNT_\ : std_logic ; +signal UN8_RXS_CNT_TC : std_logic ; +signal UN1_TXSR_APPD : std_logic ; +signal RSL_SERDES_RST_DUAL_C_6 : std_logic ; +signal UN3_RX_ALL_WELL_2_1 : std_logic ; +signal UN1_RXSDR_OR_SR_APPD : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_1_1 : std_logic ; +signal RSL_RX_SERDES_RST_C_5 : std_logic ; +signal RLOLS0_CNT_TC_1_10 : std_logic ; +signal RLOLS0_CNT_TC_1_11 : std_logic ; +signal RLOLS0_CNT_TC_1_12 : std_logic ; +signal RLOLS0_CNT_TC_1_13 : std_logic ; +signal UN1_PLOL_CNT_TC_11 : std_logic ; +signal UN1_PLOL_CNT_TC_12 : std_logic ; +signal UN1_PLOL_CNT_TC_13 : std_logic ; +signal UN1_PLOL_CNT_TC_14 : std_logic ; +signal RLOL1_CNT_TC_1_11 : std_logic ; +signal RLOL1_CNT_TC_1_12 : std_logic ; +signal RLOL1_CNT_TC_1_13 : std_logic ; +signal RLOL1_CNT_TC_1_14 : std_logic ; +signal TXSR_APPD_4 : std_logic ; +signal RSL_TX_PCS_RST_C_4 : std_logic ; +signal CO0_2 : std_logic ; +signal UN18_TXR_WT_TC_6 : std_logic ; +signal UN18_TXR_WT_TC_7 : std_logic ; +signal UN18_TXR_WT_TC_8 : std_logic ; +signal UN17_RXR_WT_TC_6 : std_logic ; +signal UN17_RXR_WT_TC_7 : std_logic ; +signal UN17_RXR_WT_TC_8 : std_logic ; +signal RXSDR_APPD_4 : std_logic ; +signal RLOLS0_CNT_TC_1_9 : std_logic ; +signal UN1_PLOL_CNT_TC_10 : std_logic ; +signal RLOL1_CNT_TC_1_10 : std_logic ; +signal \TXR_WT_CNT_\ : std_logic ; +signal RLOS_DB_CNT_CRY_0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOS_DB_CNT_CRY_2 : std_logic ; +signal RLOS_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOS_DB_CNT_S_3_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_2 : std_logic ; +signal RLOL_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOL_DB_CNT_S_3_0_S1 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_6 : std_logic ; +signal N_7 : std_logic ; +begin +\GENBLK2.RXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"2626" +) +port map ( +A => RXS_RST, +B => RXS_CNT(0), +C => RXS_CNT(1), +D => VCC, +Z => RXS_CNT_3(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"0101" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => rx_los_low_s, +C => rx_cdr_lol_s, +D => VCC, +Z => RXPR_APPD_RNO(0)); +\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 +generic map( + init => X"1222" +) +port map ( +A => PLOL0_CNT(1), +B => PLOL0_CNT9, +C => WAITA_PLOL0, +D => PLOL0_CNT(0), +Z => PLOL0_CNT_3(1)); +\GENBLK2.RXP_RST2_RNO\: LUT4 +generic map( + init => X"BABA" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => RLOS_DB_P1, +C => RLOS_DB, +D => VCC, +Z => RXP_RST25); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 +generic map( + init => X"0101" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => RLOS_DB, +C => RLOL_DB, +D => VCC, +Z => UN1_RUI_RST_DUAL_C_1_1); +\GENBLK2.GENBLK3.RUO_RX_RDYR_RNO\: LUT4 +generic map( + init => X"0002" +) +port map ( +A => RX_ALL_WELL, +B => rst_dual_c, +C => RSL_RX_PCS_RST_C_10, +D => DUAL_OR_RSERD_RST, +Z => UN3_RX_ALL_WELL_2); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0404" +) +port map ( +A => UN17_RXR_WT_TC, +B => RX_ALL_WELL, +C => DUAL_OR_RSERD_RST, +D => VCC, +Z => UN3_RX_ALL_WELL_1); +RX_ANY_RST_RNIFD021: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RX_ANY_RST, +B => UN17_RXR_WT_TC, +C => RLOS_DB, +D => RLOL_DB, +Z => RXR_WT_CNT9); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO_0\: LUT4 +generic map( + init => X"FBFB" +) +port map ( +A => rst_dual_c, +B => RX_ALL_WELL, +C => DUAL_OR_RSERD_RST, +D => VCC, +Z => UN1_RUI_RST_DUAL_C_1_I); +\GENBLK2.RXS_RST_RNIS0OP\: LUT4 +generic map( + init => X"1011" +) +port map ( +A => RLOL1_CNT_TC_1, +B => RXS_RST, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => \RLOL1_CNT_\); +\GENBLK2.GENBLK3.RXR_WT_EN_RNIQF0H1\: LUT4 +generic map( + init => X"FFEF" +) +port map ( +A => RXR_WT_EN, +B => RX_ANY_RST, +C => RX_ALL_WELL, +D => UN17_RXR_WT_TC, +Z => RXR_WT_CNTE); +\GENBLK2.RXP_RST2_RNO_0\: LUT4 +generic map( + init => X"EFEE" +) +port map ( +A => RLOLS0_CNT_TC_1, +B => DUAL_OR_RSERD_RST, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => UN2_RLOS_REDGE_1_I); +\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => UN18_TXR_WT_TC, +B => TX_ANY_RST, +C => PLL_LOL_P2, +D => VCC, +Z => UN2_PLOL_FEDGE_5_I); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RXSR_APPD(0), +B => rx_serdes_rst_c, +C => RXS_RST, +D => rsl_disable, +Z => N_2124_0); +\GENBLK2.WAITA_RLOLS0_REG_Z618\: FD1P3DX port map ( +D => WAITA_RLOLS06, +SP => UN1_RLOLS0_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => WAITA_RLOLS0); +\GENBLK2.WAIT_CALIB_REG_Z620\: FD1P3BX port map ( +D => WAIT_CALIB_RNO, +SP => UN1_RLOS_FEDGE_1, +CK => rxrefclk, +PD => rsl_rst, +Q => WAIT_CALIB); +\GENBLK2.RXS_RST_REG_Z622\: FD1P3DX port map ( +D => RXS_RST6, +SP => UN1_RXS_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_RST); +\GENBLK2.RXS_CNT[0]_REG_Z624\: FD1S3DX port map ( +D => RXS_CNT_3(0), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(0)); +\GENBLK2.RXS_CNT[1]_REG_Z626\: FD1S3DX port map ( +D => RXS_CNT_3(1), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(1)); +\GENBLK2.RXP_RST2_REG_Z628\: FD1P3BX port map ( +D => RXP_RST25, +SP => UN2_RLOS_REDGE_1_I, +CK => rxrefclk, +PD => rsl_rst, +Q => RXP_RST2); +\GENBLK2.RLOS_P2_REG_Z630\: FD1S3DX port map ( +D => RLOS_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P2); +\GENBLK2.RLOS_P1_REG_Z632\: FD1S3DX port map ( +D => rx_los_low_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P1); +\GENBLK2.RLOS_DB_P1_REG_Z634\: FD1S3BX port map ( +D => RLOS_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_P1); +\GENBLK2.RLOS_DB_CNT[0]_REG_Z636\: FD1S3BX port map ( +D => RLOS_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(0)); +\GENBLK2.RLOS_DB_CNT[1]_REG_Z638\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(1)); +\GENBLK2.RLOS_DB_CNT[2]_REG_Z640\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(2)); +\GENBLK2.RLOS_DB_CNT[3]_REG_Z642\: FD1S3BX port map ( +D => RLOS_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(3)); +\GENBLK2.RLOS_DB_REG_Z644\: FD1P3BX port map ( +D => RLOS_DB_CNT(1), +SP => UN1_RLOS_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB); +\GENBLK2.RLOLS0_CNT[0]_REG_Z646\: FD1P3DX port map ( +D => RLOLS0_CNT_S(0), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(0)); +\GENBLK2.RLOLS0_CNT[1]_REG_Z648\: FD1P3DX port map ( +D => RLOLS0_CNT_S(1), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(1)); +\GENBLK2.RLOLS0_CNT[2]_REG_Z650\: FD1P3DX port map ( +D => RLOLS0_CNT_S(2), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(2)); +\GENBLK2.RLOLS0_CNT[3]_REG_Z652\: FD1P3DX port map ( +D => RLOLS0_CNT_S(3), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(3)); +\GENBLK2.RLOLS0_CNT[4]_REG_Z654\: FD1P3DX port map ( +D => RLOLS0_CNT_S(4), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(4)); +\GENBLK2.RLOLS0_CNT[5]_REG_Z656\: FD1P3DX port map ( +D => RLOLS0_CNT_S(5), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(5)); +\GENBLK2.RLOLS0_CNT[6]_REG_Z658\: FD1P3DX port map ( +D => RLOLS0_CNT_S(6), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(6)); +\GENBLK2.RLOLS0_CNT[7]_REG_Z660\: FD1P3DX port map ( +D => RLOLS0_CNT_S(7), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(7)); +\GENBLK2.RLOLS0_CNT[8]_REG_Z662\: FD1P3DX port map ( +D => RLOLS0_CNT_S(8), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(8)); +\GENBLK2.RLOLS0_CNT[9]_REG_Z664\: FD1P3DX port map ( +D => RLOLS0_CNT_S(9), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(9)); +\GENBLK2.RLOLS0_CNT[10]_REG_Z666\: FD1P3DX port map ( +D => RLOLS0_CNT_S(10), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(10)); +\GENBLK2.RLOLS0_CNT[11]_REG_Z668\: FD1P3DX port map ( +D => RLOLS0_CNT_S(11), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(11)); +\GENBLK2.RLOLS0_CNT[12]_REG_Z670\: FD1P3DX port map ( +D => RLOLS0_CNT_S(12), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(12)); +\GENBLK2.RLOLS0_CNT[13]_REG_Z672\: FD1P3DX port map ( +D => RLOLS0_CNT_S(13), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(13)); +\GENBLK2.RLOLS0_CNT[14]_REG_Z674\: FD1P3DX port map ( +D => RLOLS0_CNT_S(14), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(14)); +\GENBLK2.RLOLS0_CNT[15]_REG_Z676\: FD1P3DX port map ( +D => RLOLS0_CNT_S(15), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(15)); +\GENBLK2.RLOLS0_CNT[16]_REG_Z678\: FD1P3DX port map ( +D => RLOLS0_CNT_S(16), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(16)); +\GENBLK2.RLOLS0_CNT[17]_REG_Z680\: FD1P3DX port map ( +D => RLOLS0_CNT_S(17), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(17)); +\GENBLK2.RLOL_P2_REG_Z682\: FD1S3DX port map ( +D => RLOL_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P2); +\GENBLK2.RLOL_P1_REG_Z684\: FD1S3DX port map ( +D => rx_cdr_lol_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P1); +\GENBLK2.RLOL_DB_P1_REG_Z686\: FD1S3BX port map ( +D => RLOL_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_P1); +\GENBLK2.RLOL_DB_CNT[0]_REG_Z688\: FD1S3BX port map ( +D => RLOL_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(0)); +\GENBLK2.RLOL_DB_CNT[1]_REG_Z690\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(1)); +\GENBLK2.RLOL_DB_CNT[2]_REG_Z692\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(2)); +\GENBLK2.RLOL_DB_CNT[3]_REG_Z694\: FD1S3BX port map ( +D => RLOL_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(3)); +\GENBLK2.RLOL_DB_REG_Z696\: FD1P3BX port map ( +D => RLOL_DB_CNT(1), +SP => UN1_RLOL_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB); +\GENBLK2.RLOL1_CNT[0]_REG_Z698\: FD1P3DX port map ( +D => RLOL1_CNT_S(0), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(0)); +\GENBLK2.RLOL1_CNT[1]_REG_Z700\: FD1P3DX port map ( +D => RLOL1_CNT_S(1), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(1)); +\GENBLK2.RLOL1_CNT[2]_REG_Z702\: FD1P3DX port map ( +D => RLOL1_CNT_S(2), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(2)); +\GENBLK2.RLOL1_CNT[3]_REG_Z704\: FD1P3DX port map ( +D => RLOL1_CNT_S(3), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(3)); +\GENBLK2.RLOL1_CNT[4]_REG_Z706\: FD1P3DX port map ( +D => RLOL1_CNT_S(4), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(4)); +\GENBLK2.RLOL1_CNT[5]_REG_Z708\: FD1P3DX port map ( +D => RLOL1_CNT_S(5), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(5)); +\GENBLK2.RLOL1_CNT[6]_REG_Z710\: FD1P3DX port map ( +D => RLOL1_CNT_S(6), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(6)); +\GENBLK2.RLOL1_CNT[7]_REG_Z712\: FD1P3DX port map ( +D => RLOL1_CNT_S(7), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(7)); +\GENBLK2.RLOL1_CNT[8]_REG_Z714\: FD1P3DX port map ( +D => RLOL1_CNT_S(8), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(8)); +\GENBLK2.RLOL1_CNT[9]_REG_Z716\: FD1P3DX port map ( +D => RLOL1_CNT_S(9), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(9)); +\GENBLK2.RLOL1_CNT[10]_REG_Z718\: FD1P3DX port map ( +D => RLOL1_CNT_S(10), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(10)); +\GENBLK2.RLOL1_CNT[11]_REG_Z720\: FD1P3DX port map ( +D => RLOL1_CNT_S(11), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(11)); +\GENBLK2.RLOL1_CNT[12]_REG_Z722\: FD1P3DX port map ( +D => RLOL1_CNT_S(12), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(12)); +\GENBLK2.RLOL1_CNT[13]_REG_Z724\: FD1P3DX port map ( +D => RLOL1_CNT_S(13), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(13)); +\GENBLK2.RLOL1_CNT[14]_REG_Z726\: FD1P3DX port map ( +D => RLOL1_CNT_S(14), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(14)); +\GENBLK2.RLOL1_CNT[15]_REG_Z728\: FD1P3DX port map ( +D => RLOL1_CNT_S(15), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(15)); +\GENBLK2.RLOL1_CNT[16]_REG_Z730\: FD1P3DX port map ( +D => RLOL1_CNT_S(16), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(16)); +\GENBLK2.RLOL1_CNT[17]_REG_Z732\: FD1P3DX port map ( +D => RLOL1_CNT_S(17), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(17)); +\GENBLK2.RLOL1_CNT[18]_REG_Z734\: FD1P3DX port map ( +D => RLOL1_CNT_S(18), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(18)); +\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z736\: FD1S3BX port map ( +D => RXSDR_APPD_2, +CK => rxrefclk, +PD => rsl_rst, +Q => RXSDR_APPD); +\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z738\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_1, +SP => UN1_DUAL_OR_RSERD_RST_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_EN); +\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z740\: FD1P3DX port map ( +D => RXR_WT_CNT_S(0), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z742\: FD1P3DX port map ( +D => RXR_WT_CNT_S(1), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(1)); +\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z744\: FD1P3DX port map ( +D => RXR_WT_CNT_S(2), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z746\: FD1P3DX port map ( +D => RXR_WT_CNT_S(3), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(3)); +\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z748\: FD1P3DX port map ( +D => RXR_WT_CNT_S(4), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z750\: FD1P3DX port map ( +D => RXR_WT_CNT_S(5), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(5)); +\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z752\: FD1P3DX port map ( +D => RXR_WT_CNT_S(6), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z754\: FD1P3DX port map ( +D => RXR_WT_CNT_S(7), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(7)); +\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z756\: FD1P3DX port map ( +D => RXR_WT_CNT_S(8), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z758\: FD1P3DX port map ( +D => RXR_WT_CNT_S(9), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(9)); +\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z760\: FD1P3DX port map ( +D => RXR_WT_CNT_S(10), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z762\: FD1P3DX port map ( +D => RXR_WT_CNT_S(11), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(11)); +\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z764\: FD1P3DX port map ( +D => UN1_RUI_RST_DUAL_C_1_1, +SP => UN1_RUI_RST_DUAL_C_1_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXDPR_APPD); +\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z766\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_2, +SP => RXR_WT_CNT9, +CK => rxrefclk, +CD => rsl_rst, +Q => RSL_RX_RDY_9); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z768\: FD1S3DX port map ( +D => N_2124_0, +CK => rxrefclk, +CD => rsl_rst, +Q => RXSR_APPD(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z770\: FD1P3DX port map ( +D => RXPR_APPD_RNO(0), +SP => UN2_RDO_SERDES_RST_DUAL_C_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXPR_APPD(0)); +\GENBLK1.WAITA_PLOL0_REG_Z772\: FD1P3DX port map ( +D => PLOL_FEDGE, +SP => UN1_PLOL0_CNT_TC_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => WAITA_PLOL0); +\GENBLK1.TXS_RST_REG_Z774\: FD1P3DX port map ( +D => UN1_PLOL_CNT_TC, +SP => UN2_PLOL_CNT_TC, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_RST); +\GENBLK1.TXS_CNT[0]_REG_Z776\: FD1S3DX port map ( +D => N_10_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(0)); +\GENBLK1.TXS_CNT[1]_REG_Z778\: FD1S3DX port map ( +D => TXS_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(1)); +\GENBLK1.TXP_RST_REG_Z780\: FD1P3DX port map ( +D => UN9_PLOL0_CNT_TC, +SP => UN1_PLOL0_CNT_TC_1, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_RST); +\GENBLK1.TXP_CNT[0]_REG_Z782\: FD1S3DX port map ( +D => N_11_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(0)); +\GENBLK1.TXP_CNT[1]_REG_Z784\: FD1S3DX port map ( +D => TXP_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(1)); +\GENBLK1.PLOL_CNT[0]_REG_Z786\: FD1S3DX port map ( +D => PLOL_CNT_S(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(0)); +\GENBLK1.PLOL_CNT[1]_REG_Z788\: FD1S3DX port map ( +D => PLOL_CNT_S(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(1)); +\GENBLK1.PLOL_CNT[2]_REG_Z790\: FD1S3DX port map ( +D => PLOL_CNT_S(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(2)); +\GENBLK1.PLOL_CNT[3]_REG_Z792\: FD1S3DX port map ( +D => PLOL_CNT_S(3), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(3)); +\GENBLK1.PLOL_CNT[4]_REG_Z794\: FD1S3DX port map ( +D => PLOL_CNT_S(4), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(4)); +\GENBLK1.PLOL_CNT[5]_REG_Z796\: FD1S3DX port map ( +D => PLOL_CNT_S(5), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(5)); +\GENBLK1.PLOL_CNT[6]_REG_Z798\: FD1S3DX port map ( +D => PLOL_CNT_S(6), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(6)); +\GENBLK1.PLOL_CNT[7]_REG_Z800\: FD1S3DX port map ( +D => PLOL_CNT_S(7), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(7)); +\GENBLK1.PLOL_CNT[8]_REG_Z802\: FD1S3DX port map ( +D => PLOL_CNT_S(8), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(8)); +\GENBLK1.PLOL_CNT[9]_REG_Z804\: FD1S3DX port map ( +D => PLOL_CNT_S(9), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(9)); +\GENBLK1.PLOL_CNT[10]_REG_Z806\: FD1S3DX port map ( +D => PLOL_CNT_S(10), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(10)); +\GENBLK1.PLOL_CNT[11]_REG_Z808\: FD1S3DX port map ( +D => PLOL_CNT_S(11), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(11)); +\GENBLK1.PLOL_CNT[12]_REG_Z810\: FD1S3DX port map ( +D => PLOL_CNT_S(12), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(12)); +\GENBLK1.PLOL_CNT[13]_REG_Z812\: FD1S3DX port map ( +D => PLOL_CNT_S(13), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(13)); +\GENBLK1.PLOL_CNT[14]_REG_Z814\: FD1S3DX port map ( +D => PLOL_CNT_S(14), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(14)); +\GENBLK1.PLOL_CNT[15]_REG_Z816\: FD1S3DX port map ( +D => PLOL_CNT_S(15), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(15)); +\GENBLK1.PLOL_CNT[16]_REG_Z818\: FD1S3DX port map ( +D => PLOL_CNT_S(16), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(16)); +\GENBLK1.PLOL_CNT[17]_REG_Z820\: FD1S3DX port map ( +D => PLOL_CNT_S(17), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(17)); +\GENBLK1.PLOL_CNT[18]_REG_Z822\: FD1S3DX port map ( +D => PLOL_CNT_S(18), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(18)); +\GENBLK1.PLOL_CNT[19]_REG_Z824\: FD1S3DX port map ( +D => PLOL_CNT_S(19), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(19)); +\GENBLK1.PLOL0_CNT[0]_REG_Z826\: FD1S3DX port map ( +D => PLOL0_CNT_3(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(0)); +\GENBLK1.PLOL0_CNT[1]_REG_Z828\: FD1S3DX port map ( +D => PLOL0_CNT_3(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(1)); +\GENBLK1.PLOL0_CNT[2]_REG_Z830\: FD1S3DX port map ( +D => PLOL0_CNT_3(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(2)); +\GENBLK1.PLL_LOL_P3_REG_Z832\: FD1S3DX port map ( +D => PLL_LOL_P2, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P3); +\GENBLK1.PLL_LOL_P2_REG_Z834\: FD1S3DX port map ( +D => PLL_LOL_P1, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P2); +\GENBLK1.PLL_LOL_P1_REG_Z836\: FD1S3DX port map ( +D => pll_lock_i, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P1); +\GENBLK1.GENBLK2.TXSR_APPD_REG_Z838\: FD1S3BX port map ( +D => TXSR_APPD_2, +CK => pll_refclki, +PD => rsl_rst, +Q => TXSR_APPD); +\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z840\: FD1P3DX port map ( +D => UN1_DUAL_OR_SERD_RST_1_1, +SP => UN1_DUAL_OR_SERD_RST_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_EN); +\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z842\: FD1P3DX port map ( +D => TXR_WT_CNT_S(0), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z844\: FD1P3DX port map ( +D => TXR_WT_CNT_S(1), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(1)); +\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z846\: FD1P3DX port map ( +D => TXR_WT_CNT_S(2), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z848\: FD1P3DX port map ( +D => TXR_WT_CNT_S(3), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(3)); +\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z850\: FD1P3DX port map ( +D => TXR_WT_CNT_S(4), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z852\: FD1P3DX port map ( +D => TXR_WT_CNT_S(5), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(5)); +\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z854\: FD1P3DX port map ( +D => TXR_WT_CNT_S(6), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z856\: FD1P3DX port map ( +D => TXR_WT_CNT_S(7), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(7)); +\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z858\: FD1P3DX port map ( +D => TXR_WT_CNT_S(8), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z860\: FD1P3DX port map ( +D => TXR_WT_CNT_S(9), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(9)); +\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z862\: FD1P3DX port map ( +D => TXR_WT_CNT_S(10), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z864\: FD1P3DX port map ( +D => TXR_WT_CNT_S(11), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(11)); +\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z866\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_3_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXDPR_APPD); +\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z868\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_5_1, +SP => UN2_PLOL_FEDGE_5_I, +CK => pll_refclki, +CD => rsl_rst, +Q => RSL_TX_RDY_8); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z870\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_8_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXPR_APPD(0)); +\GENBLK1.TXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXS_CNT(0), +B => TXS_RST, +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => N_10_I); +\GENBLK1.TXS_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => TXS_RST, +D => UN1_PLOL_CNT_TC, +Z => TXS_CNT_RNO(1)); +\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0F2F" +) +port map ( +A => TXPR_APPD(0), +B => PLL_LOL_P2, +C => UN1_DUAL_OR_SERD_RST_1_1, +D => RSL_TX_RDY_8, +Z => UN1_DUAL_OR_SERD_RST_1_I); +\GENBLK2.RXS_RST6\: LUT4 +generic map( + init => X"2020" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => RXS_RST6); +\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RXS_RST, +B => WAIT_CALIB, +C => RLOL1_CNT_TC_1, +D => RLOS_REDGE, +Z => RLOL1_CNTE); +\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS0, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => RLOLS0_CNTE); +\GENBLK1.PLOL_CNT11_I\: LUT4 +generic map( + init => X"0202" +) +port map ( +A => PLL_LOL_P2, +B => UN1_PLOL_CNT_TC, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => \PLOL_CNT_\); +\GENBLK2.RLOLS0_CNT11_I\: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOLS0_CNT11_0, +B => RLOLS0_CNT_TC_1, +C => VCC, +D => VCC, +Z => \RLOLS0_CNT_\); +\GENBLK2.UN1_RXS_CNT_TC\: LUT4 +generic map( + init => X"FEFC" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => UN8_RXS_CNT_TC, +D => RLOL1_CNT_TC_1, +Z => UN1_RXS_CNT_TC); +\GENBLK2.WAIT_CALIB_RNO\: LUT4 +generic map( + init => X"A3A3" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => WAIT_CALIB_RNO); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => UN1_TXSR_APPD, +B => PLL_LOL_P2, +C => RSL_SERDES_RST_DUAL_C_6, +D => RSL_TX_SERDES_RST_C_7, +Z => UN2_PLOL_FEDGE_8_I); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 +generic map( + init => X"FEFF" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => UN3_RX_ALL_WELL_2_1, +C => UN17_RXR_WT_TC, +D => RX_ALL_WELL, +Z => UN1_DUAL_OR_RSERD_RST_2_I); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO_0[0]\: LUT4 +generic map( + init => X"FFFB" +) +port map ( +A => UN1_RXSDR_OR_SR_APPD, +B => UN2_RDO_SERDES_RST_DUAL_C_1_1, +C => RSL_RX_SERDES_RST_C_5, +D => RSL_SERDES_RST_DUAL_C_6, +Z => UN2_RDO_SERDES_RST_DUAL_C_2_I); +\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => UN2_PLOL_CNT_TC); +\GENBLK1.GENBLK2.TXR_WT_EN_RNICEBT\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => TXR_WT_EN, +B => UN18_TXR_WT_TC, +C => TX_ANY_RST, +D => VCC, +Z => TXR_WT_CNTE); +\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => UN1_RLOS_FEDGE_1); +\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS06, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => UN1_RLOLS0_CNT_TC); +\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => rst_dual_c, +Z => UN2_PLOL_FEDGE_3_I); +\GENBLK1.TXP_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXP_CNT(0), +B => TXP_RST, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => N_11_I); +UN2_PLOL_FEDGE_5_1_Z890: LUT4 +generic map( + init => X"1111" +) +port map ( +A => PLL_LOL_P2, +B => TX_ANY_RST, +C => VCC, +D => VCC, +Z => UN2_PLOL_FEDGE_5_1); +UN1_DUAL_OR_SERD_RST_1_1_Z891: LUT4 +generic map( + init => X"0101" +) +port map ( +A => UN18_TXR_WT_TC, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => UN1_DUAL_OR_SERD_RST_1_1); +\GENBLK1.TXP_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => TXP_RST, +D => UN9_PLOL0_CNT_TC, +Z => TXP_CNT_RNO(1)); +RLOLS0_CNT_TC_1_Z893: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOLS0_CNT_TC_1_10, +B => RLOLS0_CNT_TC_1_11, +C => RLOLS0_CNT_TC_1_12, +D => RLOLS0_CNT_TC_1_13, +Z => RLOLS0_CNT_TC_1); +\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => UN1_PLOL_CNT_TC_11, +B => UN1_PLOL_CNT_TC_12, +C => UN1_PLOL_CNT_TC_13, +D => UN1_PLOL_CNT_TC_14, +Z => UN1_PLOL_CNT_TC); +RLOL1_CNT_TC_1_Z895: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL1_CNT_TC_1_11, +B => RLOL1_CNT_TC_1_12, +C => RLOL1_CNT_TC_1_13, +D => RLOL1_CNT_TC_1_14, +Z => RLOL1_CNT_TC_1); +\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOL_DB_CNT(0), +B => UN1_RLOL_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOL_DB_CNT_AXB_0); +\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOS_DB_CNT(0), +B => UN1_RLOS_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOS_DB_CNT_AXB_0); +\GENBLK1.WAITA_PLOL0_RNO\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1_I); +\GENBLK1.GENBLK2.MFOR[0].UN1_TXSR_APPD\: LUT4 +generic map( + init => X"C8C8" +) +port map ( +A => TXDPR_APPD, +B => TXSR_APPD_4, +C => RSL_TX_PCS_RST_C_4, +D => VCC, +Z => UN1_TXSR_APPD); +\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => TXSR_APPD_4, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => TXSR_APPD_2); +\GENBLK1.PLOL0_CNT_3[0]\: LUT4 +generic map( + init => X"1414" +) +port map ( +A => PLOL0_CNT9, +B => PLOL0_CNT(0), +C => WAITA_PLOL0, +D => VCC, +Z => PLOL0_CNT_3(0)); +\GENBLK1.PLOL0_CNT_3[2]\: LUT4 +generic map( + init => X"1320" +) +port map ( +A => CO0_2, +B => PLOL0_CNT9, +C => PLOL0_CNT(1), +D => PLOL0_CNT(2), +Z => PLOL0_CNT_3(2)); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN18_TXR_WT_TC_6, +B => UN18_TXR_WT_TC_7, +C => UN18_TXR_WT_TC_8, +D => VCC, +Z => UN18_TXR_WT_TC); +UN2_PLOL_FEDGE_2_Z904: LUT4 +generic map( + init => X"0101" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_6, +C => RSL_TX_SERDES_RST_C_7, +D => VCC, +Z => UN2_PLOL_FEDGE_2); +TX_ANY_RST_Z905: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_6, +B => RSL_TX_PCS_RST_C_4, +C => RSL_TX_SERDES_RST_C_7, +D => rst_dual_c, +Z => TX_ANY_RST); +RX_ANY_RST_Z906: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => DUAL_OR_RSERD_RST, +B => RSL_RX_PCS_RST_C_10, +C => rst_dual_c, +D => VCC, +Z => RX_ANY_RST); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN17_RXR_WT_TC_6, +B => UN17_RXR_WT_TC_7, +C => UN17_RXR_WT_TC_8, +D => VCC, +Z => UN17_RXR_WT_TC); +\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z908\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_BM(0)); +\UN1_RLOL_DB_CNT_ZERO[0]_Z909\: PFUMX port map ( +ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0), +C0 => RLOL_P2, +Z => UN1_RLOL_DB_CNT_ZERO(0)); +\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z910\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_BM(0)); +\UN1_RLOS_DB_CNT_ZERO[0]_Z911\: PFUMX port map ( +ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0), +C0 => RLOS_P2, +Z => UN1_RLOS_DB_CNT_ZERO(0)); +\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_MAX); +\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_MAX); +\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1); +\GENBLK2.WAITA_RLOLS06\: LUT4 +generic map( + init => X"0504" +) +port map ( +A => RLOL_DB, +B => RLOL_DB_P1, +C => RLOS_DB, +D => RLOS_DB_P1, +Z => WAITA_RLOLS06); +\RXS_CNT_3[1]_Z916\: LUT4 +generic map( + init => X"6464" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => RXS_RST, +D => VCC, +Z => RXS_CNT_3(1)); +\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD\: LUT4 +generic map( + init => X"3200" +) +port map ( +A => RXSR_APPD(0), +B => RX_ALL_WELL, +C => RXSDR_APPD_4, +D => RSL_RX_PCS_RST_C_10, +Z => UN1_RXSDR_OR_SR_APPD); +RLOLS0_CNT_TC_1_13_Z918: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RLOLS0_CNT(16), +B => RLOLS0_CNT(17), +C => RLOLS0_CNT_TC_1_9, +D => VCC, +Z => RLOLS0_CNT_TC_1_13); +\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 +generic map( + init => X"0100" +) +port map ( +A => PLOL_CNT(4), +B => PLOL_CNT(5), +C => PLOL_CNT(18), +D => UN1_PLOL_CNT_TC_10, +Z => UN1_PLOL_CNT_TC_14); +RLOL1_CNT_TC_1_14_Z920: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(11), +B => RLOL1_CNT(12), +C => RLOL1_CNT(18), +D => RLOL1_CNT_TC_1_10, +Z => RLOL1_CNT_TC_1_14); +\GENBLK2.GENBLK3.UN3_RX_ALL_WELL_2_1\: LUT4 +generic map( + init => X"0E0E" +) +port map ( +A => RXPR_APPD(0), +B => RXDPR_APPD, +C => RSL_RX_RDY_9, +D => VCC, +Z => UN3_RX_ALL_WELL_2_1); +RDO_SERDES_RST_DUAL_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => rsl_rst, +C => serdes_rst_dual_c, +D => VCC, +Z => RSL_SERDES_RST_DUAL_C_6); +RDO_TX_SERDES_RST_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXS_RST, +C => tx_serdes_rst_c, +D => VCC, +Z => RSL_TX_SERDES_RST_C_7); +\RDO_TX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXP_RST, +C => tx_pcs_rst_c, +D => VCC, +Z => RSL_TX_PCS_RST_C_4); +\RDO_RX_SERDES_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXS_RST, +C => rx_serdes_rst_c, +D => VCC, +Z => RSL_RX_SERDES_RST_C_5); +\RDO_RX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXP_RST2, +C => rx_pcs_rst_c, +D => VCC, +Z => RSL_RX_PCS_RST_C_10); +\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 +generic map( + init => X"1010" +) +port map ( +A => PLOL0_CNT(0), +B => PLOL0_CNT(1), +C => PLOL0_CNT(2), +D => VCC, +Z => UN9_PLOL0_CNT_TC); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RXR_WT_CNT(0), +B => RXR_WT_CNT(8), +C => RXR_WT_CNT(9), +D => RXR_WT_CNT(11), +Z => UN17_RXR_WT_TC_6); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RXR_WT_CNT(3), +B => RXR_WT_CNT(4), +C => RXR_WT_CNT(5), +D => RXR_WT_CNT(7), +Z => UN17_RXR_WT_TC_7); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RXR_WT_CNT(1), +B => RXR_WT_CNT(2), +C => RXR_WT_CNT(6), +D => RXR_WT_CNT(10), +Z => UN17_RXR_WT_TC_8); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => TXR_WT_CNT(0), +B => TXR_WT_CNT(8), +C => TXR_WT_CNT(9), +D => TXR_WT_CNT(11), +Z => UN18_TXR_WT_TC_6); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => TXR_WT_CNT(3), +B => TXR_WT_CNT(4), +C => TXR_WT_CNT(5), +D => TXR_WT_CNT(7), +Z => UN18_TXR_WT_TC_7); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => TXR_WT_CNT(1), +B => TXR_WT_CNT(2), +C => TXR_WT_CNT(6), +D => TXR_WT_CNT(10), +Z => UN18_TXR_WT_TC_8); +RLOLS0_CNT_TC_1_9_Z934: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(1), +B => RLOLS0_CNT(2), +C => RLOLS0_CNT(3), +D => RLOLS0_CNT(4), +Z => RLOLS0_CNT_TC_1_9); +RLOLS0_CNT_TC_1_10_Z935: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RLOLS0_CNT(0), +B => RLOLS0_CNT(10), +C => RLOLS0_CNT(14), +D => RLOLS0_CNT(15), +Z => RLOLS0_CNT_TC_1_10); +RLOLS0_CNT_TC_1_11_Z936: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(9), +B => RLOLS0_CNT(11), +C => RLOLS0_CNT(12), +D => RLOLS0_CNT(13), +Z => RLOLS0_CNT_TC_1_11); +RLOLS0_CNT_TC_1_12_Z937: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(5), +B => RLOLS0_CNT(6), +C => RLOLS0_CNT(7), +D => RLOLS0_CNT(8), +Z => RLOLS0_CNT_TC_1_12); +\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 +generic map( + init => X"1000" +) +port map ( +A => PLOL_CNT(2), +B => PLOL_CNT(3), +C => PLOL_CNT(17), +D => PLOL_CNT(19), +Z => UN1_PLOL_CNT_TC_10); +\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(13), +B => PLOL_CNT(14), +C => PLOL_CNT(15), +D => PLOL_CNT(16), +Z => UN1_PLOL_CNT_TC_11); +\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(7), +B => PLOL_CNT(8), +C => PLOL_CNT(9), +D => PLOL_CNT(11), +Z => UN1_PLOL_CNT_TC_12); +\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 +generic map( + init => X"0008" +) +port map ( +A => PLOL_CNT(1), +B => PLOL_CNT(6), +C => PLOL_CNT(10), +D => PLOL_CNT(12), +Z => UN1_PLOL_CNT_TC_13); +RLOL1_CNT_TC_1_10_Z942: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(7), +B => RLOL1_CNT(8), +C => RLOL1_CNT(9), +D => RLOL1_CNT(10), +Z => RLOL1_CNT_TC_1_10); +RLOL1_CNT_TC_1_11_Z943: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(3), +B => RLOL1_CNT(4), +C => RLOL1_CNT(5), +D => RLOL1_CNT(6), +Z => RLOL1_CNT_TC_1_11); +RLOL1_CNT_TC_1_12_Z944: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(0), +B => RLOL1_CNT(1), +C => RLOL1_CNT(2), +D => RLOL1_CNT(17), +Z => RLOL1_CNT_TC_1_12); +RLOL1_CNT_TC_1_13_Z945: LUT4 +generic map( + init => X"0040" +) +port map ( +A => RLOL1_CNT(13), +B => RLOL1_CNT(14), +C => RLOL1_CNT(15), +D => RLOL1_CNT(16), +Z => RLOL1_CNT_TC_1_13); +\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RXSDR_APPD_4, +B => serdes_rst_dual_c, +C => VCC, +D => VCC, +Z => RXSDR_APPD_2); +RX_ALL_WELL_Z947: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => VCC, +D => VCC, +Z => RX_ALL_WELL); +\GENBLK2.UN8_RXS_CNT_TC\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => VCC, +D => VCC, +Z => UN8_RXS_CNT_TC); +PLOL_FEDGE_Z949: LUT4 +generic map( + init => X"4444" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => VCC, +D => VCC, +Z => PLOL_FEDGE); +RLOS_REDGE_Z950: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => VCC, +D => VCC, +Z => RLOS_REDGE); +\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PLOL0_CNT(0), +B => WAITA_PLOL0, +C => VCC, +D => VCC, +Z => CO0_2); +UN2_RDO_SERDES_RST_DUAL_C_1_1_Z952: LUT4 +generic map( + init => X"1111" +) +port map ( +A => rx_cdr_lol_s, +B => rx_los_low_s, +C => VCC, +D => VCC, +Z => UN2_RDO_SERDES_RST_DUAL_C_1_1); +\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z953\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_AM(0)); +\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z954\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_AM(0)); +DUAL_OR_RSERD_RST_Z955: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RSL_RX_SERDES_RST_C_5, +B => serdes_rst_dual_c, +C => rsl_rst, +D => rsl_disable, +Z => DUAL_OR_RSERD_RST); +\GENBLK1.PLOL0_CNT9\: LUT4 +generic map( + init => X"AAAE" +) +port map ( +A => PLL_LOL_P2, +B => PLOL0_CNT(2), +C => PLOL0_CNT(1), +D => PLOL0_CNT(0), +Z => PLOL0_CNT9); +\GENBLK2.RLOLS0_CNT11_0\: LUT4 +generic map( + init => X"4F44" +) +port map ( +A => RLOL_DB_P1, +B => RLOL_DB, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => RLOLS0_CNT11_0); +\GENBLK1.GENBLK2.TXR_WT_CNT9_I\: LUT4 +generic map( + init => X"1555" +) +port map ( +A => TX_ANY_RST, +B => UN18_TXR_WT_TC_8, +C => UN18_TXR_WT_TC_7, +D => UN18_TXR_WT_TC_6, +Z => \TXR_WT_CNT_\); +\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOL1_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_7, +COUT => RLOL1_CNT_CRY(0), +S0 => RLOL1_CNT_CRY_0_S0(0), +S1 => RLOL1_CNT_S(0)); +\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(0), +COUT => RLOL1_CNT_CRY(2), +S0 => RLOL1_CNT_S(1), +S1 => RLOL1_CNT_S(2)); +\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(2), +COUT => RLOL1_CNT_CRY(4), +S0 => RLOL1_CNT_S(3), +S1 => RLOL1_CNT_S(4)); +\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(4), +COUT => RLOL1_CNT_CRY(6), +S0 => RLOL1_CNT_S(5), +S1 => RLOL1_CNT_S(6)); +\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(6), +COUT => RLOL1_CNT_CRY(8), +S0 => RLOL1_CNT_S(7), +S1 => RLOL1_CNT_S(8)); +\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(8), +COUT => RLOL1_CNT_CRY(10), +S0 => RLOL1_CNT_S(9), +S1 => RLOL1_CNT_S(10)); +\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(10), +COUT => RLOL1_CNT_CRY(12), +S0 => RLOL1_CNT_S(11), +S1 => RLOL1_CNT_S(12)); +\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(12), +COUT => RLOL1_CNT_CRY(14), +S0 => RLOL1_CNT_S(13), +S1 => RLOL1_CNT_S(14)); +\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(14), +COUT => RLOL1_CNT_CRY(16), +S0 => RLOL1_CNT_S(15), +S1 => RLOL1_CNT_S(16)); +\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"800a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(16), +COUT => RLOL1_CNT_CRY_0_COUT(17), +S0 => RLOL1_CNT_S(17), +S1 => RLOL1_CNT_S(18)); +\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOLS0_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_6, +COUT => RLOLS0_CNT_CRY(0), +S0 => RLOLS0_CNT_CRY_0_S0(0), +S1 => RLOLS0_CNT_S(0)); +\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(0), +COUT => RLOLS0_CNT_CRY(2), +S0 => RLOLS0_CNT_S(1), +S1 => RLOLS0_CNT_S(2)); +\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(2), +COUT => RLOLS0_CNT_CRY(4), +S0 => RLOLS0_CNT_S(3), +S1 => RLOLS0_CNT_S(4)); +\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(4), +COUT => RLOLS0_CNT_CRY(6), +S0 => RLOLS0_CNT_S(5), +S1 => RLOLS0_CNT_S(6)); +\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(6), +COUT => RLOLS0_CNT_CRY(8), +S0 => RLOLS0_CNT_S(7), +S1 => RLOLS0_CNT_S(8)); +\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(8), +COUT => RLOLS0_CNT_CRY(10), +S0 => RLOLS0_CNT_S(9), +S1 => RLOLS0_CNT_S(10)); +\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(10), +COUT => RLOLS0_CNT_CRY(12), +S0 => RLOLS0_CNT_S(11), +S1 => RLOLS0_CNT_S(12)); +\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(12), +COUT => RLOLS0_CNT_CRY(14), +S0 => RLOLS0_CNT_S(13), +S1 => RLOLS0_CNT_S(14)); +\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(14), +COUT => RLOLS0_CNT_CRY(16), +S0 => RLOLS0_CNT_S(15), +S1 => RLOLS0_CNT_S(16)); +\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(16), +COUT => RLOLS0_CNT_S_0_COUT(17), +S0 => RLOLS0_CNT_S(17), +S1 => RLOLS0_CNT_S_0_S1(17)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \TXR_WT_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => TXR_WT_CNT_CRY(0), +S0 => TXR_WT_CNT_CRY_0_S0(0), +S1 => TXR_WT_CNT_S(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(0), +COUT => TXR_WT_CNT_CRY(2), +S0 => TXR_WT_CNT_S(1), +S1 => TXR_WT_CNT_S(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(2), +COUT => TXR_WT_CNT_CRY(4), +S0 => TXR_WT_CNT_S(3), +S1 => TXR_WT_CNT_S(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(4), +COUT => TXR_WT_CNT_CRY(6), +S0 => TXR_WT_CNT_S(5), +S1 => TXR_WT_CNT_S(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(6), +COUT => TXR_WT_CNT_CRY(8), +S0 => TXR_WT_CNT_S(7), +S1 => TXR_WT_CNT_S(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(8), +COUT => TXR_WT_CNT_CRY(10), +S0 => TXR_WT_CNT_S(9), +S1 => TXR_WT_CNT_S(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(10), +COUT => TXR_WT_CNT_S_0_COUT(11), +S0 => TXR_WT_CNT_S(11), +S1 => TXR_WT_CNT_S_0_S1(11)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => RXR_WT_CNT9, +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RXR_WT_CNT_CRY(0), +S0 => RXR_WT_CNT_CRY_0_S0(0), +S1 => RXR_WT_CNT_S(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(0), +COUT => RXR_WT_CNT_CRY(2), +S0 => RXR_WT_CNT_S(1), +S1 => RXR_WT_CNT_S(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(2), +COUT => RXR_WT_CNT_CRY(4), +S0 => RXR_WT_CNT_S(3), +S1 => RXR_WT_CNT_S(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(4), +COUT => RXR_WT_CNT_CRY(6), +S0 => RXR_WT_CNT_S(5), +S1 => RXR_WT_CNT_S(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(6), +COUT => RXR_WT_CNT_CRY(8), +S0 => RXR_WT_CNT_S(7), +S1 => RXR_WT_CNT_S(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(8), +COUT => RXR_WT_CNT_CRY(10), +S0 => RXR_WT_CNT_S(9), +S1 => RXR_WT_CNT_S(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(10), +COUT => RXR_WT_CNT_S_0_COUT(11), +S0 => RXR_WT_CNT_S(11), +S1 => RXR_WT_CNT_S_0_S1(11)); +\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \PLOL_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => PLOL_CNT_CRY(0), +S0 => PLOL_CNT_CRY_0_S0(0), +S1 => PLOL_CNT_S(0)); +\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(0), +COUT => PLOL_CNT_CRY(2), +S0 => PLOL_CNT_S(1), +S1 => PLOL_CNT_S(2)); +\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(2), +COUT => PLOL_CNT_CRY(4), +S0 => PLOL_CNT_S(3), +S1 => PLOL_CNT_S(4)); +\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(4), +COUT => PLOL_CNT_CRY(6), +S0 => PLOL_CNT_S(5), +S1 => PLOL_CNT_S(6)); +\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(6), +COUT => PLOL_CNT_CRY(8), +S0 => PLOL_CNT_S(7), +S1 => PLOL_CNT_S(8)); +\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(8), +COUT => PLOL_CNT_CRY(10), +S0 => PLOL_CNT_S(9), +S1 => PLOL_CNT_S(10)); +\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(10), +COUT => PLOL_CNT_CRY(12), +S0 => PLOL_CNT_S(11), +S1 => PLOL_CNT_S(12)); +\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(12), +COUT => PLOL_CNT_CRY(14), +S0 => PLOL_CNT_S(13), +S1 => PLOL_CNT_S(14)); +\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(14), +COUT => PLOL_CNT_CRY(16), +S0 => PLOL_CNT_S(15), +S1 => PLOL_CNT_S(16)); +\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(16), +COUT => PLOL_CNT_CRY(18), +S0 => PLOL_CNT_S(17), +S1 => PLOL_CNT_S(18)); +\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(19), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(18), +COUT => PLOL_CNT_S_0_COUT(19), +S0 => PLOL_CNT_S(19), +S1 => PLOL_CNT_S_0_S1(19)); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOS_DB_CNT(0), +B1 => UN1_RLOS_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => RLOS_DB_CNT_CRY_0, +S0 => RLOS_DB_CNT_CRY_0_0_S0, +S1 => RLOS_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOS_DB_CNT_ZERO(0), +B0 => RLOS_P2, +C0 => RLOS_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOS_DB_CNT_ZERO(0), +B1 => RLOS_P2, +C1 => RLOS_DB_CNT(2), +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_0, +COUT => RLOS_DB_CNT_CRY_2, +S0 => RLOS_DB_CNT_CRY_1_0_S0, +S1 => RLOS_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOS_DB_CNT(3), +B0 => RLOS_P2, +C0 => UN1_RLOS_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_2, +COUT => RLOS_DB_CNT_S_3_0_COUT, +S0 => RLOS_DB_CNT_S_3_0_S0, +S1 => RLOS_DB_CNT_S_3_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOL_DB_CNT(0), +B1 => UN1_RLOL_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => RLOL_DB_CNT_CRY_0, +S0 => RLOL_DB_CNT_CRY_0_0_S0, +S1 => RLOL_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOL_DB_CNT_ZERO(0), +B0 => RLOL_P2, +C0 => RLOL_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOL_DB_CNT_ZERO(0), +B1 => RLOL_P2, +C1 => RLOL_DB_CNT(2), +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_0, +COUT => RLOL_DB_CNT_CRY_2, +S0 => RLOL_DB_CNT_CRY_1_0_S0, +S1 => RLOL_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOL_DB_CNT(3), +B0 => RLOL_P2, +C0 => UN1_RLOL_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_2, +COUT => RLOL_DB_CNT_S_3_0_COUT, +S0 => RLOL_DB_CNT_S_3_0_S0, +S1 => RLOL_DB_CNT_S_3_0_S1); +RXSDR_APPD_4 <= RXSDR_APPD; +TXSR_APPD_4 <= TXSR_APPD; +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_4; +rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_5; +rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_6; +rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_7; +rsl_tx_rdy <= RSL_TX_RDY_8; +rsl_rx_rdy <= RSL_RX_RDY_9; +rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_10; +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5sll_core_Z1_layer1 is +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic); +end sgmii_ecp5sll_core_Z1_layer1; + +architecture beh of sgmii_ecp5sll_core_Z1_layer1 is +signal PHB_CNT : std_logic_vector(2 downto 0); +signal PHB_CNT_I : std_logic_vector(2 downto 0); +signal RCOUNT : std_logic_vector(15 downto 0); +signal PCOUNT : std_logic_vector(21 downto 0); +signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0); +signal SLL_STATE : std_logic_vector(1 downto 0); +signal SLL_STATE_QN : std_logic_vector(1 downto 0); +signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0); +signal RCOUNT_S : std_logic_vector(15 downto 0); +signal RCOUNT_QN : std_logic_vector(15 downto 0); +signal PHB_CNT_QN : std_logic_vector(2 downto 0); +signal PHB_CNT_RNO : std_logic_vector(2 downto 1); +signal PCOUNT_S : std_logic_vector(21 downto 0); +signal PCOUNT_QN : std_logic_vector(21 downto 0); +signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0); +signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2); +signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2); +signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0); +signal PCOUNT_CRY : std_logic_vector(20 downto 0); +signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21); +signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21); +signal RCOUNT_CRY : std_logic_vector(14 downto 0); +signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15); +signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15); +signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0); +signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7); +signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7); +signal PLL_LOCK : std_logic ; +signal RTC_CTRL4_0_A3_1 : std_logic ; +signal UN13_LOCK_20 : std_logic ; +signal PPUL_SYNC_P2 : std_logic ; +signal PPUL_SYNC_P1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ; +signal UN13_LOCK_19 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ; +signal UN13_LOCK_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ; +signal UN13_LOCK_17 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_RNO : std_logic ; +signal UN13_LOCK_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_16 : std_logic ; +signal UN13_LOCK_15 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ; +signal UN13_LOCK_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ; +signal UN13_LOCK_13 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ; +signal UN13_LOCK_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ; +signal UN13_LOCK_11 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ; +signal UN13_LOCK_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ; +signal UN13_LOCK_9 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ; +signal UN13_LOCK_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ; +signal UN13_LOCK_7 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ; +signal UN13_LOCK_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ; +signal UN13_LOCK_5 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ; +signal UN13_LOCK_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ; +signal UN13_LOCK_3 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ; +signal UN13_LOCK_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ; +signal UN13_LOCK_1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ; +signal UN13_LOCK_21 : std_logic ; +signal PPUL_SYNC_P3 : std_logic ; +signal N_7 : std_logic ; +signal UN13_LOCK_0 : std_logic ; +signal RTC_CTRL4 : std_logic ; +signal RTC_CTRL : std_logic ; +signal VCC : std_logic ; +signal N_2085_0 : std_logic ; +signal UNLOCK_5 : std_logic ; +signal UNLOCK_1_SQMUXA_I : std_logic ; +signal UNLOCK : std_logic ; +signal UNLOCK_QN : std_logic ; +signal N_95_I : std_logic ; +signal N_97_I : std_logic ; +signal RTC_PUL : std_logic ; +signal RTC_PUL_P1 : std_logic ; +signal RTC_PUL_P1_QN : std_logic ; +signal RTC_PUL5 : std_logic ; +signal RTC_PUL_QN : std_logic ; +signal RTC_CTRL_QN : std_logic ; +signal RSTAT_PCLK_2 : std_logic ; +signal RSTAT_PCLK : std_logic ; +signal RSTAT_PCLK_QN : std_logic ; +signal RHB_SYNC_P1 : std_logic ; +signal RHB_SYNC_P2 : std_logic ; +signal RHB_SYNC_P2_QN : std_logic ; +signal RHB_SYNC : std_logic ; +signal RHB_SYNC_P1_QN : std_logic ; +signal PPUL_SYNC_P3_QN : std_logic ; +signal PPUL_SYNC_P2_QN : std_logic ; +signal PPUL_SYNC : std_logic ; +signal PPUL_SYNC_P1_QN : std_logic ; +signal N_53_I : std_logic ; +signal PLL_LOCK_QN : std_logic ; +signal PHB : std_logic ; +signal PHB_QN : std_logic ; +signal PDIFF_SYNC : std_logic ; +signal PDIFF_SYNC_P1 : std_logic ; +signal PDIFF_SYNC_P1_QN : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ; +signal LOCK_5 : std_logic ; +signal LOCK_1_SQMUXA_I : std_logic ; +signal LOCK : std_logic ; +signal LOCK_QN : std_logic ; +signal N_98 : std_logic ; +signal RTC_PUL5_0_O3 : std_logic ; +signal RTC_PUL5_0_A3_6 : std_logic ; +signal RTC_PUL5_0_A3_7 : std_logic ; +signal UN1_RCOUNT_1_0_A3 : std_logic ; +signal RHB_WAIT_CNT12 : std_logic ; +signal UN1_RHB_WAIT_CNT_4 : std_logic ; +signal UN1_RHB_WAIT_CNT_5 : std_logic ; +signal N_99 : std_logic ; +signal RTC_CTRL4_0_A3_12_4 : std_logic ; +signal RTC_CTRL4_0_A3_12_5 : std_logic ; +signal RTC_CTRL4_10 : std_logic ; +signal UN1_RCOUNT_1_0_A3_1 : std_logic ; +signal N_6 : std_logic ; +signal RTC_PUL5_0_A3_5 : std_logic ; +signal N_8 : std_logic ; +signal UN13_UNLOCK_CRY_21 : std_logic ; +signal UN13_LOCK_CRY_21_I : std_logic ; +signal \RHB_WAIT_CNT_\ : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ; +signal UN13_LOCK_CRY_0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S1 : std_logic ; +signal UN13_LOCK_CRY_2 : std_logic ; +signal UN13_LOCK_CRY_1_0_S0 : std_logic ; +signal UN13_LOCK_CRY_1_0_S1 : std_logic ; +signal UN13_LOCK_CRY_4 : std_logic ; +signal UN13_LOCK_CRY_3_0_S0 : std_logic ; +signal UN13_LOCK_CRY_3_0_S1 : std_logic ; +signal UN13_LOCK_CRY_6 : std_logic ; +signal UN13_LOCK_CRY_5_0_S0 : std_logic ; +signal UN13_LOCK_CRY_5_0_S1 : std_logic ; +signal UN13_LOCK_CRY_8 : std_logic ; +signal UN13_LOCK_CRY_7_0_S0 : std_logic ; +signal UN13_LOCK_CRY_7_0_S1 : std_logic ; +signal UN13_LOCK_CRY_10 : std_logic ; +signal UN13_LOCK_CRY_9_0_S0 : std_logic ; +signal UN13_LOCK_CRY_9_0_S1 : std_logic ; +signal UN13_LOCK_CRY_12 : std_logic ; +signal UN13_LOCK_CRY_11_0_S0 : std_logic ; +signal UN13_LOCK_CRY_11_0_S1 : std_logic ; +signal UN13_LOCK_CRY_14 : std_logic ; +signal UN13_LOCK_CRY_13_0_S0 : std_logic ; +signal UN13_LOCK_CRY_13_0_S1 : std_logic ; +signal UN13_LOCK_CRY_16 : std_logic ; +signal UN13_LOCK_CRY_15_0_S0 : std_logic ; +signal UN13_LOCK_CRY_15_0_S1 : std_logic ; +signal UN13_LOCK_CRY_18 : std_logic ; +signal UN13_LOCK_CRY_17_0_S0 : std_logic ; +signal UN13_LOCK_CRY_17_0_S1 : std_logic ; +signal UN13_LOCK_CRY_20 : std_logic ; +signal UN13_LOCK_CRY_19_0_S0 : std_logic ; +signal UN13_LOCK_CRY_19_0_S1 : std_logic ; +signal UN13_LOCK_CRY_21_0_COUT : std_logic ; +signal UN13_LOCK_CRY_21_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_2 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_4 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_6 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_8 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_10 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_12 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_14 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_16 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_18 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_20 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ; +signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ; +signal N_21 : std_logic ; +signal N_20 : std_logic ; +signal N_19 : std_logic ; +signal N_18 : std_logic ; +signal N_14 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_9 : std_logic ; +component sync_0s +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +component sync_0s_6 +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic ); +end component; +component sync_0s_0 +port( +ppul_sync : in std_logic; +pdiff_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +begin +PHB_RNO: INV port map ( +A => PHB_CNT(2), +Z => PHB_CNT_I(2)); +\PHB_CNT_RNO[0]\: INV port map ( +A => PHB_CNT(0), +Z => PHB_CNT_I(0)); +PLL_LOCK_RNI6JK9: INV port map ( +A => PLL_LOCK, +Z => pll_lock_i); +RTC_CTRL4_0_A3_RNO: LUT4 +generic map( + init => X"2000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => RTC_CTRL4_0_A3_1); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_20, +B => PCOUNT(20), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_20); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_19, +B => PCOUNT(19), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_19); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_18, +B => PCOUNT(18), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_18); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_Z477: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_17, +B => PCOUNT(17), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_16, +B => PCOUNT(16), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_16); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_15, +B => PCOUNT(15), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_15); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_14, +B => PCOUNT(14), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_14); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_13, +B => PCOUNT(13), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_13); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_12, +B => PCOUNT(12), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_12); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_11, +B => PCOUNT(11), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_11); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_10, +B => PCOUNT(10), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_10); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_9, +B => PCOUNT(9), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_9); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_8, +B => PCOUNT(8), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_8); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_7, +B => PCOUNT(7), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_7); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_6, +B => PCOUNT(6), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_6); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_5, +B => PCOUNT(5), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_5); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_4, +B => PCOUNT(4), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_4); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_3, +B => PCOUNT(3), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_3); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_2, +B => PCOUNT(2), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_2); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_1, +B => PCOUNT(1), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_1); +PPUL_SYNC_P3_RNIU65C: LUT4 +generic map( + init => X"2F20" +) +port map ( +A => UN13_LOCK_21, +B => PPUL_SYNC_P3, +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => N_7); +\PCOUNT_DIFF_RNO[0]\: LUT4 +generic map( + init => X"FD20" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => PCOUNT(0), +D => UN13_LOCK_0, +Z => UN1_PCOUNT_DIFF_I(0)); +RTC_CTRL_0: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RTC_CTRL4, +B => RTC_CTRL, +C => VCC, +D => VCC, +Z => N_2085_0); +UNLOCK_REG_Z498: FD1P3DX port map ( +D => UNLOCK_5, +SP => UNLOCK_1_SQMUXA_I, +CK => pll_refclki, +CD => sli_rst, +Q => UNLOCK); +\SLL_STATE[0]_REG_Z500\: FD1S3DX port map ( +D => N_95_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(0)); +\SLL_STATE[1]_REG_Z502\: FD1S3DX port map ( +D => N_97_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(1)); +RTC_PUL_P1_REG_Z504: FD1S3DX port map ( +D => RTC_PUL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL_P1); +RTC_PUL_REG_Z506: FD1P3DX port map ( +D => RTC_PUL5, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL); +RTC_CTRL_REG_Z508: FD1S3DX port map ( +D => N_2085_0, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_CTRL); +RSTAT_PCLK_REG_Z510: FD1P3DX port map ( +D => RSTAT_PCLK_2, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RSTAT_PCLK); +\RHB_WAIT_CNT[0]_REG_Z512\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(0), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(0)); +\RHB_WAIT_CNT[1]_REG_Z514\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(1), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(1)); +\RHB_WAIT_CNT[2]_REG_Z516\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(2), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(2)); +\RHB_WAIT_CNT[3]_REG_Z518\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(3), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(3)); +\RHB_WAIT_CNT[4]_REG_Z520\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(4), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(4)); +\RHB_WAIT_CNT[5]_REG_Z522\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(5), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(5)); +\RHB_WAIT_CNT[6]_REG_Z524\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(6), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(6)); +\RHB_WAIT_CNT[7]_REG_Z526\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(7), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(7)); +RHB_SYNC_P2_REG_Z528: FD1S3DX port map ( +D => RHB_SYNC_P1, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P2); +RHB_SYNC_P1_REG_Z530: FD1S3DX port map ( +D => RHB_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P1); +\RCOUNT[0]_REG_Z532\: FD1S3DX port map ( +D => RCOUNT_S(0), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(0)); +\RCOUNT[1]_REG_Z534\: FD1S3DX port map ( +D => RCOUNT_S(1), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(1)); +\RCOUNT[2]_REG_Z536\: FD1S3DX port map ( +D => RCOUNT_S(2), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(2)); +\RCOUNT[3]_REG_Z538\: FD1S3DX port map ( +D => RCOUNT_S(3), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(3)); +\RCOUNT[4]_REG_Z540\: FD1S3DX port map ( +D => RCOUNT_S(4), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(4)); +\RCOUNT[5]_REG_Z542\: FD1S3DX port map ( +D => RCOUNT_S(5), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(5)); +\RCOUNT[6]_REG_Z544\: FD1S3DX port map ( +D => RCOUNT_S(6), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(6)); +\RCOUNT[7]_REG_Z546\: FD1S3DX port map ( +D => RCOUNT_S(7), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(7)); +\RCOUNT[8]_REG_Z548\: FD1S3DX port map ( +D => RCOUNT_S(8), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(8)); +\RCOUNT[9]_REG_Z550\: FD1S3DX port map ( +D => RCOUNT_S(9), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(9)); +\RCOUNT[10]_REG_Z552\: FD1S3DX port map ( +D => RCOUNT_S(10), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(10)); +\RCOUNT[11]_REG_Z554\: FD1S3DX port map ( +D => RCOUNT_S(11), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(11)); +\RCOUNT[12]_REG_Z556\: FD1S3DX port map ( +D => RCOUNT_S(12), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(12)); +\RCOUNT[13]_REG_Z558\: FD1S3DX port map ( +D => RCOUNT_S(13), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(13)); +\RCOUNT[14]_REG_Z560\: FD1S3DX port map ( +D => RCOUNT_S(14), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(14)); +\RCOUNT[15]_REG_Z562\: FD1S3DX port map ( +D => RCOUNT_S(15), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(15)); +PPUL_SYNC_P3_REG_Z564: FD1S3DX port map ( +D => PPUL_SYNC_P2, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P3); +PPUL_SYNC_P2_REG_Z566: FD1S3DX port map ( +D => PPUL_SYNC_P1, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P2); +PPUL_SYNC_P1_REG_Z568: FD1S3DX port map ( +D => PPUL_SYNC, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P1); +PLL_LOCK_REG_Z570: FD1S3DX port map ( +D => N_53_I, +CK => pll_refclki, +CD => sli_rst, +Q => PLL_LOCK); +\PHB_CNT[0]_REG_Z572\: FD1S3DX port map ( +D => PHB_CNT_I(0), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(0)); +\PHB_CNT[1]_REG_Z574\: FD1S3DX port map ( +D => PHB_CNT_RNO(1), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(1)); +\PHB_CNT[2]_REG_Z576\: FD1S3DX port map ( +D => PHB_CNT_RNO(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(2)); +PHB_REG_Z578: FD1S3DX port map ( +D => PHB_CNT_I(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB); +PDIFF_SYNC_P1_REG_Z580: FD1S3DX port map ( +D => PDIFF_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => PDIFF_SYNC_P1); +\PCOUNT[0]_REG_Z582\: FD1S3DX port map ( +D => PCOUNT_S(0), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(0)); +\PCOUNT_DIFF[0]_REG_Z584\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_I(0), +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_0); +\PCOUNT[1]_REG_Z586\: FD1S3DX port map ( +D => PCOUNT_S(1), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(1)); +\PCOUNT_DIFF[1]_REG_Z588\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_1); +\PCOUNT_DIFF[2]_REG_Z590\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_2); +\PCOUNT[2]_REG_Z592\: FD1S3DX port map ( +D => PCOUNT_S(2), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(2)); +\PCOUNT_DIFF[3]_REG_Z594\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_3); +\PCOUNT[3]_REG_Z596\: FD1S3DX port map ( +D => PCOUNT_S(3), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(3)); +\PCOUNT_DIFF[4]_REG_Z598\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_4); +\PCOUNT[4]_REG_Z600\: FD1S3DX port map ( +D => PCOUNT_S(4), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(4)); +\PCOUNT_DIFF[5]_REG_Z602\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_5); +\PCOUNT[5]_REG_Z604\: FD1S3DX port map ( +D => PCOUNT_S(5), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(5)); +\PCOUNT[6]_REG_Z606\: FD1S3DX port map ( +D => PCOUNT_S(6), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(6)); +\PCOUNT_DIFF[6]_REG_Z608\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_6); +\PCOUNT[7]_REG_Z610\: FD1S3DX port map ( +D => PCOUNT_S(7), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(7)); +\PCOUNT_DIFF[7]_REG_Z612\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_7); +\PCOUNT[8]_REG_Z614\: FD1S3DX port map ( +D => PCOUNT_S(8), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(8)); +\PCOUNT_DIFF[8]_REG_Z616\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_8); +\PCOUNT_DIFF[9]_REG_Z618\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_9); +\PCOUNT[9]_REG_Z620\: FD1S3DX port map ( +D => PCOUNT_S(9), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(9)); +\PCOUNT[10]_REG_Z622\: FD1S3DX port map ( +D => PCOUNT_S(10), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(10)); +\PCOUNT_DIFF[10]_REG_Z624\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_10); +\PCOUNT_DIFF[11]_REG_Z626\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_11); +\PCOUNT[11]_REG_Z628\: FD1S3DX port map ( +D => PCOUNT_S(11), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(11)); +\PCOUNT[12]_REG_Z630\: FD1S3DX port map ( +D => PCOUNT_S(12), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(12)); +\PCOUNT_DIFF[12]_REG_Z632\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_12); +\PCOUNT_DIFF[13]_REG_Z634\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_13); +\PCOUNT[13]_REG_Z636\: FD1S3DX port map ( +D => PCOUNT_S(13), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(13)); +\PCOUNT_DIFF[14]_REG_Z638\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_14); +\PCOUNT[14]_REG_Z640\: FD1S3DX port map ( +D => PCOUNT_S(14), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(14)); +\PCOUNT[15]_REG_Z642\: FD1S3DX port map ( +D => PCOUNT_S(15), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(15)); +\PCOUNT_DIFF[15]_REG_Z644\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_15); +\PCOUNT[16]_REG_Z646\: FD1S3DX port map ( +D => PCOUNT_S(16), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(16)); +\PCOUNT_DIFF[16]_REG_Z648\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_16); +\PCOUNT_DIFF[17]_REG_Z650\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_17); +\PCOUNT[17]_REG_Z652\: FD1S3DX port map ( +D => PCOUNT_S(17), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(17)); +\PCOUNT_DIFF[18]_REG_Z654\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_18); +\PCOUNT[18]_REG_Z656\: FD1S3DX port map ( +D => PCOUNT_S(18), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(18)); +\PCOUNT[19]_REG_Z658\: FD1S3DX port map ( +D => PCOUNT_S(19), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(19)); +\PCOUNT_DIFF[19]_REG_Z660\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_19); +\PCOUNT[20]_REG_Z662\: FD1S3DX port map ( +D => PCOUNT_S(20), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(20)); +\PCOUNT_DIFF[20]_REG_Z664\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_20); +\PCOUNT_DIFF[21]_REG_Z666\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_S_21_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_21); +\PCOUNT[21]_REG_Z668\: FD1S3DX port map ( +D => PCOUNT_S(21), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(21)); +LOCK_REG_Z670: FD1P3DX port map ( +D => LOCK_5, +SP => LOCK_1_SQMUXA_I, +CK => pll_refclki, +CD => sli_rst, +Q => LOCK); +\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z672\: FD1S3DX port map ( +D => VCC, +CK => pll_refclki, +CD => sli_rst, +Q => RDIFF_COMP_LOCK(2)); +\SLL_STATE_RNO[0]\: LUT4 +generic map( + init => X"E050" +) +port map ( +A => N_98, +B => LOCK, +C => RSTAT_PCLK, +D => SLL_STATE(0), +Z => N_95_I); +RTC_PUL5_0_0: LUT4 +generic map( + init => X"FF80" +) +port map ( +A => RTC_PUL5_0_O3, +B => RTC_PUL5_0_A3_6, +C => RTC_PUL5_0_A3_7, +D => UN1_RCOUNT_1_0_A3, +Z => RTC_PUL5); +RSTAT_PCLK_2_IV: LUT4 +generic map( + init => X"AEEE" +) +port map ( +A => RHB_WAIT_CNT12, +B => RSTAT_PCLK, +C => UN1_RHB_WAIT_CNT_4, +D => UN1_RHB_WAIT_CNT_5, +Z => RSTAT_PCLK_2); +\SLL_STATE_RNO[1]\: LUT4 +generic map( + init => X"8088" +) +port map ( +A => N_99, +B => RSTAT_PCLK, +C => SLL_STATE(1), +D => UNLOCK, +Z => N_97_I); +RTC_CTRL4_0_A3: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_1, +B => RTC_CTRL4_0_A3_12_4, +C => RTC_CTRL4_0_A3_12_5, +D => RTC_CTRL4_10, +Z => RTC_CTRL4); +UN1_RCOUNT_1_0_A3_Z678: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_12_4, +B => RTC_CTRL4_0_A3_12_5, +C => RTC_CTRL4_10, +D => UN1_RCOUNT_1_0_A3_1, +Z => UN1_RCOUNT_1_0_A3); +LOCK_1_SQMUXA_I_Z679: LUT4 +generic map( + init => X"7575" +) +port map ( +A => LOCK, +B => PDIFF_SYNC, +C => PDIFF_SYNC_P1, +D => VCC, +Z => LOCK_1_SQMUXA_I); +UNLOCK_1_SQMUXA_I_Z680: LUT4 +generic map( + init => X"4F4F" +) +port map ( +A => PDIFF_SYNC, +B => PDIFF_SYNC_P1, +C => UNLOCK, +D => VCC, +Z => UNLOCK_1_SQMUXA_I); +RTC_PUL5_0_O3_Z681: LUT4 +generic map( + init => X"AAAB" +) +port map ( +A => N_6, +B => RCOUNT(1), +C => RCOUNT(2), +D => RCOUNT(3), +Z => RTC_PUL5_0_O3); +RTC_PUL5_0_A3_7_Z682: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RTC_PUL5_0_A3_5, +D => VCC, +Z => RTC_PUL5_0_A3_7); +\SLL_STATE_NS_I_M4[1]\: LUT4 +generic map( + init => X"EF20" +) +port map ( +A => LOCK, +B => RTC_PUL, +C => RTC_PUL_P1, +D => SLL_STATE(1), +Z => N_99); +PLL_LOCK_RNO: LUT4 +generic map( + init => X"8888" +) +port map ( +A => SLL_STATE(0), +B => SLL_STATE(1), +C => VCC, +D => VCC, +Z => N_53_I); +\PHB_CNT_RNO[2]_Z685\: LUT4 +generic map( + init => X"7878" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => PHB_CNT(2), +D => VCC, +Z => PHB_CNT_RNO(2)); +\SLL_STATE_NS_I_O4[0]\: LUT4 +generic map( + init => X"BFBF" +) +port map ( +A => RTC_PUL, +B => RTC_PUL_P1, +C => SLL_STATE(1), +D => VCC, +Z => N_98); +RTC_CTRL4_0_A3_10: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(1), +B => RCOUNT(3), +C => RCOUNT(6), +D => RCOUNT(15), +Z => RTC_CTRL4_10); +UN1_RHB_WAIT_CNT_4_Z688: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(4), +B => RHB_WAIT_CNT(5), +C => RHB_WAIT_CNT(6), +D => RHB_WAIT_CNT(7), +Z => UN1_RHB_WAIT_CNT_4); +UN1_RHB_WAIT_CNT_5_Z689: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(0), +B => RHB_WAIT_CNT(1), +C => RHB_WAIT_CNT(2), +D => RHB_WAIT_CNT(3), +Z => UN1_RHB_WAIT_CNT_5); +RTC_CTRL4_0_A3_12_4_Z690: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(11), +B => RCOUNT(12), +C => RCOUNT(13), +D => RCOUNT(14), +Z => RTC_CTRL4_0_A3_12_4); +RTC_CTRL4_0_A3_12_5_Z691: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RCOUNT(9), +D => RCOUNT(10), +Z => RTC_CTRL4_0_A3_12_5); +RTC_PUL5_0_A3_5_Z692: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(6), +B => RCOUNT(13), +C => RCOUNT(14), +D => RCOUNT(15), +Z => RTC_PUL5_0_A3_5); +RTC_PUL5_0_A3_6_Z693: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(9), +B => RCOUNT(10), +C => RCOUNT(11), +D => RCOUNT(12), +Z => RTC_PUL5_0_A3_6); +PCOUNT10_0_O3: LUT4 +generic map( + init => X"DDDD" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => VCC, +D => VCC, +Z => N_8); +\PHB_CNT_RNO[1]_Z695\: LUT4 +generic map( + init => X"6666" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => VCC, +D => VCC, +Z => PHB_CNT_RNO(1)); +RTC_CTRL4_0_O3: LUT4 +generic map( + init => X"7777" +) +port map ( +A => RCOUNT(4), +B => RCOUNT(5), +C => VCC, +D => VCC, +Z => N_6); +UNLOCK_5_Z697: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_UNLOCK_CRY_21, +C => VCC, +D => VCC, +Z => UNLOCK_5); +LOCK_5_Z698: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_LOCK_CRY_21_I, +C => VCC, +D => VCC, +Z => LOCK_5); +RHB_WAIT_CNT12_Z699: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RHB_SYNC_P1, +B => RHB_SYNC_P2, +C => VCC, +D => VCC, +Z => RHB_WAIT_CNT12); +\UN1_PCOUNT_DIFF[0]_Z700\: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_0, +B => PCOUNT(0), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF(0)); +UN1_RCOUNT_1_0_A3_1_Z701: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => UN1_RCOUNT_1_0_A3_1); +RHB_SYNC_P2_RNIU9TG1: LUT4 +generic map( + init => X"7077" +) +port map ( +A => UN1_RHB_WAIT_CNT_5, +B => UN1_RHB_WAIT_CNT_4, +C => RHB_SYNC_P2, +D => RHB_SYNC_P1, +Z => \RHB_WAIT_CNT_\); +\PCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => N_8, +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_9, +COUT => PCOUNT_CRY(0), +S0 => PCOUNT_CRY_0_S0(0), +S1 => PCOUNT_S(0)); +\PCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(0), +COUT => PCOUNT_CRY(2), +S0 => PCOUNT_S(1), +S1 => PCOUNT_S(2)); +\PCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(2), +COUT => PCOUNT_CRY(4), +S0 => PCOUNT_S(3), +S1 => PCOUNT_S(4)); +\PCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(4), +COUT => PCOUNT_CRY(6), +S0 => PCOUNT_S(5), +S1 => PCOUNT_S(6)); +\PCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(6), +COUT => PCOUNT_CRY(8), +S0 => PCOUNT_S(7), +S1 => PCOUNT_S(8)); +\PCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(8), +COUT => PCOUNT_CRY(10), +S0 => PCOUNT_S(9), +S1 => PCOUNT_S(10)); +\PCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(10), +COUT => PCOUNT_CRY(12), +S0 => PCOUNT_S(11), +S1 => PCOUNT_S(12)); +\PCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(12), +COUT => PCOUNT_CRY(14), +S0 => PCOUNT_S(13), +S1 => PCOUNT_S(14)); +\PCOUNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(16), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(14), +COUT => PCOUNT_CRY(16), +S0 => PCOUNT_S(15), +S1 => PCOUNT_S(16)); +\PCOUNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(17), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(18), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(16), +COUT => PCOUNT_CRY(18), +S0 => PCOUNT_S(17), +S1 => PCOUNT_S(18)); +\PCOUNT_CRY_0[19]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(19), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(20), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(18), +COUT => PCOUNT_CRY(20), +S0 => PCOUNT_S(19), +S1 => PCOUNT_S(20)); +\PCOUNT_S_0[21]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(21), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(20), +COUT => PCOUNT_S_0_COUT(21), +S0 => PCOUNT_S(21), +S1 => PCOUNT_S_0_S1(21)); +\RCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => UN1_RCOUNT_1_0_A3, +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => RCOUNT_CRY(0), +S0 => RCOUNT_CRY_0_S0(0), +S1 => RCOUNT_S(0)); +\RCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(0), +COUT => RCOUNT_CRY(2), +S0 => RCOUNT_S(1), +S1 => RCOUNT_S(2)); +\RCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(2), +COUT => RCOUNT_CRY(4), +S0 => RCOUNT_S(3), +S1 => RCOUNT_S(4)); +\RCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(4), +COUT => RCOUNT_CRY(6), +S0 => RCOUNT_S(5), +S1 => RCOUNT_S(6)); +\RCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(6), +COUT => RCOUNT_CRY(8), +S0 => RCOUNT_S(7), +S1 => RCOUNT_S(8)); +\RCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(8), +COUT => RCOUNT_CRY(10), +S0 => RCOUNT_S(9), +S1 => RCOUNT_S(10)); +\RCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(10), +COUT => RCOUNT_CRY(12), +S0 => RCOUNT_S(11), +S1 => RCOUNT_S(12)); +\RCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(12), +COUT => RCOUNT_CRY(14), +S0 => RCOUNT_S(13), +S1 => RCOUNT_S(14)); +\RCOUNT_S_0[15]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(14), +COUT => RCOUNT_S_0_COUT(15), +S0 => RCOUNT_S(15), +S1 => RCOUNT_S_0_S1(15)); +\RHB_WAIT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RHB_WAIT_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RHB_WAIT_CNT_CRY(0), +S0 => RHB_WAIT_CNT_CRY_0_S0(0), +S1 => RHB_WAIT_CNT_S(0)); +\RHB_WAIT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(0), +COUT => RHB_WAIT_CNT_CRY(2), +S0 => RHB_WAIT_CNT_S(1), +S1 => RHB_WAIT_CNT_S(2)); +\RHB_WAIT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(2), +COUT => RHB_WAIT_CNT_CRY(4), +S0 => RHB_WAIT_CNT_S(3), +S1 => RHB_WAIT_CNT_S(4)); +\RHB_WAIT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(4), +COUT => RHB_WAIT_CNT_CRY(6), +S0 => RHB_WAIT_CNT_S(5), +S1 => RHB_WAIT_CNT_S(6)); +\RHB_WAIT_CNT_S_0[7]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(6), +COUT => RHB_WAIT_CNT_S_0_COUT(7), +S0 => RHB_WAIT_CNT_S(7), +S1 => RHB_WAIT_CNT_S_0_S1(7)); +UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500f", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF(0), +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => UN1_PCOUNT_DIFF_1_CRY_0, +S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1); +UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_1, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_2, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_0, +COUT => UN1_PCOUNT_DIFF_1_CRY_2, +S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1); +UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_2, +COUT => UN1_PCOUNT_DIFF_1_CRY_4, +S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1); +UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_4, +COUT => UN1_PCOUNT_DIFF_1_CRY_6, +S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1); +UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_6, +COUT => UN1_PCOUNT_DIFF_1_CRY_8, +S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1); +UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_8, +COUT => UN1_PCOUNT_DIFF_1_CRY_10, +S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1); +UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_10, +COUT => UN1_PCOUNT_DIFF_1_CRY_12, +S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1); +UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_12, +COUT => UN1_PCOUNT_DIFF_1_CRY_14, +S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1); +UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_14, +COUT => UN1_PCOUNT_DIFF_1_CRY_16, +S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1); +UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C +generic map( + INIT0 => X"b404", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => RDIFF_COMP_LOCK(2), +C0 => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_16, +COUT => UN1_PCOUNT_DIFF_1_CRY_18, +S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1); +UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_18, +COUT => UN1_PCOUNT_DIFF_1_CRY_20, +S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1); +UN1_PCOUNT_DIFF_1_S_21_0: CCU2C +generic map( + INIT0 => X"350a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => PCOUNT(21), +B0 => UN13_LOCK_21, +C0 => N_8, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_20, +COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT, +S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0, +S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1); +UN13_LOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => UN13_LOCK_CRY_0, +S0 => UN13_LOCK_CRY_0_0_S0, +S1 => UN13_LOCK_CRY_0_0_S1); +UN13_LOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_0, +COUT => UN13_LOCK_CRY_2, +S0 => UN13_LOCK_CRY_1_0_S0, +S1 => UN13_LOCK_CRY_1_0_S1); +UN13_LOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_2, +COUT => UN13_LOCK_CRY_4, +S0 => UN13_LOCK_CRY_3_0_S0, +S1 => UN13_LOCK_CRY_3_0_S1); +UN13_LOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_4, +COUT => UN13_LOCK_CRY_6, +S0 => UN13_LOCK_CRY_5_0_S0, +S1 => UN13_LOCK_CRY_5_0_S1); +UN13_LOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_6, +COUT => UN13_LOCK_CRY_8, +S0 => UN13_LOCK_CRY_7_0_S0, +S1 => UN13_LOCK_CRY_7_0_S1); +UN13_LOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_8, +COUT => UN13_LOCK_CRY_10, +S0 => UN13_LOCK_CRY_9_0_S0, +S1 => UN13_LOCK_CRY_9_0_S1); +UN13_LOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_10, +COUT => UN13_LOCK_CRY_12, +S0 => UN13_LOCK_CRY_11_0_S0, +S1 => UN13_LOCK_CRY_11_0_S1); +UN13_LOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_12, +COUT => UN13_LOCK_CRY_14, +S0 => UN13_LOCK_CRY_13_0_S0, +S1 => UN13_LOCK_CRY_13_0_S1); +UN13_LOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_14, +COUT => UN13_LOCK_CRY_16, +S0 => UN13_LOCK_CRY_15_0_S0, +S1 => UN13_LOCK_CRY_15_0_S1); +UN13_LOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_16, +COUT => UN13_LOCK_CRY_18, +S0 => UN13_LOCK_CRY_17_0_S0, +S1 => UN13_LOCK_CRY_17_0_S1); +UN13_LOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_18, +COUT => UN13_LOCK_CRY_20, +S0 => UN13_LOCK_CRY_19_0_S0, +S1 => UN13_LOCK_CRY_19_0_S1); +UN13_LOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_20, +COUT => UN13_LOCK_CRY_21_0_COUT, +S0 => UN13_LOCK_CRY_21_0_S0, +S1 => UN13_LOCK_CRY_21_I); +UN13_UNLOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => UN13_UNLOCK_CRY_0, +S0 => UN13_UNLOCK_CRY_0_0_S0, +S1 => UN13_UNLOCK_CRY_0_0_S1); +UN13_UNLOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_0, +COUT => UN13_UNLOCK_CRY_2, +S0 => UN13_UNLOCK_CRY_1_0_S0, +S1 => UN13_UNLOCK_CRY_1_0_S1); +UN13_UNLOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_2, +COUT => UN13_UNLOCK_CRY_4, +S0 => UN13_UNLOCK_CRY_3_0_S0, +S1 => UN13_UNLOCK_CRY_3_0_S1); +UN13_UNLOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_4, +COUT => UN13_UNLOCK_CRY_6, +S0 => UN13_UNLOCK_CRY_5_0_S0, +S1 => UN13_UNLOCK_CRY_5_0_S1); +UN13_UNLOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_6, +COUT => UN13_UNLOCK_CRY_8, +S0 => UN13_UNLOCK_CRY_7_0_S0, +S1 => UN13_UNLOCK_CRY_7_0_S1); +UN13_UNLOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_8, +COUT => UN13_UNLOCK_CRY_10, +S0 => UN13_UNLOCK_CRY_9_0_S0, +S1 => UN13_UNLOCK_CRY_9_0_S1); +UN13_UNLOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_10, +COUT => UN13_UNLOCK_CRY_12, +S0 => UN13_UNLOCK_CRY_11_0_S0, +S1 => UN13_UNLOCK_CRY_11_0_S1); +UN13_UNLOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_12, +COUT => UN13_UNLOCK_CRY_14, +S0 => UN13_UNLOCK_CRY_13_0_S0, +S1 => UN13_UNLOCK_CRY_13_0_S1); +UN13_UNLOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_14, +COUT => UN13_UNLOCK_CRY_16, +S0 => UN13_UNLOCK_CRY_15_0_S0, +S1 => UN13_UNLOCK_CRY_15_0_S1); +UN13_UNLOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_16, +COUT => UN13_UNLOCK_CRY_18, +S0 => UN13_UNLOCK_CRY_17_0_S0, +S1 => UN13_UNLOCK_CRY_17_0_S1); +UN13_UNLOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_18, +COUT => UN13_UNLOCK_CRY_20, +S0 => UN13_UNLOCK_CRY_19_0_S0, +S1 => UN13_UNLOCK_CRY_19_0_S1); +UN13_UNLOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_20, +COUT => UN13_UNLOCK_CRY_21_0_COUT, +S0 => UN13_UNLOCK_CRY_21_0_S0, +S1 => UN13_UNLOCK_CRY_21); +PHB_SYNC_INST: sync_0s port map ( +phb => PHB, +rhb_sync => RHB_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +RTC_SYNC_INST: sync_0s_6 port map ( +rtc_pul => RTC_PUL, +ppul_sync => PPUL_SYNC, +sli_rst => sli_rst, +tx_pclk => tx_pclk); +PDIFF_SYNC_INST: sync_0s_0 port map ( +ppul_sync => PPUL_SYNC, +pdiff_sync => PDIFF_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5 is +port( +hdoutp : out std_logic; +hdoutn : out std_logic; +hdinp : in std_logic; +hdinn : in std_logic; +rxrefclk : in std_logic; +tx_pclk : out std_logic; +txi_clk : in std_logic; +txdata : in std_logic_vector(7 downto 0); +tx_k : in std_logic_vector(0 downto 0); +xmit : in std_logic_vector(0 downto 0); +tx_disp_correct : in std_logic_vector(0 downto 0); +rxdata : out std_logic_vector(7 downto 0); +rx_k : out std_logic_vector(0 downto 0); +rx_disp_err : out std_logic_vector(0 downto 0); +rx_cv_err : out std_logic_vector(0 downto 0); +signal_detect_c : in std_logic; +rx_los_low_s : out std_logic; +lsm_status_s : out std_logic; +ctc_urun_s : out std_logic; +ctc_orun_s : out std_logic; +rx_cdr_lol_s : out std_logic; +ctc_ins_s : out std_logic; +ctc_del_s : out std_logic; +sli_rst : in std_logic; +tx_pwrup_c : in std_logic; +rx_pwrup_c : in std_logic; +sci_wrdata : in std_logic_vector(7 downto 0); +sci_addr : in std_logic_vector(5 downto 0); +sci_rddata : out std_logic_vector(7 downto 0); +sci_en_dual : in std_logic; +sci_sel_dual : in std_logic; +sci_en : in std_logic; +sci_sel : in std_logic; +sci_rd : in std_logic; +sci_wrn : in std_logic; +sci_int : out std_logic; +cyawstn : in std_logic; +serdes_pdb : in std_logic; +pll_refclki : in std_logic; +rsl_disable : in std_logic; +rsl_rst : in std_logic; +serdes_rst_dual_c : in std_logic; +rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +pll_lol : out std_logic; +rsl_tx_rdy : out std_logic; +rx_serdes_rst_c : in std_logic; +rx_pcs_rst_c : in std_logic; +rsl_rx_rdy : out std_logic); +end sgmii_ecp5; + +architecture beh of sgmii_ecp5 is +signal TX_PCLK_11 : std_logic ; +signal RX_LOS_LOW_S_12 : std_logic ; +signal RX_CDR_LOL_S_13 : std_logic ; +signal RSL_TX_PCS_RST_C : std_logic ; +signal RSL_RX_PCS_RST_C : std_logic ; +signal RSL_RX_SERDES_RST_C : std_logic ; +signal RSL_SERDES_RST_DUAL_C : std_logic ; +signal RSL_TX_SERDES_RST_C : std_logic ; +signal N47_1 : std_logic ; +signal N48_1 : std_logic ; +signal N1_1 : std_logic ; +signal N2_1 : std_logic ; +signal N3_1 : std_logic ; +signal N4_1 : std_logic ; +signal N5_1 : std_logic ; +signal N49_1 : std_logic ; +signal N6_1 : std_logic ; +signal N50_1 : std_logic ; +signal N7_1 : std_logic ; +signal N51_1 : std_logic ; +signal N8_1 : std_logic ; +signal N52_1 : std_logic ; +signal N9_1 : std_logic ; +signal N53_1 : std_logic ; +signal N54_1 : std_logic ; +signal N55_1 : std_logic ; +signal N56_1 : std_logic ; +signal N57_1 : std_logic ; +signal N58_1 : std_logic ; +signal N59_1 : std_logic ; +signal N60_1 : std_logic ; +signal N61_1 : std_logic ; +signal N62_1 : std_logic ; +signal N63_1 : std_logic ; +signal N64_1 : std_logic ; +signal N65_1 : std_logic ; +signal N10_1 : std_logic ; +signal N66_1 : std_logic ; +signal N67_1 : std_logic ; +signal N68_1 : std_logic ; +signal N69_1 : std_logic ; +signal N70_1 : std_logic ; +signal N71_1 : std_logic ; +signal N72_1 : std_logic ; +signal N73_1 : std_logic ; +signal N74_1 : std_logic ; +signal N75_1 : std_logic ; +signal N76_1 : std_logic ; +signal N77_1 : std_logic ; +signal N78_1 : std_logic ; +signal N79_1 : std_logic ; +signal N80_1 : std_logic ; +signal N81_1 : std_logic ; +signal N82_1 : std_logic ; +signal N83_1 : std_logic ; +signal N84_1 : std_logic ; +signal N85_1 : std_logic ; +signal N86_1 : std_logic ; +signal N87_1 : std_logic ; +signal N88_1 : std_logic ; +signal N11_1 : std_logic ; +signal N89_1 : std_logic ; +signal N12_1 : std_logic ; +signal N90_1 : std_logic ; +signal N13_1 : std_logic ; +signal N91_1 : std_logic ; +signal N92_1 : std_logic ; +signal N93_1 : std_logic ; +signal N94_1 : std_logic ; +signal N95_1 : std_logic ; +signal N14_1 : std_logic ; +signal N96_1 : std_logic ; +signal N15_1 : std_logic ; +signal N97_1 : std_logic ; +signal N98_1 : std_logic ; +signal N99_1 : std_logic ; +signal N100_1 : std_logic ; +signal N101_1 : std_logic ; +signal N112_1 : std_logic ; +signal N16_1 : std_logic ; +signal N17_1 : std_logic ; +signal N18_1 : std_logic ; +signal N19_1 : std_logic ; +signal N20_1 : std_logic ; +signal N21_1 : std_logic ; +signal N22_1 : std_logic ; +signal N23_1 : std_logic ; +signal N24_1 : std_logic ; +signal N25_1 : std_logic ; +signal N26_1 : std_logic ; +signal N27_1 : std_logic ; +signal N28_1 : std_logic ; +signal N29_1 : std_logic ; +signal N30_1 : std_logic ; +signal N31_1 : std_logic ; +signal N32_1 : std_logic ; +signal N33_1 : std_logic ; +signal N34_1 : std_logic ; +signal N35_1 : std_logic ; +signal N36_1 : std_logic ; +signal N37_1 : std_logic ; +signal N38_1 : std_logic ; +signal N39_1 : std_logic ; +signal N40_1 : std_logic ; +signal N41_1 : std_logic ; +signal N42_1 : std_logic ; +signal N43_1 : std_logic ; +signal N46_1 : std_logic ; +signal TX_PCLK_I : std_logic ; +signal GND : std_logic ; +signal VCC : std_logic ; +signal \SLL_INST.PLL_LOCK_I_14\ : std_logic ; +component sgmii_ecp5sll_core_Z1_layer1 +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic ); +end component; +component sgmii_ecp5rsl_core_Z2_layer1 +port( +rx_pcs_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +tx_serdes_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rsl_disable : in std_logic; +rx_serdes_rst_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rst_dual_c : in std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic ); +end component; +begin +VCC_0: VHI port map ( +Z => VCC); +GND_0: VLO port map ( +Z => GND); +PUR_INST: PUR port map ( +PUR => VCC); +GSR_INST: GSR port map ( +GSR => VCC); +TX_PCLK_11 <= TX_PCLK_I; +DCU0_INST: DCUA +generic map( + D_MACROPDB => "0b1", + D_IB_PWDNB => "0b1", + D_XGE_MODE => "0b0", + D_LOW_MARK => "0d4", + D_HIGH_MARK => "0d12", + D_BUS8BIT_SEL => "0b0", + D_CDR_LOL_SET => "0b00", + D_BITCLK_LOCAL_EN => "0b1", + D_BITCLK_ND_EN => "0b0", + D_BITCLK_FROM_ND_EN => "0b0", + D_SYNC_LOCAL_EN => "0b1", + D_SYNC_ND_EN => "0b0", + CH0_UC_MODE => "0b0", + CH0_PCIE_MODE => "0b0", + CH0_RIO_MODE => "0b0", + CH0_WA_MODE => "0b0", + CH0_INVERT_RX => "0b0", + CH0_INVERT_TX => "0b0", + CH0_PRBS_SELECTION => "0b0", + CH0_GE_AN_ENABLE => "0b0", + CH0_PRBS_LOCK => "0b0", + CH0_PRBS_ENABLE => "0b0", + CH0_ENABLE_CG_ALIGN => "0b1", + CH0_TX_GEAR_MODE => "0b0", + CH0_RX_GEAR_MODE => "0b0", + CH0_PCS_DET_TIME_SEL => "0b00", + CH0_PCIE_EI_EN => "0b0", + CH0_TX_GEAR_BYPASS => "0b0", + CH0_ENC_BYPASS => "0b0", + CH0_SB_BYPASS => "0b0", + CH0_RX_SB_BYPASS => "0b0", + CH0_WA_BYPASS => "0b0", + CH0_DEC_BYPASS => "0b0", + CH0_CTC_BYPASS => "0b0", + CH0_RX_GEAR_BYPASS => "0b0", + CH0_LSM_DISABLE => "0b0", + CH0_MATCH_2_ENABLE => "0b1", + CH0_MATCH_4_ENABLE => "0b0", + CH0_MIN_IPG_CNT => "0b11", + CH0_CC_MATCH_1 => "0x000", + CH0_CC_MATCH_2 => "0x000", + CH0_CC_MATCH_3 => "0x1BC", + CH0_CC_MATCH_4 => "0x050", + CH0_UDF_COMMA_MASK => "0x3ff", + CH0_UDF_COMMA_A => "0x283", + CH0_UDF_COMMA_B => "0x17C", + CH0_RX_DCO_CK_DIV => "0b010", + CH0_RCV_DCC_EN => "0b0", + CH0_REQ_LVL_SET => "0b00", + CH0_REQ_EN => "0b1", + CH0_RTERM_RX => "0d22", + CH0_PDEN_SEL => "0b1", + CH0_LDR_RX2CORE_SEL => "0b0", + CH0_LDR_CORE2TX_SEL => "0b0", + CH0_TPWDNB => "0b1", + CH0_RATE_MODE_TX => "0b0", + CH0_RTERM_TX => "0d19", + CH0_TX_CM_SEL => "0b00", + CH0_TDRV_PRE_EN => "0b0", + CH0_TDRV_SLICE0_SEL => "0b01", + CH0_TDRV_SLICE1_SEL => "0b00", + CH0_TDRV_SLICE2_SEL => "0b01", + CH0_TDRV_SLICE3_SEL => "0b01", + CH0_TDRV_SLICE4_SEL => "0b01", + CH0_TDRV_SLICE5_SEL => "0b01", + CH0_TDRV_SLICE0_CUR => "0b101", + CH0_TDRV_SLICE1_CUR => "0b000", + CH0_TDRV_SLICE2_CUR => "0b11", + CH0_TDRV_SLICE3_CUR => "0b11", + CH0_TDRV_SLICE4_CUR => "0b11", + CH0_TDRV_SLICE5_CUR => "0b00", + CH0_TDRV_DAT_SEL => "0b00", + CH0_TX_DIV11_SEL => "0b0", + CH0_RPWDNB => "0b1", + CH0_RATE_MODE_RX => "0b0", + CH0_RLOS_SEL => "0b1", + CH0_RX_LOS_LVL => "0b010", + CH0_RX_LOS_CEQ => "0b11", + CH0_RX_LOS_HYST_EN => "0b0", + CH0_RX_LOS_EN => "0b1", + CH0_RX_DIV11_SEL => "0b0", + CH0_SEL_SD_RX_CLK => "0b0", + CH0_FF_RX_H_CLK_EN => "0b0", + CH0_FF_RX_F_CLK_DIS => "0b0", + CH0_FF_TX_H_CLK_EN => "0b0", + CH0_FF_TX_F_CLK_DIS => "0b0", + CH0_RX_RATE_SEL => "0d8", + CH0_TDRV_POST_EN => "0b0", + CH0_TX_POST_SIGN => "0b0", + CH0_TX_PRE_SIGN => "0b0", + CH0_RXTERM_CM => "0b11", + CH0_RXIN_CM => "0b11", + CH0_LEQ_OFFSET_SEL => "0b0", + CH0_LEQ_OFFSET_TRIM => "0b000", + D_TX_MAX_RATE => "1.25", + CH0_CDR_MAX_RATE => "1.25", + CH0_TXAMPLITUDE => "0d1100", + CH0_TXDEPRE => "DISABLED", + CH0_TXDEPOST => "DISABLED", + CH0_PROTOCOL => "GBE", + D_ISETLOS => "0d0", + D_SETIRPOLY_AUX => "0b00", + D_SETICONST_AUX => "0b00", + D_SETIRPOLY_CH => "0b00", + D_SETICONST_CH => "0b00", + D_REQ_ISET => "0b000", + D_PD_ISET => "0b00", + D_DCO_CALIB_TIME_SEL => "0b00", + CH0_DCOCTLGI => "0b010", + CH0_DCOATDDLY => "0b00", + CH0_DCOATDCFG => "0b00", + CH0_DCOBYPSATD => "0b1", + CH0_DCOSCALEI => "0b00", + CH0_DCOITUNE4LSB => "0b111", + CH0_DCOIOSTUNE => "0b000", + CH0_DCODISBDAVOID => "0b0", + CH0_DCOCALDIV => "0b001", + CH0_DCONUOFLSB => "0b101", + CH0_DCOIUPDNX2 => "0b1", + CH0_DCOSTEP => "0b00", + CH0_DCOSTARTVAL => "0b000", + CH0_DCOFLTDAC => "0b01", + CH0_DCOITUNE => "0b00", + CH0_DCOFTNRG => "0b110", + CH0_CDR_CNT4SEL => "0b00", + CH0_CDR_CNT8SEL => "0b00", + CH0_BAND_THRESHOLD => "0d0", + CH0_AUTO_FACQ_EN => "0b1", + CH0_AUTO_CALIB_EN => "0b1", + CH0_CALIB_CK_MODE => "0b0", + CH0_REG_BAND_OFFSET => "0d0", + CH0_REG_BAND_SEL => "0d0", + CH0_REG_IDAC_SEL => "0d0", + CH0_REG_IDAC_EN => "0b0", + D_TXPLL_PWDNB => "0b1", + D_SETPLLRC => "0d1", + D_REFCK_MODE => "0b001", + D_TX_VCO_CK_DIV => "0b010", + D_PLL_LOL_SET => "0b00", + D_RG_EN => "0b0", + D_RG_SET => "0b00", + D_CMUSETISCL4VCO => "0b000", + D_CMUSETI4VCO => "0b00", + D_CMUSETINITVCT => "0b00", + D_CMUSETZGM => "0b000", + D_CMUSETP2AGM => "0b000", + D_CMUSETP1GM => "0b000", + D_CMUSETI4CPZ => "0d3", + D_CMUSETI4CPP => "0d3", + D_CMUSETICP4Z => "0b101", + D_CMUSETICP4P => "0b01", + D_CMUSETBIASI => "0b00" +) +port map ( +CH0_HDINP => hdinp, +CH1_HDINP => GND, +CH0_HDINN => hdinn, +CH1_HDINN => GND, +D_TXBIT_CLKP_FROM_ND => GND, +D_TXBIT_CLKN_FROM_ND => GND, +D_SYNC_ND => GND, +D_TXPLL_LOL_FROM_ND => GND, +CH0_RX_REFCLK => rxrefclk, +CH1_RX_REFCLK => GND, +CH0_FF_RXI_CLK => TX_PCLK_11, +CH1_FF_RXI_CLK => VCC, +CH0_FF_TXI_CLK => txi_clk, +CH1_FF_TXI_CLK => VCC, +CH0_FF_EBRD_CLK => TX_PCLK_11, +CH1_FF_EBRD_CLK => VCC, +CH0_FF_TX_D_0 => txdata(0), +CH1_FF_TX_D_0 => GND, +CH0_FF_TX_D_1 => txdata(1), +CH1_FF_TX_D_1 => GND, +CH0_FF_TX_D_2 => txdata(2), +CH1_FF_TX_D_2 => GND, +CH0_FF_TX_D_3 => txdata(3), +CH1_FF_TX_D_3 => GND, +CH0_FF_TX_D_4 => txdata(4), +CH1_FF_TX_D_4 => GND, +CH0_FF_TX_D_5 => txdata(5), +CH1_FF_TX_D_5 => GND, +CH0_FF_TX_D_6 => txdata(6), +CH1_FF_TX_D_6 => GND, +CH0_FF_TX_D_7 => txdata(7), +CH1_FF_TX_D_7 => GND, +CH0_FF_TX_D_8 => tx_k(0), +CH1_FF_TX_D_8 => GND, +CH0_FF_TX_D_9 => GND, +CH1_FF_TX_D_9 => GND, +CH0_FF_TX_D_10 => xmit(0), +CH1_FF_TX_D_10 => GND, +CH0_FF_TX_D_11 => tx_disp_correct(0), +CH1_FF_TX_D_11 => GND, +CH0_FF_TX_D_12 => GND, +CH1_FF_TX_D_12 => GND, +CH0_FF_TX_D_13 => GND, +CH1_FF_TX_D_13 => GND, +CH0_FF_TX_D_14 => GND, +CH1_FF_TX_D_14 => GND, +CH0_FF_TX_D_15 => GND, +CH1_FF_TX_D_15 => GND, +CH0_FF_TX_D_16 => GND, +CH1_FF_TX_D_16 => GND, +CH0_FF_TX_D_17 => GND, +CH1_FF_TX_D_17 => GND, +CH0_FF_TX_D_18 => GND, +CH1_FF_TX_D_18 => GND, +CH0_FF_TX_D_19 => GND, +CH1_FF_TX_D_19 => GND, +CH0_FF_TX_D_20 => GND, +CH1_FF_TX_D_20 => GND, +CH0_FF_TX_D_21 => GND, +CH1_FF_TX_D_21 => GND, +CH0_FF_TX_D_22 => GND, +CH1_FF_TX_D_22 => GND, +CH0_FF_TX_D_23 => GND, +CH1_FF_TX_D_23 => GND, +CH0_FFC_EI_EN => GND, +CH1_FFC_EI_EN => GND, +CH0_FFC_PCIE_DET_EN => GND, +CH1_FFC_PCIE_DET_EN => GND, +CH0_FFC_PCIE_CT => GND, +CH1_FFC_PCIE_CT => GND, +CH0_FFC_SB_INV_RX => GND, +CH1_FFC_SB_INV_RX => GND, +CH0_FFC_ENABLE_CGALIGN => GND, +CH1_FFC_ENABLE_CGALIGN => GND, +CH0_FFC_SIGNAL_DETECT => signal_detect_c, +CH1_FFC_SIGNAL_DETECT => GND, +CH0_FFC_FB_LOOPBACK => GND, +CH1_FFC_FB_LOOPBACK => GND, +CH0_FFC_SB_PFIFO_LP => GND, +CH1_FFC_SB_PFIFO_LP => GND, +CH0_FFC_PFIFO_CLR => GND, +CH1_FFC_PFIFO_CLR => GND, +CH0_FFC_RATE_MODE_RX => GND, +CH1_FFC_RATE_MODE_RX => GND, +CH0_FFC_RATE_MODE_TX => GND, +CH1_FFC_RATE_MODE_TX => GND, +CH0_FFC_DIV11_MODE_RX => GND, +CH1_FFC_DIV11_MODE_RX => GND, +CH0_FFC_RX_GEAR_MODE => GND, +CH1_FFC_RX_GEAR_MODE => GND, +CH0_FFC_TX_GEAR_MODE => GND, +CH1_FFC_TX_GEAR_MODE => GND, +CH0_FFC_DIV11_MODE_TX => GND, +CH1_FFC_DIV11_MODE_TX => GND, +CH0_FFC_LDR_CORE2TX_EN => GND, +CH1_FFC_LDR_CORE2TX_EN => GND, +CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C, +CH1_FFC_LANE_TX_RST => GND, +CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C, +CH1_FFC_LANE_RX_RST => GND, +CH0_FFC_RRST => RSL_RX_SERDES_RST_C, +CH1_FFC_RRST => GND, +CH0_FFC_TXPWDNB => tx_pwrup_c, +CH1_FFC_TXPWDNB => GND, +CH0_FFC_RXPWDNB => rx_pwrup_c, +CH1_FFC_RXPWDNB => GND, +CH0_LDR_CORE2TX => GND, +CH1_LDR_CORE2TX => GND, +D_SCIWDATA0 => sci_wrdata(0), +D_SCIWDATA1 => sci_wrdata(1), +D_SCIWDATA2 => sci_wrdata(2), +D_SCIWDATA3 => sci_wrdata(3), +D_SCIWDATA4 => sci_wrdata(4), +D_SCIWDATA5 => sci_wrdata(5), +D_SCIWDATA6 => sci_wrdata(6), +D_SCIWDATA7 => sci_wrdata(7), +D_SCIADDR0 => sci_addr(0), +D_SCIADDR1 => sci_addr(1), +D_SCIADDR2 => sci_addr(2), +D_SCIADDR3 => sci_addr(3), +D_SCIADDR4 => sci_addr(4), +D_SCIADDR5 => sci_addr(5), +D_SCIENAUX => sci_en_dual, +D_SCISELAUX => sci_sel_dual, +CH0_SCIEN => sci_en, +CH1_SCIEN => GND, +CH0_SCISEL => sci_sel, +CH1_SCISEL => GND, +D_SCIRD => sci_rd, +D_SCIWSTN => sci_wrn, +D_CYAWSTN => cyawstn, +D_FFC_SYNC_TOGGLE => GND, +D_FFC_DUAL_RST => rst_dual_c, +D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C, +D_FFC_MACROPDB => serdes_pdb, +D_FFC_TRST => RSL_TX_SERDES_RST_C, +CH0_FFC_CDR_EN_BITSLIP => GND, +CH1_FFC_CDR_EN_BITSLIP => GND, +D_SCAN_ENABLE => GND, +D_SCAN_IN_0 => GND, +D_SCAN_IN_1 => GND, +D_SCAN_IN_2 => GND, +D_SCAN_IN_3 => GND, +D_SCAN_IN_4 => GND, +D_SCAN_IN_5 => GND, +D_SCAN_IN_6 => GND, +D_SCAN_IN_7 => GND, +D_SCAN_MODE => GND, +D_SCAN_RESET => GND, +D_CIN0 => GND, +D_CIN1 => GND, +D_CIN2 => GND, +D_CIN3 => GND, +D_CIN4 => GND, +D_CIN5 => GND, +D_CIN6 => GND, +D_CIN7 => GND, +D_CIN8 => GND, +D_CIN9 => GND, +D_CIN10 => GND, +D_CIN11 => GND, +CH0_HDOUTP => hdoutp, +CH1_HDOUTP => N47_1, +CH0_HDOUTN => hdoutn, +CH1_HDOUTN => N48_1, +D_TXBIT_CLKP_TO_ND => N1_1, +D_TXBIT_CLKN_TO_ND => N2_1, +D_SYNC_PULSE2ND => N3_1, +D_TXPLL_LOL_TO_ND => N4_1, +CH0_FF_RX_F_CLK => N5_1, +CH1_FF_RX_F_CLK => N49_1, +CH0_FF_RX_H_CLK => N6_1, +CH1_FF_RX_H_CLK => N50_1, +CH0_FF_TX_F_CLK => N7_1, +CH1_FF_TX_F_CLK => N51_1, +CH0_FF_TX_H_CLK => N8_1, +CH1_FF_TX_H_CLK => N52_1, +CH0_FF_RX_PCLK => N9_1, +CH1_FF_RX_PCLK => N53_1, +CH0_FF_TX_PCLK => TX_PCLK_I, +CH1_FF_TX_PCLK => N54_1, +CH0_FF_RX_D_0 => rxdata(0), +CH1_FF_RX_D_0 => N55_1, +CH0_FF_RX_D_1 => rxdata(1), +CH1_FF_RX_D_1 => N56_1, +CH0_FF_RX_D_2 => rxdata(2), +CH1_FF_RX_D_2 => N57_1, +CH0_FF_RX_D_3 => rxdata(3), +CH1_FF_RX_D_3 => N58_1, +CH0_FF_RX_D_4 => rxdata(4), +CH1_FF_RX_D_4 => N59_1, +CH0_FF_RX_D_5 => rxdata(5), +CH1_FF_RX_D_5 => N60_1, +CH0_FF_RX_D_6 => rxdata(6), +CH1_FF_RX_D_6 => N61_1, +CH0_FF_RX_D_7 => rxdata(7), +CH1_FF_RX_D_7 => N62_1, +CH0_FF_RX_D_8 => rx_k(0), +CH1_FF_RX_D_8 => N63_1, +CH0_FF_RX_D_9 => rx_disp_err(0), +CH1_FF_RX_D_9 => N64_1, +CH0_FF_RX_D_10 => rx_cv_err(0), +CH1_FF_RX_D_10 => N65_1, +CH0_FF_RX_D_11 => N10_1, +CH1_FF_RX_D_11 => N66_1, +CH0_FF_RX_D_12 => N67_1, +CH1_FF_RX_D_12 => N68_1, +CH0_FF_RX_D_13 => N69_1, +CH1_FF_RX_D_13 => N70_1, +CH0_FF_RX_D_14 => N71_1, +CH1_FF_RX_D_14 => N72_1, +CH0_FF_RX_D_15 => N73_1, +CH1_FF_RX_D_15 => N74_1, +CH0_FF_RX_D_16 => N75_1, +CH1_FF_RX_D_16 => N76_1, +CH0_FF_RX_D_17 => N77_1, +CH1_FF_RX_D_17 => N78_1, +CH0_FF_RX_D_18 => N79_1, +CH1_FF_RX_D_18 => N80_1, +CH0_FF_RX_D_19 => N81_1, +CH1_FF_RX_D_19 => N82_1, +CH0_FF_RX_D_20 => N83_1, +CH1_FF_RX_D_20 => N84_1, +CH0_FF_RX_D_21 => N85_1, +CH1_FF_RX_D_21 => N86_1, +CH0_FF_RX_D_22 => N87_1, +CH1_FF_RX_D_22 => N88_1, +CH0_FF_RX_D_23 => N11_1, +CH1_FF_RX_D_23 => N89_1, +CH0_FFS_PCIE_DONE => N12_1, +CH1_FFS_PCIE_DONE => N90_1, +CH0_FFS_PCIE_CON => N13_1, +CH1_FFS_PCIE_CON => N91_1, +CH0_FFS_RLOS => RX_LOS_LOW_S_12, +CH1_FFS_RLOS => N92_1, +CH0_FFS_LS_SYNC_STATUS => lsm_status_s, +CH1_FFS_LS_SYNC_STATUS => N93_1, +CH0_FFS_CC_UNDERRUN => ctc_urun_s, +CH1_FFS_CC_UNDERRUN => N94_1, +CH0_FFS_CC_OVERRUN => ctc_orun_s, +CH1_FFS_CC_OVERRUN => N95_1, +CH0_FFS_RXFBFIFO_ERROR => N14_1, +CH1_FFS_RXFBFIFO_ERROR => N96_1, +CH0_FFS_TXFBFIFO_ERROR => N15_1, +CH1_FFS_TXFBFIFO_ERROR => N97_1, +CH0_FFS_RLOL => RX_CDR_LOL_S_13, +CH1_FFS_RLOL => N98_1, +CH0_FFS_SKP_ADDED => ctc_ins_s, +CH1_FFS_SKP_ADDED => N99_1, +CH0_FFS_SKP_DELETED => ctc_del_s, +CH1_FFS_SKP_DELETED => N100_1, +CH0_LDR_RX2CORE => N101_1, +CH1_LDR_RX2CORE => N112_1, +D_SCIRDATA0 => sci_rddata(0), +D_SCIRDATA1 => sci_rddata(1), +D_SCIRDATA2 => sci_rddata(2), +D_SCIRDATA3 => sci_rddata(3), +D_SCIRDATA4 => sci_rddata(4), +D_SCIRDATA5 => sci_rddata(5), +D_SCIRDATA6 => sci_rddata(6), +D_SCIRDATA7 => sci_rddata(7), +D_SCIINT => sci_int, +D_SCAN_OUT_0 => N16_1, +D_SCAN_OUT_1 => N17_1, +D_SCAN_OUT_2 => N18_1, +D_SCAN_OUT_3 => N19_1, +D_SCAN_OUT_4 => N20_1, +D_SCAN_OUT_5 => N21_1, +D_SCAN_OUT_6 => N22_1, +D_SCAN_OUT_7 => N23_1, +D_COUT0 => N24_1, +D_COUT1 => N25_1, +D_COUT2 => N26_1, +D_COUT3 => N27_1, +D_COUT4 => N28_1, +D_COUT5 => N29_1, +D_COUT6 => N30_1, +D_COUT7 => N31_1, +D_COUT8 => N32_1, +D_COUT9 => N33_1, +D_COUT10 => N34_1, +D_COUT11 => N35_1, +D_COUT12 => N36_1, +D_COUT13 => N37_1, +D_COUT14 => N38_1, +D_COUT15 => N39_1, +D_COUT16 => N40_1, +D_COUT17 => N41_1, +D_COUT18 => N42_1, +D_COUT19 => N43_1, +D_REFCLKI => pll_refclki, +D_FFS_PLOL => N46_1); +SLL_INST: sgmii_ecp5sll_core_Z1_layer1 port map ( +tx_pclk => TX_PCLK_11, +sli_rst => sli_rst, +pll_refclki => pll_refclki, +pll_lock_i => \SLL_INST.PLL_LOCK_I_14\); +RSL_INST: sgmii_ecp5rsl_core_Z2_layer1 port map ( +rx_pcs_rst_c => rx_pcs_rst_c, +tx_pcs_rst_c => tx_pcs_rst_c, +tx_serdes_rst_c => tx_serdes_rst_c, +serdes_rst_dual_c => serdes_rst_dual_c, +rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C, +rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C, +rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C, +rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C, +rsl_tx_rdy => rsl_tx_rdy, +pll_lock_i => \SLL_INST.PLL_LOCK_I_14\, +pll_refclki => pll_refclki, +rsl_rx_rdy => rsl_rx_rdy, +rsl_rst => rsl_rst, +rxrefclk => rxrefclk, +rsl_disable => rsl_disable, +rx_serdes_rst_c => rx_serdes_rst_c, +rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C, +rst_dual_c => rst_dual_c, +rx_cdr_lol_s => RX_CDR_LOL_S_13, +rx_los_low_s => RX_LOS_LOW_S_12); +tx_pclk <= TX_PCLK_11; +rx_los_low_s <= RX_LOS_LOW_S_12; +rx_cdr_lol_s <= RX_CDR_LOL_S_13; +pll_lol <= \SLL_INST.PLL_LOCK_I_14\; +end beh; + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vm new file mode 100644 index 0000000..ece1a16 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vm @@ -0,0 +1,6626 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Fri May 10 09:02:16 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v " +// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v " +// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v " +// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v " +// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v " +// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh " +// file 16 "\/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v " +// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 18 "\/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc " + +`timescale 100 ps/100 ps +module sync_0s ( + phb, + rhb_sync, + sli_rst, + pll_refclki +) +; +input phb ; +output rhb_sync ; +input sli_rst ; +input pll_refclki ; +wire phb ; +wire rhb_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_0 ; +wire VCC ; +wire data_p1_QN_0 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(phb), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s */ + +module sync_0s_6 ( + rtc_pul, + ppul_sync, + sli_rst, + tx_pclk +) +; +input rtc_pul ; +output ppul_sync ; +input sli_rst ; +input tx_pclk ; +wire rtc_pul ; +wire ppul_sync ; +wire sli_rst ; +wire tx_pclk ; +wire data_p1 ; +wire data_p2_QN ; +wire VCC ; +wire data_p1_QN ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(rtc_pul), + .CK(tx_pclk), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_6 */ + +module sync_0s_0 ( + ppul_sync, + pdiff_sync, + sli_rst, + pll_refclki +) +; +input ppul_sync ; +output pdiff_sync ; +input sli_rst ; +input pll_refclki ; +wire ppul_sync ; +wire pdiff_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_1 ; +wire VCC ; +wire data_p1_QN_1 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(ppul_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_0 */ + +module sgmii_ecp5sll_core_Z1_layer1 ( + tx_pclk, + sli_rst, + pll_refclki, + pll_lock_i +) +; +input tx_pclk ; +input sli_rst ; +input pll_refclki ; +output pll_lock_i ; +wire tx_pclk ; +wire sli_rst ; +wire pll_refclki ; +wire pll_lock_i ; +wire [2:0] phb_cnt; +wire [2:0] phb_cnt_i; +wire [15:0] rcount; +wire [21:0] pcount; +wire [0:0] un1_pcount_diff_i; +wire [1:0] sll_state; +wire [1:0] sll_state_QN; +wire [7:0] rhb_wait_cnt_s; +wire [7:0] rhb_wait_cnt; +wire [7:0] rhb_wait_cnt_QN; +wire [15:0] rcount_s; +wire [15:0] rcount_QN; +wire [2:0] phb_cnt_QN; +wire [2:1] phb_cnt_RNO; +wire [21:0] pcount_s; +wire [21:0] pcount_QN; +wire [21:0] pcount_diff_QN; +wire [2:2] rdiff_comp_lock; +wire [2:2] rdiff_comp_lock_QN; +wire [0:0] un1_pcount_diff; +wire [20:0] pcount_cry; +wire [0:0] pcount_cry_0_S0; +wire [21:21] pcount_s_0_COUT; +wire [21:21] pcount_s_0_S1; +wire [14:0] rcount_cry; +wire [0:0] rcount_cry_0_S0; +wire [15:15] rcount_s_0_COUT; +wire [15:15] rcount_s_0_S1; +wire [6:0] rhb_wait_cnt_cry; +wire [0:0] rhb_wait_cnt_cry_0_S0; +wire [7:7] rhb_wait_cnt_s_0_COUT; +wire [7:7] rhb_wait_cnt_s_0_S1; +wire pll_lock ; +wire rtc_ctrl4_0_a3_1 ; +wire un13_lock_20 ; +wire ppul_sync_p2 ; +wire ppul_sync_p1 ; +wire un1_pcount_diff_1_axb_20 ; +wire un13_lock_19 ; +wire un1_pcount_diff_1_axb_19 ; +wire un13_lock_18 ; +wire un1_pcount_diff_1_axb_18 ; +wire un13_lock_17 ; +wire un1_pcount_diff_1_cry_17_0_RNO ; +wire un13_lock_16 ; +wire un1_pcount_diff_1_axb_16 ; +wire un13_lock_15 ; +wire un1_pcount_diff_1_axb_15 ; +wire un13_lock_14 ; +wire un1_pcount_diff_1_axb_14 ; +wire un13_lock_13 ; +wire un1_pcount_diff_1_axb_13 ; +wire un13_lock_12 ; +wire un1_pcount_diff_1_axb_12 ; +wire un13_lock_11 ; +wire un1_pcount_diff_1_axb_11 ; +wire un13_lock_10 ; +wire un1_pcount_diff_1_axb_10 ; +wire un13_lock_9 ; +wire un1_pcount_diff_1_axb_9 ; +wire un13_lock_8 ; +wire un1_pcount_diff_1_axb_8 ; +wire un13_lock_7 ; +wire un1_pcount_diff_1_axb_7 ; +wire un13_lock_6 ; +wire un1_pcount_diff_1_axb_6 ; +wire un13_lock_5 ; +wire un1_pcount_diff_1_axb_5 ; +wire un13_lock_4 ; +wire un1_pcount_diff_1_axb_4 ; +wire un13_lock_3 ; +wire un1_pcount_diff_1_axb_3 ; +wire un13_lock_2 ; +wire un1_pcount_diff_1_axb_2 ; +wire un13_lock_1 ; +wire un1_pcount_diff_1_axb_1 ; +wire un13_lock_21 ; +wire ppul_sync_p3 ; +wire N_7 ; +wire un13_lock_0 ; +wire rtc_ctrl4 ; +wire rtc_ctrl ; +wire VCC ; +wire N_2085_0 ; +wire unlock_5 ; +wire unlock_1_sqmuxa_i ; +wire unlock ; +wire unlock_QN ; +wire N_95_i ; +wire N_97_i ; +wire rtc_pul ; +wire rtc_pul_p1 ; +wire rtc_pul_p1_QN ; +wire rtc_pul5 ; +wire rtc_pul_QN ; +wire rtc_ctrl_QN ; +wire rstat_pclk_2 ; +wire rstat_pclk ; +wire rstat_pclk_QN ; +wire rhb_sync_p1 ; +wire rhb_sync_p2 ; +wire rhb_sync_p2_QN ; +wire rhb_sync ; +wire rhb_sync_p1_QN ; +wire ppul_sync_p3_QN ; +wire ppul_sync_p2_QN ; +wire ppul_sync ; +wire ppul_sync_p1_QN ; +wire N_53_i ; +wire pll_lock_QN ; +wire phb ; +wire phb_QN ; +wire pdiff_sync ; +wire pdiff_sync_p1 ; +wire pdiff_sync_p1_QN ; +wire un1_pcount_diff_1_cry_1_0_S0 ; +wire un1_pcount_diff_1_cry_1_0_S1 ; +wire un1_pcount_diff_1_cry_3_0_S0 ; +wire un1_pcount_diff_1_cry_3_0_S1 ; +wire un1_pcount_diff_1_cry_5_0_S0 ; +wire un1_pcount_diff_1_cry_5_0_S1 ; +wire un1_pcount_diff_1_cry_7_0_S0 ; +wire un1_pcount_diff_1_cry_7_0_S1 ; +wire un1_pcount_diff_1_cry_9_0_S0 ; +wire un1_pcount_diff_1_cry_9_0_S1 ; +wire un1_pcount_diff_1_cry_11_0_S0 ; +wire un1_pcount_diff_1_cry_11_0_S1 ; +wire un1_pcount_diff_1_cry_13_0_S0 ; +wire un1_pcount_diff_1_cry_13_0_S1 ; +wire un1_pcount_diff_1_cry_15_0_S0 ; +wire un1_pcount_diff_1_cry_15_0_S1 ; +wire un1_pcount_diff_1_cry_17_0_S0 ; +wire un1_pcount_diff_1_cry_17_0_S1 ; +wire un1_pcount_diff_1_cry_19_0_S0 ; +wire un1_pcount_diff_1_cry_19_0_S1 ; +wire un1_pcount_diff_1_s_21_0_S0 ; +wire lock_5 ; +wire lock_1_sqmuxa_i ; +wire lock ; +wire lock_QN ; +wire N_98 ; +wire rtc_pul5_0_o3 ; +wire rtc_pul5_0_a3_6 ; +wire rtc_pul5_0_a3_7 ; +wire un1_rcount_1_0_a3 ; +wire rhb_wait_cnt12 ; +wire un1_rhb_wait_cnt_4 ; +wire un1_rhb_wait_cnt_5 ; +wire N_99 ; +wire rtc_ctrl4_0_a3_12_4 ; +wire rtc_ctrl4_0_a3_12_5 ; +wire rtc_ctrl4_10 ; +wire un1_rcount_1_0_a3_1 ; +wire N_6 ; +wire rtc_pul5_0_a3_5 ; +wire N_8 ; +wire un13_unlock_cry_21 ; +wire un13_lock_cry_21_i ; +wire rhb_wait_cnt_scalar ; +wire un1_pcount_diff_1_cry_0 ; +wire un1_pcount_diff_1_cry_0_0_S0 ; +wire un1_pcount_diff_1_cry_0_0_S1 ; +wire un1_pcount_diff_1_cry_2 ; +wire un1_pcount_diff_1_cry_4 ; +wire un1_pcount_diff_1_cry_6 ; +wire un1_pcount_diff_1_cry_8 ; +wire un1_pcount_diff_1_cry_10 ; +wire un1_pcount_diff_1_cry_12 ; +wire un1_pcount_diff_1_cry_14 ; +wire un1_pcount_diff_1_cry_16 ; +wire un1_pcount_diff_1_cry_18 ; +wire un1_pcount_diff_1_cry_20 ; +wire un1_pcount_diff_1_s_21_0_COUT ; +wire un1_pcount_diff_1_s_21_0_S1 ; +wire un13_lock_cry_0 ; +wire un13_lock_cry_0_0_S0 ; +wire un13_lock_cry_0_0_S1 ; +wire un13_lock_cry_2 ; +wire un13_lock_cry_1_0_S0 ; +wire un13_lock_cry_1_0_S1 ; +wire un13_lock_cry_4 ; +wire un13_lock_cry_3_0_S0 ; +wire un13_lock_cry_3_0_S1 ; +wire un13_lock_cry_6 ; +wire un13_lock_cry_5_0_S0 ; +wire un13_lock_cry_5_0_S1 ; +wire un13_lock_cry_8 ; +wire un13_lock_cry_7_0_S0 ; +wire un13_lock_cry_7_0_S1 ; +wire un13_lock_cry_10 ; +wire un13_lock_cry_9_0_S0 ; +wire un13_lock_cry_9_0_S1 ; +wire un13_lock_cry_12 ; +wire un13_lock_cry_11_0_S0 ; +wire un13_lock_cry_11_0_S1 ; +wire un13_lock_cry_14 ; +wire un13_lock_cry_13_0_S0 ; +wire un13_lock_cry_13_0_S1 ; +wire un13_lock_cry_16 ; +wire un13_lock_cry_15_0_S0 ; +wire un13_lock_cry_15_0_S1 ; +wire un13_lock_cry_18 ; +wire un13_lock_cry_17_0_S0 ; +wire un13_lock_cry_17_0_S1 ; +wire un13_lock_cry_20 ; +wire un13_lock_cry_19_0_S0 ; +wire un13_lock_cry_19_0_S1 ; +wire un13_lock_cry_21_0_COUT ; +wire un13_lock_cry_21_0_S0 ; +wire un13_unlock_cry_0 ; +wire un13_unlock_cry_0_0_S0 ; +wire un13_unlock_cry_0_0_S1 ; +wire un13_unlock_cry_2 ; +wire un13_unlock_cry_1_0_S0 ; +wire un13_unlock_cry_1_0_S1 ; +wire un13_unlock_cry_4 ; +wire un13_unlock_cry_3_0_S0 ; +wire un13_unlock_cry_3_0_S1 ; +wire un13_unlock_cry_6 ; +wire un13_unlock_cry_5_0_S0 ; +wire un13_unlock_cry_5_0_S1 ; +wire un13_unlock_cry_8 ; +wire un13_unlock_cry_7_0_S0 ; +wire un13_unlock_cry_7_0_S1 ; +wire un13_unlock_cry_10 ; +wire un13_unlock_cry_9_0_S0 ; +wire un13_unlock_cry_9_0_S1 ; +wire un13_unlock_cry_12 ; +wire un13_unlock_cry_11_0_S0 ; +wire un13_unlock_cry_11_0_S1 ; +wire un13_unlock_cry_14 ; +wire un13_unlock_cry_13_0_S0 ; +wire un13_unlock_cry_13_0_S1 ; +wire un13_unlock_cry_16 ; +wire un13_unlock_cry_15_0_S0 ; +wire un13_unlock_cry_15_0_S1 ; +wire un13_unlock_cry_18 ; +wire un13_unlock_cry_17_0_S0 ; +wire un13_unlock_cry_17_0_S1 ; +wire un13_unlock_cry_20 ; +wire un13_unlock_cry_19_0_S0 ; +wire un13_unlock_cry_19_0_S1 ; +wire un13_unlock_cry_21_0_COUT ; +wire un13_unlock_cry_21_0_S0 ; +wire N_21 ; +wire N_20 ; +wire N_19 ; +wire N_18 ; +wire N_14 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_9 ; + INV phb_RNO ( + .A(phb_cnt[2]), + .Z(phb_cnt_i[2]) +); + INV \phb_cnt_RNO[0] ( + .A(phb_cnt[0]), + .Z(phb_cnt_i[0]) +); + INV pll_lock_RNI6JK9 ( + .A(pll_lock), + .Z(pll_lock_i) +); + LUT4 rtc_ctrl4_0_a3_RNO ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(rtc_ctrl4_0_a3_1) +); +defparam rtc_ctrl4_0_a3_RNO.init=16'h2000; + LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 ( + .A(un13_lock_20), + .B(pcount[20]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_20) +); +defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_19_0_RNO ( + .A(un13_lock_19), + .B(pcount[19]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_19) +); +defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 ( + .A(un13_lock_18), + .B(pcount[18]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_18) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_cZ ( + .A(un13_lock_17), + .B(pcount[17]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_cry_17_0_RNO) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_cZ.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO_0 ( + .A(un13_lock_16), + .B(pcount[16]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_16) +); +defparam un1_pcount_diff_1_cry_15_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO ( + .A(un13_lock_15), + .B(pcount[15]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_15) +); +defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 ( + .A(un13_lock_14), + .B(pcount[14]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_14) +); +defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO ( + .A(un13_lock_13), + .B(pcount[13]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_13) +); +defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 ( + .A(un13_lock_12), + .B(pcount[12]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_12) +); +defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO ( + .A(un13_lock_11), + .B(pcount[11]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_11) +); +defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 ( + .A(un13_lock_10), + .B(pcount[10]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_10) +); +defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO ( + .A(un13_lock_9), + .B(pcount[9]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_9) +); +defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 ( + .A(un13_lock_8), + .B(pcount[8]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_8) +); +defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO ( + .A(un13_lock_7), + .B(pcount[7]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_7) +); +defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 ( + .A(un13_lock_6), + .B(pcount[6]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_6) +); +defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO ( + .A(un13_lock_5), + .B(pcount[5]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_5) +); +defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 ( + .A(un13_lock_4), + .B(pcount[4]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_4) +); +defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO ( + .A(un13_lock_3), + .B(pcount[3]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_3) +); +defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 ( + .A(un13_lock_2), + .B(pcount[2]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_2) +); +defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO ( + .A(un13_lock_1), + .B(pcount[1]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_1) +); +defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355; + LUT4 ppul_sync_p3_RNIU65C ( + .A(un13_lock_21), + .B(ppul_sync_p3), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(N_7) +); +defparam ppul_sync_p3_RNIU65C.init=16'h2F20; + LUT4 \pcount_diff_RNO[0] ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(pcount[0]), + .D(un13_lock_0), + .Z(un1_pcount_diff_i[0]) +); +defparam \pcount_diff_RNO[0] .init=16'hFD20; +// @16:1304 + LUT4 rtc_ctrl_0 ( + .A(rtc_ctrl4), + .B(rtc_ctrl), + .C(VCC), + .D(VCC), + .Z(N_2085_0) +); +defparam rtc_ctrl_0.init=16'hEEEE; +// @16:1278 + FD1P3DX unlock_reg ( + .D(unlock_5), + .SP(unlock_1_sqmuxa_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(unlock) +); +// @16:1801 + FD1S3DX \sll_state_reg[0] ( + .D(N_95_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[0]) +); +// @16:1801 + FD1S3DX \sll_state_reg[1] ( + .D(N_97_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[1]) +); +// @16:1304 + FD1S3DX rtc_pul_p1_reg ( + .D(rtc_pul), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul_p1) +); +// @16:1304 + FD1P3DX rtc_pul_reg ( + .D(rtc_pul5), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul) +); +// @16:1304 + FD1S3DX rtc_ctrl_reg ( + .D(N_2085_0), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_ctrl) +); +// @16:1350 + FD1P3DX rstat_pclk_reg ( + .D(rstat_pclk_2), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rstat_pclk) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[0] ( + .D(rhb_wait_cnt_s[0]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[0]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[1] ( + .D(rhb_wait_cnt_s[1]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[1]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[2] ( + .D(rhb_wait_cnt_s[2]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[2]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[3] ( + .D(rhb_wait_cnt_s[3]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[3]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[4] ( + .D(rhb_wait_cnt_s[4]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[4]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[5] ( + .D(rhb_wait_cnt_s[5]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[5]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[6] ( + .D(rhb_wait_cnt_s[6]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[6]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[7] ( + .D(rhb_wait_cnt_s[7]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[7]) +); +// @16:1350 + FD1S3DX rhb_sync_p2_reg ( + .D(rhb_sync_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p2) +); +// @16:1350 + FD1S3DX rhb_sync_p1_reg ( + .D(rhb_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p1) +); +// @16:1304 + FD1S3DX \rcount_reg[0] ( + .D(rcount_s[0]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[0]) +); +// @16:1304 + FD1S3DX \rcount_reg[1] ( + .D(rcount_s[1]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[1]) +); +// @16:1304 + FD1S3DX \rcount_reg[2] ( + .D(rcount_s[2]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[2]) +); +// @16:1304 + FD1S3DX \rcount_reg[3] ( + .D(rcount_s[3]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[3]) +); +// @16:1304 + FD1S3DX \rcount_reg[4] ( + .D(rcount_s[4]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[4]) +); +// @16:1304 + FD1S3DX \rcount_reg[5] ( + .D(rcount_s[5]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[5]) +); +// @16:1304 + FD1S3DX \rcount_reg[6] ( + .D(rcount_s[6]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[6]) +); +// @16:1304 + FD1S3DX \rcount_reg[7] ( + .D(rcount_s[7]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[7]) +); +// @16:1304 + FD1S3DX \rcount_reg[8] ( + .D(rcount_s[8]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[8]) +); +// @16:1304 + FD1S3DX \rcount_reg[9] ( + .D(rcount_s[9]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[9]) +); +// @16:1304 + FD1S3DX \rcount_reg[10] ( + .D(rcount_s[10]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[10]) +); +// @16:1304 + FD1S3DX \rcount_reg[11] ( + .D(rcount_s[11]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[11]) +); +// @16:1304 + FD1S3DX \rcount_reg[12] ( + .D(rcount_s[12]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[12]) +); +// @16:1304 + FD1S3DX \rcount_reg[13] ( + .D(rcount_s[13]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[13]) +); +// @16:1304 + FD1S3DX \rcount_reg[14] ( + .D(rcount_s[14]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[14]) +); +// @16:1304 + FD1S3DX \rcount_reg[15] ( + .D(rcount_s[15]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[15]) +); +// @16:1408 + FD1S3DX ppul_sync_p3_reg ( + .D(ppul_sync_p2), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p3) +); +// @16:1408 + FD1S3DX ppul_sync_p2_reg ( + .D(ppul_sync_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p2) +); +// @16:1408 + FD1S3DX ppul_sync_p1_reg ( + .D(ppul_sync), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p1) +); +// @16:1879 + FD1S3DX pll_lock_reg ( + .D(N_53_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pll_lock) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[0] ( + .D(phb_cnt_i[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[0]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[1] ( + .D(phb_cnt_RNO[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[1]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[2] ( + .D(phb_cnt_RNO[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[2]) +); +// @16:1759 + FD1S3DX phb_reg ( + .D(phb_cnt_i[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb) +); +// @16:1278 + FD1S3DX pdiff_sync_p1_reg ( + .D(pdiff_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync_p1) +); +// @16:1759 + FD1S3DX \pcount_reg[0] ( + .D(pcount_s[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[0]) +); +// @16:1759 + FD1P3BX \pcount_diff[0] ( + .D(un1_pcount_diff_i[0]), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_0) +); +// @16:1759 + FD1S3DX \pcount_reg[1] ( + .D(pcount_s[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[1]) +); +// @16:1759 + FD1P3BX \pcount_diff[1] ( + .D(un1_pcount_diff_1_cry_1_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_1) +); +// @16:1759 + FD1P3BX \pcount_diff[2] ( + .D(un1_pcount_diff_1_cry_1_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_2) +); +// @16:1759 + FD1S3DX \pcount_reg[2] ( + .D(pcount_s[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[2]) +); +// @16:1759 + FD1P3BX \pcount_diff[3] ( + .D(un1_pcount_diff_1_cry_3_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_3) +); +// @16:1759 + FD1S3DX \pcount_reg[3] ( + .D(pcount_s[3]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[3]) +); +// @16:1759 + FD1P3BX \pcount_diff[4] ( + .D(un1_pcount_diff_1_cry_3_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_4) +); +// @16:1759 + FD1S3DX \pcount_reg[4] ( + .D(pcount_s[4]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[4]) +); +// @16:1759 + FD1P3BX \pcount_diff[5] ( + .D(un1_pcount_diff_1_cry_5_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_5) +); +// @16:1759 + FD1S3DX \pcount_reg[5] ( + .D(pcount_s[5]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[5]) +); +// @16:1759 + FD1S3DX \pcount_reg[6] ( + .D(pcount_s[6]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[6]) +); +// @16:1759 + FD1P3BX \pcount_diff[6] ( + .D(un1_pcount_diff_1_cry_5_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_6) +); +// @16:1759 + FD1S3DX \pcount_reg[7] ( + .D(pcount_s[7]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[7]) +); +// @16:1759 + FD1P3BX \pcount_diff[7] ( + .D(un1_pcount_diff_1_cry_7_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_7) +); +// @16:1759 + FD1S3DX \pcount_reg[8] ( + .D(pcount_s[8]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[8]) +); +// @16:1759 + FD1P3BX \pcount_diff[8] ( + .D(un1_pcount_diff_1_cry_7_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_8) +); +// @16:1759 + FD1P3BX \pcount_diff[9] ( + .D(un1_pcount_diff_1_cry_9_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_9) +); +// @16:1759 + FD1S3DX \pcount_reg[9] ( + .D(pcount_s[9]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[9]) +); +// @16:1759 + FD1S3DX \pcount_reg[10] ( + .D(pcount_s[10]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[10]) +); +// @16:1759 + FD1P3BX \pcount_diff[10] ( + .D(un1_pcount_diff_1_cry_9_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_10) +); +// @16:1759 + FD1P3BX \pcount_diff[11] ( + .D(un1_pcount_diff_1_cry_11_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_11) +); +// @16:1759 + FD1S3DX \pcount_reg[11] ( + .D(pcount_s[11]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[11]) +); +// @16:1759 + FD1S3DX \pcount_reg[12] ( + .D(pcount_s[12]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[12]) +); +// @16:1759 + FD1P3BX \pcount_diff[12] ( + .D(un1_pcount_diff_1_cry_11_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_12) +); +// @16:1759 + FD1P3BX \pcount_diff[13] ( + .D(un1_pcount_diff_1_cry_13_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_13) +); +// @16:1759 + FD1S3DX \pcount_reg[13] ( + .D(pcount_s[13]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[13]) +); +// @16:1759 + FD1P3BX \pcount_diff[14] ( + .D(un1_pcount_diff_1_cry_13_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_14) +); +// @16:1759 + FD1S3DX \pcount_reg[14] ( + .D(pcount_s[14]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[14]) +); +// @16:1759 + FD1S3DX \pcount_reg[15] ( + .D(pcount_s[15]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[15]) +); +// @16:1759 + FD1P3BX \pcount_diff[15] ( + .D(un1_pcount_diff_1_cry_15_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_15) +); +// @16:1759 + FD1S3DX \pcount_reg[16] ( + .D(pcount_s[16]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[16]) +); +// @16:1759 + FD1P3DX \pcount_diff[16] ( + .D(un1_pcount_diff_1_cry_15_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_16) +); +// @16:1759 + FD1P3DX \pcount_diff[17] ( + .D(un1_pcount_diff_1_cry_17_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_17) +); +// @16:1759 + FD1S3DX \pcount_reg[17] ( + .D(pcount_s[17]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[17]) +); +// @16:1759 + FD1P3DX \pcount_diff[18] ( + .D(un1_pcount_diff_1_cry_17_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_18) +); +// @16:1759 + FD1S3DX \pcount_reg[18] ( + .D(pcount_s[18]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[18]) +); +// @16:1759 + FD1S3DX \pcount_reg[19] ( + .D(pcount_s[19]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[19]) +); +// @16:1759 + FD1P3DX \pcount_diff[19] ( + .D(un1_pcount_diff_1_cry_19_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_19) +); +// @16:1759 + FD1S3DX \pcount_reg[20] ( + .D(pcount_s[20]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[20]) +); +// @16:1759 + FD1P3DX \pcount_diff[20] ( + .D(un1_pcount_diff_1_cry_19_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_20) +); +// @16:1759 + FD1P3DX \pcount_diff[21] ( + .D(un1_pcount_diff_1_s_21_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_21) +); +// @16:1759 + FD1S3DX \pcount_reg[21] ( + .D(pcount_s[21]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[21]) +); +// @16:1278 + FD1P3DX lock_reg ( + .D(lock_5), + .SP(lock_1_sqmuxa_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(lock) +); +// @16:1739 + FD1S3DX \genblk5.rdiff_comp_lock[2] ( + .D(VCC), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rdiff_comp_lock[2]) +); +// @16:1801 + LUT4 \sll_state_RNO[0] ( + .A(N_98), + .B(lock), + .C(rstat_pclk), + .D(sll_state[0]), + .Z(N_95_i) +); +defparam \sll_state_RNO[0] .init=16'hE050; +// @16:1334 + LUT4 rtc_pul5_0_0 ( + .A(rtc_pul5_0_o3), + .B(rtc_pul5_0_a3_6), + .C(rtc_pul5_0_a3_7), + .D(un1_rcount_1_0_a3), + .Z(rtc_pul5) +); +defparam rtc_pul5_0_0.init=16'hFF80; +// @16:1389 + LUT4 rstat_pclk_2_iv ( + .A(rhb_wait_cnt12), + .B(rstat_pclk), + .C(un1_rhb_wait_cnt_4), + .D(un1_rhb_wait_cnt_5), + .Z(rstat_pclk_2) +); +defparam rstat_pclk_2_iv.init=16'hAEEE; +// @16:1801 + LUT4 \sll_state_RNO[1] ( + .A(N_99), + .B(rstat_pclk), + .C(sll_state[1]), + .D(unlock), + .Z(N_97_i) +); +defparam \sll_state_RNO[1] .init=16'h8088; +// @16:1328 + LUT4 rtc_ctrl4_0_a3 ( + .A(rtc_ctrl4_0_a3_1), + .B(rtc_ctrl4_0_a3_12_4), + .C(rtc_ctrl4_0_a3_12_5), + .D(rtc_ctrl4_10), + .Z(rtc_ctrl4) +); +defparam rtc_ctrl4_0_a3.init=16'h8000; +// @16:1319 + LUT4 un1_rcount_1_0_a3_cZ ( + .A(rtc_ctrl4_0_a3_12_4), + .B(rtc_ctrl4_0_a3_12_5), + .C(rtc_ctrl4_10), + .D(un1_rcount_1_0_a3_1), + .Z(un1_rcount_1_0_a3) +); +defparam un1_rcount_1_0_a3_cZ.init=16'h8000; +// @16:1278 + LUT4 lock_1_sqmuxa_i_cZ ( + .A(lock), + .B(pdiff_sync), + .C(pdiff_sync_p1), + .D(VCC), + .Z(lock_1_sqmuxa_i) +); +defparam lock_1_sqmuxa_i_cZ.init=16'h7575; +// @16:1278 + LUT4 unlock_1_sqmuxa_i_cZ ( + .A(pdiff_sync), + .B(pdiff_sync_p1), + .C(unlock), + .D(VCC), + .Z(unlock_1_sqmuxa_i) +); +defparam unlock_1_sqmuxa_i_cZ.init=16'h4F4F; +// @16:1334 + LUT4 rtc_pul5_0_o3_cZ ( + .A(N_6), + .B(rcount[1]), + .C(rcount[2]), + .D(rcount[3]), + .Z(rtc_pul5_0_o3) +); +defparam rtc_pul5_0_o3_cZ.init=16'hAAAB; +// @16:1334 + LUT4 rtc_pul5_0_a3_7_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rtc_pul5_0_a3_5), + .D(VCC), + .Z(rtc_pul5_0_a3_7) +); +defparam rtc_pul5_0_a3_7_cZ.init=16'h1010; +// @16:1801 + LUT4 \sll_state_ns_i_m4[1] ( + .A(lock), + .B(rtc_pul), + .C(rtc_pul_p1), + .D(sll_state[1]), + .Z(N_99) +); +defparam \sll_state_ns_i_m4[1] .init=16'hEF20; +// @16:1879 + LUT4 pll_lock_RNO ( + .A(sll_state[0]), + .B(sll_state[1]), + .C(VCC), + .D(VCC), + .Z(N_53_i) +); +defparam pll_lock_RNO.init=16'h8888; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[2] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(phb_cnt[2]), + .D(VCC), + .Z(phb_cnt_RNO[2]) +); +defparam \phb_cnt_RNO_cZ[2] .init=16'h7878; +// @16:1801 + LUT4 \sll_state_ns_i_o4[0] ( + .A(rtc_pul), + .B(rtc_pul_p1), + .C(sll_state[1]), + .D(VCC), + .Z(N_98) +); +defparam \sll_state_ns_i_o4[0] .init=16'hBFBF; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_10 ( + .A(rcount[1]), + .B(rcount[3]), + .C(rcount[6]), + .D(rcount[15]), + .Z(rtc_ctrl4_10) +); +defparam rtc_ctrl4_0_a3_10.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_4_cZ ( + .A(rhb_wait_cnt[4]), + .B(rhb_wait_cnt[5]), + .C(rhb_wait_cnt[6]), + .D(rhb_wait_cnt[7]), + .Z(un1_rhb_wait_cnt_4) +); +defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_5_cZ ( + .A(rhb_wait_cnt[0]), + .B(rhb_wait_cnt[1]), + .C(rhb_wait_cnt[2]), + .D(rhb_wait_cnt[3]), + .Z(un1_rhb_wait_cnt_5) +); +defparam un1_rhb_wait_cnt_5_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_4_cZ ( + .A(rcount[11]), + .B(rcount[12]), + .C(rcount[13]), + .D(rcount[14]), + .Z(rtc_ctrl4_0_a3_12_4) +); +defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_5_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rcount[9]), + .D(rcount[10]), + .Z(rtc_ctrl4_0_a3_12_5) +); +defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000; +// @16:1334 + LUT4 rtc_pul5_0_a3_5_cZ ( + .A(rcount[6]), + .B(rcount[13]), + .C(rcount[14]), + .D(rcount[15]), + .Z(rtc_pul5_0_a3_5) +); +defparam rtc_pul5_0_a3_5_cZ.init=16'h0001; +// @16:1334 + LUT4 rtc_pul5_0_a3_6_cZ ( + .A(rcount[9]), + .B(rcount[10]), + .C(rcount[11]), + .D(rcount[12]), + .Z(rtc_pul5_0_a3_6) +); +defparam rtc_pul5_0_a3_6_cZ.init=16'h0001; +// @16:1768 + LUT4 pcount10_0_o3 ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(VCC), + .D(VCC), + .Z(N_8) +); +defparam pcount10_0_o3.init=16'hDDDD; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[1] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(VCC), + .D(VCC), + .Z(phb_cnt_RNO[1]) +); +defparam \phb_cnt_RNO_cZ[1] .init=16'h6666; +// @16:1328 + LUT4 rtc_ctrl4_0_o3 ( + .A(rcount[4]), + .B(rcount[5]), + .C(VCC), + .D(VCC), + .Z(N_6) +); +defparam rtc_ctrl4_0_o3.init=16'h7777; +// @16:1286 + LUT4 unlock_5_cZ ( + .A(pdiff_sync), + .B(un13_unlock_cry_21), + .C(VCC), + .D(VCC), + .Z(unlock_5) +); +defparam unlock_5_cZ.init=16'h8888; +// @16:1292 + LUT4 lock_5_cZ ( + .A(pdiff_sync), + .B(un13_lock_cry_21_i), + .C(VCC), + .D(VCC), + .Z(lock_5) +); +defparam lock_5_cZ.init=16'h8888; +// @16:1389 + LUT4 rhb_wait_cnt12_cZ ( + .A(rhb_sync_p1), + .B(rhb_sync_p2), + .C(VCC), + .D(VCC), + .Z(rhb_wait_cnt12) +); +defparam rhb_wait_cnt12_cZ.init=16'h2222; +// @16:1786 + LUT4 \un1_pcount_diff_cZ[0] ( + .A(un13_lock_0), + .B(pcount[0]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff[0]) +); +defparam \un1_pcount_diff_cZ[0] .init=16'h5355; +// @16:1319 + LUT4 un1_rcount_1_0_a3_1_cZ ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(un1_rcount_1_0_a3_1) +); +defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000; +// @16:1350 + LUT4 rhb_sync_p2_RNIU9TG1 ( + .A(un1_rhb_wait_cnt_5), + .B(un1_rhb_wait_cnt_4), + .C(rhb_sync_p2), + .D(rhb_sync_p1), + .Z(rhb_wait_cnt_scalar) +); +defparam rhb_sync_p2_RNIU9TG1.init=16'h7077; + CCU2C \pcount_cry_0[0] ( + .A0(VCC), + .B0(N_8), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_9), + .COUT(pcount_cry[0]), + .S0(pcount_cry_0_S0[0]), + .S1(pcount_s[0]) +); +defparam \pcount_cry_0[0] .INIT0=16'h500c; +defparam \pcount_cry_0[0] .INIT1=16'h8000; +defparam \pcount_cry_0[0] .INJECT1_0="NO"; +defparam \pcount_cry_0[0] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[1] ( + .A0(N_8), + .B0(pcount[1]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[0]), + .COUT(pcount_cry[2]), + .S0(pcount_s[1]), + .S1(pcount_s[2]) +); +defparam \pcount_cry_0[1] .INIT0=16'h8000; +defparam \pcount_cry_0[1] .INIT1=16'h8000; +defparam \pcount_cry_0[1] .INJECT1_0="NO"; +defparam \pcount_cry_0[1] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[3] ( + .A0(N_8), + .B0(pcount[3]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[2]), + .COUT(pcount_cry[4]), + .S0(pcount_s[3]), + .S1(pcount_s[4]) +); +defparam \pcount_cry_0[3] .INIT0=16'h8000; +defparam \pcount_cry_0[3] .INIT1=16'h8000; +defparam \pcount_cry_0[3] .INJECT1_0="NO"; +defparam \pcount_cry_0[3] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[5] ( + .A0(N_8), + .B0(pcount[5]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[4]), + .COUT(pcount_cry[6]), + .S0(pcount_s[5]), + .S1(pcount_s[6]) +); +defparam \pcount_cry_0[5] .INIT0=16'h8000; +defparam \pcount_cry_0[5] .INIT1=16'h8000; +defparam \pcount_cry_0[5] .INJECT1_0="NO"; +defparam \pcount_cry_0[5] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[7] ( + .A0(N_8), + .B0(pcount[7]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[6]), + .COUT(pcount_cry[8]), + .S0(pcount_s[7]), + .S1(pcount_s[8]) +); +defparam \pcount_cry_0[7] .INIT0=16'h8000; +defparam \pcount_cry_0[7] .INIT1=16'h8000; +defparam \pcount_cry_0[7] .INJECT1_0="NO"; +defparam \pcount_cry_0[7] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[9] ( + .A0(N_8), + .B0(pcount[9]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[8]), + .COUT(pcount_cry[10]), + .S0(pcount_s[9]), + .S1(pcount_s[10]) +); +defparam \pcount_cry_0[9] .INIT0=16'h8000; +defparam \pcount_cry_0[9] .INIT1=16'h8000; +defparam \pcount_cry_0[9] .INJECT1_0="NO"; +defparam \pcount_cry_0[9] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[11] ( + .A0(N_8), + .B0(pcount[11]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[10]), + .COUT(pcount_cry[12]), + .S0(pcount_s[11]), + .S1(pcount_s[12]) +); +defparam \pcount_cry_0[11] .INIT0=16'h8000; +defparam \pcount_cry_0[11] .INIT1=16'h8000; +defparam \pcount_cry_0[11] .INJECT1_0="NO"; +defparam \pcount_cry_0[11] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[13] ( + .A0(N_8), + .B0(pcount[13]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[12]), + .COUT(pcount_cry[14]), + .S0(pcount_s[13]), + .S1(pcount_s[14]) +); +defparam \pcount_cry_0[13] .INIT0=16'h8000; +defparam \pcount_cry_0[13] .INIT1=16'h8000; +defparam \pcount_cry_0[13] .INJECT1_0="NO"; +defparam \pcount_cry_0[13] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[15] ( + .A0(N_8), + .B0(pcount[15]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[16]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[14]), + .COUT(pcount_cry[16]), + .S0(pcount_s[15]), + .S1(pcount_s[16]) +); +defparam \pcount_cry_0[15] .INIT0=16'h8000; +defparam \pcount_cry_0[15] .INIT1=16'h8000; +defparam \pcount_cry_0[15] .INJECT1_0="NO"; +defparam \pcount_cry_0[15] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[17] ( + .A0(N_8), + .B0(pcount[17]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[18]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[16]), + .COUT(pcount_cry[18]), + .S0(pcount_s[17]), + .S1(pcount_s[18]) +); +defparam \pcount_cry_0[17] .INIT0=16'h8000; +defparam \pcount_cry_0[17] .INIT1=16'h8000; +defparam \pcount_cry_0[17] .INJECT1_0="NO"; +defparam \pcount_cry_0[17] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[19] ( + .A0(N_8), + .B0(pcount[19]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[20]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[18]), + .COUT(pcount_cry[20]), + .S0(pcount_s[19]), + .S1(pcount_s[20]) +); +defparam \pcount_cry_0[19] .INIT0=16'h8000; +defparam \pcount_cry_0[19] .INIT1=16'h8000; +defparam \pcount_cry_0[19] .INJECT1_0="NO"; +defparam \pcount_cry_0[19] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_s_0[21] ( + .A0(N_8), + .B0(pcount[21]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[20]), + .COUT(pcount_s_0_COUT[21]), + .S0(pcount_s[21]), + .S1(pcount_s_0_S1[21]) +); +defparam \pcount_s_0[21] .INIT0=16'h800a; +defparam \pcount_s_0[21] .INIT1=16'h5003; +defparam \pcount_s_0[21] .INJECT1_0="NO"; +defparam \pcount_s_0[21] .INJECT1_1="NO"; + CCU2C \rcount_cry_0[0] ( + .A0(VCC), + .B0(un1_rcount_1_0_a3), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(rcount_cry[0]), + .S0(rcount_cry_0_S0[0]), + .S1(rcount_s[0]) +); +defparam \rcount_cry_0[0] .INIT0=16'h5003; +defparam \rcount_cry_0[0] .INIT1=16'h4000; +defparam \rcount_cry_0[0] .INJECT1_0="NO"; +defparam \rcount_cry_0[0] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[1] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[1]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[0]), + .COUT(rcount_cry[2]), + .S0(rcount_s[1]), + .S1(rcount_s[2]) +); +defparam \rcount_cry_0[1] .INIT0=16'h4000; +defparam \rcount_cry_0[1] .INIT1=16'h4000; +defparam \rcount_cry_0[1] .INJECT1_0="NO"; +defparam \rcount_cry_0[1] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[3] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[3]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[2]), + .COUT(rcount_cry[4]), + .S0(rcount_s[3]), + .S1(rcount_s[4]) +); +defparam \rcount_cry_0[3] .INIT0=16'h4000; +defparam \rcount_cry_0[3] .INIT1=16'h4000; +defparam \rcount_cry_0[3] .INJECT1_0="NO"; +defparam \rcount_cry_0[3] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[5] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[5]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[4]), + .COUT(rcount_cry[6]), + .S0(rcount_s[5]), + .S1(rcount_s[6]) +); +defparam \rcount_cry_0[5] .INIT0=16'h4000; +defparam \rcount_cry_0[5] .INIT1=16'h4000; +defparam \rcount_cry_0[5] .INJECT1_0="NO"; +defparam \rcount_cry_0[5] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[7] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[7]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[6]), + .COUT(rcount_cry[8]), + .S0(rcount_s[7]), + .S1(rcount_s[8]) +); +defparam \rcount_cry_0[7] .INIT0=16'h4000; +defparam \rcount_cry_0[7] .INIT1=16'h4000; +defparam \rcount_cry_0[7] .INJECT1_0="NO"; +defparam \rcount_cry_0[7] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[9] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[9]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[8]), + .COUT(rcount_cry[10]), + .S0(rcount_s[9]), + .S1(rcount_s[10]) +); +defparam \rcount_cry_0[9] .INIT0=16'h4000; +defparam \rcount_cry_0[9] .INIT1=16'h4000; +defparam \rcount_cry_0[9] .INJECT1_0="NO"; +defparam \rcount_cry_0[9] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[11] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[11]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[10]), + .COUT(rcount_cry[12]), + .S0(rcount_s[11]), + .S1(rcount_s[12]) +); +defparam \rcount_cry_0[11] .INIT0=16'h4000; +defparam \rcount_cry_0[11] .INIT1=16'h4000; +defparam \rcount_cry_0[11] .INJECT1_0="NO"; +defparam \rcount_cry_0[11] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[13] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[13]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[12]), + .COUT(rcount_cry[14]), + .S0(rcount_s[13]), + .S1(rcount_s[14]) +); +defparam \rcount_cry_0[13] .INIT0=16'h4000; +defparam \rcount_cry_0[13] .INIT1=16'h4000; +defparam \rcount_cry_0[13] .INJECT1_0="NO"; +defparam \rcount_cry_0[13] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_s_0[15] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[15]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[14]), + .COUT(rcount_s_0_COUT[15]), + .S0(rcount_s[15]), + .S1(rcount_s_0_S1[15]) +); +defparam \rcount_s_0[15] .INIT0=16'h4005; +defparam \rcount_s_0[15] .INIT1=16'h5003; +defparam \rcount_s_0[15] .INJECT1_0="NO"; +defparam \rcount_s_0[15] .INJECT1_1="NO"; + CCU2C \rhb_wait_cnt_cry_0[0] ( + .A0(VCC), + .B0(rhb_wait_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rhb_wait_cnt_cry[0]), + .S0(rhb_wait_cnt_cry_0_S0[0]), + .S1(rhb_wait_cnt_s[0]) +); +defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c; +defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[1] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[0]), + .COUT(rhb_wait_cnt_cry[2]), + .S0(rhb_wait_cnt_s[1]), + .S1(rhb_wait_cnt_s[2]) +); +defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[3] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[2]), + .COUT(rhb_wait_cnt_cry[4]), + .S0(rhb_wait_cnt_s[3]), + .S1(rhb_wait_cnt_s[4]) +); +defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[5] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[4]), + .COUT(rhb_wait_cnt_cry[6]), + .S0(rhb_wait_cnt_s[5]), + .S1(rhb_wait_cnt_s[6]) +); +defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_s_0[7] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[6]), + .COUT(rhb_wait_cnt_s_0_COUT[7]), + .S0(rhb_wait_cnt_s[7]), + .S1(rhb_wait_cnt_s_0_S1[7]) +); +defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a; +defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO"; + CCU2C un1_pcount_diff_1_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff[0]), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(un1_pcount_diff_1_cry_0), + .S0(un1_pcount_diff_1_cry_0_0_S0), + .S1(un1_pcount_diff_1_cry_0_0_S1) +); +defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003; +defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_1_0 ( + .A0(un1_pcount_diff_1_axb_1), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_2), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_0), + .COUT(un1_pcount_diff_1_cry_2), + .S0(un1_pcount_diff_1_cry_1_0_S0), + .S1(un1_pcount_diff_1_cry_1_0_S1) +); +defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_3_0 ( + .A0(un1_pcount_diff_1_axb_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_2), + .COUT(un1_pcount_diff_1_cry_4), + .S0(un1_pcount_diff_1_cry_3_0_S0), + .S1(un1_pcount_diff_1_cry_3_0_S1) +); +defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_5_0 ( + .A0(un1_pcount_diff_1_axb_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_4), + .COUT(un1_pcount_diff_1_cry_6), + .S0(un1_pcount_diff_1_cry_5_0_S0), + .S1(un1_pcount_diff_1_cry_5_0_S1) +); +defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_7_0 ( + .A0(un1_pcount_diff_1_axb_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_6), + .COUT(un1_pcount_diff_1_cry_8), + .S0(un1_pcount_diff_1_cry_7_0_S0), + .S1(un1_pcount_diff_1_cry_7_0_S1) +); +defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_9_0 ( + .A0(un1_pcount_diff_1_axb_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_8), + .COUT(un1_pcount_diff_1_cry_10), + .S0(un1_pcount_diff_1_cry_9_0_S0), + .S1(un1_pcount_diff_1_cry_9_0_S1) +); +defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_11_0 ( + .A0(un1_pcount_diff_1_axb_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_10), + .COUT(un1_pcount_diff_1_cry_12), + .S0(un1_pcount_diff_1_cry_11_0_S0), + .S1(un1_pcount_diff_1_cry_11_0_S1) +); +defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_13_0 ( + .A0(un1_pcount_diff_1_axb_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_12), + .COUT(un1_pcount_diff_1_cry_14), + .S0(un1_pcount_diff_1_cry_13_0_S0), + .S1(un1_pcount_diff_1_cry_13_0_S1) +); +defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_15_0 ( + .A0(un1_pcount_diff_1_axb_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_14), + .COUT(un1_pcount_diff_1_cry_16), + .S0(un1_pcount_diff_1_cry_15_0_S0), + .S1(un1_pcount_diff_1_cry_15_0_S1) +); +defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_17_0 ( + .A0(N_8), + .B0(rdiff_comp_lock[2]), + .C0(un1_pcount_diff_1_cry_17_0_RNO), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_16), + .COUT(un1_pcount_diff_1_cry_18), + .S0(un1_pcount_diff_1_cry_17_0_S0), + .S1(un1_pcount_diff_1_cry_17_0_S1) +); +defparam un1_pcount_diff_1_cry_17_0.INIT0=16'hb404; +defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_19_0 ( + .A0(un1_pcount_diff_1_axb_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_18), + .COUT(un1_pcount_diff_1_cry_20), + .S0(un1_pcount_diff_1_cry_19_0_S0), + .S1(un1_pcount_diff_1_cry_19_0_S1) +); +defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_s_21_0 ( + .A0(pcount[21]), + .B0(un13_lock_21), + .C0(N_8), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_20), + .COUT(un1_pcount_diff_1_s_21_0_COUT), + .S0(un1_pcount_diff_1_s_21_0_S0), + .S1(un1_pcount_diff_1_s_21_0_S1) +); +defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a; +defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003; +defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO"; + CCU2C un13_lock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(un13_lock_cry_0), + .S0(un13_lock_cry_0_0_S0), + .S1(un13_lock_cry_0_0_S1) +); +defparam un13_lock_cry_0_0.INIT0=16'h5003; +defparam un13_lock_cry_0_0.INIT1=16'h900a; +defparam un13_lock_cry_0_0.INJECT1_0="NO"; +defparam un13_lock_cry_0_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_0), + .COUT(un13_lock_cry_2), + .S0(un13_lock_cry_1_0_S0), + .S1(un13_lock_cry_1_0_S1) +); +defparam un13_lock_cry_1_0.INIT0=16'h900a; +defparam un13_lock_cry_1_0.INIT1=16'h900a; +defparam un13_lock_cry_1_0.INJECT1_0="NO"; +defparam un13_lock_cry_1_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_3_0 ( + .A0(un13_lock_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_2), + .COUT(un13_lock_cry_4), + .S0(un13_lock_cry_3_0_S0), + .S1(un13_lock_cry_3_0_S1) +); +defparam un13_lock_cry_3_0.INIT0=16'h500a; +defparam un13_lock_cry_3_0.INIT1=16'h500a; +defparam un13_lock_cry_3_0.INJECT1_0="NO"; +defparam un13_lock_cry_3_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_5_0 ( + .A0(un13_lock_5), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_4), + .COUT(un13_lock_cry_6), + .S0(un13_lock_cry_5_0_S0), + .S1(un13_lock_cry_5_0_S1) +); +defparam un13_lock_cry_5_0.INIT0=16'h900a; +defparam un13_lock_cry_5_0.INIT1=16'h500a; +defparam un13_lock_cry_5_0.INJECT1_0="NO"; +defparam un13_lock_cry_5_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_6), + .COUT(un13_lock_cry_8), + .S0(un13_lock_cry_7_0_S0), + .S1(un13_lock_cry_7_0_S1) +); +defparam un13_lock_cry_7_0.INIT0=16'h500a; +defparam un13_lock_cry_7_0.INIT1=16'h500a; +defparam un13_lock_cry_7_0.INJECT1_0="NO"; +defparam un13_lock_cry_7_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_8), + .COUT(un13_lock_cry_10), + .S0(un13_lock_cry_9_0_S0), + .S1(un13_lock_cry_9_0_S1) +); +defparam un13_lock_cry_9_0.INIT0=16'h500a; +defparam un13_lock_cry_9_0.INIT1=16'h500a; +defparam un13_lock_cry_9_0.INJECT1_0="NO"; +defparam un13_lock_cry_9_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_10), + .COUT(un13_lock_cry_12), + .S0(un13_lock_cry_11_0_S0), + .S1(un13_lock_cry_11_0_S1) +); +defparam un13_lock_cry_11_0.INIT0=16'h500a; +defparam un13_lock_cry_11_0.INIT1=16'h500a; +defparam un13_lock_cry_11_0.INJECT1_0="NO"; +defparam un13_lock_cry_11_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_12), + .COUT(un13_lock_cry_14), + .S0(un13_lock_cry_13_0_S0), + .S1(un13_lock_cry_13_0_S1) +); +defparam un13_lock_cry_13_0.INIT0=16'h500a; +defparam un13_lock_cry_13_0.INIT1=16'h500a; +defparam un13_lock_cry_13_0.INJECT1_0="NO"; +defparam un13_lock_cry_13_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_14), + .COUT(un13_lock_cry_16), + .S0(un13_lock_cry_15_0_S0), + .S1(un13_lock_cry_15_0_S1) +); +defparam un13_lock_cry_15_0.INIT0=16'h500a; +defparam un13_lock_cry_15_0.INIT1=16'h500a; +defparam un13_lock_cry_15_0.INJECT1_0="NO"; +defparam un13_lock_cry_15_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_16), + .COUT(un13_lock_cry_18), + .S0(un13_lock_cry_17_0_S0), + .S1(un13_lock_cry_17_0_S1) +); +defparam un13_lock_cry_17_0.INIT0=16'h500a; +defparam un13_lock_cry_17_0.INIT1=16'h500a; +defparam un13_lock_cry_17_0.INJECT1_0="NO"; +defparam un13_lock_cry_17_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_18), + .COUT(un13_lock_cry_20), + .S0(un13_lock_cry_19_0_S0), + .S1(un13_lock_cry_19_0_S1) +); +defparam un13_lock_cry_19_0.INIT0=16'h500a; +defparam un13_lock_cry_19_0.INIT1=16'h500a; +defparam un13_lock_cry_19_0.INJECT1_0="NO"; +defparam un13_lock_cry_19_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_20), + .COUT(un13_lock_cry_21_0_COUT), + .S0(un13_lock_cry_21_0_S0), + .S1(un13_lock_cry_21_i) +); +defparam un13_lock_cry_21_0.INIT0=16'h500f; +defparam un13_lock_cry_21_0.INIT1=16'ha003; +defparam un13_lock_cry_21_0.INJECT1_0="NO"; +defparam un13_lock_cry_21_0.INJECT1_1="NO"; + CCU2C un13_unlock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(un13_unlock_cry_0), + .S0(un13_unlock_cry_0_0_S0), + .S1(un13_unlock_cry_0_0_S1) +); +defparam un13_unlock_cry_0_0.INIT0=16'h5003; +defparam un13_unlock_cry_0_0.INIT1=16'h500a; +defparam un13_unlock_cry_0_0.INJECT1_0="NO"; +defparam un13_unlock_cry_0_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_0), + .COUT(un13_unlock_cry_2), + .S0(un13_unlock_cry_1_0_S0), + .S1(un13_unlock_cry_1_0_S1) +); +defparam un13_unlock_cry_1_0.INIT0=16'h900a; +defparam un13_unlock_cry_1_0.INIT1=16'h900a; +defparam un13_unlock_cry_1_0.INJECT1_0="NO"; +defparam un13_unlock_cry_1_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_3_0 ( + .A0(un13_lock_3), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_2), + .COUT(un13_unlock_cry_4), + .S0(un13_unlock_cry_3_0_S0), + .S1(un13_unlock_cry_3_0_S1) +); +defparam un13_unlock_cry_3_0.INIT0=16'h900a; +defparam un13_unlock_cry_3_0.INIT1=16'h500a; +defparam un13_unlock_cry_3_0.INJECT1_0="NO"; +defparam un13_unlock_cry_3_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_5_0 ( + .A0(un13_lock_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_4), + .COUT(un13_unlock_cry_6), + .S0(un13_unlock_cry_5_0_S0), + .S1(un13_unlock_cry_5_0_S1) +); +defparam un13_unlock_cry_5_0.INIT0=16'h500a; +defparam un13_unlock_cry_5_0.INIT1=16'h900a; +defparam un13_unlock_cry_5_0.INJECT1_0="NO"; +defparam un13_unlock_cry_5_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_6), + .COUT(un13_unlock_cry_8), + .S0(un13_unlock_cry_7_0_S0), + .S1(un13_unlock_cry_7_0_S1) +); +defparam un13_unlock_cry_7_0.INIT0=16'h500a; +defparam un13_unlock_cry_7_0.INIT1=16'h500a; +defparam un13_unlock_cry_7_0.INJECT1_0="NO"; +defparam un13_unlock_cry_7_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_8), + .COUT(un13_unlock_cry_10), + .S0(un13_unlock_cry_9_0_S0), + .S1(un13_unlock_cry_9_0_S1) +); +defparam un13_unlock_cry_9_0.INIT0=16'h500a; +defparam un13_unlock_cry_9_0.INIT1=16'h500a; +defparam un13_unlock_cry_9_0.INJECT1_0="NO"; +defparam un13_unlock_cry_9_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_10), + .COUT(un13_unlock_cry_12), + .S0(un13_unlock_cry_11_0_S0), + .S1(un13_unlock_cry_11_0_S1) +); +defparam un13_unlock_cry_11_0.INIT0=16'h500a; +defparam un13_unlock_cry_11_0.INIT1=16'h500a; +defparam un13_unlock_cry_11_0.INJECT1_0="NO"; +defparam un13_unlock_cry_11_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_12), + .COUT(un13_unlock_cry_14), + .S0(un13_unlock_cry_13_0_S0), + .S1(un13_unlock_cry_13_0_S1) +); +defparam un13_unlock_cry_13_0.INIT0=16'h500a; +defparam un13_unlock_cry_13_0.INIT1=16'h500a; +defparam un13_unlock_cry_13_0.INJECT1_0="NO"; +defparam un13_unlock_cry_13_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_14), + .COUT(un13_unlock_cry_16), + .S0(un13_unlock_cry_15_0_S0), + .S1(un13_unlock_cry_15_0_S1) +); +defparam un13_unlock_cry_15_0.INIT0=16'h500a; +defparam un13_unlock_cry_15_0.INIT1=16'h500a; +defparam un13_unlock_cry_15_0.INJECT1_0="NO"; +defparam un13_unlock_cry_15_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_16), + .COUT(un13_unlock_cry_18), + .S0(un13_unlock_cry_17_0_S0), + .S1(un13_unlock_cry_17_0_S1) +); +defparam un13_unlock_cry_17_0.INIT0=16'h500a; +defparam un13_unlock_cry_17_0.INIT1=16'h500a; +defparam un13_unlock_cry_17_0.INJECT1_0="NO"; +defparam un13_unlock_cry_17_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_18), + .COUT(un13_unlock_cry_20), + .S0(un13_unlock_cry_19_0_S0), + .S1(un13_unlock_cry_19_0_S1) +); +defparam un13_unlock_cry_19_0.INIT0=16'h500a; +defparam un13_unlock_cry_19_0.INIT1=16'h500a; +defparam un13_unlock_cry_19_0.INJECT1_0="NO"; +defparam un13_unlock_cry_19_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_20), + .COUT(un13_unlock_cry_21_0_COUT), + .S0(un13_unlock_cry_21_0_S0), + .S1(un13_unlock_cry_21) +); +defparam un13_unlock_cry_21_0.INIT0=16'h500f; +defparam un13_unlock_cry_21_0.INIT1=16'h5003; +defparam un13_unlock_cry_21_0.INJECT1_0="NO"; +defparam un13_unlock_cry_21_0.INJECT1_1="NO"; +//@16:1801 +//@8:424 +// @16:1211 + sync_0s phb_sync_inst ( + .phb(phb), + .rhb_sync(rhb_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); +// @16:1220 + sync_0s_6 rtc_sync_inst ( + .rtc_pul(rtc_pul), + .ppul_sync(ppul_sync), + .sli_rst(sli_rst), + .tx_pclk(tx_pclk) +); +// @16:1228 + sync_0s_0 pdiff_sync_inst ( + .ppul_sync(ppul_sync), + .pdiff_sync(pdiff_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sgmii_ecp5sll_core_Z1_layer1 */ + +module sgmii_ecp5rsl_core_Z2_layer1 ( + rx_pcs_rst_c, + tx_pcs_rst_c, + tx_serdes_rst_c, + serdes_rst_dual_c, + rsl_tx_pcs_rst_c, + rsl_rx_serdes_rst_c, + rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c, + rsl_tx_rdy, + pll_lock_i, + pll_refclki, + rsl_rx_rdy, + rsl_rst, + rxrefclk, + rsl_disable, + rx_serdes_rst_c, + rsl_rx_pcs_rst_c, + rst_dual_c, + rx_cdr_lol_s, + rx_los_low_s +) +; +input rx_pcs_rst_c ; +input tx_pcs_rst_c ; +input tx_serdes_rst_c ; +input serdes_rst_dual_c ; +output rsl_tx_pcs_rst_c ; +output rsl_rx_serdes_rst_c ; +output rsl_serdes_rst_dual_c ; +output rsl_tx_serdes_rst_c ; +output rsl_tx_rdy ; +input pll_lock_i ; +input pll_refclki ; +output rsl_rx_rdy ; +input rsl_rst ; +input rxrefclk ; +input rsl_disable ; +input rx_serdes_rst_c ; +output rsl_rx_pcs_rst_c ; +input rst_dual_c ; +input rx_cdr_lol_s ; +input rx_los_low_s ; +wire rx_pcs_rst_c ; +wire tx_pcs_rst_c ; +wire tx_serdes_rst_c ; +wire serdes_rst_dual_c ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire rsl_tx_rdy ; +wire pll_lock_i ; +wire pll_refclki ; +wire rsl_rx_rdy ; +wire rsl_rst ; +wire rxrefclk ; +wire rsl_disable ; +wire rx_serdes_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rst_dual_c ; +wire rx_cdr_lol_s ; +wire rx_los_low_s ; +wire [1:0] rxs_cnt; +wire [1:0] rxs_cnt_3; +wire [0:0] rxpr_appd_RNO; +wire [2:0] plol0_cnt; +wire [2:0] plol0_cnt_3; +wire [0:0] rxsr_appd; +wire [1:0] rxs_cnt_QN; +wire [3:0] rlos_db_cnt; +wire [3:0] rlos_db_cnt_QN; +wire [17:0] rlols0_cnt_s; +wire [17:0] rlols0_cnt; +wire [17:0] rlols0_cnt_QN; +wire [3:0] rlol_db_cnt; +wire [3:0] rlol_db_cnt_QN; +wire [18:0] rlol1_cnt_s; +wire [18:0] rlol1_cnt; +wire [18:0] rlol1_cnt_QN; +wire [11:0] rxr_wt_cnt_s; +wire [11:0] rxr_wt_cnt; +wire [11:0] rxr_wt_cnt_QN; +wire [0:0] rxsr_appd_QN; +wire [0:0] rxpr_appd; +wire [0:0] rxpr_appd_QN; +wire [1:0] txs_cnt; +wire [1:0] txs_cnt_QN; +wire [1:1] txs_cnt_RNO; +wire [1:0] txp_cnt; +wire [1:0] txp_cnt_QN; +wire [1:1] txp_cnt_RNO; +wire [19:0] plol_cnt_s; +wire [19:0] plol_cnt; +wire [19:0] plol_cnt_QN; +wire [2:0] plol0_cnt_QN; +wire [11:0] txr_wt_cnt_s; +wire [11:0] txr_wt_cnt; +wire [11:0] txr_wt_cnt_QN; +wire [0:0] txpr_appd; +wire [0:0] txpr_appd_QN; +wire [0:0] un1_rlol_db_cnt_zero; +wire [0:0] un1_rlos_db_cnt_zero; +wire [0:0] un1_rlol_db_cnt_zero_bm; +wire [0:0] un1_rlol_db_cnt_zero_am; +wire [0:0] un1_rlos_db_cnt_zero_bm; +wire [0:0] un1_rlos_db_cnt_zero_am; +wire [16:0] rlol1_cnt_cry; +wire [0:0] rlol1_cnt_cry_0_S0; +wire [17:17] rlol1_cnt_cry_0_COUT; +wire [16:0] rlols0_cnt_cry; +wire [0:0] rlols0_cnt_cry_0_S0; +wire [17:17] rlols0_cnt_s_0_COUT; +wire [17:17] rlols0_cnt_s_0_S1; +wire [10:0] txr_wt_cnt_cry; +wire [0:0] txr_wt_cnt_cry_0_S0; +wire [11:11] txr_wt_cnt_s_0_COUT; +wire [11:11] txr_wt_cnt_s_0_S1; +wire [10:0] rxr_wt_cnt_cry; +wire [0:0] rxr_wt_cnt_cry_0_S0; +wire [11:11] rxr_wt_cnt_s_0_COUT; +wire [11:11] rxr_wt_cnt_s_0_S1; +wire [18:0] plol_cnt_cry; +wire [0:0] plol_cnt_cry_0_S0; +wire [19:19] plol_cnt_s_0_COUT; +wire [19:19] plol_cnt_s_0_S1; +wire rxs_rst ; +wire VCC ; +wire dual_or_rserd_rst ; +wire plol0_cnt9 ; +wire waita_plol0 ; +wire rlos_db_p1 ; +wire rlos_db ; +wire rxp_rst25 ; +wire rlol_db ; +wire un1_rui_rst_dual_c_1_1 ; +wire rx_all_well ; +wire un3_rx_all_well_2 ; +wire un17_rxr_wt_tc ; +wire un3_rx_all_well_1 ; +wire rx_any_rst ; +wire rxr_wt_cnt9 ; +wire un1_rui_rst_dual_c_1_i ; +wire rlol1_cnt_tc_1 ; +wire rlol1_cnt_scalar ; +wire rxr_wt_en ; +wire rxr_wt_cnte ; +wire rlols0_cnt_tc_1 ; +wire un2_rlos_redge_1_i ; +wire un18_txr_wt_tc ; +wire tx_any_rst ; +wire pll_lol_p2 ; +wire un2_plol_fedge_5_i ; +wire N_2124_0 ; +wire waita_rlols06 ; +wire un1_rlols0_cnt_tc ; +wire waita_rlols0 ; +wire waita_rlols0_QN ; +wire wait_calib_RNO ; +wire un1_rlos_fedge_1 ; +wire wait_calib ; +wire wait_calib_QN ; +wire rxs_rst6 ; +wire un1_rxs_cnt_tc ; +wire rxs_rst_QN ; +wire rxp_rst2 ; +wire rxp_rst2_QN ; +wire rlos_p1 ; +wire rlos_p2 ; +wire rlos_p2_QN ; +wire rlos_p1_QN ; +wire rlos_db_p1_QN ; +wire rlos_db_cnt_axb_0 ; +wire rlos_db_cnt_cry_1_0_S0 ; +wire rlos_db_cnt_cry_1_0_S1 ; +wire rlos_db_cnt_s_3_0_S0 ; +wire un1_rlos_db_cnt_max ; +wire rlos_db_QN ; +wire rlols0_cnte ; +wire rlol_p1 ; +wire rlol_p2 ; +wire rlol_p2_QN ; +wire rlol_p1_QN ; +wire rlol_db_p1 ; +wire rlol_db_p1_QN ; +wire rlol_db_cnt_axb_0 ; +wire rlol_db_cnt_cry_1_0_S0 ; +wire rlol_db_cnt_cry_1_0_S1 ; +wire rlol_db_cnt_s_3_0_S0 ; +wire un1_rlol_db_cnt_max ; +wire rlol_db_QN ; +wire rlol1_cnte ; +wire rxsdr_appd_2 ; +wire rxsdr_appd_4 ; +wire rxsdr_appd_QN ; +wire un1_dual_or_rserd_rst_2_i ; +wire rxr_wt_en_QN ; +wire rxdpr_appd ; +wire rxdpr_appd_QN ; +wire ruo_rx_rdyr_QN ; +wire un2_rdo_serdes_rst_dual_c_2_i ; +wire plol_fedge ; +wire un1_plol0_cnt_tc_1_i ; +wire waita_plol0_QN ; +wire un1_plol_cnt_tc ; +wire un2_plol_cnt_tc ; +wire txs_rst ; +wire txs_rst_QN ; +wire N_10_i ; +wire un9_plol0_cnt_tc ; +wire un1_plol0_cnt_tc_1 ; +wire txp_rst ; +wire txp_rst_QN ; +wire N_11_i ; +wire pll_lol_p3 ; +wire pll_lol_p3_QN ; +wire pll_lol_p1 ; +wire pll_lol_p2_QN ; +wire pll_lol_p1_QN ; +wire txsr_appd_2 ; +wire txsr_appd_4 ; +wire txsr_appd_QN ; +wire un1_dual_or_serd_rst_1_1 ; +wire un1_dual_or_serd_rst_1_i ; +wire txr_wt_en ; +wire txr_wt_en_QN ; +wire txr_wt_cnte ; +wire un2_plol_fedge_2 ; +wire un2_plol_fedge_3_i ; +wire txdpr_appd ; +wire txdpr_appd_QN ; +wire un2_plol_fedge_5_1 ; +wire ruo_tx_rdyr_QN ; +wire un2_plol_fedge_8_i ; +wire rlos_redge ; +wire rlols0_cnt11_0 ; +wire plol_cnt_scalar ; +wire rlols0_cnt_scalar ; +wire un8_rxs_cnt_tc ; +wire un1_txsr_appd ; +wire un3_rx_all_well_2_1 ; +wire un1_rxsdr_or_sr_appd ; +wire un2_rdo_serdes_rst_dual_c_1_1 ; +wire rlols0_cnt_tc_1_10 ; +wire rlols0_cnt_tc_1_11 ; +wire rlols0_cnt_tc_1_12 ; +wire rlols0_cnt_tc_1_13 ; +wire un1_plol_cnt_tc_11 ; +wire un1_plol_cnt_tc_12 ; +wire un1_plol_cnt_tc_13 ; +wire un1_plol_cnt_tc_14 ; +wire rlol1_cnt_tc_1_11 ; +wire rlol1_cnt_tc_1_12 ; +wire rlol1_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_14 ; +wire CO0_2 ; +wire un18_txr_wt_tc_6 ; +wire un18_txr_wt_tc_7 ; +wire un18_txr_wt_tc_8 ; +wire un17_rxr_wt_tc_6 ; +wire un17_rxr_wt_tc_7 ; +wire un17_rxr_wt_tc_8 ; +wire rlols0_cnt_tc_1_9 ; +wire un1_plol_cnt_tc_10 ; +wire rlol1_cnt_tc_1_10 ; +wire txr_wt_cnt_scalar ; +wire rlos_db_cnt_cry_0 ; +wire rlos_db_cnt_cry_0_0_S0 ; +wire rlos_db_cnt_cry_0_0_S1 ; +wire rlos_db_cnt_cry_2 ; +wire rlos_db_cnt_s_3_0_COUT ; +wire rlos_db_cnt_s_3_0_S1 ; +wire rlol_db_cnt_cry_0 ; +wire rlol_db_cnt_cry_0_0_S0 ; +wire rlol_db_cnt_cry_0_0_S1 ; +wire rlol_db_cnt_cry_2 ; +wire rlol_db_cnt_s_3_0_COUT ; +wire rlol_db_cnt_s_3_0_S1 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_6 ; +wire N_7 ; + LUT4 \genblk2.rxs_cnt_RNO[0] ( + .A(rxs_rst), + .B(rxs_cnt[0]), + .C(rxs_cnt[1]), + .D(VCC), + .Z(rxs_cnt_3[0]) +); +defparam \genblk2.rxs_cnt_RNO[0] .init=16'h2626; + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] ( + .A(dual_or_rserd_rst), + .B(rx_los_low_s), + .C(rx_cdr_lol_s), + .D(VCC), + .Z(rxpr_appd_RNO[0]) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'h0101; + LUT4 \genblk1.plol0_cnt_RNO[1] ( + .A(plol0_cnt[1]), + .B(plol0_cnt9), + .C(waita_plol0), + .D(plol0_cnt[0]), + .Z(plol0_cnt_3[1]) +); +defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222; + LUT4 \genblk2.rxp_rst2_RNO ( + .A(dual_or_rserd_rst), + .B(rlos_db_p1), + .C(rlos_db), + .D(VCC), + .Z(rxp_rst25) +); +defparam \genblk2.rxp_rst2_RNO .init=16'hBABA; + LUT4 \genblk2.genblk3.rxdpr_appd_RNO ( + .A(dual_or_rserd_rst), + .B(rlos_db), + .C(rlol_db), + .D(VCC), + .Z(un1_rui_rst_dual_c_1_1) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'h0101; + LUT4 \genblk2.genblk3.ruo_rx_rdyr_RNO ( + .A(rx_all_well), + .B(rst_dual_c), + .C(rsl_rx_pcs_rst_c), + .D(dual_or_rserd_rst), + .Z(un3_rx_all_well_2) +); +defparam \genblk2.genblk3.ruo_rx_rdyr_RNO .init=16'h0002; + LUT4 \genblk2.genblk3.rxr_wt_en_RNO ( + .A(un17_rxr_wt_tc), + .B(rx_all_well), + .C(dual_or_rserd_rst), + .D(VCC), + .Z(un3_rx_all_well_1) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h0404; + LUT4 rx_any_rst_RNIFD021 ( + .A(rx_any_rst), + .B(un17_rxr_wt_tc), + .C(rlos_db), + .D(rlol_db), + .Z(rxr_wt_cnt9) +); +defparam rx_any_rst_RNIFD021.init=16'hFFFE; + LUT4 \genblk2.genblk3.rxdpr_appd_RNO_0 ( + .A(rst_dual_c), + .B(rx_all_well), + .C(dual_or_rserd_rst), + .D(VCC), + .Z(un1_rui_rst_dual_c_1_i) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO_0 .init=16'hFBFB; + LUT4 \genblk2.rxs_rst_RNIS0OP ( + .A(rlol1_cnt_tc_1), + .B(rxs_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlol1_cnt_scalar) +); +defparam \genblk2.rxs_rst_RNIS0OP .init=16'h1011; + LUT4 \genblk2.genblk3.rxr_wt_en_RNIQF0H1 ( + .A(rxr_wt_en), + .B(rx_any_rst), + .C(rx_all_well), + .D(un17_rxr_wt_tc), + .Z(rxr_wt_cnte) +); +defparam \genblk2.genblk3.rxr_wt_en_RNIQF0H1 .init=16'hFFEF; + LUT4 \genblk2.rxp_rst2_RNO_0 ( + .A(rlols0_cnt_tc_1), + .B(dual_or_rserd_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(un2_rlos_redge_1_i) +); +defparam \genblk2.rxp_rst2_RNO_0 .init=16'hEFEE; + LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO ( + .A(un18_txr_wt_tc), + .B(tx_any_rst), + .C(pll_lol_p2), + .D(VCC), + .Z(un2_plol_fedge_5_i) +); +defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hFEFE; + LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] ( + .A(rxsr_appd[0]), + .B(rx_serdes_rst_c), + .C(rxs_rst), + .D(rsl_disable), + .Z(N_2124_0) +); +defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE; +// @16:759 + FD1P3DX \genblk2.waita_rlols0 ( + .D(waita_rlols06), + .SP(un1_rlols0_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(waita_rlols0) +); +// @16:656 + FD1P3BX \genblk2.wait_calib ( + .D(wait_calib_RNO), + .SP(un1_rlos_fedge_1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(wait_calib) +); +// @16:694 + FD1P3DX \genblk2.rxs_rst ( + .D(rxs_rst6), + .SP(un1_rxs_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_rst) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[0] ( + .D(rxs_cnt_3[0]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[0]) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[1] ( + .D(rxs_cnt_3[1]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[1]) +); +// @16:806 + FD1P3BX \genblk2.rxp_rst2 ( + .D(rxp_rst25), + .SP(un2_rlos_redge_1_i), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxp_rst2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p2 ( + .D(rlos_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p1 ( + .D(rx_los_low_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p1) +); +// @16:567 + FD1S3BX \genblk2.rlos_db_p1 ( + .D(rlos_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_p1) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[0] ( + .D(rlos_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[0]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[1] ( + .D(rlos_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[1]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[2] ( + .D(rlos_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[2]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[3] ( + .D(rlos_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[3]) +); +// @16:649 + FD1P3BX \genblk2.rlos_db ( + .D(rlos_db_cnt[1]), + .SP(un1_rlos_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[0] ( + .D(rlols0_cnt_s[0]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[0]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[1] ( + .D(rlols0_cnt_s[1]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[1]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[2] ( + .D(rlols0_cnt_s[2]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[2]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[3] ( + .D(rlols0_cnt_s[3]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[3]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[4] ( + .D(rlols0_cnt_s[4]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[4]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[5] ( + .D(rlols0_cnt_s[5]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[5]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[6] ( + .D(rlols0_cnt_s[6]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[6]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[7] ( + .D(rlols0_cnt_s[7]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[7]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[8] ( + .D(rlols0_cnt_s[8]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[8]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[9] ( + .D(rlols0_cnt_s[9]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[9]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[10] ( + .D(rlols0_cnt_s[10]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[10]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[11] ( + .D(rlols0_cnt_s[11]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[11]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[12] ( + .D(rlols0_cnt_s[12]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[12]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[13] ( + .D(rlols0_cnt_s[13]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[13]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[14] ( + .D(rlols0_cnt_s[14]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[14]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[15] ( + .D(rlols0_cnt_s[15]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[15]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[16] ( + .D(rlols0_cnt_s[16]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[16]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[17] ( + .D(rlols0_cnt_s[17]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[17]) +); +// @16:567 + FD1S3DX \genblk2.rlol_p2 ( + .D(rlol_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p2) +); +// @16:567 + FD1S3DX \genblk2.rlol_p1 ( + .D(rx_cdr_lol_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p1) +); +// @16:567 + FD1S3BX \genblk2.rlol_db_p1 ( + .D(rlol_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_p1) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[0] ( + .D(rlol_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[0]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[1] ( + .D(rlol_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[1]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[2] ( + .D(rlol_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[2]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[3] ( + .D(rlol_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[3]) +); +// @16:633 + FD1P3BX \genblk2.rlol_db ( + .D(rlol_db_cnt[1]), + .SP(un1_rlol_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[0] ( + .D(rlol1_cnt_s[0]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[0]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[1] ( + .D(rlol1_cnt_s[1]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[1]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[2] ( + .D(rlol1_cnt_s[2]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[2]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[3] ( + .D(rlol1_cnt_s[3]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[3]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[4] ( + .D(rlol1_cnt_s[4]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[4]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[5] ( + .D(rlol1_cnt_s[5]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[5]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[6] ( + .D(rlol1_cnt_s[6]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[6]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[7] ( + .D(rlol1_cnt_s[7]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[7]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[8] ( + .D(rlol1_cnt_s[8]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[8]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[9] ( + .D(rlol1_cnt_s[9]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[9]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[10] ( + .D(rlol1_cnt_s[10]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[10]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[11] ( + .D(rlol1_cnt_s[11]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[11]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[12] ( + .D(rlol1_cnt_s[12]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[12]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[13] ( + .D(rlol1_cnt_s[13]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[13]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[14] ( + .D(rlol1_cnt_s[14]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[14]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[15] ( + .D(rlol1_cnt_s[15]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[15]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[16] ( + .D(rlol1_cnt_s[16]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[16]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[17] ( + .D(rlol1_cnt_s[17]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[17]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[18] ( + .D(rlol1_cnt_s[18]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[18]) +); +// @16:865 + FD1S3BX \genblk2.genblk3.rxsdr_appd ( + .D(rxsdr_appd_2), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxsdr_appd_4) +); +// @16:900 + FD1P3DX \genblk2.genblk3.rxr_wt_en ( + .D(un3_rx_all_well_1), + .SP(un1_dual_or_rserd_rst_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_en) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0] ( + .D(rxr_wt_cnt_s[0]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[0]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1] ( + .D(rxr_wt_cnt_s[1]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[1]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2] ( + .D(rxr_wt_cnt_s[2]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[2]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3] ( + .D(rxr_wt_cnt_s[3]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[3]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4] ( + .D(rxr_wt_cnt_s[4]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[4]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5] ( + .D(rxr_wt_cnt_s[5]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[5]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6] ( + .D(rxr_wt_cnt_s[6]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[6]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7] ( + .D(rxr_wt_cnt_s[7]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[7]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8] ( + .D(rxr_wt_cnt_s[8]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[8]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9] ( + .D(rxr_wt_cnt_s[9]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[9]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10] ( + .D(rxr_wt_cnt_s[10]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[10]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11] ( + .D(rxr_wt_cnt_s[11]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[11]) +); +// @16:871 + FD1P3DX \genblk2.genblk3.rxdpr_appd ( + .D(un1_rui_rst_dual_c_1_1), + .SP(un1_rui_rst_dual_c_1_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxdpr_appd) +); +// @16:920 + FD1P3DX \genblk2.genblk3.ruo_rx_rdyr ( + .D(un3_rx_all_well_2), + .SP(rxr_wt_cnt9), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rsl_rx_rdy) +); +// @16:882 + FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0] ( + .D(N_2124_0), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxsr_appd[0]) +); +// @16:888 + FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0] ( + .D(rxpr_appd_RNO[0]), + .SP(un2_rdo_serdes_rst_dual_c_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxpr_appd[0]) +); +// @16:443 + FD1P3DX \genblk1.waita_plol0 ( + .D(plol_fedge), + .SP(un1_plol0_cnt_tc_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(waita_plol0) +); +// @16:422 + FD1P3DX \genblk1.txs_rst ( + .D(un1_plol_cnt_tc), + .SP(un2_plol_cnt_tc), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_rst) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[0] ( + .D(N_10_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[0]) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[1] ( + .D(txs_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[1]) +); +// @16:461 + FD1P3DX \genblk1.txp_rst ( + .D(un9_plol0_cnt_tc), + .SP(un1_plol0_cnt_tc_1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_rst) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[0] ( + .D(N_11_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[0]) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[1] ( + .D(txp_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[0] ( + .D(plol_cnt_s[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[0]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[1] ( + .D(plol_cnt_s[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[2] ( + .D(plol_cnt_s[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[2]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[3] ( + .D(plol_cnt_s[3]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[3]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[4] ( + .D(plol_cnt_s[4]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[4]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[5] ( + .D(plol_cnt_s[5]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[5]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[6] ( + .D(plol_cnt_s[6]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[6]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[7] ( + .D(plol_cnt_s[7]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[7]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[8] ( + .D(plol_cnt_s[8]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[8]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[9] ( + .D(plol_cnt_s[9]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[9]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[10] ( + .D(plol_cnt_s[10]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[10]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[11] ( + .D(plol_cnt_s[11]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[11]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[12] ( + .D(plol_cnt_s[12]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[12]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[13] ( + .D(plol_cnt_s[13]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[13]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[14] ( + .D(plol_cnt_s[14]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[14]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[15] ( + .D(plol_cnt_s[15]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[15]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[16] ( + .D(plol_cnt_s[16]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[16]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[17] ( + .D(plol_cnt_s[17]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[17]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[18] ( + .D(plol_cnt_s[18]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[18]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[19] ( + .D(plol_cnt_s[19]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[19]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[0] ( + .D(plol0_cnt_3[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[0]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[1] ( + .D(plol0_cnt_3[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[1]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[2] ( + .D(plol0_cnt_3[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[2]) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p3 ( + .D(pll_lol_p2), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p3) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p2 ( + .D(pll_lol_p1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p2) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p1 ( + .D(pll_lock_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p1) +); +// @16:492 + FD1S3BX \genblk1.genblk2.txsr_appd ( + .D(txsr_appd_2), + .CK(pll_refclki), + .PD(rsl_rst), + .Q(txsr_appd_4) +); +// @16:519 + FD1P3DX \genblk1.genblk2.txr_wt_en ( + .D(un1_dual_or_serd_rst_1_1), + .SP(un1_dual_or_serd_rst_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_en) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[0] ( + .D(txr_wt_cnt_s[0]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[0]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[1] ( + .D(txr_wt_cnt_s[1]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[1]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[2] ( + .D(txr_wt_cnt_s[2]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[2]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[3] ( + .D(txr_wt_cnt_s[3]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[3]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[4] ( + .D(txr_wt_cnt_s[4]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[4]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[5] ( + .D(txr_wt_cnt_s[5]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[5]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[6] ( + .D(txr_wt_cnt_s[6]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[6]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[7] ( + .D(txr_wt_cnt_s[7]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[7]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[8] ( + .D(txr_wt_cnt_s[8]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[8]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[9] ( + .D(txr_wt_cnt_s[9]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[9]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[10] ( + .D(txr_wt_cnt_s[10]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[10]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[11] ( + .D(txr_wt_cnt_s[11]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[11]) +); +// @16:498 + FD1P3DX \genblk1.genblk2.txdpr_appd ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_3_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txdpr_appd) +); +// @16:537 + FD1P3DX \genblk1.genblk2.ruo_tx_rdyr ( + .D(un2_plol_fedge_5_1), + .SP(un2_plol_fedge_5_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(rsl_tx_rdy) +); +// @16:509 + FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0] ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_8_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txpr_appd[0]) +); +// @16:422 + LUT4 \genblk1.txs_cnt_RNO[0] ( + .A(txs_cnt[0]), + .B(txs_rst), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(N_10_i) +); +defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6; +// @16:434 + LUT4 \genblk1.txs_cnt_RNO[1] ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(txs_rst), + .D(un1_plol_cnt_tc), + .Z(txs_cnt_RNO[1]) +); +defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C; +// @16:519 + LUT4 \genblk1.genblk2.txr_wt_en_RNO ( + .A(txpr_appd[0]), + .B(pll_lol_p2), + .C(un1_dual_or_serd_rst_1_1), + .D(rsl_tx_rdy), + .Z(un1_dual_or_serd_rst_1_i) +); +defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F; +// @16:317 + LUT4 \genblk2.rxs_rst6 ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(rxs_rst6) +); +defparam \genblk2.rxs_rst6 .init=16'h2020; +// @8:394 + LUT4 \genblk2.wait_calib_RNIKRP81 ( + .A(rxs_rst), + .B(wait_calib), + .C(rlol1_cnt_tc_1), + .D(rlos_redge), + .Z(rlol1_cnte) +); +defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE; +// @8:394 + LUT4 \genblk2.waita_rlols0_RNI266C ( + .A(rlols0_cnt11_0), + .B(waita_rlols0), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(rlols0_cnte) +); +defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE; +// @16:412 + LUT4 \genblk1.plol_cnt11_i ( + .A(pll_lol_p2), + .B(un1_plol_cnt_tc), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(plol_cnt_scalar) +); +defparam \genblk1.plol_cnt11_i .init=16'h0202; +// @16:778 + LUT4 \genblk2.rlols0_cnt11_i ( + .A(rlols0_cnt11_0), + .B(rlols0_cnt_tc_1), + .C(VCC), + .D(VCC), + .Z(rlols0_cnt_scalar) +); +defparam \genblk2.rlols0_cnt11_i .init=16'h1111; +// @16:317 + LUT4 \genblk2.un1_rxs_cnt_tc ( + .A(rlol_db), + .B(rlos_db), + .C(un8_rxs_cnt_tc), + .D(rlol1_cnt_tc_1), + .Z(un1_rxs_cnt_tc) +); +defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC; +// @8:394 + LUT4 \genblk2.wait_calib_RNO ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(wait_calib_RNO) +); +defparam \genblk2.wait_calib_RNO .init=16'hA3A3; +// @16:509 + LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] ( + .A(un1_txsr_appd), + .B(pll_lol_p2), + .C(rsl_serdes_rst_dual_c), + .D(rsl_tx_serdes_rst_c), + .Z(un2_plol_fedge_8_i) +); +defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFFFE; +// @16:900 + LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0 ( + .A(dual_or_rserd_rst), + .B(un3_rx_all_well_2_1), + .C(un17_rxr_wt_tc), + .D(rx_all_well), + .Z(un1_dual_or_rserd_rst_2_i) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFEFF; +// @16:888 + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] ( + .A(un1_rxsdr_or_sr_appd), + .B(un2_rdo_serdes_rst_dual_c_1_1), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un2_rdo_serdes_rst_dual_c_2_i) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] .init=16'hFFFB; +// @16:259 + LUT4 \genblk1.un2_plol_cnt_tc ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(un2_plol_cnt_tc) +); +defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8; +// @8:394 + LUT4 \genblk1.genblk2.txr_wt_en_RNICEBT ( + .A(txr_wt_en), + .B(un18_txr_wt_tc), + .C(tx_any_rst), + .D(VCC), + .Z(txr_wt_cnte) +); +defparam \genblk1.genblk2.txr_wt_en_RNICEBT .init=16'hFEFE; +// @16:322 + LUT4 \genblk2.un1_rlos_fedge_1 ( + .A(rlos_db), + .B(rlos_db_p1), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(un1_rlos_fedge_1) +); +defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6; +// @16:340 + LUT4 \genblk2.un1_rlols0_cnt_tc ( + .A(rlols0_cnt11_0), + .B(waita_rlols06), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(un1_rlols0_cnt_tc) +); +defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE; +// @16:498 + LUT4 \genblk1.genblk2.txdpr_appd_RNO ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(rst_dual_c), + .Z(un2_plol_fedge_3_i) +); +defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFFFE; +// @16:461 + LUT4 \genblk1.txp_cnt_RNO[0] ( + .A(txp_cnt[0]), + .B(txp_rst), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(N_11_i) +); +defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6; +// @16:282 + LUT4 un2_plol_fedge_5_1_cZ ( + .A(pll_lol_p2), + .B(tx_any_rst), + .C(VCC), + .D(VCC), + .Z(un2_plol_fedge_5_1) +); +defparam un2_plol_fedge_5_1_cZ.init=16'h1111; +// @16:522 + LUT4 un1_dual_or_serd_rst_1_1_cZ ( + .A(un18_txr_wt_tc), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un1_dual_or_serd_rst_1_1) +); +defparam un1_dual_or_serd_rst_1_1_cZ.init=16'h0101; +// @16:473 + LUT4 \genblk1.txp_cnt_RNO[1] ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(txp_rst), + .D(un9_plol0_cnt_tc), + .Z(txp_cnt_RNO[1]) +); +defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C; +// @16:388 + LUT4 rlols0_cnt_tc_1_cZ ( + .A(rlols0_cnt_tc_1_10), + .B(rlols0_cnt_tc_1_11), + .C(rlols0_cnt_tc_1_12), + .D(rlols0_cnt_tc_1_13), + .Z(rlols0_cnt_tc_1) +); +defparam rlols0_cnt_tc_1_cZ.init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc ( + .A(un1_plol_cnt_tc_11), + .B(un1_plol_cnt_tc_12), + .C(un1_plol_cnt_tc_13), + .D(un1_plol_cnt_tc_14), + .Z(un1_plol_cnt_tc) +); +defparam \genblk1.un1_plol_cnt_tc .init=16'h8000; +// @16:387 + LUT4 rlol1_cnt_tc_1_cZ ( + .A(rlol1_cnt_tc_1_11), + .B(rlol1_cnt_tc_1_12), + .C(rlol1_cnt_tc_1_13), + .D(rlol1_cnt_tc_1_14), + .Z(rlol1_cnt_tc_1) +); +defparam rlol1_cnt_tc_1_cZ.init=16'h8000; +// @16:625 + LUT4 \un1_genblk2.rlol_db_cnt_axb_0 ( + .A(rlol_db_cnt[0]), + .B(un1_rlol_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlol_db_cnt_axb_0) +); +defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999; +// @16:641 + LUT4 \un1_genblk2.rlos_db_cnt_axb_0 ( + .A(rlos_db_cnt[0]), + .B(un1_rlos_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlos_db_cnt_axb_0) +); +defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999; +// @16:443 + LUT4 \genblk1.waita_plol0_RNO ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1_i) +); +defparam \genblk1.waita_plol0_RNO .init=16'hF6F6; +// @16:514 + LUT4 \genblk1.genblk2.mfor[0].un1_txsr_appd ( + .A(txdpr_appd), + .B(txsr_appd_4), + .C(rsl_tx_pcs_rst_c), + .D(VCC), + .Z(un1_txsr_appd) +); +defparam \genblk1.genblk2.mfor[0].un1_txsr_appd .init=16'hC8C8; +// @16:493 + LUT4 \genblk1.genblk2.txsr_appd_2 ( + .A(txsr_appd_4), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(txsr_appd_2) +); +defparam \genblk1.genblk2.txsr_appd_2 .init=16'hFEFE; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[0] ( + .A(plol0_cnt9), + .B(plol0_cnt[0]), + .C(waita_plol0), + .D(VCC), + .Z(plol0_cnt_3[0]) +); +defparam \genblk1.plol0_cnt_3[0] .init=16'h1414; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[2] ( + .A(CO0_2), + .B(plol0_cnt9), + .C(plol0_cnt[1]), + .D(plol0_cnt[2]), + .Z(plol0_cnt_3[2]) +); +defparam \genblk1.plol0_cnt_3[2] .init=16'h1320; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc ( + .A(un18_txr_wt_tc_6), + .B(un18_txr_wt_tc_7), + .C(un18_txr_wt_tc_8), + .D(VCC), + .Z(un18_txr_wt_tc) +); +defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080; +// @16:211 + LUT4 un2_plol_fedge_2_cZ ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un2_plol_fedge_2) +); +defparam un2_plol_fedge_2_cZ.init=16'h0101; +// @16:490 + LUT4 tx_any_rst_cZ ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_tx_pcs_rst_c), + .C(rsl_tx_serdes_rst_c), + .D(rst_dual_c), + .Z(tx_any_rst) +); +defparam tx_any_rst_cZ.init=16'hFFFE; +// @16:863 + LUT4 rx_any_rst_cZ ( + .A(dual_or_rserd_rst), + .B(rsl_rx_pcs_rst_c), + .C(rst_dual_c), + .D(VCC), + .Z(rx_any_rst) +); +defparam rx_any_rst_cZ.init=16'hFEFE; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc ( + .A(un17_rxr_wt_tc_6), + .B(un17_rxr_wt_tc_7), + .C(un17_rxr_wt_tc_8), + .D(VCC), + .Z(un17_rxr_wt_tc) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_bm[0]) +); +defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlol_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlol_db_cnt_zero_bm[0]), + .BLUT(un1_rlol_db_cnt_zero_am[0]), + .C0(rlol_p2), + .Z(un1_rlol_db_cnt_zero[0]) +); +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_bm[0]) +); +defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlos_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlos_db_cnt_zero_bm[0]), + .BLUT(un1_rlos_db_cnt_zero_am[0]), + .C0(rlos_p2), + .Z(un1_rlos_db_cnt_zero[0]) +); +// @16:309 + LUT4 \genblk2.un1_rlol_db_cnt_max ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_max) +); +defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001; +// @16:315 + LUT4 \genblk2.un1_rlos_db_cnt_max ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_max) +); +defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001; +// @16:269 + LUT4 \genblk1.un1_plol0_cnt_tc_1 ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1) +); +defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8; +// @16:764 + LUT4 \genblk2.waita_rlols06 ( + .A(rlol_db), + .B(rlol_db_p1), + .C(rlos_db), + .D(rlos_db_p1), + .Z(waita_rlols06) +); +defparam \genblk2.waita_rlols06 .init=16'h0504; +// @16:708 + LUT4 \rxs_cnt_3_cZ[1] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[1]) +); +defparam \rxs_cnt_3_cZ[1] .init=16'h6464; +// @16:893 + LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd ( + .A(rxsr_appd[0]), + .B(rx_all_well), + .C(rxsdr_appd_4), + .D(rsl_rx_pcs_rst_c), + .Z(un1_rxsdr_or_sr_appd) +); +defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd .init=16'h3200; +// @16:388 + LUT4 rlols0_cnt_tc_1_13_cZ ( + .A(rlols0_cnt[16]), + .B(rlols0_cnt[17]), + .C(rlols0_cnt_tc_1_9), + .D(VCC), + .Z(rlols0_cnt_tc_1_13) +); +defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_14 ( + .A(plol_cnt[4]), + .B(plol_cnt[5]), + .C(plol_cnt[18]), + .D(un1_plol_cnt_tc_10), + .Z(un1_plol_cnt_tc_14) +); +defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_14_cZ ( + .A(rlol1_cnt[11]), + .B(rlol1_cnt[12]), + .C(rlol1_cnt[18]), + .D(rlol1_cnt_tc_1_10), + .Z(rlol1_cnt_tc_1_14) +); +defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100; +// @16:906 + LUT4 \genblk2.genblk3.un3_rx_all_well_2_1 ( + .A(rxpr_appd[0]), + .B(rxdpr_appd), + .C(rsl_rx_rdy), + .D(VCC), + .Z(un3_rx_all_well_2_1) +); +defparam \genblk2.genblk3.un3_rx_all_well_2_1 .init=16'h0E0E; +// @16:375 + LUT4 rdo_serdes_rst_dual_c ( + .A(rsl_disable), + .B(rsl_rst), + .C(serdes_rst_dual_c), + .D(VCC), + .Z(rsl_serdes_rst_dual_c) +); +defparam rdo_serdes_rst_dual_c.init=16'hF4F4; +// @16:438 + LUT4 rdo_tx_serdes_rst_c ( + .A(rsl_disable), + .B(txs_rst), + .C(tx_serdes_rst_c), + .D(VCC), + .Z(rsl_tx_serdes_rst_c) +); +defparam rdo_tx_serdes_rst_c.init=16'hF4F4; +// @16:479 + LUT4 \rdo_tx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(txp_rst), + .C(tx_pcs_rst_c), + .D(VCC), + .Z(rsl_tx_pcs_rst_c) +); +defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:743 + LUT4 \rdo_rx_serdes_rst_c_1[0] ( + .A(rsl_disable), + .B(rxs_rst), + .C(rx_serdes_rst_c), + .D(VCC), + .Z(rsl_rx_serdes_rst_c) +); +defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4; +// @16:852 + LUT4 \rdo_rx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(rxp_rst2), + .C(rx_pcs_rst_c), + .D(VCC), + .Z(rsl_rx_pcs_rst_c) +); +defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:459 + LUT4 \genblk1.un9_plol0_cnt_tc ( + .A(plol0_cnt[0]), + .B(plol0_cnt[1]), + .C(plol0_cnt[2]), + .D(VCC), + .Z(un9_plol0_cnt_tc) +); +defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6 ( + .A(rxr_wt_cnt[0]), + .B(rxr_wt_cnt[8]), + .C(rxr_wt_cnt[9]), + .D(rxr_wt_cnt[11]), + .Z(un17_rxr_wt_tc_6) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7 ( + .A(rxr_wt_cnt[3]), + .B(rxr_wt_cnt[4]), + .C(rxr_wt_cnt[5]), + .D(rxr_wt_cnt[7]), + .Z(un17_rxr_wt_tc_7) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8 ( + .A(rxr_wt_cnt[1]), + .B(rxr_wt_cnt[2]), + .C(rxr_wt_cnt[6]), + .D(rxr_wt_cnt[10]), + .Z(un17_rxr_wt_tc_8) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_6 ( + .A(txr_wt_cnt[0]), + .B(txr_wt_cnt[8]), + .C(txr_wt_cnt[9]), + .D(txr_wt_cnt[11]), + .Z(un18_txr_wt_tc_6) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_7 ( + .A(txr_wt_cnt[3]), + .B(txr_wt_cnt[4]), + .C(txr_wt_cnt[5]), + .D(txr_wt_cnt[7]), + .Z(un18_txr_wt_tc_7) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_8 ( + .A(txr_wt_cnt[1]), + .B(txr_wt_cnt[2]), + .C(txr_wt_cnt[6]), + .D(txr_wt_cnt[10]), + .Z(un18_txr_wt_tc_8) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_9_cZ ( + .A(rlols0_cnt[1]), + .B(rlols0_cnt[2]), + .C(rlols0_cnt[3]), + .D(rlols0_cnt[4]), + .Z(rlols0_cnt_tc_1_9) +); +defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_10_cZ ( + .A(rlols0_cnt[0]), + .B(rlols0_cnt[10]), + .C(rlols0_cnt[14]), + .D(rlols0_cnt[15]), + .Z(rlols0_cnt_tc_1_10) +); +defparam rlols0_cnt_tc_1_10_cZ.init=16'h4000; +// @16:388 + LUT4 rlols0_cnt_tc_1_11_cZ ( + .A(rlols0_cnt[9]), + .B(rlols0_cnt[11]), + .C(rlols0_cnt[12]), + .D(rlols0_cnt[13]), + .Z(rlols0_cnt_tc_1_11) +); +defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_12_cZ ( + .A(rlols0_cnt[5]), + .B(rlols0_cnt[6]), + .C(rlols0_cnt[7]), + .D(rlols0_cnt[8]), + .Z(rlols0_cnt_tc_1_12) +); +defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_10 ( + .A(plol_cnt[2]), + .B(plol_cnt[3]), + .C(plol_cnt[17]), + .D(plol_cnt[19]), + .Z(un1_plol_cnt_tc_10) +); +defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h1000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_11 ( + .A(plol_cnt[13]), + .B(plol_cnt[14]), + .C(plol_cnt[15]), + .D(plol_cnt[16]), + .Z(un1_plol_cnt_tc_11) +); +defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_12 ( + .A(plol_cnt[7]), + .B(plol_cnt[8]), + .C(plol_cnt[9]), + .D(plol_cnt[11]), + .Z(un1_plol_cnt_tc_12) +); +defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_13 ( + .A(plol_cnt[1]), + .B(plol_cnt[6]), + .C(plol_cnt[10]), + .D(plol_cnt[12]), + .Z(un1_plol_cnt_tc_13) +); +defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0008; +// @16:387 + LUT4 rlol1_cnt_tc_1_10_cZ ( + .A(rlol1_cnt[7]), + .B(rlol1_cnt[8]), + .C(rlol1_cnt[9]), + .D(rlol1_cnt[10]), + .Z(rlol1_cnt_tc_1_10) +); +defparam rlol1_cnt_tc_1_10_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_11_cZ ( + .A(rlol1_cnt[3]), + .B(rlol1_cnt[4]), + .C(rlol1_cnt[5]), + .D(rlol1_cnt[6]), + .Z(rlol1_cnt_tc_1_11) +); +defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_12_cZ ( + .A(rlol1_cnt[0]), + .B(rlol1_cnt[1]), + .C(rlol1_cnt[2]), + .D(rlol1_cnt[17]), + .Z(rlol1_cnt_tc_1_12) +); +defparam rlol1_cnt_tc_1_12_cZ.init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_13_cZ ( + .A(rlol1_cnt[13]), + .B(rlol1_cnt[14]), + .C(rlol1_cnt[15]), + .D(rlol1_cnt[16]), + .Z(rlol1_cnt_tc_1_13) +); +defparam rlol1_cnt_tc_1_13_cZ.init=16'h0040; +// @16:866 + LUT4 \genblk2.genblk3.rxsdr_appd_2 ( + .A(rxsdr_appd_4), + .B(serdes_rst_dual_c), + .C(VCC), + .D(VCC), + .Z(rxsdr_appd_2) +); +defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE; +// @16:601 + LUT4 rx_all_well_cZ ( + .A(rlol_db), + .B(rlos_db), + .C(VCC), + .D(VCC), + .Z(rx_all_well) +); +defparam rx_all_well_cZ.init=16'h1111; +// @16:436 + LUT4 \genblk2.un8_rxs_cnt_tc ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(VCC), + .D(VCC), + .Z(un8_rxs_cnt_tc) +); +defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888; +// @16:441 + LUT4 plol_fedge_cZ ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(VCC), + .D(VCC), + .Z(plol_fedge) +); +defparam plol_fedge_cZ.init=16'h4444; +// @16:757 + LUT4 rlos_redge_cZ ( + .A(rlos_db), + .B(rlos_db_p1), + .C(VCC), + .D(VCC), + .Z(rlos_redge) +); +defparam rlos_redge_cZ.init=16'h2222; +// @16:457 + LUT4 \genblk1.plol0_cnt_3_RNO[2] ( + .A(plol0_cnt[0]), + .B(waita_plol0), + .C(VCC), + .D(VCC), + .Z(CO0_2) +); +defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888; +// @16:891 + LUT4 un2_rdo_serdes_rst_dual_c_1_1_cZ ( + .A(rx_cdr_lol_s), + .B(rx_los_low_s), + .C(VCC), + .D(VCC), + .Z(un2_rdo_serdes_rst_dual_c_1_1) +); +defparam un2_rdo_serdes_rst_dual_c_1_1_cZ.init=16'h1111; +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_am_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_am[0]) +); +defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_am_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_am[0]) +); +defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:861 + LUT4 dual_or_rserd_rst_cZ ( + .A(rsl_rx_serdes_rst_c), + .B(serdes_rst_dual_c), + .C(rsl_rst), + .D(rsl_disable), + .Z(dual_or_rserd_rst) +); +defparam dual_or_rserd_rst_cZ.init=16'hEEFE; +// @16:454 + LUT4 \genblk1.plol0_cnt9 ( + .A(pll_lol_p2), + .B(plol0_cnt[2]), + .C(plol0_cnt[1]), + .D(plol0_cnt[0]), + .Z(plol0_cnt9) +); +defparam \genblk1.plol0_cnt9 .init=16'hAAAE; +// @16:783 + LUT4 \genblk2.rlols0_cnt11_0 ( + .A(rlol_db_p1), + .B(rlol_db), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlols0_cnt11_0) +); +defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44; +// @16:527 + LUT4 \genblk1.genblk2.txr_wt_cnt9_i ( + .A(tx_any_rst), + .B(un18_txr_wt_tc_8), + .C(un18_txr_wt_tc_7), + .D(un18_txr_wt_tc_6), + .Z(txr_wt_cnt_scalar) +); +defparam \genblk1.genblk2.txr_wt_cnt9_i .init=16'h1555; + CCU2C \genblk2.rlol1_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlol1_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_7), + .COUT(rlol1_cnt_cry[0]), + .S0(rlol1_cnt_cry_0_S0[0]), + .S1(rlol1_cnt_s[0]) +); +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[1] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[0]), + .COUT(rlol1_cnt_cry[2]), + .S0(rlol1_cnt_s[1]), + .S1(rlol1_cnt_s[2]) +); +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[3] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[2]), + .COUT(rlol1_cnt_cry[4]), + .S0(rlol1_cnt_s[3]), + .S1(rlol1_cnt_s[4]) +); +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[5] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[4]), + .COUT(rlol1_cnt_cry[6]), + .S0(rlol1_cnt_s[5]), + .S1(rlol1_cnt_s[6]) +); +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[7] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[6]), + .COUT(rlol1_cnt_cry[8]), + .S0(rlol1_cnt_s[7]), + .S1(rlol1_cnt_s[8]) +); +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[9] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[8]), + .COUT(rlol1_cnt_cry[10]), + .S0(rlol1_cnt_s[9]), + .S1(rlol1_cnt_s[10]) +); +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[11] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[10]), + .COUT(rlol1_cnt_cry[12]), + .S0(rlol1_cnt_s[11]), + .S1(rlol1_cnt_s[12]) +); +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[13] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[12]), + .COUT(rlol1_cnt_cry[14]), + .S0(rlol1_cnt_s[13]), + .S1(rlol1_cnt_s[14]) +); +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[15] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[14]), + .COUT(rlol1_cnt_cry[16]), + .S0(rlol1_cnt_s[15]), + .S1(rlol1_cnt_s[16]) +); +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[17] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[16]), + .COUT(rlol1_cnt_cry_0_COUT[17]), + .S0(rlol1_cnt_s[17]), + .S1(rlol1_cnt_s[18]) +); +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO"; + CCU2C \genblk2.rlols0_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlols0_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_6), + .COUT(rlols0_cnt_cry[0]), + .S0(rlols0_cnt_cry_0_S0[0]), + .S1(rlols0_cnt_s[0]) +); +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[1] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[0]), + .COUT(rlols0_cnt_cry[2]), + .S0(rlols0_cnt_s[1]), + .S1(rlols0_cnt_s[2]) +); +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[3] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[2]), + .COUT(rlols0_cnt_cry[4]), + .S0(rlols0_cnt_s[3]), + .S1(rlols0_cnt_s[4]) +); +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[5] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[4]), + .COUT(rlols0_cnt_cry[6]), + .S0(rlols0_cnt_s[5]), + .S1(rlols0_cnt_s[6]) +); +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[7] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[6]), + .COUT(rlols0_cnt_cry[8]), + .S0(rlols0_cnt_s[7]), + .S1(rlols0_cnt_s[8]) +); +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[9] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[8]), + .COUT(rlols0_cnt_cry[10]), + .S0(rlols0_cnt_s[9]), + .S1(rlols0_cnt_s[10]) +); +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[11] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[10]), + .COUT(rlols0_cnt_cry[12]), + .S0(rlols0_cnt_s[11]), + .S1(rlols0_cnt_s[12]) +); +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[13] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[12]), + .COUT(rlols0_cnt_cry[14]), + .S0(rlols0_cnt_s[13]), + .S1(rlols0_cnt_s[14]) +); +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[15] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[14]), + .COUT(rlols0_cnt_cry[16]), + .S0(rlols0_cnt_s[15]), + .S1(rlols0_cnt_s[16]) +); +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_s_0[17] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[16]), + .COUT(rlols0_cnt_s_0_COUT[17]), + .S0(rlols0_cnt_s[17]), + .S1(rlols0_cnt_s_0_S1[17]) +); +defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a; +defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO"; + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(txr_wt_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(txr_wt_cnt_cry[0]), + .S0(txr_wt_cnt_cry_0_S0[0]), + .S1(txr_wt_cnt_s[0]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[0]), + .COUT(txr_wt_cnt_cry[2]), + .S0(txr_wt_cnt_s[1]), + .S1(txr_wt_cnt_s[2]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[2]), + .COUT(txr_wt_cnt_cry[4]), + .S0(txr_wt_cnt_s[3]), + .S1(txr_wt_cnt_s[4]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[4]), + .COUT(txr_wt_cnt_cry[6]), + .S0(txr_wt_cnt_s[5]), + .S1(txr_wt_cnt_s[6]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[6]), + .COUT(txr_wt_cnt_cry[8]), + .S0(txr_wt_cnt_s[7]), + .S1(txr_wt_cnt_s[8]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[8]), + .COUT(txr_wt_cnt_cry[10]), + .S0(txr_wt_cnt_s[9]), + .S1(txr_wt_cnt_s[10]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[10]), + .COUT(txr_wt_cnt_s_0_COUT[11]), + .S0(txr_wt_cnt_s[11]), + .S1(txr_wt_cnt_s_0_S1[11]) +); +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h800a; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(rxr_wt_cnt9), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rxr_wt_cnt_cry[0]), + .S0(rxr_wt_cnt_cry_0_S0[0]), + .S1(rxr_wt_cnt_s[0]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[0]), + .COUT(rxr_wt_cnt_cry[2]), + .S0(rxr_wt_cnt_s[1]), + .S1(rxr_wt_cnt_s[2]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[2]), + .COUT(rxr_wt_cnt_cry[4]), + .S0(rxr_wt_cnt_s[3]), + .S1(rxr_wt_cnt_s[4]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[4]), + .COUT(rxr_wt_cnt_cry[6]), + .S0(rxr_wt_cnt_s[5]), + .S1(rxr_wt_cnt_s[6]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[6]), + .COUT(rxr_wt_cnt_cry[8]), + .S0(rxr_wt_cnt_s[7]), + .S1(rxr_wt_cnt_s[8]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[8]), + .COUT(rxr_wt_cnt_cry[10]), + .S0(rxr_wt_cnt_s[9]), + .S1(rxr_wt_cnt_s[10]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[10]), + .COUT(rxr_wt_cnt_s_0_COUT[11]), + .S0(rxr_wt_cnt_s[11]), + .S1(rxr_wt_cnt_s_0_S1[11]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk1.plol_cnt_cry_0[0] ( + .A0(VCC), + .B0(plol_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(plol_cnt_cry[0]), + .S0(plol_cnt_cry_0_S0[0]), + .S1(plol_cnt_s[0]) +); +defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[1] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[0]), + .COUT(plol_cnt_cry[2]), + .S0(plol_cnt_s[1]), + .S1(plol_cnt_s[2]) +); +defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[3] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[2]), + .COUT(plol_cnt_cry[4]), + .S0(plol_cnt_s[3]), + .S1(plol_cnt_s[4]) +); +defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[5] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[4]), + .COUT(plol_cnt_cry[6]), + .S0(plol_cnt_s[5]), + .S1(plol_cnt_s[6]) +); +defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[7] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[6]), + .COUT(plol_cnt_cry[8]), + .S0(plol_cnt_s[7]), + .S1(plol_cnt_s[8]) +); +defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[9] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[8]), + .COUT(plol_cnt_cry[10]), + .S0(plol_cnt_s[9]), + .S1(plol_cnt_s[10]) +); +defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[11] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[10]), + .COUT(plol_cnt_cry[12]), + .S0(plol_cnt_s[11]), + .S1(plol_cnt_s[12]) +); +defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[13] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[12]), + .COUT(plol_cnt_cry[14]), + .S0(plol_cnt_s[13]), + .S1(plol_cnt_s[14]) +); +defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[15] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[14]), + .COUT(plol_cnt_cry[16]), + .S0(plol_cnt_s[15]), + .S1(plol_cnt_s[16]) +); +defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[17] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[16]), + .COUT(plol_cnt_cry[18]), + .S0(plol_cnt_s[17]), + .S1(plol_cnt_s[18]) +); +defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_s_0[19] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[19]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[18]), + .COUT(plol_cnt_s_0_COUT[19]), + .S0(plol_cnt_s[19]), + .S1(plol_cnt_s_0_S1[19]) +); +defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a; +defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlos_db_cnt[0]), + .B1(un1_rlos_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(rlos_db_cnt_cry_0), + .S0(rlos_db_cnt_cry_0_0_S0), + .S1(rlos_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0 ( + .A0(un1_rlos_db_cnt_zero[0]), + .B0(rlos_p2), + .C0(rlos_db_cnt[1]), + .D0(VCC), + .A1(un1_rlos_db_cnt_zero[0]), + .B1(rlos_p2), + .C1(rlos_db_cnt[2]), + .D1(VCC), + .CIN(rlos_db_cnt_cry_0), + .COUT(rlos_db_cnt_cry_2), + .S0(rlos_db_cnt_cry_1_0_S0), + .S1(rlos_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_s_3_0 ( + .A0(rlos_db_cnt[3]), + .B0(rlos_p2), + .C0(un1_rlos_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlos_db_cnt_cry_2), + .COUT(rlos_db_cnt_s_3_0_COUT), + .S0(rlos_db_cnt_s_3_0_S0), + .S1(rlos_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlol_db_cnt[0]), + .B1(un1_rlol_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(rlol_db_cnt_cry_0), + .S0(rlol_db_cnt_cry_0_0_S0), + .S1(rlol_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0 ( + .A0(un1_rlol_db_cnt_zero[0]), + .B0(rlol_p2), + .C0(rlol_db_cnt[1]), + .D0(VCC), + .A1(un1_rlol_db_cnt_zero[0]), + .B1(rlol_p2), + .C1(rlol_db_cnt[2]), + .D1(VCC), + .CIN(rlol_db_cnt_cry_0), + .COUT(rlol_db_cnt_cry_2), + .S0(rlol_db_cnt_cry_1_0_S0), + .S1(rlol_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_s_3_0 ( + .A0(rlol_db_cnt[3]), + .B0(rlol_p2), + .C0(un1_rlol_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlol_db_cnt_cry_2), + .COUT(rlol_db_cnt_s_3_0_COUT), + .S0(rlol_db_cnt_s_3_0_S0), + .S1(rlol_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO"; +//@16:865 +//@16:492 + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sgmii_ecp5rsl_core_Z2_layer1 */ + +module sgmii_ecp5 ( + hdoutp, + hdoutn, + hdinp, + hdinn, + rxrefclk, + tx_pclk, + txi_clk, + txdata, + tx_k, + xmit, + tx_disp_correct, + rxdata, + rx_k, + rx_disp_err, + rx_cv_err, + signal_detect_c, + rx_los_low_s, + lsm_status_s, + ctc_urun_s, + ctc_orun_s, + rx_cdr_lol_s, + ctc_ins_s, + ctc_del_s, + sli_rst, + tx_pwrup_c, + rx_pwrup_c, + sci_wrdata, + sci_addr, + sci_rddata, + sci_en_dual, + sci_sel_dual, + sci_en, + sci_sel, + sci_rd, + sci_wrn, + sci_int, + cyawstn, + serdes_pdb, + pll_refclki, + rsl_disable, + rsl_rst, + serdes_rst_dual_c, + rst_dual_c, + tx_serdes_rst_c, + tx_pcs_rst_c, + pll_lol, + rsl_tx_rdy, + rx_serdes_rst_c, + rx_pcs_rst_c, + rsl_rx_rdy +) +; +output hdoutp ; +output hdoutn ; +input hdinp ; +input hdinn ; +input rxrefclk ; +output tx_pclk ; +input txi_clk ; +input [7:0] txdata ; +input [0:0] tx_k ; +input [0:0] xmit ; +input [0:0] tx_disp_correct ; +output [7:0] rxdata ; +output [0:0] rx_k ; +output [0:0] rx_disp_err ; +output [0:0] rx_cv_err ; +input signal_detect_c ; +output rx_los_low_s ; +output lsm_status_s ; +output ctc_urun_s ; +output ctc_orun_s ; +output rx_cdr_lol_s ; +output ctc_ins_s ; +output ctc_del_s ; +input sli_rst ; +input tx_pwrup_c ; +input rx_pwrup_c ; +input [7:0] sci_wrdata ; +input [5:0] sci_addr ; +output [7:0] sci_rddata ; +input sci_en_dual ; +input sci_sel_dual ; +input sci_en ; +input sci_sel ; +input sci_rd ; +input sci_wrn ; +output sci_int ; +input cyawstn ; +input serdes_pdb ; +input pll_refclki ; +input rsl_disable ; +input rsl_rst ; +input serdes_rst_dual_c ; +input rst_dual_c ; +input tx_serdes_rst_c ; +input tx_pcs_rst_c ; +output pll_lol ; +output rsl_tx_rdy ; +input rx_serdes_rst_c ; +input rx_pcs_rst_c ; +output rsl_rx_rdy ; +wire hdoutp ; +wire hdoutn ; +wire hdinp ; +wire hdinn ; +wire rxrefclk ; +wire tx_pclk ; +wire txi_clk ; +wire signal_detect_c ; +wire rx_los_low_s ; +wire lsm_status_s ; +wire ctc_urun_s ; +wire ctc_orun_s ; +wire rx_cdr_lol_s ; +wire ctc_ins_s ; +wire ctc_del_s ; +wire sli_rst ; +wire tx_pwrup_c ; +wire rx_pwrup_c ; +wire sci_en_dual ; +wire sci_sel_dual ; +wire sci_en ; +wire sci_sel ; +wire sci_rd ; +wire sci_wrn ; +wire sci_int ; +wire cyawstn ; +wire serdes_pdb ; +wire pll_refclki ; +wire rsl_disable ; +wire rsl_rst ; +wire serdes_rst_dual_c ; +wire rst_dual_c ; +wire tx_serdes_rst_c ; +wire tx_pcs_rst_c ; +wire pll_lol ; +wire rsl_tx_rdy ; +wire rx_serdes_rst_c ; +wire rx_pcs_rst_c ; +wire rsl_rx_rdy ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire n47_1 ; +wire n48_1 ; +wire n1_1 ; +wire n2_1 ; +wire n3_1 ; +wire n4_1 ; +wire n5_1 ; +wire n49_1 ; +wire n6_1 ; +wire n50_1 ; +wire n7_1 ; +wire n51_1 ; +wire n8_1 ; +wire n52_1 ; +wire n9_1 ; +wire n53_1 ; +wire n54_1 ; +wire n55_1 ; +wire n56_1 ; +wire n57_1 ; +wire n58_1 ; +wire n59_1 ; +wire n60_1 ; +wire n61_1 ; +wire n62_1 ; +wire n63_1 ; +wire n64_1 ; +wire n65_1 ; +wire n10_1 ; +wire n66_1 ; +wire n67_1 ; +wire n68_1 ; +wire n69_1 ; +wire n70_1 ; +wire n71_1 ; +wire n72_1 ; +wire n73_1 ; +wire n74_1 ; +wire n75_1 ; +wire n76_1 ; +wire n77_1 ; +wire n78_1 ; +wire n79_1 ; +wire n80_1 ; +wire n81_1 ; +wire n82_1 ; +wire n83_1 ; +wire n84_1 ; +wire n85_1 ; +wire n86_1 ; +wire n87_1 ; +wire n88_1 ; +wire n11_1 ; +wire n89_1 ; +wire n12_1 ; +wire n90_1 ; +wire n13_1 ; +wire n91_1 ; +wire n92_1 ; +wire n93_1 ; +wire n94_1 ; +wire n95_1 ; +wire n14_1 ; +wire n96_1 ; +wire n15_1 ; +wire n97_1 ; +wire n98_1 ; +wire n99_1 ; +wire n100_1 ; +wire n101_1 ; +wire n112_1 ; +wire n16_1 ; +wire n17_1 ; +wire n18_1 ; +wire n19_1 ; +wire n20_1 ; +wire n21_1 ; +wire n22_1 ; +wire n23_1 ; +wire n24_1 ; +wire n25_1 ; +wire n26_1 ; +wire n27_1 ; +wire n28_1 ; +wire n29_1 ; +wire n30_1 ; +wire n31_1 ; +wire n32_1 ; +wire n33_1 ; +wire n34_1 ; +wire n35_1 ; +wire n36_1 ; +wire n37_1 ; +wire n38_1 ; +wire n39_1 ; +wire n40_1 ; +wire n41_1 ; +wire n42_1 ; +wire n43_1 ; +wire n46_1 ; +wire GND ; +wire VCC ; + VHI VCC_0 ( + .Z(VCC) +); + VLO GND_0 ( + .Z(GND) +); +// @16:865 + PUR PUR_INST ( + .PUR(VCC) +); +// @16:865 + GSR GSR_INST ( + .GSR(VCC) +); +// @8:162 +(* CHAN="CH0" *) DCUA DCU0_inst ( + .CH0_HDINP(hdinp), + .CH1_HDINP(GND), + .CH0_HDINN(hdinn), + .CH1_HDINN(GND), + .D_TXBIT_CLKP_FROM_ND(GND), + .D_TXBIT_CLKN_FROM_ND(GND), + .D_SYNC_ND(GND), + .D_TXPLL_LOL_FROM_ND(GND), + .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(GND), + .CH0_FF_RXI_CLK(tx_pclk), + .CH1_FF_RXI_CLK(VCC), + .CH0_FF_TXI_CLK(txi_clk), + .CH1_FF_TXI_CLK(VCC), + .CH0_FF_EBRD_CLK(tx_pclk), + .CH1_FF_EBRD_CLK(VCC), + .CH0_FF_TX_D_0(txdata[0]), + .CH1_FF_TX_D_0(GND), + .CH0_FF_TX_D_1(txdata[1]), + .CH1_FF_TX_D_1(GND), + .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(GND), + .CH0_FF_TX_D_3(txdata[3]), + .CH1_FF_TX_D_3(GND), + .CH0_FF_TX_D_4(txdata[4]), + .CH1_FF_TX_D_4(GND), + .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(GND), + .CH0_FF_TX_D_6(txdata[6]), + .CH1_FF_TX_D_6(GND), + .CH0_FF_TX_D_7(txdata[7]), + .CH1_FF_TX_D_7(GND), + .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(GND), + .CH0_FF_TX_D_9(GND), + .CH1_FF_TX_D_9(GND), + .CH0_FF_TX_D_10(xmit[0]), + .CH1_FF_TX_D_10(GND), + .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(GND), + .CH0_FF_TX_D_12(GND), + .CH1_FF_TX_D_12(GND), + .CH0_FF_TX_D_13(GND), + .CH1_FF_TX_D_13(GND), + .CH0_FF_TX_D_14(GND), + .CH1_FF_TX_D_14(GND), + .CH0_FF_TX_D_15(GND), + .CH1_FF_TX_D_15(GND), + .CH0_FF_TX_D_16(GND), + .CH1_FF_TX_D_16(GND), + .CH0_FF_TX_D_17(GND), + .CH1_FF_TX_D_17(GND), + .CH0_FF_TX_D_18(GND), + .CH1_FF_TX_D_18(GND), + .CH0_FF_TX_D_19(GND), + .CH1_FF_TX_D_19(GND), + .CH0_FF_TX_D_20(GND), + .CH1_FF_TX_D_20(GND), + .CH0_FF_TX_D_21(GND), + .CH1_FF_TX_D_21(GND), + .CH0_FF_TX_D_22(GND), + .CH1_FF_TX_D_22(GND), + .CH0_FF_TX_D_23(GND), + .CH1_FF_TX_D_23(GND), + .CH0_FFC_EI_EN(GND), + .CH1_FFC_EI_EN(GND), + .CH0_FFC_PCIE_DET_EN(GND), + .CH1_FFC_PCIE_DET_EN(GND), + .CH0_FFC_PCIE_CT(GND), + .CH1_FFC_PCIE_CT(GND), + .CH0_FFC_SB_INV_RX(GND), + .CH1_FFC_SB_INV_RX(GND), + .CH0_FFC_ENABLE_CGALIGN(GND), + .CH1_FFC_ENABLE_CGALIGN(GND), + .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(GND), + .CH0_FFC_FB_LOOPBACK(GND), + .CH1_FFC_FB_LOOPBACK(GND), + .CH0_FFC_SB_PFIFO_LP(GND), + .CH1_FFC_SB_PFIFO_LP(GND), + .CH0_FFC_PFIFO_CLR(GND), + .CH1_FFC_PFIFO_CLR(GND), + .CH0_FFC_RATE_MODE_RX(GND), + .CH1_FFC_RATE_MODE_RX(GND), + .CH0_FFC_RATE_MODE_TX(GND), + .CH1_FFC_RATE_MODE_TX(GND), + .CH0_FFC_DIV11_MODE_RX(GND), + .CH1_FFC_DIV11_MODE_RX(GND), + .CH0_FFC_RX_GEAR_MODE(GND), + .CH1_FFC_RX_GEAR_MODE(GND), + .CH0_FFC_TX_GEAR_MODE(GND), + .CH1_FFC_TX_GEAR_MODE(GND), + .CH0_FFC_DIV11_MODE_TX(GND), + .CH1_FFC_DIV11_MODE_TX(GND), + .CH0_FFC_LDR_CORE2TX_EN(GND), + .CH1_FFC_LDR_CORE2TX_EN(GND), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), + .CH1_FFC_LANE_TX_RST(GND), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), + .CH1_FFC_LANE_RX_RST(GND), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), + .CH1_FFC_RRST(GND), + .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(GND), + .CH0_FFC_RXPWDNB(rx_pwrup_c), + .CH1_FFC_RXPWDNB(GND), + .CH0_LDR_CORE2TX(GND), + .CH1_LDR_CORE2TX(GND), + .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), + .D_SCIWDATA2(sci_wrdata[2]), + .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), + .D_SCIWDATA5(sci_wrdata[5]), + .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), + .D_SCIADDR0(sci_addr[0]), + .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), + .D_SCIADDR3(sci_addr[3]), + .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), + .D_SCIENAUX(sci_en_dual), + .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), + .CH1_SCIEN(GND), + .CH0_SCISEL(sci_sel), + .CH1_SCISEL(GND), + .D_SCIRD(sci_rd), + .D_SCIWSTN(sci_wrn), + .D_CYAWSTN(cyawstn), + .D_FFC_SYNC_TOGGLE(GND), + .D_FFC_DUAL_RST(rst_dual_c), + .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), + .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(GND), + .CH1_FFC_CDR_EN_BITSLIP(GND), + .D_SCAN_ENABLE(GND), + .D_SCAN_IN_0(GND), + .D_SCAN_IN_1(GND), + .D_SCAN_IN_2(GND), + .D_SCAN_IN_3(GND), + .D_SCAN_IN_4(GND), + .D_SCAN_IN_5(GND), + .D_SCAN_IN_6(GND), + .D_SCAN_IN_7(GND), + .D_SCAN_MODE(GND), + .D_SCAN_RESET(GND), + .D_CIN0(GND), + .D_CIN1(GND), + .D_CIN2(GND), + .D_CIN3(GND), + .D_CIN4(GND), + .D_CIN5(GND), + .D_CIN6(GND), + .D_CIN7(GND), + .D_CIN8(GND), + .D_CIN9(GND), + .D_CIN10(GND), + .D_CIN11(GND), + .CH0_HDOUTP(hdoutp), + .CH1_HDOUTP(n47_1), + .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n48_1), + .D_TXBIT_CLKP_TO_ND(n1_1), + .D_TXBIT_CLKN_TO_ND(n2_1), + .D_SYNC_PULSE2ND(n3_1), + .D_TXPLL_LOL_TO_ND(n4_1), + .CH0_FF_RX_F_CLK(n5_1), + .CH1_FF_RX_F_CLK(n49_1), + .CH0_FF_RX_H_CLK(n6_1), + .CH1_FF_RX_H_CLK(n50_1), + .CH0_FF_TX_F_CLK(n7_1), + .CH1_FF_TX_F_CLK(n51_1), + .CH0_FF_TX_H_CLK(n8_1), + .CH1_FF_TX_H_CLK(n52_1), + .CH0_FF_RX_PCLK(n9_1), + .CH1_FF_RX_PCLK(n53_1), + .CH0_FF_TX_PCLK(tx_pclk), + .CH1_FF_TX_PCLK(n54_1), + .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n55_1), + .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n56_1), + .CH0_FF_RX_D_2(rxdata[2]), + .CH1_FF_RX_D_2(n57_1), + .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n58_1), + .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n59_1), + .CH0_FF_RX_D_5(rxdata[5]), + .CH1_FF_RX_D_5(n60_1), + .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n61_1), + .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n62_1), + .CH0_FF_RX_D_8(rx_k[0]), + .CH1_FF_RX_D_8(n63_1), + .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n64_1), + .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n65_1), + .CH0_FF_RX_D_11(n10_1), + .CH1_FF_RX_D_11(n66_1), + .CH0_FF_RX_D_12(n67_1), + .CH1_FF_RX_D_12(n68_1), + .CH0_FF_RX_D_13(n69_1), + .CH1_FF_RX_D_13(n70_1), + .CH0_FF_RX_D_14(n71_1), + .CH1_FF_RX_D_14(n72_1), + .CH0_FF_RX_D_15(n73_1), + .CH1_FF_RX_D_15(n74_1), + .CH0_FF_RX_D_16(n75_1), + .CH1_FF_RX_D_16(n76_1), + .CH0_FF_RX_D_17(n77_1), + .CH1_FF_RX_D_17(n78_1), + .CH0_FF_RX_D_18(n79_1), + .CH1_FF_RX_D_18(n80_1), + .CH0_FF_RX_D_19(n81_1), + .CH1_FF_RX_D_19(n82_1), + .CH0_FF_RX_D_20(n83_1), + .CH1_FF_RX_D_20(n84_1), + .CH0_FF_RX_D_21(n85_1), + .CH1_FF_RX_D_21(n86_1), + .CH0_FF_RX_D_22(n87_1), + .CH1_FF_RX_D_22(n88_1), + .CH0_FF_RX_D_23(n11_1), + .CH1_FF_RX_D_23(n89_1), + .CH0_FFS_PCIE_DONE(n12_1), + .CH1_FFS_PCIE_DONE(n90_1), + .CH0_FFS_PCIE_CON(n13_1), + .CH1_FFS_PCIE_CON(n91_1), + .CH0_FFS_RLOS(rx_los_low_s), + .CH1_FFS_RLOS(n92_1), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n93_1), + .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n94_1), + .CH0_FFS_CC_OVERRUN(ctc_orun_s), + .CH1_FFS_CC_OVERRUN(n95_1), + .CH0_FFS_RXFBFIFO_ERROR(n14_1), + .CH1_FFS_RXFBFIFO_ERROR(n96_1), + .CH0_FFS_TXFBFIFO_ERROR(n15_1), + .CH1_FFS_TXFBFIFO_ERROR(n97_1), + .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n98_1), + .CH0_FFS_SKP_ADDED(ctc_ins_s), + .CH1_FFS_SKP_ADDED(n99_1), + .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n100_1), + .CH0_LDR_RX2CORE(n101_1), + .CH1_LDR_RX2CORE(n112_1), + .D_SCIRDATA0(sci_rddata[0]), + .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), + .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), + .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n16_1), + .D_SCAN_OUT_1(n17_1), + .D_SCAN_OUT_2(n18_1), + .D_SCAN_OUT_3(n19_1), + .D_SCAN_OUT_4(n20_1), + .D_SCAN_OUT_5(n21_1), + .D_SCAN_OUT_6(n22_1), + .D_SCAN_OUT_7(n23_1), + .D_COUT0(n24_1), + .D_COUT1(n25_1), + .D_COUT2(n26_1), + .D_COUT3(n27_1), + .D_COUT4(n28_1), + .D_COUT5(n29_1), + .D_COUT6(n30_1), + .D_COUT7(n31_1), + .D_COUT8(n32_1), + .D_COUT9(n33_1), + .D_COUT10(n34_1), + .D_COUT11(n35_1), + .D_COUT12(n36_1), + .D_COUT13(n37_1), + .D_COUT14(n38_1), + .D_COUT15(n39_1), + .D_COUT16(n40_1), + .D_COUT17(n41_1), + .D_COUT18(n42_1), + .D_COUT19(n43_1), + .D_REFCLKI(pll_refclki), + .D_FFS_PLOL(n46_1) +); +defparam DCU0_inst.D_MACROPDB = "0b1"; +defparam DCU0_inst.D_IB_PWDNB = "0b1"; +defparam DCU0_inst.D_XGE_MODE = "0b0"; +defparam DCU0_inst.D_LOW_MARK = "0d4"; +defparam DCU0_inst.D_HIGH_MARK = "0d12"; +defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; +defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; +defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; +defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; +defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; +defparam DCU0_inst.CH0_UC_MODE = "0b0"; +defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; +defparam DCU0_inst.CH0_RIO_MODE = "0b0"; +defparam DCU0_inst.CH0_WA_MODE = "0b0"; +defparam DCU0_inst.CH0_INVERT_RX = "0b0"; +defparam DCU0_inst.CH0_INVERT_TX = "0b0"; +defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; +defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0"; +defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; +defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; +defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; +defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; +defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; +defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_CTC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; +defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1"; +defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; +defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; +defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC"; +defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050"; +defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; +defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; +defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; +defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010"; +defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; +defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00"; +defparam DCU0_inst.CH0_REQ_EN = "0b1"; +defparam DCU0_inst.CH0_RTERM_RX = "0d22"; +defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; +defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; +defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; +defparam DCU0_inst.CH0_TPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0"; +defparam DCU0_inst.CH0_RTERM_TX = "0d19"; +defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; +defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101"; +defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; +defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; +defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; +defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_RPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0"; +defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; +defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010"; +defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; +defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; +defparam DCU0_inst.CH0_RX_LOS_EN = "0b1"; +defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0"; +defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; +defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; +defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; +defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; +defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; +defparam DCU0_inst.CH0_RXIN_CM = "0b11"; +defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; +defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; +defparam DCU0_inst.D_TX_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100"; +defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; +defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; +defparam DCU0_inst.CH0_PROTOCOL = "GBE"; +defparam DCU0_inst.D_ISETLOS = "0d0"; +defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; +defparam DCU0_inst.D_SETICONST_AUX = "0b00"; +defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; +defparam DCU0_inst.D_SETICONST_CH = "0b00"; +defparam DCU0_inst.D_REQ_ISET = "0b000"; +defparam DCU0_inst.D_PD_ISET = "0b00"; +defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; +defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; +defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; +defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; +defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; +defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; +defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; +defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; +defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; +defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; +defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; +defparam DCU0_inst.CH0_DCOSTEP = "0b00"; +defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; +defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; +defparam DCU0_inst.CH0_DCOITUNE = "0b00"; +defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; +defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; +defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; +defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; +defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; +defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; +defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; +defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; +defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; +defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; +defparam DCU0_inst.D_SETPLLRC = "0d1"; +defparam DCU0_inst.D_REFCK_MODE = "0b001"; +defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; +defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; +defparam DCU0_inst.D_RG_EN = "0b0"; +defparam DCU0_inst.D_RG_SET = "0b00"; +defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; +defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; +defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; +defparam DCU0_inst.D_CMUSETZGM = "0b000"; +defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; +defparam DCU0_inst.D_CMUSETP1GM = "0b000"; +defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; +defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; +defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; +defparam DCU0_inst.D_CMUSETICP4P = "0b01"; +defparam DCU0_inst.D_CMUSETBIASI = "0b00"; +// @8:424 + sgmii_ecp5sll_core_Z1_layer1 sll_inst ( + .tx_pclk(tx_pclk), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki), + .pll_lock_i(pll_lol) +); +// @8:394 + sgmii_ecp5rsl_core_Z2_layer1 rsl_inst ( + .rx_pcs_rst_c(rx_pcs_rst_c), + .tx_pcs_rst_c(tx_pcs_rst_c), + .tx_serdes_rst_c(tx_serdes_rst_c), + .serdes_rst_dual_c(serdes_rst_dual_c), + .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c), + .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c), + .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c), + .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rsl_tx_rdy(rsl_tx_rdy), + .pll_lock_i(pll_lol), + .pll_refclki(pll_refclki), + .rsl_rx_rdy(rsl_rx_rdy), + .rsl_rst(rsl_rst), + .rxrefclk(rxrefclk), + .rsl_disable(rsl_disable), + .rx_serdes_rst_c(rx_serdes_rst_c), + .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c), + .rst_dual_c(rst_dual_c), + .rx_cdr_lol_s(rx_cdr_lol_s), + .rx_los_low_s(rx_los_low_s) +); +endmodule /* sgmii_ecp5 */ + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf new file mode 100644 index 0000000..9cbac38 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf @@ -0,0 +1,29 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints +#FREQUENCY PORT "pll_refclki" 100.0 MHz; +#FREQUENCY PORT "rxrefclk" 100.0 MHz; +#FREQUENCY NET "tx_pclk" 100.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk"; +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap new file mode 100644 index 0000000..3910cac --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap new file mode 100644 index 0000000..af92e0b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap new file mode 100644 index 0000000..3793ead --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap @@ -0,0 +1 @@ +./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db new file mode 100644 index 0000000000000000000000000000000000000000..f26fd6af62093a2882e7d380ad36bb0ae93eb77f GIT binary patch literal 20480 zcmeI3&uL&#F;;$SB{+9Kcc<#*ngrI)aU)-AF27(OBDJ>UhmB8d*6BcdG_IX$4?$@3B_64 z3tUUFiuSdp>)I{GG);RA#~C=%HU*vjkv2W;eBk_AEB*b7fWZ{GrP1x|FXS)iU_$~( z00|%gB!C2v01`j~NB{|(KmrGsr>1kWv-)9PSxtv4;R@M_-_P86ys^Hs!FJYfZ*8z* zJXyTvHD7RBv7Qy!yH;?6xm*Rp9*%pK)8)fqR|*vlhcCS5aA13`%jJlc9|+e9UT(*d zP0w?`%b5CX-Lq*fb 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sgmii_ecp5. +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +@N|Running in 64-bit mode + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml new file mode 100644 index 0000000..797309b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml @@ -0,0 +1,41 @@ + + + + + + /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr + Synopsys HDL Compiler + + + Completed + + + + 15 + /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt + + + 76 + /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt + + + 0 + /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt + + + - + + + 00h:00m:02s + + + - + + + 1557471731 + + + \ No newline at end of file diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt new file mode 100644 index 0000000..d386b26 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt @@ -0,0 +1,77 @@ +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml new file mode 100644 index 0000000..8733c9b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt +Resource Usage + + +221 + + +0 + + +0 + + +0 + + +154 + + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt new file mode 100644 index 0000000..d8e3e2c --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt @@ -0,0 +1,22 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..c6da126 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +3 / 0 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..05527dc --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +22 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt + + + +4 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt + + + +0h:00m:03s + + +0h:00m:03s + + +153MB + + +1557471736 + + + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..8f866cb --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml @@ -0,0 +1,41 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +sgmii_ecp5|pll_refclki +100.0 MHz +168.9 MHz +4.079 + + +sgmii_ecp5|rxrefclk +100.0 MHz +167.9 MHz +4.043 + + +sgmii_ecp5|tx_pclk_inferred_clock +100.0 MHz +237.5 MHz +5.789 + + +System +100.0 MHz +840.7 MHz +8.810 + + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt new file mode 100644 index 0000000..6170ebf --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt @@ -0,0 +1,4 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt new file mode 100644 index 0000000..bd89dbb --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt @@ -0,0 +1,9 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml new file mode 100644 index 0000000..3878c1e --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +9 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt + + + +3 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +144MB + + +1557471733 + + + diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt new file mode 100644 index 0000000..3044eef --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt @@ -0,0 +1,3 @@ +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr new file mode 100644 index 0000000..5d31417 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr @@ -0,0 +1,357 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:02:09 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 09:02:10 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:11 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:11 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..a986936281551f5f31b97a5f3f9dab68cedc9ff9 GIT binary patch literal 28672 zcmeI5U2G#)6@cy7j`Qy>n`NQxwwI-}yEL`u*RkF1w!7Pqrb$S5leDa&Wi+-Y&LrcR z*_m;EmK1O#1VWXNc;SHuo{)IxGvXD2kPzab4-=oy zZmwXgWUk}i^PO|&-gEAqbFz4IPWLplYB_b)Lt^ZSSUetk4WU>pmV)0j{I+j#xRY%E z0WJRfuv;qj(#PK!g;&Kh-;Kdfbc-|)X&}--q=85Skp?0SL>h=R5NRONK%{|41OMk5 z@Z#z77cRt`FMDd)(CV7&sx{4Rw|zHmOLQB`K&rPBBqnGq5+Eks&n(9m-LpL`% zf3;rHd0;~~yIyR=J9X2$jD!4S<^k4yI`i+$KQbR>9t{6;_{pK{;PrvG)9d|TPklf6 z;bLyhs%ts5>gcMOtLa|ObIP(?$$47c zHdIf`*^afYRlJ;AtLwUdRJ4jMcimN7Yt=KXnqJ9nUM%sGVzI>ejl6r!Fp#6EU?VUq zQe9WCnRU(dT;y4(tb2%;khO|xnprkB&u#4zg@duj}_zPq)nMmg<kwnC6#WT(kTF(@GRFSnRAI7)BGeAIH4$(WTC{9 zR^GjZy;aQTXw`;URZXwU8P1xPr(uV6yq~&Qg~^gEfmpaL9#O1`6o_^6Ygk)iUZT+z zIGHa^mU!F<((dAp31)Tmdsty$`UZp!B>o_ghie!RA%MYk6QaJdqdGfi%W^jMwfIaD zi>pu+x0o+radE?Q4;OdGtn?IcFaZJ<=Rv^N^CB0DKC_!^)r%#O1F_)1=Yv8K^>j3t z-Q-)!+IzPTM0sHvi!v#+MZxi04x&F#uV^_qi|UqH&52o_Q?~O`&fPKXvg&F%P<{@+ zHs^X(|Lb`{Eb*WcXas(DQG*Wv143+u&qCKS8aP11fuHUAJ$~<92>Tz?*F*H){{|dV zG8~f6!69)L@6Dfuz&_K=^o?zf{%-X7k?%$Ee-!^yTkMG9|BzO8qWJ$b*X$_zol*RM ziiVBi|4`PQ^(g*7y$yvZ{tu-ONAds3cEO_f|2TVwQT%_xJ=iGzhn?r+Ez2 zHB3+ODk}p2=v(pX=NV%RZcc~8c#$#2;GT3ijGtqSF&K)5!nlSAW1X4vk?*yCcj7B# z)}CbzwU_&Ta@1#7Lk$kIohzSCj(UML)Zl0vChF6yp#}%tFj1dk4K+CShKO2wlAvxd zGXnRz2~cjQfkh_ z`ZytF=nC;(-tWn;5clK%4`P|8#|ooMBlhrnLq8e(#lZda$LaC@Tp7kQAH&^@{|O zoh>2?zJPj}F-8imfO?5B#^54ID5H-00%MF6ydCv<#uzC$JL(r0V+`Nd@vr~C8p|w? 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 4.90ns 155 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 09:02:16 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.043 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.902 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.043 + + Number of logic level(s): 11 + Starting point: rsl_inst.genblk2\.rxs_rst / Q + Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - +rxs_rst Net - - - - 6 +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - +rsl_rx_serdes_rst_c Net - - - - 3 +rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - +rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - +dual_or_rserd_rst Net - - - - 9 +rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - +rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - +rx_any_rst Net - - - - 2 +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - +rxr_wt_cnt9 Net - - - - 14 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - +rxr_wt_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - +rxr_wt_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - +rxr_wt_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - +rxr_wt_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - +rxr_wt_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - +rxr_wt_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - +rxr_wt_cnt_s[11] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - +================================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 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+CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 +CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 +CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr new file mode 100644 index 0000000..8337c2b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr @@ -0,0 +1,12 @@ +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:02:12 2019 + +###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr new file mode 100644 index 0000000..0a65ebd --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr @@ -0,0 +1,86 @@ +# Fri May 10 09:02:12 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! 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    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:12 2019
+
+###########################################################]
+
+
     +
    +
+# Fri May 10 09:02:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+Linked File: sgmii_ecp5_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N:BN362 : sgmii_ecp5_softlogic.v(1408) | Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1244) | Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1252) | Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1236) | Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1268) | Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1260) | Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W:MT529 : sgmii_ecp5_softlogic.v(1988) | Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : sgmii_ecp5_softlogic.v(567) | Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : sgmii_ecp5_softlogic.v(1988) | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:MO225 : sgmii_ecp5_softlogic.v(1801) | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 09:02:13 2019
+
+###########################################################]
+
+
     +
    +
+# Fri May 10 09:02:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:MO225 : sgmii_ecp5_softlogic.v(1801) | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N:MO231 : sgmii_ecp5_softlogic.v(1350) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(1304) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(1759) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(412) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(909) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(527) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(778) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(680) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     4.90ns		 155 /       221
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+ClockId0001        pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+ClockId0002        rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+ClockId0003        DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W:MT246 : sgmii_ecp5.vhd(162) | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 09:02:16 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 09:02:16 2019
+
+###########################################################]
+
+
     diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm new file mode 100644 index 0000000..7eb2da0 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/statusReport.html b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..3cf8cd2 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/statusReport.html @@ -0,0 +1,115 @@ + + + Project Status Summary Page + + + + + + +
    + + + + + + + + + + +
    Project Settings
    Project Name sgmii_ecp5 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module sgmii_ecp5
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete15760-00m:02s-5/10/19
    9:02 AM
    (premap)Complete9300m:00s0m:00s144MB5/10/19
    9:02 AM
    (fpga_mapper)Complete22400m:03s0m:03s153MB5/10/19
    9:02 AM
    Multi-srs GeneratorComplete5/10/19
    9:02 AM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 221I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 154

    + + + + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    sgmii_ecp5|pll_refclki100.0 MHz168.9 MHz4.079
    sgmii_ecp5|rxrefclk100.0 MHz167.9 MHz4.043
    sgmii_ecp5|tx_pclk_inferred_clock100.0 MHz237.5 MHz5.789
    System100.0 MHz840.7 MHz8.810
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 3 / 0

    +
    +
    + \ No newline at end of file diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/.cckTransfer new file mode 100644 index 0000000000000000000000000000000000000000..b4c45f7568eff1935f2bb86e32cabafe5d0c22e6 GIT binary patch literal 456 zcmV;(0XP01iwFP!0000015#C0RVXORFG)=>pKqQ)N6H;gm~}q>39KS z8E=J0|4m>w&WRXu@FiknLB_ZVh}r0Sk1g}?!GF|X^&pEO=dq)2HRhxpPVMR!ZtGn) zE6sR5KLTji(+bsP8)fuf&$PwoPbaje_2b70?P?>@#t>p{*bm1BJv6-Ua0o(vpSjqi z4!H}+L1lQ$Hzb*DVbV;J4L&m5Wz@{%6d~`~5$b(o15!DPOGYOa89VSC(u~n_n2iY1 zgP1{%C1hAC@}@#+5^wT3{Rz=FrFX6~>tfofs y<#{gtcmZW<0o=o~`0^Q+=)e0ssL2{{sMNLS0y`0ssJEw%q>! literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_mh_info b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_mh_info new file mode 100644 index 0000000..1a725a4 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_mh_info @@ -0,0 +1,2 @@ +|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info| +|2| diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile new file mode 100644 index 0000000..d5a098c --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile @@ -0,0 +1,69 @@ +%%% protect protected_file +#OPTIONS:"|-bldtbl|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 +@E8lFkRDC#HolHO_CbD6 +HNLssI$RF +s Fbk0kE0R80Fkb +R4Fbk0kE0R80FkM +R4HkMb08REHRMb4M +HbRk0EM8HM +R4HkMb0GRssOCVD4 R +0FkbRk00bG_ORD 4M +HbRk00_GHORD 4M +HbRk00NG80UNR +bHMk00RGR_ 4M +HbRk0G0lHRH4 +M0bkR_0G8bH#_sOFs0CORF4 +kk0b0GRs8NN0RFU +kk0b0GRs_4 R +0FkbRk0s8G_H_#bCRss4k +F00bkR_sGOCP_s4sR +bHMk#0RHNoMDC_800CO_4OR +0FkbRk0sDG_FD#_F#I_RF4 +kk0b0#RDl0_#N#0k_4#R +0FkbRk0O_0OkMsk_4#R +0FkbRk0O_0OFMsk_4#R +0FkbRk0sOG_8Ds_F#D_RF4 +kk0b00ROOM_H#R_#4k +F00bkROO0_D8C_4#R +bHMk#0RDsH_#40R +bHMk00RGI_bs_kbO +R4HkMb0GRs_sbIkOb_RH4 +M0bkRH#O_8IsNR0NUM +HbRk0#_OHNs88RFn +kk0b0OR#H8_s8NN0RHU +M0bkRH#O__CM8DkNRH4 +M0bkRH#O_D#C_N8kD +R4HkMb0OR#HM_CRH4 +M0bkRH#O_D#CRH4 +M0bkRH#O_Rs84M +HbRk0#_OHIRsM4k +F00bkRH#O_0HMRH4 +M0bkRNO$IM#0RH4 +M0bkRs#C8_C#bR8L4M +HbRk0b_DDsOCVDR H4M +HbRk0s_#D8NH#LRDC4M +HbRk0s_#DsR#04M +HbRk0#8CsCs#_#80_k_NDO +R4HkMb0#Rs0k_8NOD_RH4 +M0bkR_0G#8CsCs#_#O0_RH4 +M0bkR_0Gb_O#s_#0O +R4Fbk0kb0RDDD_F4DR +0FkbRk0s_#D0sG_84$R +bHMks0RGC_#s#8C_0s#_4OR +bHMks0RGO_b##_s0R_O4k +F00bkRDs#__sGsR8$4M +C88lFk +DC + +@ diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdep b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdep new file mode 100644 index 0000000..23da417 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdep @@ -0,0 +1,33 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 +0 "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work sgmii_ecp5 v1 0 +module work sgmii_ecp5 0 + +# Unbound Instances to File Association +inst work sgmii_ecp5 sgmii_ecp5sll_core 0 +inst work sgmii_ecp5 sgmii_ecp5rsl_core 0 +inst work sgmii_ecp5 dcua 0 + + +# Configuration files used diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdeporig b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdeporig new file mode 100644 index 0000000..7f50852 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdeporig @@ -0,0 +1,29 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728 +0 "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work sgmii_ecp5 v1 0 +module work sgmii_ecp5 0 + +# Unbound Instances to File Association +inst work sgmii_ecp5 sgmii_ecp5sll_core 0 +inst work sgmii_ecp5 sgmii_ecp5rsl_core 0 +inst work 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+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557471729 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630 +#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557471728 +#numinternalfiles:6 +#defaultlanguage:verilog +0 "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog +#Dependency Lists(Uses List) +0 -1 +#Dependency Lists(Users Of) +0 -1 +#Design Unit to File Association +module work sgmii_ecp5rsl_core 0 +module work sync 0 +module work sgmii_ecp5sll_core 0 +#Unbound instances to file Association. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr new file mode 100644 index 0000000..37d628b --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr @@ -0,0 +1 @@ +#XMR Information diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info new file mode 100644 index 0000000..ddcec68 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info @@ -0,0 +1,2 @@ +|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;| +|work.sgmii_ecp5sll_core|parameter PPROTOCOL "GBE";,parameter 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0000000..52a25c2 --- /dev/null +++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.tlg @@ -0,0 +1,252 @@ +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. 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TMS, TDI, JTDO2, JTDO1, +output TDO, JTDI, JTCK, JRTI2, JRTI1, +output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 ) +/* synthesis syn_black_box syn_noprune=1 */; //synthesis syn_black_box +parameter ER1 = "ENABLED"; +parameter ER2 = "ENABLED"; +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAG_ECP5UM.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAG_ECP5UM.v new file mode 100644 index 0000000..ac5e46d --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAG_ECP5UM.v @@ -0,0 +1,219 @@ +module JTAG_ECP5UM( + grst_ni, + tck, + tms, + tdi, + tdo, + PC_Clk, + PC_Data_In, + PC_Ready, + PC_Reset, + Cnt, + PC_Data_Out, + PC_Ack, + PC_Error); + + input grst_ni; + input tck; + input tms; + input tdi; + output tdo; + input PC_Data_Out; + input PC_Ack; + input PC_Error; + output PC_Clk; + output PC_Data_In; + output PC_Ready; + output PC_Reset; + output Cnt; + wire JTCK; + wire JTDI; + wire JSHIFT; + wire JRSTN; + wire JCE1; + reg JTDI_x; + reg JSHIFT_x; + reg JRSTN_x; + reg JCE1_x; + reg JTDO1; + reg[5:0] Count; + reg[2:0] State; + reg JTD01_a; + reg JTD01_b; + reg PC_Ready_i; + reg PC_Clk_a; + reg PC_Clk_b; + reg PC_Reset; + reg PC_Data_In; + +JTAGG JTAGG( + + // External Pad Interface + .TCK (tck), + .TMS (tms), + .TDI (tdi), + .TDO (tdo), + + + .JTDO1 (JTDO1), + .JTDO2 (1'b0), + .JTDI (JTDI), + .JTCK (JTCK), + .JRTI1 (), + .JRTI2 (), + .JSHIFT (JSHIFT), + .JUPDATE (), + .JRSTN (JRSTN), + .JCE1 (JCE1), + .JCE2 () + +// Oringal XP I/O List + // .JTDO1 (JTDO1), + // .JTDO2 (0), + // .JTCK (JTCK), + // .JRTI1 (), + // .JRTI2 (), + // .JTDI (JTDI), + // .JSHIFT (JSHIFT), + // .JUPDATE(), + // .JRSTN (JRSTN), + // .JCE1 (JCE1), + // .JCE2 () + + +); + + +initial +begin +// PC_Clk_a = 1'b0; +// State = 3'd0; +// Count = 6'd0; +end + + always @(negedge JTCK or negedge grst_ni) // Delayed Data + begin + if (~grst_ni) begin + JTDI_x <= 1'b0; + JSHIFT_x <= 1'b0; + JRSTN_x <= 1'b0; + JCE1_x <= 1'b0; + end else begin + JTDI_x <= JTDI; + JSHIFT_x <= JSHIFT; + JRSTN_x <= JRSTN; + JCE1_x <= JCE1; + end + end + + always @(posedge JTCK or negedge grst_ni) begin // Count + if (~grst_ni) begin + Count <= 6'b0; + end else begin + if (JCE1_x == 1) begin + if (JSHIFT_x == 0) begin + Count <= 0; + end else begin + Count <= Count + 1; + end + end + end + end + +//* kes (011006): Only states 6, 5, and 1 are actualy used. First +//* three bits of tdi provide opcode and determine selective clock +//* assertion to target below. These are always required. +always @(posedge JTCK or negedge grst_ni) begin + if (~grst_ni) begin + State <= 3'b0; + end else begin + if ((Count == 1) | (Count == 2) | (Count == 3)) begin // 0 1 0 Ph2 of Write + State <= {State[1:0], JTDI_x}; // 0 1 1 (Don't Care) + end // 1 0 0 (Don't Care) + end + end + // 1 0 1 Ph1 of Read + // 1 1 0 Ph1 of Write + // 1 1 1 (Don't Care) + + always @(posedge JTCK or negedge grst_ni) begin + if (~grst_ni) begin + JTDO1 <= 1'b0; + JTD01_b <= 1'b0; + JTD01_a <= 1'b0; + end else begin + if (Count == 4) begin + JTDO1 <= PC_Ack; + JTD01_b <= PC_Error; + end else begin + JTDO1 <= JTD01_b; + JTD01_b <= JTD01_a; + end + JTD01_a <= PC_Data_Out; + end + end + + always @(posedge JTCK or negedge grst_ni) begin + if (~grst_ni) begin + PC_Data_In <= 1'b0; + PC_Reset <= 1'b0; + end else begin + if (Count > 3) begin + PC_Data_In <= JTDI_x; // PC_Data_In + end + PC_Reset <= JRSTN_x; // PC_Reset + end + end + +//* kes (011006): Writes and Phase 1 read operations require the full 55+ +//* (actually ~58) cycles of tdi even though many tdi bits/fields are +//* unused & not passed on to the target. Done to simplify I guess. +//* tdi bits are selectively passed by turning on and off the clock +//* used by the target. Phase 2 reads are shorter - see below. + always @(posedge JTCK or negedge grst_ni) begin + if (~grst_ni) begin + PC_Clk_a <= 1'b0; + end else begin + if (((State == 'b001) & (Count > 3) & (Count <= 12)) | // Read Data (+ extra clock at 12) + ((State == 'b110) & (Count > 16) & (Count <= 24)) | // Write Data + ((State[2] == 1 ) & (Count > 30) & (Count <= 48)) | // Address + ((State == 'b010) & (Count == 12) )) begin // (extra clock at 12 for writes) + if (PC_Clk_a == 1) begin + PC_Clk_a <= 0; + end else begin + PC_Clk_a <= 1; + end + end + end + end + + always @(negedge JTCK or negedge grst_ni) + if (~grst_ni) begin + PC_Clk_b <= 1'b0; + end else begin + PC_Clk_b <= PC_Clk_a; + end + +//* kes (011006): Ready only generted for writes and phase 1 reads. Phase2 +//* reads do not require additional work inside orcastra.v other than to +//* shift data back when this models selectively provides clocks as part +//* of the phase 2 operation. It can be shorter then than write & ph1 write + always @(posedge JTCK or negedge grst_ni) begin + if (~grst_ni) begin + PC_Ready_i <= 1'b0; + end else begin + if ((Count == 55) & (State[2] == 1)) begin + PC_Ready_i <= 1; + end else begin + if (Count == 3) begin + PC_Ready_i <= 0; + end + end + end + end + + assign PC_Ready = PC_Ready_i; + assign PC_Clk = PC_Clk_a ^ PC_Clk_b; + assign Cnt = Count; + +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/rxmac_clk_pll.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/rxmac_clk_pll.v new file mode 100644 index 0000000..7d2dfbe --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/rxmac_clk_pll.v @@ -0,0 +1,87 @@ +/* Verilog netlist generated by SCUBA Diamond_2.2_Beta (60) */ +/* Module Version: 5.3 */ +/* D:\lscc\diamond\2.2\ispfpga\bin\nt\scuba.exe -w -n rxmac_clk_pll -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -fclkop 125 -fclkop_tol 0.0 -phasep 0 -fclkos 125 -fclkos_tol 0.0 -phases 0 -fclkos2 62.5 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -rst -lock -fb_mode 9 -e */ +/* Tue Mar 12 11:17:39 2013 */ + + +`timescale 1 ns / 1 ps +module rxmac_clk_pll (CLK, RESET, CLKFB, CLKOP, CLKOS, CLKOK, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute rxmac_clk_pll dont_touch true + input wire CLK; + input wire CLKFB; + input wire RESET; + output wire CLKOP; + output wire CLKOS; + output wire CLKOK; + output wire LOCK; + + wire REFCLK; + wire CLKOS2_t; + wire CLKOS_t; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "ENABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 9 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 4 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 4 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 10 ; + defparam PLLInst_0.CLKOS_DIV = 5 ; + defparam PLLInst_0.CLKOP_DIV = 5 ; + defparam PLLInst_0.CLKFB_DIV = 1 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "USERCLOCK" ; + EHXPLLL PLLInst_0 (.CLKI(CLK), .CLKFB(CLKFB), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(RESET), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), + .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOS2="62.500000" */ + /* synthesis FREQUENCY_PIN_CLKOS="125.000000" */ + /* synthesis FREQUENCY_PIN_CLKOP="125.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="125.000000" */ + /* synthesis ICP_CURRENT="13" */ + /* synthesis LPF_RESISTOR="24" */; + + assign CLKOK = CLKOS2_t; + assign CLKOS = CLKOS_t; + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 62.500000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 125.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 125.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 125.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 13 + // exemplar attribute PLLInst_0 LPF_RESISTOR 24 + // exemplar end + +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/txmac_clk_pll.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/txmac_clk_pll.v new file mode 100644 index 0000000..845300d --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/txmac_clk_pll.v @@ -0,0 +1,87 @@ +/* Verilog netlist generated by SCUBA Diamond_2.2_Beta (60) */ +/* Module Version: 5.3 */ +/* D:\lscc\diamond\2.2\ispfpga\bin\nt\scuba.exe -w -n txmac_clk_pll -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -fclkop 125 -fclkop_tol 0.0 -phasep 0 -fclkos 125 -fclkos_tol 0.0 -phases 0 -fclkos2 62.5 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -rst -lock -fb_mode 9 -e */ +/* Tue Mar 12 11:17:39 2013 */ + + +`timescale 1 ns / 1 ps +module txmac_clk_pll (CLK, RESET, CLKFB, CLKOP, CLKOS, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute txmac_clk_pll dont_touch true + input wire CLK; + input wire CLKFB; + input wire RESET; + output wire CLKOP; + output wire CLKOS; + output wire LOCK; + + wire REFCLK; + wire CLKOS2_t; + wire CLKOS_t; + wire CLKOP_t; + wire CLKOK; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "ENABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 9 ; + defparam PLLInst_0.CLKOS_FPHASE = 4 ; + defparam PLLInst_0.CLKOS_CPHASE = 6 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 4 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 10 ; + defparam PLLInst_0.CLKOS_DIV = 5 ; + defparam PLLInst_0.CLKOP_DIV = 5 ; + defparam PLLInst_0.CLKFB_DIV = 1 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "USERCLOCK" ; + EHXPLLL PLLInst_0 (.CLKI(CLK), .CLKFB(CLKFB), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(RESET), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), + .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOS2="62.500000" */ + /* synthesis FREQUENCY_PIN_CLKOS="125.000000" */ + /* synthesis FREQUENCY_PIN_CLKOP="125.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="125.000000" */ + /* synthesis ICP_CURRENT="13" */ + /* synthesis LPF_RESISTOR="24" */; + + assign CLKOK = CLKOS2_t; + assign CLKOS = CLKOS_t; + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 62.500000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 125.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 125.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 125.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 13 + // exemplar attribute PLLInst_0 LPF_RESISTOR 24 + // exemplar end + +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/readme.htm b/gbe/cores/sgmii/tsmac/ts_mac_eval/readme.htm new file mode 100644 index 0000000..b878a81 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/readme.htm @@ -0,0 +1,1355 @@ + + + + + + + + + + + + + +LatticeCORE IP Module Readme + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    + +
    + +

    Tri-Speed Ethernet Media Access Controller ReadMe

    + +

     

    + +

    General Information

    + +
    + +


    +Copyright Notice

    + + + + + +
    +

    Copyright 2000-2016© + Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This + confidential and proprietary software may be used only as authorized by a licensing + agreement from Lattice Semiconductor Corporation. The entire notice above + must be reproduced on all authorized copies and copies may only be made to + the extent permitted by a licensing agreement from Lattice Semiconductor + Corporation.

    +
    + +
    + +


    +Contacting +Lattice

    + +
    + +

     

    + + + + + + + + + + + + + + + + + + + + + + + +
    +

    Mail:

    +     		+

    Lattice + Semiconductor Corporation
    +5555 NE Moore + Court
    Hillsboro, + OR +  97124
    U.S.A.

    +
    +

    Telephone:

    +     		+

    1-800-Lattice + (USA and Canada)

    +
    +

     

    +     		+

    1-503-268-8001 + (other locations)

    +
    +

    Website:

    +     		+

    http://www.latticesemi.com

    +
    +

    E-mail:

    +     		+

    techsupport@latticesemi.com

    +
    + +

     

    + +
    + +

    IP Module Information

    + +
    + +


    +About this Module

    + + + + + + + + + + + + + + + + + + + +
    +

    IP Name:

    +     		+

    Tri-Speed + Ethernet Media Access Controller

    +
    +

    IP + Version:

    +     		+

    4.1

    +
    +

    IP + Release Date:

    +     		+

    Aug 2016

    +
    +

    Target + Technology:

    +     		+

    LatticeXP2, LatticeECP3, ECP5U, + ECP5UM, ECP5UM5G

    +
    + +


    +Software Requirements

    + + + + + + + + + + + + + + + +
    +

    Synthesis Tools + Supported:

    +     		+

    Synplify Pro for Lattice K-2015.09L-2
    + Lattice LSE Synthesis tool

    +
    +

    Simulation + Tools Supported:

    +     		+

    Active-HD 10.2(Windows + only)
    + ModelSim SE 10

    +
    +

    Lattice + Tool Supported:

    +     		+

    Diamond 3.7 or later

    +
    + +

     

    + +
    + +

    Implementing the IP Module +Using Lattice Diamond SW

    + +
    + +


    +Instantiating the Core

    + + + + + +
    +

    The + generated Tri-Speed_MAC core package includes + black-box (<user_name>_bb.v) and instance (<username>_inst.v) + templates that can be used to instantiate the core in a top-level design.

    +

    An + example RTL top-level reference source file(ts_mac_top.v) that can be used as + an instantiation template for the IP core is provided in <project_dir>\ts_mac_eval\<username>\src\rtl\top. + Users may also use this top-level reference as the starting template for the + top-level for their complete design.

    +
    + +


    +Hardware Evaluation

    + + + + + +
    +

    Lattice's IP hardware evaluation capability makes it + possible to create IP cores that operate in hardware for a limited period of + time (approximately four hours) without requiring the purchase on an IP + license. The hardware evaluation capability is enabled by default. It can be + disabled by Project->Active Strategy->Translate + Design Settings. The setting is + called "Hardware Evaluation" and the options are "Enable" + or "Disable".
    +      
    + When the Hardware Evaluation feature is enabled in the design, it will + generate a programming file that may be downloaded into the device. After initialization, + the IP core will be operational for approximately four hours. After four + hours, the device will stop working and it will be necessary to reprogram the + device to re-enable operation. This hardware evaluation capability is only + enabled if the core has not been licensed. During implementation, a license + check is performed. If the hardware evaluation feature is disabled, a pop-up + window will be displayed indicating a license failure. Click"OK" + in the window and the bitstream will not be generated. If a license is + detected, no pop-up window is displayed and core generation is completed with + no restrictions.

    +
    + +


    +Implementing the core only +design in a Top-Level Design

    + + + + + + + + +
    +

    As + described previously, the top-level file ts_mac_core_only_top.v + and ts_mac_core_only_top.vhd files provided in <project_dir>\ts_mac_eval\<username>\src\rtl\top + support the ability to implement just the Tri-Speed_MAC + IP core.

    +

    Push-button + top-level implementation of this top-level is supported via the Diamond project file <username>_core_only_eval.ldf located in <project_dir>\ts_mac_eval\<username>\impl\<synthesis>. +

    +

    This + design is intended only to provide an accurate indication of the device + utilization associated with the core itself and should not be used as an + actual implementation example.

    +
    +


    + To use the + project file:

    +
      +
    • Select File->Open->Project + in Lattice Diamond.
      • +
    • Browse to \<project_dir>\ts_mac_eval\<username>\impl\<synthesis> in the Open Project + dialog box.
      • +
    • Select and + open <username>_core_only_eval.ldf.At this point, all + of the files needed to support top-level synthesis and implementation + will be imported to the project.
      • +
    • Implement + the complete design via the standard Lattice Diamond GUI flow.
      • +
    +

     

    +
    + +

     

    + +

    Implementing +the reference design in a Top-Level Design

    + + + + + + + + +
    +

    Push-button + top-level implementation of a sample reference design is also supported via + the + Diamond project file <username>_reference_eval.ldf located in <project_dir>\ts_mac_eval\<username>\impl\<synthesis>. +

    +

    Implementation + of the reference evaluation configuration is targeted to a specific device + and package type for each device family. Specifically:

    +

    XP2:            LFXP2-17E-6F484C

    +

    ECP3:         LFE3-95EA-8FN484C

    +

    ECP5U:       LFE5U-85F-8BG756C

    +

    ECP5UM:     LFE5UM-85F-8BG756C

    +

    ECP5UM5G:     LFE5UM5G-85F-8BG756C

    +
    +


    + To use the + project file:

    +
      +
    • Select File->Open->Project + in Lattice Diamond.
    • Browse to \<project_dir>\ts_mac_eval\<username>\impl\<synthesis> in the Open Project + dialog box.
      • +
    • Select and + open <username>_reference_eval.ldf. At this point, all + of the files needed to support top-level synthesis and implementation + will be imported to the project.
      • +
    • Implement + the complete design via the standard Diamond GUI flow.
      • +
    +
    + +


    +Running Functional and Post +Route Timing +Simulation

    + + + + + + + + +
    +

    The + functional simulation includes a configuration-specific behavioral model of + the Tri_Speed MAC, which is + instantiated in an FPGA top level along with some test logic (PLLs, and registers + with Read/Write Interface). This FPGA top is instantiated in an eval + testbench that configures FPGA test logic registers and Tri_Speed + MAC IP core registers. The testbench files can be found in \<project_dir>\ts_mac_eval\testbench.
    +
    + Both Active-HDL and ModelSim are supported for simulation.

    +
    +

    Functional + Simulation
    + The + generated IP core package includes the configuration-specific behavior model + (<username>_beh.v) for functional simulation. ModelSim simulation is + supported via testbench files provided in \<project_dir>\ts_mac_eval\<username>\src\rtl\top\. Models required for simulation are provided + in the \<project_dir>\ts_mac_eval\models + directory.

    +

     

    +

    Users + may run the eval simulation by doing the following with ModelSim SE:

    +
      +
    • Open + ModelSim.
      • +
    • Under the File + tab, select Change Directory
    • Set the + directory to \<project_dir>\ts_mac_eval\<username>\sim\modelsim.
    • Select OK. +
    • Under the + Tools tab, select TCL, then select Execute Macro.
    • Select file + <username>_eval_se.do for ModelSim SE.
    +


    + NOTE1: When the simulation completes, a pop-up window will appear + asking "are you sure you want to finish?" Answer "no" to + analyze the results (answering "yes" closes ModelSim).

    +

    Users + may run the eval simulation by doing the following with Active-HDL(Windows Only):

    +
      +
    • Open Active-HDL.
      • +
    • Under the tools + tab, select Execute Macro...
      • +
    • Select file + \<project_dir>\ts_mac_eval\<username>\sim\aldec\<username>_eval.do
      • +
    • Select + OK.
      • +
    +

     

    +

    Post Route Timing Simulation

    +

    In order to run + the Post + Route + timing simulation, an IP license is required. For post route simulation, you + need to generate the timing simulation file by Selecting "Export Files->Verilog Simulation + File" in Process Window; This IP only supports Verilog TOP timing simulation).Users may run the + timing simulation by doing the following with ModelSim SE:

    +
      +
    • Open + ModelSim.
    • Under the File + tab, select Change Directory
    • Set the + directory to \<project_dir>\ts_mac_eval\<username>\sim\modelsim.
    • Select OK. +
    • Under the + Tools tab, select TCL, then select Execute Macro.
    • Select file + <username>_eval_timing_<lse|synp>_se.do for ModelSim + SE.
    +

    NOTE: When the + simulation completes, a pop-up window may appear asking, "are you sure + you want to finish?" Answer "No" to analyze the results + (answering "Yes" closes ModelSim).

    +

     

    +

    Users may run the + timing simulation by doing the following with Active-HDL(Windows only):

    +
      +
    • Open + Active-HDL.
      • +
    • Under the tools + tab, select Execute Macro...
      • +
    • Select file + \<project_dir>\ts_mac_eval\<username>\sim\aldec\<username>_eval_timing_<lse|synp>.do
      • +
    • Select + OK.
      • +
    +

     

    +
    + +


    +Reference Information
    +
    +The following documents provide more information on implementing this core:

    + +     +
    + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/tests/testcase.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/tests/testcase.v new file mode 100644 index 0000000..529fe15 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/tests/testcase.v @@ -0,0 +1,121 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: test_1.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +reg [7:0] dummy_data; + + +initial begin + $display(" .") ; + $display(" ==============================================================") ; + $display(" INFO : EVAL SIMULATION") ; + $display(" ==============================================================") ; + $display(" INFO : NOTE: This simulation includes the TSMAC IP Core,") ; + $display(" INFO : instantiated in an FPGA top level that consists of ") ; + $display(" INFO : test logic (MAC client side loop back logic, PLLs, ") ; + $display(" INFO : and registers with Read/Write Intf). This FPGA top ") ; + $display(" INFO : is instantiated in an eval testbench that configures ") ; + $display(" INFO : FPGA test logic and TSMAC IP core registers and sources") ; + $display(" INFO : ethernet packets (testcase.v)") ; + $display(" ==============================================================") ; + $display(" .") ; + $display(" .") ; + $display(" INFO : testcase STARTING") ; + repeat (10) @(posedge clk_125) ; + reset_n <= 1'b0 ; + repeat (10) @(posedge clk_125) ; + reset_n <= 1'b1 ; + +// delay to wait for initialization + repeat (10) @(posedge clk_125 ); + + // Test logic registers + orc_write(18'h08006, 8'hC1); // fifo AFL + orc_write(18'h08007, 8'h01); // fifo AFH + orc_write(18'h08008, 8'h05); // fifo AEL + orc_write(18'h08001, 8'h07); // tstcntl + orc_read(18'h08000, dummy_data); // verid + orc_read(18'h08006, dummy_data); // fifo AFL + orc_read(18'h08007, dummy_data); // fifo AFH + orc_read(18'h08008, dummy_data); // fifo AEL + + // MDIO registers + `ifdef MIIM_MODULE + orc_write(18'h00016, 8'h00); // to - MDIO DATA reg + orc_write(18'h00017, 8'h80); // to - MDIO DATA reg + orc_write(18'h00014, 8'h00); // to - MDIO ACCESS CTL reg + orc_write(18'h00015, 8'h21); // to - MDIO ACCESS CTL reg + #20000 + orc_read(18'h00014, dummy_data); // to - MDIO ACCESS CTL reg + orc_read(18'h00015, dummy_data); // to - MDIO ACCESS CTL reg + `endif + + // MAC registers + orc_write(18'h0000a, 8'hcd); // MAC Addr reg 0 + orc_write(18'h0000b, 8'haa); // MAC Addr reg 0 + orc_write(18'h0000c, 8'h12); // MAC Addr reg 1 + orc_write(18'h0000d, 8'hef); // MAC Addr reg 1 + orc_write(18'h0000e, 8'h56); // MAC Addr reg 2 + orc_write(18'h0000f, 8'h34); // MAC Addr reg 2 + + orc_write(18'h00002, 8'h9a); // to host bus - TX_RX_CTL reg + orc_read(18'h00002, dummy_data); // to host bus - TX_RX_CTL reg + + orc_write(18'h00008, 8'h48); // to host bus - IPG reg + orc_read(18'h00008, dummy_data); // to host bus - IPG reg + orc_read(18'h00009, dummy_data); // to host bus - IPG reg + + // Default to simulate with 1000M mode + orc_write(18'h00000, 8'h0f); // to host bus - mode reg + // To simulate the 100M mode, use the following mode reg + // orc_write(18'h00000, 8'h0e); // to host bus - mode reg + orc_read(18'h00000, dummy_data); // to host bus - mode reg + + + // FRAME TEMPLATE + // rx_frmgen (gben(1), des_addr(48), frm_len(14), num_premb(4), num_ipg(5), badcrc(1), norm_vlan_paus(2), + // pause_timer(16), bad_pcode(1), len_type(1), len_chkerr(1), badsfd(1), runt_frmid(3), frm_patn(4)); + + rx_frmgen(1'b1, 48'haacdef123456, 14'd75, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b1, 48'haacdef123456, 14'd70, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b1, 48'haacdef123456, 14'd66, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b1, 48'haacdef123456, 14'd64, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b1, 48'haacdef123456, 14'd32, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + /* For 100M Classic mode, use following rx_frmgen + rx_frmgen(1'b0, 48'haacdef123456, 14'd75, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b0, 48'haacdef123456, 14'd70, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b0, 48'haacdef123456, 14'd66, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b0, 48'haacdef123456, 14'd64, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + + rx_frmgen(1'b0, 48'haacdef123456, 14'd32, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE, + `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); + */ + + repeat (500) @(posedge clk_125 ); + // To simulate the 100M mode, will need long simulation time and should use following one: + //repeat (2000) @(posedge clk_125 ); + + $stop ; +end + +// ============================================================================= + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/env_params.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/env_params.v new file mode 100644 index 0000000..494f6e0 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/env_params.v @@ -0,0 +1,34 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: env_params.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +parameter K28_5 = 8'hBC , + K28_1 = 8'h3C , + K28_7 = 8'hFC , + D5_6 = 8'hC5 , + D16_2 = 8'h50 , + D21_5 = 8'hB5 , + D2_2 = 8'h42 , + D0_0 = 8'h00 , + K23_7 = 8'hF7 , + K27_7 = 8'hFB , + K29_7 = 8'hFD , + K30_7 = 8'hFE ; + +parameter ZEROS = 0 ; +parameter ONES = 1 ; +parameter INC = 2 ; +parameter DEC = 3 ; +parameter RAND = 4 ; + +parameter NPTI = 3'd0; +parameter NPTR = 3'd1; +parameter PTER = 3'd2; +parameter PTES = 3'd3; +parameter PTEI = 3'd4; +parameter PTEC = 3'd5; + +//============================================================================== + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/orcastra_drv.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/orcastra_drv.v new file mode 100644 index 0000000..e30f810 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/orcastra_drv.v @@ -0,0 +1,210 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: orcastra_drv.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== +// +`timescale 1 ns/100 ps + +`define FAIL 1'b1 +`define PASS 1'b0 +`define SYS_DATA 8 // system bus data bus size +`define SYS_ADDR 18 // system bus address bus size +`define SYS_SIZE 2 // system bus transfer size +`define half_period 10 // pc_clk half period = 200 ns + +module orcastra_drv( + pc_clk, + pc_datain, + pc_dataout, + pc_retry, + pc_error, + pc_ready, + pc_ack +); + +output pc_clk; +output pc_datain; +output pc_ready; +input pc_ack; +input pc_dataout; +input pc_retry; +input pc_error; + +reg pc_clk; +reg pc_ready; +reg wr; +reg da; +reg a; + +initial begin + pc_clk = 1'b0; + pc_ready = 1'b0; + wr = 1'b0; +end + +assign pc_datain = (wr) ? da:a; + +task single_write; + +input [`SYS_ADDR-1:0] address; +input [`SYS_DATA-1:0] data; +inout ret_status; + +integer i; + +reg status; +reg ret_status; + +begin + + status = `PASS; + + if (!status) begin + + wr = 1'b1; + + da = 0; + #`half_period + + // serial data phase + for (i=0;i<8;i=i+1) begin + + pc_clk = 1; + da = data[i]; + #`half_period; + pc_clk = 0; + #`half_period; + + end + + #`half_period; + #`half_period; + #`half_period; + #`half_period; + #`half_period; + + + // serial address phase + for (i=17;i>=0;i=i-1) begin + + pc_clk = 1; + da = address[i]; + #`half_period; + pc_clk = 0; + #`half_period; + + end + + da = 0; // WRITE + + pc_ready = 1; + //#`half_period; + //#`half_period; + //#`half_period; + //#`half_period; + //pc_ready = 0; + + // wait for an acknowledge and then wait ten clocks (simulate PC) + @(posedge pc_ack); + + for (i=10;i>=0;i=i-1) begin + #`half_period; + #`half_period; + end + + pc_ready = 0; // bring pc_ready low + + wr = 1'b0; + status = `PASS; + + end + + ret_status = ret_status | status; + +end + +endtask + +task single_read; + +input [`SYS_ADDR-1:0] address; +output [`SYS_DATA-1:0] data; +inout ret_status; + +reg status; +reg ret_status; +reg [7:0] data; + +integer i; + +begin + + status = `PASS; + + if (!status) begin + + a = 0; + #`half_period + + // serial address phase + for (i=17;i>=0;i=i-1) begin + + pc_clk = 1; + a = address[i]; + #`half_period; + pc_clk = 0; + #`half_period; + + end + + a = 1; // READ + + pc_ready = 1; + //#`half_period; + //#`half_period; + //#`half_period; + //#`half_period; + //pc_ready = 0; + + // wait for an acknowledge and then wait ten clocks (simulate PC) + @(posedge pc_ack); + + for (i=10;i>=0;i=i-1) begin + #`half_period; + #`half_period; + end + + pc_ready = 0; // bring pc_ready low + + // extra clock ??????? + pc_clk = 1; + #`half_period; + pc_clk = 0; + #`half_period; + + // serial data phase - read data + for (i=0;i<8;i=i+1) begin + + pc_clk = 1; + #`half_period; + pc_clk = 0; + data[i] = pc_dataout; + #`half_period; + + end + + #`half_period; + #`half_period; + + status = `PASS; + + end + + ret_status = ret_status | status; + +end + +endtask + +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/pkt_mon.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/pkt_mon.v new file mode 100644 index 0000000..d42b3ed --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/pkt_mon.v @@ -0,0 +1,624 @@ +/*================================================================ +-- Copyright (c) 2004 - Lattice Semiconductor Corporation +-- - NetCom IP +-- +-- This program is controlled by a written license agreement. +-- Unauthorized Reproduction or Use is Expressly Prohibited. +-- ================================================================*/ + +// file name: pkt_mon.v +// version: 1.0 +// date: may 13, 2008 +// +// code type: Behavioral Level +// +// Overview: This module monitors ethernet packets, and checks +// their crc and then prints them to a file. +// +// Rev: 0.0 - Initial Ver N.G +/*=================================================================*/ + +`timescale 1ns/100ps + + +// DEFINES + + +module pkt_mon( + reset_n, + gbit_en, + tx_clk, + `ifdef SGMII_TSMAC + tx_clk_en, + `endif + tx_en, + tx_er, + txd + ); + + + + // ethernet ports + input [7:0] txd; + input tx_er; + input tx_en; + + // general ports + input reset_n; // active low global reset + input gbit_en; // GbE mode enable + input tx_clk; // tx clock + + `ifdef SGMII_TSMAC + input tx_clk_en; + `endif + + integer out_file; // pointer to output file - ethernet_pkts_sink + + wire nib_enb; // + wire nib_enb_0; // nib_0 enable select (3:0) + wire nib_enb_1; // nib_0 enable select (7:4) + + // ------------------------------ + // signals related to monitor FSM + // ------------------------------ + reg [1:0] m_st; + reg [11:0] byt_cnt; + reg [15:0] pkt_cnt; + reg [7:0] txd_fe ; + reg [7:0] txd_fe_B ; + reg byte_valid_fe ; + reg tx_en_1d ; + reg tx_er_1d ; + reg tx_en_2d ; + reg tx_er_2d ; + reg [7:0] txd_1d ; + reg nib_cnt; // nibble counter - toggles + + reg [7:0] len_B0 ; + reg [15:0] len_B0B1 ; + reg [31:0] crc_reg; + reg [31:0] crc_reg_latched; + reg [7:0] Rx_CRC_B0 ; + reg [7:0] Rx_CRC_B1 ; + reg [7:0] Rx_CRC_B2 ; + reg [31:0] Rx_CRC ; + reg tx_error_latched ; + reg control_pkt ; + reg pause_pkt ; + reg vlan_pkt ; + reg [7:0] op_code_B0 ; + reg [7:0] vlan_len_B0 ; + + + parameter[1:0] + IDLE = 0, + PREMB = 1, + PKT_BODY = 2; + + parameter CRC_INIT_VALUE = 32'hffff_ffff; + + // ------------------------------ + + + +// Initializations +initial +begin + out_file = $fopen("ethernet_pkts_sink"); + m_st = 0; + byt_cnt = 0; + pkt_cnt = 0; + len_B0 = 0; + len_B0B1 = 0; + Rx_CRC_B0 = 0; + Rx_CRC_B1 = 0; + Rx_CRC_B2 = 0; + Rx_CRC = 0; +end + + + // wire assignments + assign nib_enb = nib_cnt; + assign nib_enb_0 = ( (nib_enb == 1'd0) && (tx_en == 1'b1) ) ? 1:0; + assign nib_enb_1 = ( (nib_enb == 1'd1) && (tx_en == 1'b1) ) ? 1:0; + + + // --------------------------------------------------------------------------------- + // 10/100 nib to bytes + // --------------------------------------------------------------------------------- + always @(posedge tx_clk or negedge reset_n) begin + if (~reset_n) begin + nib_cnt <= 1'b0; + txd_fe[7:0] <= 8'b0; + byte_valid_fe <= 1'b0; + tx_en_1d <= 1'b0; + tx_en_2d <= 1'b0; + tx_er_1d <= 1'b0; + tx_er_2d <= 1'b0; + txd_1d <= 8'b0; + txd_fe_B <= 8'b0; + end + else begin + + txd_1d <= txd; + tx_en_1d <= tx_en; + tx_en_2d <= tx_en_1d; + tx_er_1d <= tx_er; + tx_er_2d <= tx_er_1d; + + byte_valid_fe <= nib_enb_1 & tx_en_1d; + + if (tx_en && nib_cnt == 1'b0) begin + nib_cnt <= 1'b1; + end + else begin + nib_cnt <= 1'b0; + end + + if (nib_enb_0) begin + txd_fe[3:0] <= txd[3:0]; + end + if (nib_enb_1) begin + txd_fe_B[7:0] <= {txd[3:0],txd_fe[3:0]}; + end + end + end // always + + + +// ------------------------------------------------------------------------------------------------------- +// Ethernet PACKETS SINK MONITOR +// ------------------------------------------------------------------------------------------------------- +always@(posedge tx_clk) begin + case (m_st) + + IDLE: + begin + byt_cnt = 0; + crc_reg = 32'hffff_ffff; + crc_reg_latched = 32'hffff_ffff; + tx_error_latched = 1'b0; + control_pkt <= 1'b0; + pause_pkt <= 1'b0; + vlan_pkt <= 1'b0; + op_code_B0 <= 8'd0; + vlan_len_B0 <= 8'd0; + + if (gbit_en) begin + `ifdef SGMII_TSMAC + if (tx_en == 1 && byt_cnt == 0) begin + byt_cnt <= byt_cnt + 1; + pkt_cnt <= pkt_cnt + 1; + $fdisplay(out_file, "-----------------------------------------------"); + $fdisplay(out_file, "PKT %d \t BYTE \t DATA \t TX_EN \t TX_ER", pkt_cnt); + $fdisplay(out_file, "-----------------------------------------------"); + m_st = PREMB; + end + `else // CLASSIC_TSMAC OR GBE_MAC + if (tx_en == 1 && byt_cnt == 0) begin + byt_cnt <= byt_cnt + 1; + pkt_cnt <= pkt_cnt + 1; + $fdisplay(out_file, "-----------------------------------------------"); + $fdisplay(out_file, "PKT %d \t BYTE \t DATA \t TX_EN \t TX_ER", pkt_cnt); + $fdisplay(out_file, "-----------------------------------------------"); + m_st = PREMB; + end + `endif + + end + else begin + + if (tx_en_1d == 1 && byt_cnt == 0) begin + byt_cnt <= byt_cnt + 1; + pkt_cnt <= pkt_cnt + 1; + $fdisplay(out_file, "-----------------------------------------------"); + $fdisplay(out_file, "PKT %d \t BYTE \t DATA \t TX_EN \t TX_ER", pkt_cnt); + $fdisplay(out_file, "-----------------------------------------------"); + m_st = PREMB; + end + + end + end + PREMB: + begin + + if (gbit_en) begin + + `ifdef SGMII_TSMAC + if (tx_en_1d && txd_1d[7:0] != 8'hd5 && tx_clk_en == 1) begin + byt_cnt <= byt_cnt + 1; + $fdisplay(out_file, "preamble \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + m_st = PREMB; + end + else if (tx_en_1d && txd_1d[7:0] == 8'hd5 && tx_clk_en == 1) begin + byt_cnt <= 1; + $fdisplay(out_file, "SFD \t \t \t %h \t %b \t %b",txd_1d,tx_en_1d,tx_er_1d); + m_st = PKT_BODY; + end + `else // CLASSIC_TSMAC OR GBE_MAC + if (tx_en_1d && txd_1d[7:0] != 8'hd5) begin + byt_cnt <= byt_cnt + 1; + $fdisplay(out_file, "preamble \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + m_st = PREMB; + end + else if (tx_en_1d && txd_1d[7:0] == 8'hd5) begin + byt_cnt <= 1; + $fdisplay(out_file, "SFD \t \t \t %h \t %b \t %b",txd_1d,tx_en_1d,tx_er_1d); + m_st = PKT_BODY; + end + `endif + + end + else begin + + if (tx_en_2d && txd_fe_B[7:0] != 8'hd5) begin + if (byte_valid_fe) begin + byt_cnt <= byt_cnt + 1; + $fdisplay(out_file, "preamble \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + m_st = PREMB; + end + end + else if (tx_en_2d && txd_fe_B[7:0] == 8'hd5) begin + if (byte_valid_fe) begin + byt_cnt <= 1; + $fdisplay(out_file, "SFD \t \t \t %h \t %b \t %b",txd_fe_B,tx_en_2d,tx_er_2d); + m_st = PKT_BODY; + end + end + + end + + end + PKT_BODY: + begin + + if (gbit_en) begin + + `ifdef SGMII_TSMAC + if (tx_en_1d && tx_clk_en == 1) begin + `else // CLASSIC_TSMAC OR GBE_MAC + if (tx_en_1d) begin + `endif + byt_cnt <= byt_cnt + 1; + m_st = PKT_BODY; + + if (byt_cnt == 12'd1) begin + crc_reg = nextCRC32_D8(txd_1d, CRC_INIT_VALUE); + end + else if (byt_cnt == (len_B0B1 + 12'd15)) begin + crc_reg_latched = crc_rev(crc_reg); + end + else begin + crc_reg = nextCRC32_D8(txd_1d, crc_reg); + end + + if (byt_cnt == 12'd13) begin + len_B0 <= txd_1d; + end + if (byt_cnt == 12'd15 && control_pkt) begin + op_code_B0 <= txd_1d; + end + if (byt_cnt == 12'd17 && vlan_pkt) begin + vlan_len_B0 <= txd_1d; + end + if (byt_cnt == 12'd14) begin + if ({len_B0,txd_1d} < 16'd46) begin // short pkt + len_B0B1 <= 16'd46; + end + else if ({len_B0,txd_1d} == 16'h8808) begin // control pkt + control_pkt <= 1'b1; + end + else if ({len_B0,txd_1d} == 16'h8100) begin // vlan tagged pkt + vlan_pkt <= 1'b1; + end + else begin + len_B0B1 <= {len_B0,txd_1d}; + end + end + else if (byt_cnt == 12'd16 && control_pkt) begin + if ({op_code_B0,txd_1d} == 16'h0001) begin // pause pkt + pause_pkt <= 1'b1; + len_B0B1 <= 16'd46; + end + end + else if (byt_cnt == 12'd18 && vlan_pkt) begin + len_B0B1 <= {vlan_len_B0,txd_1d} + 16'd4; + end + + if (byt_cnt == (len_B0B1 + 12'd15)) begin + Rx_CRC_B0 <= txd_1d; + end + if (byt_cnt == (len_B0B1 + 12'd16)) begin + Rx_CRC_B1 <= txd_1d; + end + if (byt_cnt == (len_B0B1 + 12'd17)) begin + Rx_CRC_B2 <= txd_1d; + end + if (byt_cnt == (len_B0B1 + 12'd18)) begin + Rx_CRC <= {txd_1d,Rx_CRC_B2,Rx_CRC_B1,Rx_CRC_B0}; + end + + if (byt_cnt >= 12'd1 && byt_cnt <= 12'd6 ) begin + $fdisplay(out_file, "DA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + else if (byt_cnt >= 12'd7 && byt_cnt <= 12'd12 ) begin + $fdisplay(out_file, "SA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + else if (byt_cnt >= 12'd13 && byt_cnt <= 12'd14 ) begin + if ((byt_cnt == 12'd13 && txd_1d == 8'h81) + || (byt_cnt == 12'd14 && {len_B0,txd_1d} == 16'h8100)) begin + $fdisplay(out_file, "TAG \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + else begin + $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + end + else if ((byt_cnt >= 12'd15 && byt_cnt <= 12'd16) && vlan_pkt ) begin + $fdisplay(out_file, "TAGC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + else if ((byt_cnt >= 12'd17 && byt_cnt <= 12'd18) && vlan_pkt ) begin + $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + else if (byt_cnt >= (len_B0B1 + 12'd15) && byt_cnt <= (len_B0B1 + 12'd18) ) begin + $fdisplay(out_file, "CRC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + else begin + $fdisplay(out_file, "Data \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d); + end + + if (tx_er_1d == 1'b1) begin + tx_error_latched <= 1'b1; + end + + end + `ifdef SGMII_TSMAC + else if (tx_en_1d == 0 && tx_clk_en == 1) begin + `else // CLASSIC_TSMAC OR GBE_MAC + else if (tx_en_1d == 0) begin + `endif + byt_cnt <= 0; + $fdisplay(out_file, "-----------------------------------------------"); + $fdisplay(out_file, "RECEIVED CRC \t \t %h ",Rx_CRC); + $fdisplay(out_file, "EXPECTED CRC \t \t %h ",crc_reg_latched); + if ( Rx_CRC == crc_reg_latched && !tx_error_latched) begin + $fdisplay(out_file, "GOOD PKT"); + end + else begin + $fdisplay(out_file, "BAD PKT"); + end + if (pause_pkt) begin + $fdisplay(out_file, "THIS IS A PAUSE PACKET"); + end + else if (vlan_pkt) begin + $fdisplay(out_file, "THIS IS A VLAN TAGGED PACKET"); + end + $fdisplay(out_file, " "); + $fdisplay(out_file, " "); + $fdisplay(out_file, " "); + m_st = IDLE; + end + + end // (gbit_en) + else begin // gbit_en == 0 (10/100 mode) + + if (tx_en_2d) begin + + if (byte_valid_fe) begin + + byt_cnt <= byt_cnt + 1; + m_st = PKT_BODY; + + if (byt_cnt == 12'd1) begin + crc_reg = nextCRC32_D8(txd_fe_B, CRC_INIT_VALUE); + end + else if (byt_cnt == (len_B0B1 + 12'd15)) begin + crc_reg_latched = crc_rev(crc_reg); + end + else begin + crc_reg = nextCRC32_D8(txd_fe_B, crc_reg); + end + + + if (byt_cnt == 12'd13) begin + len_B0 <= txd_fe_B; + end + if (byt_cnt == 12'd15 && control_pkt) begin + op_code_B0 <= txd_1d; + end + if (byt_cnt == 12'd17 && vlan_pkt) begin + vlan_len_B0 <= txd_fe_B; + end + if (byt_cnt == 12'd14) begin + if ({len_B0,txd_fe_B} < 16'd46) begin // short pkt + len_B0B1 <= 16'd46; + end + else if ({len_B0,txd_fe_B} == 16'h8808) begin // control pkt + control_pkt <= 1'b1; + end + else if ({len_B0,txd_fe_B} == 16'h8100) begin // vlan tagged pkt + vlan_pkt <= 1'b1; + end + else begin + len_B0B1 <= {len_B0,txd_fe_B}; + end + end + else if (byt_cnt == 12'd16 && control_pkt) begin + if ({op_code_B0,txd_fe_B} == 16'h0001) begin // pause pkt + pause_pkt <= 1'b1; + len_B0B1 <= 16'd46; + end + end + else if (byt_cnt == 12'd18 && vlan_pkt) begin + len_B0B1 <= {vlan_len_B0,txd_fe_B} + 16'd4; + end + + + if (byt_cnt == (len_B0B1 + 12'd15)) begin + Rx_CRC_B0 <= txd_fe_B; + end + if (byt_cnt == (len_B0B1 + 12'd16)) begin + Rx_CRC_B1 <= txd_fe_B; + end + if (byt_cnt == (len_B0B1 + 12'd17)) begin + Rx_CRC_B2 <= txd_fe_B; + end + if (byt_cnt == (len_B0B1 + 12'd18)) begin + Rx_CRC <= {txd_fe_B,Rx_CRC_B2,Rx_CRC_B1,Rx_CRC_B0}; + end + + if (byt_cnt >= 12'd1 && byt_cnt <= 12'd6 ) begin + $fdisplay(out_file, "DA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + else if (byt_cnt >= 12'd7 && byt_cnt <= 12'd12 ) begin + $fdisplay(out_file, "SA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + else if (byt_cnt >= 12'd13 && byt_cnt <= 12'd14 ) begin + if ((byt_cnt == 12'd13 && txd_fe_B == 8'h81) + || (byt_cnt == 12'd14 && {len_B0,txd_fe_B} == 16'h8100)) begin + $fdisplay(out_file, "TAG \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + else begin + $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + end + else if ((byt_cnt >= 12'd15 && byt_cnt <= 12'd16) && vlan_pkt ) begin + $fdisplay(out_file, "TAGC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + else if ((byt_cnt >= 12'd17 && byt_cnt <= 12'd18) && vlan_pkt ) begin + $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + else if (byt_cnt >= (len_B0B1 + 12'd15) && byt_cnt <= (len_B0B1 + 12'd18) ) begin + $fdisplay(out_file, "CRC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + else begin + $fdisplay(out_file, "Data \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d); + end + + if (tx_er_2d == 1'b1) begin + tx_error_latched <= 1'b1; + end + + end // if (byte_valid_fe) + + end // if (tx_en_2d) + else if (tx_en_2d == 0) begin + byt_cnt <= 0; + $fdisplay(out_file, "-----------------------------------------------"); + $fdisplay(out_file, "RECEIVED CRC \t \t %h ",Rx_CRC); + $fdisplay(out_file, "EXPECTED CRC \t \t %h ",crc_reg_latched); + if ( Rx_CRC == crc_reg_latched && !tx_error_latched) begin + $fdisplay(out_file, "GOOD PKT"); + end + else begin + $fdisplay(out_file, "BAD PKT"); + end + if (pause_pkt) begin + $fdisplay(out_file, "THIS IS A PAUSE PACKET"); + end + else if (vlan_pkt) begin + $fdisplay(out_file, "THIS IS A VLAN TAGGED PACKET"); + end + $fdisplay(out_file, " "); + $fdisplay(out_file, " "); + $fdisplay(out_file, " "); + m_st = IDLE; + end // if (tx_en_2d == 0) + + end // gbit_en == 0 (10/100 mode) + + end // PKT_BODY + endcase //case (m_st) + +end //always@( posedge tx_clk) begin + + +function [31:0] nextCRC32_D8; + + input [7:0] Data; + input [31:0] CRC; + + reg [7:0] D; + reg [31:0] C; + reg [31:0] NewCRC; + + begin + D[0] = Data[7]; + D[1] = Data[6]; + D[2] = Data[5]; + D[3] = Data[4]; + D[4] = Data[3]; + D[5] = Data[2]; + D[6] = Data[1]; + D[7] = Data[0]; + C = CRC; + + NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30]; + NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ + C[31]; + NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ + C[26] ^ C[30] ^ C[31]; + NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ + C[31]; + NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ + C[27] ^ C[28] ^ C[30]; + NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ + C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ + C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ + C[27] ^ C[29] ^ C[31]; + NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ + C[27] ^ C[28]; + NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ + C[28] ^ C[29]; + NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ + C[27] ^ C[29]; + NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ + C[27] ^ C[28]; + NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ + C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30]; + NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ + C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ + C[28] ^ C[30] ^ C[31]; + NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ + C[29] ^ C[31]; + NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29]; + NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30]; + NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31]; + NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31]; + NewCRC[20] = D[4] ^ C[12] ^ C[28]; + NewCRC[21] = D[5] ^ C[13] ^ C[29]; + NewCRC[22] = D[0] ^ C[14] ^ C[24]; + NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30]; + NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31]; + NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27]; + NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ + C[28] ^ C[30]; + NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ + C[29] ^ C[31]; + NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30]; + NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31]; + NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31]; + NewCRC[31] = D[5] ^ C[23] ^ C[29]; + + nextCRC32_D8 = NewCRC; + + end + +endfunction + + +function [31:0] crc_rev; + + input [31:0] data_in; + integer crc_i; + begin + for (crc_i = 0; crc_i < 32; crc_i = crc_i+1) begin + crc_rev[crc_i] = ~data_in[31 - crc_i]; + end + end +endfunction + +endmodule + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rdwr_task.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rdwr_task.v new file mode 100644 index 0000000..f88f46a --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rdwr_task.v @@ -0,0 +1,50 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: rdwr_task.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +// MPI Write +task orc_write; +input [17:0] address; +input [7:0] data; +reg ret_status; +begin +orcastra_drv.single_write(address,data,ret_status); +end +endtask + +// MPI Read +task orc_read; +input [17:0] address; +output [7:0] data; +reg ret_status; +reg [7:0] read_data; +begin +orcastra_drv.single_read(address,read_data,ret_status); +data = read_data[7:0]; +$display(" READ at address: %h at time: %t data is : %h", address, $time, data ) ; +end +endtask + +// Register Write +task reg_wr; +input [17:0] waddr; +input [7:0] wdata; +begin + orc_write(waddr,wdata); +end +endtask + +// Register Read +task reg_rd; +input [17:0] raddr; +output [7:0] rdata; +reg [7:0] read_data; +begin + orc_read(raddr,read_data); + rdata = read_data; +end +endtask + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rx_gen_tasks.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rx_gen_tasks.v new file mode 100644 index 0000000..de3b30a --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rx_gen_tasks.v @@ -0,0 +1,853 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: rx_gen_tasks.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + + task rx_frmgen; + /*( gben, + des_addr, + frm_len, + num_premb, + num_ipg, + badcrc, //1'b0 is for good crc, 1'b1 is for bad crc + norm_vlan_paus, //2'b00 is for normal frame, 2'b01 is for VLAN tagged frame, + //2'b10 is for pause frame, + //2'b11 is for pause frame with customized des_addr + pause_timer, //valid only when norm_vlan_paus is set to 2'b10 + bad_pcode, //1'b0 is for good pause op-code, 1'b1 is for bad pause op-code + len_type, //1'b0 is for length field, 1'b1 is for type field + len_chkerr, //1'b0 is for no length check error, + //1'b1 is for generating length check error + badsfd, //1'b0 is for good sfd, 1'b1 is for bad sfd + runt_frmid, + frm_patn //4'd0 is a normal frame without any following condition + //4'd1 is for assert one clock long rx_er during frame + //4'd2 is for non-padded frame which is less than 64 bytes + //4'd14 is for non-padded frame which is less than 64 with dribble nibble + //4'd15 is for dribble nibble frame + );*/ + input gben; //bit 0 in frm_info + input [47:0] des_addr; //bit 48:1 in frm_info + input [13:0] frm_len; //bit 62:49 in frm_info + input [3:0] num_premb; //bit 66:63 in frm_info + input [4:0] num_ipg; //bit 71:67 in frm_info + input badcrc; //bit 72 in frm_info + input [1:0] norm_vlan_paus; //bit 74:73 in frm_info + input [15:0] pause_timer; //bit 90:75 in frm_info + input bad_pcode; //bit 91 in frm_info + input len_type; //bit 92 in frm_info + input len_chkerr; //bit 93 in frm_info + input badsfd; //bit 94 in frm_info + input [2:0] runt_frmid; //bit 97:95 in frm_info + input [3:0] frm_patn; //bit 101:98 in frm_info + + integer i; + reg [13:0] reg_i; + reg [13:0] data_len; + + reg [7:0] strt_rxd; + reg [31:0] crc_reg; + reg [101:0] frm_info; + + reg [7:0] rxd_reg; + //reg rxdv; + //reg rxer; + //reg [7:0] rxd; + event frm_data; + + + parameter PREAMBLE_NIB = 4'h5; + parameter SFD_NIB1 = 4'hd; + parameter GOODSFD_NIB2 = 4'h5; + parameter BADSFD_NIB2 = 4'h3; + parameter RNDM_FRM_TYPE1 = 4'h5; + parameter RNDM_FRM_TYPE2 = 4'hd; + parameter CRC_INIT_VALUE = 32'hffff_ffff; + parameter TAG_CTRL_NIB1 = 4'd1; + parameter TAG_CTRL_NIB2 = 4'd2; + parameter TAG_CTRL_NIB3 = 4'd3; + parameter TAG_CTRL_NIB4 = 4'd4; + parameter PAUSE_LENTYPE1 = 4'h8; //length/type field for pause frame is 16'h8808 + parameter PAUSE_LENTYPE2 = 4'h0; //reversed version of it is 16'h1110 + parameter PAUSE_LENTYPE3 = 4'h8; + parameter PAUSE_LENTYPE4 = 4'h8; + + parameter PAUSE_DES_NIB0 = 4'h1; //destination address for pause frame is 48'h0180_c200_0001 + parameter PAUSE_DES_NIB1 = 4'h0; + parameter PAUSE_DES_NIB2 = 4'h0; + parameter PAUSE_DES_NIB3 = 4'h0; + parameter PAUSE_DES_NIB4 = 4'h0; + parameter PAUSE_DES_NIB5 = 4'h0; + parameter PAUSE_DES_NIB6 = 4'h2; + parameter PAUSE_DES_NIB7 = 4'hc; + parameter PAUSE_DES_NIB8 = 4'h0; + parameter PAUSE_DES_NIB9 = 4'h8; + parameter PAUSE_DES_NIB10 = 4'h1; + parameter PAUSE_DES_NIB11 = 4'h0; + +// parameter PAUSE_OP_NIB1 = 4'h0; +// parameter PAUSE_OP_NIB2 = 4'h0; +// parameter PAUSE_OP_NIB3 = 4'h8; +// parameter PAUSE_OP_NIB4 = 4'h0; + + parameter PAUSE_D_NIB1 = 4'h0; + parameter PAUSE_D_NIB2 = 4'h0; + + //runt frame ID + //8'd0 do not generate runt frame + //8'd1 runt frame with preamble only + //8'd2 runt frame with preamble and sfd + //8'd3 runt frame with preamble, sfd and destination address + //8'd4 runt frame with preamble, sfd, destination address and source address +`define PAUSE_OP_NIB4 4'h0 +`define PAUSE_OP_NIB3 4'h0 +`define PAUSE_OP_NIB2 4'h0 +`define PAUSE_OP_NIB1 4'h1 +//`define PAUSE_OP_NIB4 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[15:12] +//`define PAUSE_OP_NIB3 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[11:8] +//`define PAUSE_OP_NIB2 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[7:4] +//`define PAUSE_OP_NIB1 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[3:0] + +//`include "rx_gen_tasks.inc.v" + + begin + frm_info = {frm_patn, runt_frmid, badsfd, len_chkerr, len_type, bad_pcode, pause_timer, + norm_vlan_paus, badcrc, num_ipg, num_premb, frm_len, des_addr, gben}; + + if (num_ipg == 0) begin + rxdv = 1'b0; + rxer = 1'b1; + rxd = 8'h0f; // carrier extend + end + else begin + rxdv = 1'b0; + rxer = 1'b0; + rxd = 8'b0; + end + + $display("INFO:%t New Frame is generated:", $time); + if(!norm_vlan_paus[0] && !norm_vlan_paus[1]) + $display("\t\tIt is a normal frame;"); + else if(norm_vlan_paus[0] && !norm_vlan_paus[1]) + $display("\t\tIt is a VLAN tagged frame;"); + else if(norm_vlan_paus[1]) + $display("\t\tIt is a Pause frame;"); + $display("\t\tData length is %d(DEC);", frm_len); + $display("\t\tDestination address is %h(HEX);", des_addr); + $display("\t\t%d bytes of preamble;", num_premb); + if(badsfd) + $display("\t\tBad SFD will be appended;"); + $display("\t\tIPG number is %d(DEC);", num_ipg); + if(len_chkerr) + $display("\t\tLength check err will be generated;"); + if(badcrc) + $display("\t\tBad CRC will be generated.\n"); + else + $display("\t\tGood CRC will be generated.\n"); + + if(num_ipg == 0) + $display("\t\t6 clocks of carrier extension will be generated.\n"); + + //wait for proper IPG or 6 clks of Carrier Extend + if (num_ipg == 0) begin + repeat (6) begin + @(negedge rxmac_clk); + end + end + else begin + repeat (num_ipg-1) begin + @(negedge rxmac_clk); + end + end + + crc_reg = 32'hffff_ffff; + + //Preamble generation + if(num_premb > 4'd0) begin + repeat (num_premb) begin + @(negedge rxmac_clk) + rxdv = 1'b1; + + if (num_ipg == 0) begin // carrier extend + rxer = 1'b0; + end + + rxd_reg = {PREAMBLE_NIB, PREAMBLE_NIB}; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + //$display ("%t rxd_reg is %h\n", $time, rxd_reg); + end // repeat (num_premb) + end // if (num_premb > 4'd0) + + + //SFD generation + if(runt_frmid !== 8'd1) begin + if(!badsfd) begin + @(negedge rxmac_clk) + rxdv = 1'b1; + rxd_reg = {SFD_NIB1, GOODSFD_NIB2}; + end // if (!badsfd) + else begin + @(negedge rxmac_clk) + rxdv = 1'b1; + rxd_reg = {SFD_NIB1, BADSFD_NIB2}; + end + end + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + + //destination address generation + if (norm_vlan_paus == 2'b10) begin //pause frame + @(negedge rxmac_clk) + rxd_reg = {PAUSE_DES_NIB11, PAUSE_DES_NIB10}; + crc_reg = nextCRC32_D8(rxd_reg, CRC_INIT_VALUE); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {PAUSE_DES_NIB9, PAUSE_DES_NIB8}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {PAUSE_DES_NIB7, PAUSE_DES_NIB6}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {PAUSE_DES_NIB5, PAUSE_DES_NIB4}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {PAUSE_DES_NIB3, PAUSE_DES_NIB2}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {PAUSE_DES_NIB1, PAUSE_DES_NIB0}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if (norm_vlan_paus == 2'b10) + else begin + if( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) ) begin + @(negedge rxmac_clk) + rxd_reg = des_addr[47:40]; + crc_reg = nextCRC32_D8(rxd_reg, CRC_INIT_VALUE); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = des_addr[39:32]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = des_addr[31:24]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = des_addr[23:16]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = des_addr[15:8]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = des_addr[7:0]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if ( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) ) + end // else: !if(norm_vlan_paus == 2'b10) + + //source address generation + if( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) && (runt_frmid !== 8'd3) ) begin + @(negedge rxmac_clk) + rxd_reg = {`SRC_NIB11, `SRC_NIB10}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {`SRC_NIB9, `SRC_NIB8}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {`SRC_NIB7, `SRC_NIB6}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {`SRC_NIB5, `SRC_NIB4}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {`SRC_NIB3, `SRC_NIB2}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {`SRC_NIB1, `SRC_NIB0}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if ( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) ) + + //VLAN tagged field + if(norm_vlan_paus == 2'b01) begin + @(negedge rxmac_clk) + rxd_reg = 8'b1000_0001; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = 8'b0000_0000; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {TAG_CTRL_NIB4, TAG_CTRL_NIB3}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {TAG_CTRL_NIB2, TAG_CTRL_NIB1}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if (norm_vlan_paus == 2'b01) + + //length/type field generation + if((norm_vlan_paus == 2'b10) || (norm_vlan_paus == 2'b11)) begin //pause frame + @(negedge rxmac_clk) + rxd_reg = {PAUSE_LENTYPE4, PAUSE_LENTYPE3}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = {PAUSE_LENTYPE2, PAUSE_LENTYPE1}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if (norm_vlan_paus[1] == 1'b1) + else begin + if( (runt_frmid != 8'd1) && (runt_frmid != 8'd2) && (runt_frmid != 8'd3) + && (runt_frmid != 8'd4) ) begin + if(!len_type) begin + if(!len_chkerr) begin + @(negedge rxmac_clk) + rxd_reg = {5'b00000,frm_len[10:8]}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = frm_len[7:0]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if (!len_chkerr) + else begin + @(negedge rxmac_clk) + rxd_reg = {5'b00000, frm_len[10:8]}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = frm_len[7:0] + 8'h01; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // else: !if(!len_chkerr) + end // if (!len_type) + else begin + @(negedge rxmac_clk) + rxd_reg = {RNDM_FRM_TYPE2, RNDM_FRM_TYPE1}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = 8'h00; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // else: !if(!len_type) + end // if ( (runt_frmid != 8'd1) && (runt_frmid != 8'd2) && (runt_frmid != 8'd3)... + end // else: !if(norm_vlan_paus == 2'b10) + + //MAC control op-code and parameter, frame data for pause frame + if((norm_vlan_paus == 2'b11) || (norm_vlan_paus == 2'b10)) begin //pause frame + @(negedge rxmac_clk) + if(bad_pcode) + rxd_reg = ~{`PAUSE_OP_NIB4, `PAUSE_OP_NIB3}; + else + rxd_reg = {`PAUSE_OP_NIB4, `PAUSE_OP_NIB3}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxer = (frm_patn === 4'd1); //generating rx_er during pause frame + rxd_reg = {`PAUSE_OP_NIB2, `PAUSE_OP_NIB1}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxer = 1'b0; //de-assert rx_er + rxd_reg = pause_timer[15:8]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = pause_timer[7:0]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + for (i=0; i<42; i=i+1) begin + @(negedge rxmac_clk) + rxd_reg = {PAUSE_D_NIB2, PAUSE_D_NIB1}; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end + end // if (norm_vlan_paus[1] == 1'b1) + //else if(runt_frmid == 4'd0) begin + else if(runt_frmid == 4'd0 || (runt_frmid == 4'd2 && frm_patn == 4'd3) ) begin // N.G change + + //frame data generation + strt_rxd = $random; + rxer = (frm_patn === 4'd1); + @(negedge rxmac_clk) + rxd_reg = strt_rxd[7:0]; + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + rxer = 1'b0; + //for (i=(frm_len-18-1);i>=1;i=i-1) begin + if( !norm_vlan_paus[0] && !norm_vlan_paus[1] ) begin + //if ( (frm_len < 14'd46) && ((frm_patn != 4'd2) && (frm_patn != 4'd14)) ) begin + if ( (frm_len < 14'd46) && ((frm_patn != 4'd2) && (frm_patn != 4'd14) && (frm_patn != 4'd3)) ) begin + data_len = 14'd46; + end + else begin + data_len = frm_len; + end + end + else if( norm_vlan_paus[0] && !norm_vlan_paus[1] ) begin + if( (frm_len < 14'd42) && (frm_patn != 4'd2) ) begin + data_len = 14'd42; + end + else begin + //data_len = frm_len - 4; + data_len = frm_len; + end + end + else + data_len = frm_len; + //for (i=(frm_len-1);i>=1;i=i-1) begin + for (i=(data_len-1);i>=1;i=i-1) begin + @(negedge rxmac_clk) + + rxd_reg = rxd_reg+8'd1; + + /* + if (i == 0) begin + rxd_reg = 8'h24; + end else begin + rxd_reg = 8'h55; + end + */ + + crc_reg = nextCRC32_D8(rxd_reg, crc_reg); + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // for (i=frm_len-1;i<1;i=i-1) + end // else: !if(norm_vlan_paus[1] == 1'b1) + + //FCS generation + if(runt_frmid === 3'd0) begin + if(!badcrc) begin + crc_reg = crc_rev(crc_reg); + @(negedge rxmac_clk) + rxd_reg = crc_reg[7:0]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = crc_reg[15:8]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = crc_reg[23:16]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = crc_reg[31:24]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // if (badfcs) + else begin + @(negedge rxmac_clk) + rxd_reg = crc_reg[7:0]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = crc_reg[15:8]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = crc_reg[23:16]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + @(negedge rxmac_clk) + rxd_reg = crc_reg[31:24]; + if (gben == 1) begin + rxd[7:0] = rxd_reg[7:0]; + end else begin + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxd[3:0] = rxd_reg[7:4]; + end + end // else: !if(badfcs) + end // if (runt_frmid === 8'd0) + + if (gben == 1) begin + @(negedge rxmac_clk) + rxdv = 1'b0; + end else begin + if ((frm_patn == 4'd15) || (frm_patn == 4'd14)) begin + @(negedge rxmac_clk) + rxd_reg = $random; + rxd[3:0] = rxd_reg[3:0]; + @(posedge rxmac_clk) + rxdv = 1'b0; + end else begin + @(negedge rxmac_clk) + rxdv = 1'b0; + end + end + end +endtask + +function [31:0] nextCRC32_D8; + + input [7:0] Data; + input [31:0] CRC; + + reg [7:0] D; + reg [31:0] C; + reg [31:0] NewCRC; + + begin + D[0] = Data[7]; + D[1] = Data[6]; + D[2] = Data[5]; + D[3] = Data[4]; + D[4] = Data[3]; + D[5] = Data[2]; + D[6] = Data[1]; + D[7] = Data[0]; + C = CRC; + + NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30]; + NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ + C[31]; + NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ + C[26] ^ C[30] ^ C[31]; + NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ + C[31]; + NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ + C[27] ^ C[28] ^ C[30]; + NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ + C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ + C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ + C[27] ^ C[29] ^ C[31]; + NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ + C[27] ^ C[28]; + NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ + C[28] ^ C[29]; + NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ + C[27] ^ C[29]; + NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ + C[27] ^ C[28]; + NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ + C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30]; + NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ + C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ + C[28] ^ C[30] ^ C[31]; + NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ + C[29] ^ C[31]; + NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29]; + NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30]; + NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31]; + NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31]; + NewCRC[20] = D[4] ^ C[12] ^ C[28]; + NewCRC[21] = D[5] ^ C[13] ^ C[29]; + NewCRC[22] = D[0] ^ C[14] ^ C[24]; + NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30]; + NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31]; + NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27]; + NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ + C[28] ^ C[30]; + NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ + C[29] ^ C[31]; + NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30]; + NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31]; + NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31]; + NewCRC[31] = D[5] ^ C[23] ^ C[29]; + + nextCRC32_D8 = NewCRC; + + end + +endfunction + + +function [31:0] crc_rev; + + input [31:0] data_in; + integer crc_i; + begin + for (crc_i = 0; crc_i < 32; crc_i = crc_i+1) begin + crc_rev[crc_i] = ~data_in[31 - crc_i]; + end + end +endfunction + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_ts_mac.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_ts_mac.v new file mode 100644 index 0000000..fc85e57 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_ts_mac.v @@ -0,0 +1,328 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: test_ts_mac.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +`timescale 1 ns/100 ps + +module test_ts_mac ; + +`include "env_params.v" +`include "test_tsmac_params.v" + + +reg reset_n ; +reg tx_clk_125 ; +reg rx_clk_125 ; +reg tx_clk_25 ; +reg rx_clk_25 ; +reg clk_125 ; +reg clk_12_5 ; +reg sys_clk ; +reg hclk ; + +wire gtx_clk; +wire tx_en; +wire tx_er; +wire [7:0] txd; + +wire tx_clk; +wire rx_clk; + +`ifdef MIIM_MODULE + tri mdio; +`endif + +reg [7:0] rxd; +reg rxer; +reg rxdv; +reg col; +reg crs; + +reg tdi; +reg tms; +reg tck; + +wire rxmac_clk_wire; +wire txmac_clk_wire; +wire rxmac_clk; +wire txmac_clk; + +// test points +wire [7:0] tx_fifodata; +wire tx_fifoavail; +wire tx_fifoeof; +wire tx_fifoempty; +wire tx_sndpausreq; +wire tx_fifoctrl; +wire tx_fifo_full_ri; +wire tx_macread; +wire tx_discfrm; +wire tx_staten; +wire tx_done; +wire gbit_en; // gbit_en signal + +`ifdef SGMII_TSMAC + wire txmac_clk_en; + wire rxmac_clk_en; + wire clk_en_1000; + reg clk_en_100_tx; + reg clk_en_100_rx; +`endif + +initial begin + reset_n = 1; + #50; + reset_n = 0; + #100; + reset_n = 1; +end + +initial begin + col = 0; + tx_clk_125 = 0; + rx_clk_125 = 0; + tx_clk_25 = 0; + rx_clk_25 = 0; + clk_125 = 0; + clk_12_5 = 0; + hclk = 0; + sys_clk = 0; + rxd = 8'h00; + rxdv = 0; + rxer = 0; + crs = 0; + `ifdef SGMII_TSMAC + clk_en_100_tx = 0; + clk_en_100_rx = 0; + `endif + tdi = 0; + tms = 0; + tck = 0; + + `ifdef GBE_MAC + `else +`ifdef GATE_SIM_VHD + force U1_ts_mac_top.gbit_en_c = 1; + #40; + release U1_ts_mac_top.gbit_en_c; +`else + force U1_ts_mac_top.gbit_en_wire = 1; + #40; + release U1_ts_mac_top.gbit_en_wire; +`endif + `endif + + //force U1_ts_mac_top.U1_ts_mac_core.U1_tx_mac.U1_tx_readfifo.tx_fifodata = 0; + //#300; + //release U1_ts_mac_top.U1_ts_mac_core.U1_tx_mac.U1_tx_readfifo.tx_fifodata; + + //#85000 + //#103000 + //force U1_ts_mac_top.u1_tst_logic.tx_fifo_empty_ri = 1; + //#1000; + //release U1_ts_mac_top.u1_tst_logic.tx_fifo_empty_ri; +end + +GSR GSR_INST (.GSR(reset_n)) /* synthesis syn_noprune = 1 */ ; +PUR PUR_INST (.PUR(1'b1)) /* synthesis syn_noprune = 1 */ ; +//TSALL TSALL_INST (1'b1) /* synthesis syn_noprune = 1 */ ; + +`ifdef CLASSIC_TSMAC + assign tx_clk = (gbit_en) ? tx_clk_125:tx_clk_25; + assign rx_clk = (gbit_en) ? rx_clk_125:rx_clk_25; +`else // SGMII_TSMAC OR GBE_MAC + assign tx_clk = tx_clk_125; + assign rx_clk = rx_clk_125; +`endif + +// rxmac_clk goes to rx_gen_task to drive pkts +`ifdef SGMII_TSMAC + assign rxmac_clk = (gbit_en) ? clk_125:clk_12_5; // +`else // CLASSIC_TSMAC OR GBE_MAC + assign rxmac_clk = rxmac_clk_wire; +`endif + + + ts_mac_top U1_ts_mac_top ( + + // clock and reset + + .gtx_clk (gtx_clk), + .tx_clk (tx_clk), + + `ifdef SGMII_TSMAC + .txmac_clk_en (txmac_clk_en), + .rxmac_clk_en (rxmac_clk_en), + `endif + + `ifdef MIIM_MODULE + .mdc (mdc), + `endif + + .sys_clk (sys_clk), + .hclk (hclk), + .rx_clk (rx_clk), + .rxmac_clk (rxmac_clk_wire), + .txmac_clk (txmac_clk_wire), + .reset_n (reset_n), + + // Input signals to the GMII + .rx_dv (rxdv), + .rx_er (rxer), + .rxd (rxd), + + `ifndef GBE_MAC + .col (col), + .crs (crs), + `endif + + // orcastra interface + .pc_clk (pc_clk), + .pc_datain (pc_datain), + .pc_dataout (pc_dataout), + .pc_retry (pc_retry), + .pc_error (pc_error), + .pc_ready (pc_ready), + .pc_ack (pc_ack), + .jtag_present (), + .jtag_parallel (1'b0), + + // JTAG Signals + .tdi (tdi), + .tms (tms), + .tck (tck), + .tdo (), + + // Input/Output signal from the MII Management Interface + `ifdef MIIM_MODULE + .mdio (mdio), + `endif + + // Output signals from the GMII + .tx_en (tx_en), + .tx_er (tx_er), + .txd (txd), + + // These are test points on the evaluation board + .tx_fifodata (tx_fifodata), + .tx_fifoavail (tx_fifoavail), + .tx_fifoeof (tx_fifoeof), + .tx_fifoempty (tx_fifoempty), + .tx_sndpausreq (tx_sndpausreq), + .tx_fifoctrl (tx_fifoctrl), + .tx_fifo_full_ri (tx_fifo_full_ri), + .tx_macread (tx_macread), + .tx_discfrm (tx_discfrm), + .tx_staten (tx_staten), + .tx_done (tx_done), + .gbit_en (gbit_en), + .phy_reset_n(phy_reset_n) + ); + + + + orcastra_drv orcastra_drv( + .pc_clk (pc_clk), + .pc_datain (pc_datain), + .pc_dataout (pc_dataout), + .pc_retry (pc_retry), + .pc_error (pc_error), + .pc_ready (pc_ready), + .pc_ack (pc_ack) + ); + + + pkt_mon pkt_mon( + .reset_n (reset_n), + + `ifdef SGMII_TSMAC + .gbit_en (1'b1), + .tx_clk_en (txmac_clk_en), + `else + .gbit_en (gbit_en), + `endif + + .tx_clk (tx_clk), + .tx_en (tx_en), + .tx_er (tx_er), + .txd (txd) + ); + + + //jtag_drv jtag_drv ( + // .PTDO ( tdo ), + // .PTCK ( tck ), + // .PTDI ( tdi ), + // .PTMS ( tms ) + // ); + +`define SRC_NIB11 4'hd +`define SRC_NIB10 4'he +`define SRC_NIB9 4'ha +`define SRC_NIB8 4'hd +`define SRC_NIB7 4'hd +`define SRC_NIB6 4'he +`define SRC_NIB5 4'ha +`define SRC_NIB4 4'hd +`define SRC_NIB3 4'hb +`define SRC_NIB2 4'he +`define SRC_NIB1 4'he +`define SRC_NIB0 4'hf +// ============================================================================= +`include "rx_gen_tasks.v" +`include "testcase.v" +`include "rdwr_task.v" +// ============================================================================= + + +// Clocks generation +// 125 Mhz clock +always #4 clk_125 = ~clk_125 ; +always #4 tx_clk_125 = ~tx_clk_125 ; +always #4 rx_clk_125 = ~rx_clk_125 ; +always #20 tx_clk_25 = ~tx_clk_25 ; +always #20 rx_clk_25 = ~rx_clk_25 ; +always #40 clk_12_5 = ~clk_12_5 ; +// 125 Mhz clock +always #4 sys_clk = ~sys_clk ; +// 50 Mhz clock +always #10 hclk = ~hclk; + +// Clock enable generation +`ifdef SGMII_TSMAC + + assign clk_en_1000 = 1'b1; + + always @(posedge clk_125) begin + #72 clk_en_100_tx = 1'b1; + #8 clk_en_100_tx = 1'b0; + end + + always @(posedge clk_125) begin + #72 clk_en_100_rx = 1'b1; + #8 clk_en_100_rx = 1'b0; + end + + assign txmac_clk_en = (gbit_en) ? clk_en_1000:clk_en_100_tx; + assign rxmac_clk_en = (gbit_en) ? clk_en_1000:clk_en_100_rx; + +`endif + +initial begin + $timeformat (-9 ,1 , "ns", 10); +end + +// Timeout generation to finish hung test cases. +initial begin + repeat (10000000) @(posedge clk_125 ); + $display(" INFO : Simulation Time Out, Test case Terminated") ; + $finish ; +end + +endmodule +// ============================================================================= + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_tsmac_params.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_tsmac_params.v new file mode 100644 index 0000000..7e61bcb --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_tsmac_params.v @@ -0,0 +1,118 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: test_tsmac_params.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +parameter GETH_GMII_DATA = 8; // GMII data width in 1000 Mbps mode +parameter FETH_GMII_DATA = 4; // MII data width in 10/100 Mbps mode +parameter HADDR_BUS_WIDTH = 8; // CPU I/F address bus width +parameter FIFO_DATA_WIDTH = 16; // FIFO I/F data bus width +parameter FIFO_DATA_BYTEN = 2; // Byte enable signals for FIFO data +parameter PAUSE_TIME_WIDTH = 16; // Pause frame parameter width +parameter TX_STAT_VEC_WIDTH = 31; // Transmit Status Vector Width +parameter VLAN_TAG_WIDTH = 16; // VLAN Tag Information +parameter TX_BYTEN_WIDTH = 2; // Byte enable from Tx MAC to GMII module +parameter TX_IPG_RNG = 16; // IPG register +parameter TX_DATA_WIDTH = 16; // Tx MAC data path + +/////////////////////////////////////////////////////////////////////// +// The following are the text maxros used by the task transmit +// frame generator. + +`ifdef FETH_MODE + `define DATA_SIZE 4 +`else + `define DATA_SIZE 8 +`endif + + +`define TAG_DFL 4'h0 +`define TAG_DTY 4'h1 +`define TAG_VFL 4'h2 +`define TAG_VTY 4'h3 +`define TAG_PCO 4'h4 +`define TAG_PIO 4'h5 +`define TAG_DATA 4'h6 +`define TAG_DAPA 4'h7 +`define TAG_PAD 4'h8 +`define TAG_CRC 4'h9 +`define TAG_DACR 4'ha +`define TAG_DA 4'hb +`define TAG_SA 4'hc +`define TAG_PRE 4'hd +`define TAG_PRS 4'he + +`define NEOF 1'b0 +`define EOF 1'b1 + +`define PRE_FIRST_WORD 16'b 10101010_10101010 +`define PRE_SECOND_WORD 16'b 10101010_10101010 +`define PRE_THIRD_WORD 16'b 10101010_10101010 +`define PRE_AND_SFD 16'b 10101010_10101011 + + +`define TB_CTRL_FRAME 1'b1 +`define TB_DATA_FRAME 1'b0 + +/////////////////////////////////////////////////////////////////////// +// The following are the text maxros used by the task receive +// frame generator. +// parameter PAUSE_OP_NIB1 = 4'h0; +// parameter PAUSE_OP_NIB2 = 4'h0; +// parameter PAUSE_OP_NIB3 = 4'h8; +// parameter PAUSE_OP_NIB4 = 4'h0; +//`define PAUSE_OP_NIB1 4'h0 +//`define PAUSE_OP_NIB2 4'h0 +//`define PAUSE_OP_NIB3 4'h8 +//`define PAUSE_OP_NIB4 4'h0 + +`define RX_GB_EN 1'b1 +`define RX_FE_EN 1'b0 +`define RX_BAD_CRC 1'b1 +`define RX_GOOD_CRC 1'b0 +`define RX_NORM_FRM 2'b00 +`define RX_VLAN_FRM 2'b01 +`define RX_PAUS_FRM 2'b10 +`define RX_PAUS_FRM_CUS 2'b11 +`define RX_BAD_OPCODE 1'b1 +`define RX_GOOD_OPCODE 1'b0 +`define RX_LEN_FIELD 1'b0 +`define RX_TYP_FIELD 1'b1 +`define RX_LENCHK_ER 1'b1 +`define RX_LENCHK_NOER 1'b0 +`define RX_BAD_SFD 1'b1 +`define RX_GOOD_SFD 1'b0 +`define RX_RUNT_NOT 3'd0 +`define RX_RUNT_PREM 3'd1 +`define RX_RUNT_SFD 3'd2 +`define RX_RUNT_DES 3'd3 +`define RX_RUNT_SRC 3'd4 +`define RX_FRMPTN_NOER 4'd0 +`define RX_FRMPTN_ER 4'd1 +`define RX_FRMPTN_NOPAD 4'd2 +`define RX_FRMPTN_DRNOPAD 4'd14 +`define RX_FRMPTN_DRIB 4'd15 + +`ifdef FETH_MODE + `define MIN_IPG 5'd16 + `define STD_IPG 5'd24 + `define ETH_10_100 +`endif +`ifdef GETH_MODE + `define MIN_IPG 5'd8 + `define STD_IPG 5'd12 + `define ETH_GBIT +`endif +`ifdef TSETH_MODE + `ifdef SET_GIGABIT + `define MIN_IPG 5'd8 + `define STD_IPG 5'd12 + `define ETH_GBIT + `else + `define MIN_IPG 5'd16 + `define STD_IPG 5'd24 + `define ETH_10_100 + `endif +`endif + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/ts_mac_defines.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/ts_mac_defines.v new file mode 100644 index 0000000..d5ac36a --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/ts_mac_defines.v @@ -0,0 +1,2 @@ +`define SGMII_TSMAC +`define DEVICE_ECP5UM diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.ldf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.ldf new file mode 100644 index 0000000..a364ce2 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.ldf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.lpf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.lpf new file mode 100644 index 0000000..0a818b6 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.lpf @@ -0,0 +1,29 @@ +COMMERCIAL ; + +# Period Constraints +FREQUENCY NET "hclk_c" 100.0 MHz; +FREQUENCY NET "rxmac_clk_c" 125.0 MHz PAR_ADJ 20; +FREQUENCY NET "txmac_clk_c" 125.0 MHz PAR_ADJ 20; + +BLOCK ASYNCPATHS ; +BLOCK INTERCLOCKDOMAIN PATHS; + +#Begin multicycle path from constraints +MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2X; +#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_rxer_m*" 2X; +#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_rxdv_m*" 2X; +#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_nibdrib_m*" 2X; +MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2X; +MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2X; +#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/enable_sfd_alig*" 2X; +MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X; +MULTICYCLE FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X; +MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X; +MULTICYCLE FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X; +#End multicycle path from constraints + +#Begin false path from constraints +BLOCK PATH FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac*" ; +BLOCK PATH FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_rx_mac*" ; +#End false path from constraints + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval_setting.sty b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval_setting.sty new file mode 100644 index 0000000..e35e905 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval_setting.sty @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.ldf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.ldf new file mode 100644 index 0000000..dedb25d --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.ldf @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.lpf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.lpf new file mode 100644 index 0000000..bfe1274 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.lpf @@ -0,0 +1,71 @@ +COMMERCIAL ; +# Period Constraints +FREQUENCY NET "hclk_c" 100.00 MHz PAR_ADJ 20; +FREQUENCY NET "txmac_clk_c" 125.00 MHz PAR_ADJ 20; +FREQUENCY NET "rxmac_clk_c" 125.00 MHz PAR_ADJ 20; +FREQUENCY NET "pc_clk_mux" 50.00 MHz ; +USE PRIMARY PURE NET "txmac_clk_c"; + +BLOCK ASYNCPATHS ; +BLOCK INTERCLOCKDOMAIN PATHS ; + +#Begin multicycle path from constraints +MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ; +#MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxer_m*" 2.000000 X ; +#MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxdv_m*" 2.000000 X ; +#MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_nibdrib_m*" 2.000000 X ; +MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ; +MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ; +#MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/enable_sfd_alig*" 2.000000 X ; +MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ; +MULTICYCLE FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ; +MULTICYCLE TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ; +MULTICYCLE FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ; +#End multicycle path from constraints + +#Begin false path from constraints +BLOCK PATH FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ; +BLOCK PATH FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ; +#BLOCK NET "pkt_loop_clksel_ri" ; +BLOCK NET "gbit_en_wire" ; +#End false path from constraints + +# GMII input signals +# Input setup and hold +# set these values according to your specific design requirements +#DEFINE PORT GROUP "TSU_GRP" "rx_dv" +# "rx_er" +# "rxd*"; +#INPUT_SETUP GROUP "TSU_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "rx_clk" ; +# GMII output signals +# Output Clock to Out +# set these values according to your specific design requirements +#DEFINE PORT GROUP "TCO_GRP" "tx_en" +# "rx_er" +# "txd*"; +#CLOCK_TO_OUT GROUP "TCO_GRP" MAX 5.000000 ns MIN 1.000000 ns CLKNET "txmac_clk_c" CLKOUT PORT "gtx_clk" ; + +# If I/O timing for these pins is a problem add these +#PRIORITIZE NET "rxd_c_0" 100; +#PRIORITIZE NET "rxd_c_1" 100; +#PRIORITIZE NET "rxd_c_2" 100; +#PRIORITIZE NET "rxd_c_3" 100; +#PRIORITIZE NET "rxd_c_4" 100; +#PRIORITIZE NET "rxd_c_5" 100; +#PRIORITIZE NET "rxd_c_6" 100; +#PRIORITIZE NET "rxd_c_7" 100; +#PRIORITIZE NET "rx_dv_c" 100; +#PRIORITIZE NET "rx_er_c" 100; +#PRIORITIZE NET "rx_clk_c" 80; +#PRIORITIZE NET "tx_clk_c" 40; + +#MAXDELAY NET "rxd_c_0" 1.5 ns; +#MAXDELAY NET "rxd_c_1" 1.5 ns; +#MAXDELAY NET "rxd_c_2" 1.5 ns; +#MAXDELAY NET "rxd_c_3" 1.5 ns; +#MAXDELAY NET "rxd_c_4" 1.5 ns; +#MAXDELAY NET "rxd_c_5" 1.5 ns; +#MAXDELAY NET "rxd_c_6" 1.5 ns; +#MAXDELAY NET "rxd_c_7" 1.5 ns; +#MAXDELAY NET "rx_dv_c" 1.5 ns; +#MAXDELAY NET "rx_er_c" 1.5 ns; diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval_setting.sty b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval_setting.sty new file mode 100644 index 0000000..aaaa01e --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval_setting.sty @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_se.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_se.do new file mode 100644 index 0000000..9f74d40 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_se.do @@ -0,0 +1,27 @@ +if {!0} { + vlib work +} +vmap work work +#==== compile +vlog -novopt -incr \ ++incdir+../../src/params \ ++incdir+../../../testbench/top \ ++incdir+../../../testbench/tests \ +-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/pmi +libext+.v \ +-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v \ +-y ../../src/rtl/template +libext+.v \ +-y ../../../models/ecp5um +libext+.v \ +../../src/params/ts_mac_defines.v \ +../../../../tsmac_beh.v \ +../../src/rtl/top/ts_mac_top.v \ +../../../testbench/top/pkt_mon.v \ +../../../testbench/top/orcastra_drv.v \ +../../../testbench/top/test_ts_mac.v + +vcom ../../src/rtl/top/ts_mac_core_only_top.vhd +#==== run the simulation +vsim -novopt -L work work.test_ts_mac -l tsmac_eval.log + +view structure wave +do wave.do +run -all diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_timing_synp_se.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_timing_synp_se.do new file mode 100644 index 0000000..4ac6dc5 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_timing_synp_se.do @@ -0,0 +1,29 @@ +if {!0} { + vlib work +} +vmap work work + +#==== compile +vlog -novopt -incr +define+GATE_SIM_VHD \ ++incdir+../../src/params \ ++incdir+../../../testbench/top \ ++incdir+../../../testbench/tests \ +-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/pmi +libext+.v \ +-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v \ +-y ../../../models/ecp5um +libext+.v \ +../../impl/synplify/impl/tsmac_reference_eval_impl_vo.vo \ +../../src/params/ts_mac_defines.v \ +../../../testbench/top/pkt_mon.v \ +../../../testbench/top/orcastra_drv.v \ +../../../testbench/top/test_ts_mac.v + +#==== run the simulation +vsim -novopt -L work \ + +nowarnTFMPC +nowarnPCDPC +notimingchecks \ + -multisource_delay max +transport_int_delays +transport_path_delays -v2k_int_delays \ + work.test_ts_mac \ + -l tsmac_eval.log + +view structure wave +do wave_sdf.do +run -all diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave.do new file mode 100644 index 0000000..4d17855 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave.do @@ -0,0 +1,79 @@ +add wave -noupdate -divider {CORE IO Signals} +add wave -noupdate -divider {Tx MAC Application Interface} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/txmac_clk +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifodata +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoeof +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoavail +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoempty +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_sndpaustim +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_sndpausreq +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoctrl +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_macread +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_discfrm +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_done +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_staten +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_statvec +add wave -noupdate -divider {Rx MAC Aplication Interface} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rxmac_clk +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_dbout +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_eof +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_error +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_fifo_error +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_write +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_stat_en +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_stat_vector +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_fifo_full +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/ignore_pkt +add wave -noupdate -divider {CPU Interface Signals} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hclk +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/haddr +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hdatain +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hcs_n +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hwrite_n +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hread_n +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hdataout +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hdataout_en_n +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hready_n +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/gbit_en +add wave -noupdate -divider {GMII Signals} +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/txd +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_er +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rxd +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_dv +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_er +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/col +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/crs +add wave -noupdate -divider {FPGA IO Signals} +add wave -noupdate -divider {Clocks and Resets} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/clk_125 +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/sys_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_wire +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_wire +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/hclk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/reset_n +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/phy_reset_n +add wave -noupdate -divider {GMII Signals} +add wave -noupdate -divider {Transmit} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/gtx_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_er +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/txd +add wave -noupdate -divider {Receive} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rx_clk +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/rxd +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxer +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxdv +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/col +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/crs +add wave -noupdate -divider {Register Read Write Interface} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_datain +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_dataout +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_retry +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_error +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ready +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ack diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave_sdf.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave_sdf.do new file mode 100644 index 0000000..999382b --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave_sdf.do @@ -0,0 +1,32 @@ +add wave -noupdate -divider {Clocks and Resets} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/clk_125 +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/sys_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_wire +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_wire +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/hclk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/reset_n +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/phy_reset_n +add wave -noupdate -divider {GMII Signals} +add wave -noupdate -divider {Transmit} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/gtx_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_en +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_er +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/txd +add wave -noupdate -divider {Receive} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rx_clk +add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/rxd +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxer +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxdv +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/col +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/crs +add wave -noupdate -divider {Register Read Write Interface} +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_clk +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_datain +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_dataout +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_retry +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_error +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ready +add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ack \ No newline at end of file diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/params/ts_mac_defines.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/params/ts_mac_defines.v new file mode 100644 index 0000000..d5ac36a --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/params/ts_mac_defines.v @@ -0,0 +1,2 @@ +`define SGMII_TSMAC +`define DEVICE_ECP5UM diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_2048x9.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_2048x9.v new file mode 100644 index 0000000..3400eca --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_2048x9.v @@ -0,0 +1,345 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: fifo_2048x9.v +// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +module fifo_2048x9 ( +// INPUTS + wclk, // write clock for fifo + wren, // write select for fifo + datain, // 8 data + control for fifo + reset, // clear fifo active high + rclk, // read clock for fifo + rden, // read select for fifo + aff_thrhd, // 9 bit almost full flag threshold value for fifo + afe_thrhd, // 9 bit almost full flag threshold value for fifo + wclk_en, // RAM write clock enable + rclk_en, // RAM read clock enable + +// OUTPUTS + daout, // 8 data + control for outputs + empty, // empty flag + almost_full, // almost full flag + almost_empty, // almost empty flag + full // full flag + ); +parameter pdevice_family = "ECP"; + +input wclk; // write clock for fifo +input wren; // write select for fifo +input reset; // clear fifo - active low +input rclk; // read clock for fifo +input rden; // read select for fifo +input [8:0] datain; // 8 data + control for fifo +input [8:0] aff_thrhd; // 9 bit almost full flag threshold value +input [8:0] afe_thrhd; // 9 bit almost empty flag threshold value for output fifo +input wclk_en; +input rclk_en; + +output almost_full, almost_empty, full, empty; +output [8:0] daout; // 8 data + control for fifo + +// DECLARATIONS +wire [8:0] wr_addr_a; +wire [8:0] wr_addr_b; +wire [8:0] wr_addr_c; +wire [8:0] wr_addr_d; +wire [8:0] rd_addr_a; +wire [8:0] rd_addr_b; +wire [8:0] rd_addr_c; +wire [8:0] rd_addr_d; +wire wr_en_a_clk_en; // fifo write enable +wire wr_en_b_clk_en; // fifo write enable +wire wr_en_c_clk_en; // fifo write enable +wire wr_en_d_clk_en; // fifo write enable +wire wr_en_a, rd_en_a; // fifo write enable +wire wr_en_b, rd_en_b; // fifo write enable +wire wr_en_c, rd_en_c; // fifo write enable +wire wr_en_d, rd_en_d; // fifo write enable +wire [8:0] aff_thrhd; +wire [8:0] afe_thrhd; +wire [8:0] ram_da_out_a; // ram_512x9 data output +reg [8:0] ram_da_out_a_d; // ram_512x9 data output +wire [8:0] ram_da_out_b; // ram_512x9 data output +reg [8:0] ram_da_out_b_d; // ram_512x9 data output +wire [8:0] ram_da_out_c; // ram_512x9 data output +reg [8:0] ram_da_out_c_d; // ram_512x9 data output +wire [8:0] ram_da_out_d; // ram_512x9 data output +wire rd_a; // fifo read/write +wire rd_b; // fifo read/write +wire rd_c; // fifo read/write +reg wr_b; // fifo read/write +reg wr_b_d; // fifo read/write +reg wr_c; // fifo read/write +reg wr_c_d; // fifo read/write +reg wr_d; // fifo read/write +reg wr_d_d; // fifo read/write +wire empty_a; // fifo empty +wire empty_b; // fifo empty +wire empty_c; // fifo empty +wire almost_full_b; // fifo full +wire almost_full_c; // fifo full +wire almost_full_d; // fifo full +assign rd_a = ~empty_a & ~almost_full_b; +assign rd_b = ~empty_b & ~almost_full_c; +assign rd_c = ~empty_c & ~almost_full_d; +assign wr_en_a_clk_en = wr_en_a & wclk_en; +assign wr_en_b_clk_en = wr_en_b & rclk_en; +assign wr_en_c_clk_en = wr_en_c & rclk_en; +assign wr_en_d_clk_en = wr_en_d & rclk_en; + +wire [8:0] daout; // 8 data + control for fifo +assign #1 daout[8:0] = ram_da_out_d[8:0]; +/* + * params SYNC_MODE and RAM_MODE set in level above + * and passed through. + */ +//parameter SYNC_MODE = "SYNC";// rd/wr clocks same +//parameter RAM_MODE = "REG"; //input reg +parameter SYNC_MODE = "ASYNC"; +parameter RAM_MODE = "NOREG"; +defparam ff_ctl_a.SYNC_MODE = SYNC_MODE; +defparam ff_ctl_a.RAM_MODE = RAM_MODE; +defparam ff_ctl_b.RAM_MODE = RAM_MODE; +defparam ff_ctl_c.RAM_MODE = RAM_MODE; +defparam ff_ctl_d.RAM_MODE = RAM_MODE; + + always @(posedge rclk or negedge reset) begin + if (~reset) begin + wr_b <= 1'b0; + wr_b_d <= 1'b0; + wr_c <= 1'b0; + wr_c_d <= 1'b0; + wr_d <= 1'b0; + wr_d_d <= 1'b0; + ram_da_out_a_d <= 9'b000000000; + ram_da_out_b_d <= 9'b000000000; + ram_da_out_c_d <= 9'b000000000; + end + else begin + if(rclk_en == 1) begin + wr_b <= rd_a; + wr_b_d <= wr_b; + wr_c <= rd_b; + wr_c_d <= wr_c; + wr_d <= rd_c; + wr_d_d <= wr_d; + ram_da_out_a_d <= ram_da_out_a; + ram_da_out_b_d <= ram_da_out_b; + ram_da_out_c_d <= ram_da_out_c; + end // if + end // else + end // always + +fifo_512_ctl ff_ctl_a( + // Inputs + .ckw(wclk), + .ckw_en(wclk_en), + .csw(wren), + .rst_wr(reset), + .rst_rd(reset), + .ckr(rclk), + .ckr_en(rclk_en), + .csr(rd_a), + .aff_thrhd(aff_thrhd[8:0]), + .afe_thrhd(9'b000110000), + // Outputs + .wr_adr(wr_addr_a[8:0]), + .rd_adr(rd_addr_a[8:0]), + .ff(full), + .aff(almost_full), + .afe(almost_empty_a), + .ef(empty_a), + .wr_en(wr_en_a), + .rd_en(rd_en_a), + .ram_rd_en() + ); + +pmi_ram_dp + #(.pmi_wr_addr_depth(512), + .pmi_wr_addr_width(9), + .pmi_wr_data_width(9), + .pmi_rd_addr_depth(512), + .pmi_rd_addr_width(9), + .pmi_rd_data_width(9), + .pmi_regmode("noreg"), + .pmi_gsr("enable"), + .pmi_resetmode("sync"), + .pmi_init_file("none"), + .pmi_init_file_format("binary"), + .pmi_family(pdevice_family), + .module_type("pmi_ram_dp") + ) +U1_pmi_ram_dp (.Data(datain[8:0]), + .WrAddress(wr_addr_a[8:0]), + .RdAddress(rd_addr_a[8:0]), + .WrClock(wclk), + .RdClock(rclk), + .WrClockEn(wr_en_a_clk_en), + //.RdClockEn(1'b1), + .RdClockEn(rclk_en), + .WE(1'b1), + .Reset(1'b0), + .Q(ram_da_out_a[8:0]) + ); + +fifo_512_ctl ff_ctl_b( + // Inputs + .ckw(rclk), + .ckw_en(rclk_en), + .csw(wr_b_d), + .rst_wr(reset), + .rst_rd(reset), + .ckr(rclk), + .ckr_en(rclk_en), + .csr(rd_b), + .aff_thrhd(9'b111111100), + .afe_thrhd(9'b000000000), + // Outputs + .wr_adr(wr_addr_b[8:0]), + .rd_adr(rd_addr_b[8:0]), + .ff(full_b), + .aff(almost_full_b), + .afe(almost_empty_b), + .ef(empty_b), + .wr_en(wr_en_b), + .rd_en(rd_en_b), + .ram_rd_en() + ); + +pmi_ram_dp + #(.pmi_wr_addr_depth(512), + .pmi_wr_addr_width(9), + .pmi_wr_data_width(9), + .pmi_rd_addr_depth(512), + .pmi_rd_addr_width(9), + .pmi_rd_data_width(9), + .pmi_regmode("noreg"), + .pmi_gsr("enable"), + .pmi_resetmode("sync"), + .pmi_init_file("none"), + .pmi_init_file_format("binary"), + .pmi_family(pdevice_family), + .module_type("pmi_ram_dp") + ) +U2_pmi_ram_dp (.Data(ram_da_out_a_d[8:0]), + .WrAddress(wr_addr_b[8:0]), + .RdAddress(rd_addr_b[8:0]), + .WrClock(rclk), + .RdClock(rclk), + .WrClockEn(wr_en_b_clk_en), + //.RdClockEn(1'b1), + .RdClockEn(rclk_en), + .WE(1'b1), + .Reset(1'b0), + .Q(ram_da_out_b[8:0]) + ); + + +fifo_512_ctl ff_ctl_c( + // Inputs + .ckw(rclk), + .ckw_en(rclk_en), + .csw(wr_c_d), + .rst_wr(reset), + .rst_rd(reset), + .ckr(rclk), + .ckr_en(rclk_en), + .csr(rd_c), + .aff_thrhd(9'b111111100), + .afe_thrhd(9'b000000000), + // Outputs + .wr_adr(wr_addr_c[8:0]), + .rd_adr(rd_addr_c[8:0]), + .ff(full_c), + .aff(almost_full_c), + .afe(almost_empty_c), + .ef(empty_c), + .wr_en(wr_en_c), + .rd_en(rd_en_c), + .ram_rd_en() + ); + +pmi_ram_dp + #(.pmi_wr_addr_depth(512), + .pmi_wr_addr_width(9), + .pmi_wr_data_width(9), + .pmi_rd_addr_depth(512), + .pmi_rd_addr_width(9), + .pmi_rd_data_width(9), + .pmi_regmode("noreg"), + .pmi_gsr("enable"), + .pmi_resetmode("sync"), + .pmi_init_file("none"), + .pmi_init_file_format("binary"), + .pmi_family(pdevice_family), + .module_type("pmi_ram_dp") + ) +U3_pmi_ram_dp (.Data(ram_da_out_b_d[8:0]), + .WrAddress(wr_addr_c[8:0]), + .RdAddress(rd_addr_c[8:0]), + .WrClock(rclk), + .RdClock(rclk), + .WrClockEn(wr_en_c_clk_en), + //.RdClockEn(1'b1), + .RdClockEn(rclk_en), + .WE(1'b1), + .Reset(1'b0), + .Q(ram_da_out_c[8:0]) + ); + + +fifo_512_ctl ff_ctl_d( + // Inputs + .ckw(rclk), + .ckw_en(rclk_en), + .csw(wr_d_d), + .rst_wr(reset), + .rst_rd(reset), + .ckr(rclk), + .ckr_en(rclk_en), + .csr(rden), + .aff_thrhd(9'b111111100), + .afe_thrhd(afe_thrhd[8:0]), + // Outputs + .wr_adr(wr_addr_d[8:0]), + .rd_adr(rd_addr_d[8:0]), + .ff(full_d), + .aff(almost_full_d), + .afe(almost_empty), + .ef(empty), + .wr_en(wr_en_d), + .rd_en(rd_en_d), + .ram_rd_en() + ); + +pmi_ram_dp + #(.pmi_wr_addr_depth(512), + .pmi_wr_addr_width(9), + .pmi_wr_data_width(9), + .pmi_rd_addr_depth(512), + .pmi_rd_addr_width(9), + .pmi_rd_data_width(9), + .pmi_regmode("noreg"), + .pmi_gsr("enable"), + .pmi_resetmode("sync"), + .pmi_init_file("none"), + .pmi_init_file_format("binary"), + .pmi_family(pdevice_family), + .module_type("pmi_ram_dp") + ) +U4_pmi_ram_dp (.Data(ram_da_out_c_d[8:0]), + .WrAddress(wr_addr_d[8:0]), + .RdAddress(rd_addr_d[8:0]), + .WrClock(rclk), + .RdClock(rclk), + .WrClockEn(wr_en_d_clk_en), + //.RdClockEn(1'b1), + .RdClockEn(rclk_en), + .WE(1'b1), + .Reset(1'b0), + .Q(ram_da_out_d[8:0]) + ); + +endmodule // end of fifo_2048x9 diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_512_ctl.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_512_ctl.v new file mode 100644 index 0000000..7d20d97 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_512_ctl.v @@ -0,0 +1,373 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: fifo_512_ctl.v +// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +module fifo_512_ctl ( +// INPUTS + ckw, // write clock for fifo + ckw_en, // write clock enable for fifo + csw, // write select for fifo + rst_wr, // fifo write clock domain reset active low + rst_rd, // fifo read clock domain reset active low + ckr, // read clock for fifo + ckr_en, // read clock enable for fifo + csr, // read select for fifo + aff_thrhd, // 9 bit almost full flag threshold value + afe_thrhd, // 9 bit almost empty flag threshold value + +// OUTPUTS + wr_adr, // FIFO write address to ram + rd_adr, // FIFO read address to ram + ef, // empty flag + aff, // almost full flag + afe, // almost empty flag + ff, // full flag + wr_en, // ram write enable + rd_en, // read enable + ram_rd_en // ram read enable to the ram + ); + +parameter SYNC_MODE = "SYNC"; +parameter RAM_MODE = "REG"; + +input ckw; // write clock for fifo +input ckw_en; // write clock enable for fifo +input csw; // write select for fifo +input rst_wr; // fifo write clock domain reset active low +input rst_rd; // fifo read clock domain reset active low +input ckr; // read clock for fifo +input ckr_en; // resd clock enable for fifo +input csr; // read select for fifo +input [8:0] aff_thrhd; // 9 bit almost full flag threshold value +input [8:0] afe_thrhd; // 9 bit almost empty flag threshold value + +output [8:0] wr_adr; +output [8:0] rd_adr; +output wr_en, rd_en, ram_rd_en; +output ef, ff, aff, afe; + +// DECLARATIONS +wire wr_en; +wire rd_en; +wire ram_rd_en; +wire [9:0] sync_wcnt, sync_rcnt; +wire [9:0] async_wcnt, async_rcnt; +wire [9:0] wcnt; +wire [9:0] rcnt; +wire [8:0] wr_adr, rd_adr; + +reg [9:0] wr_addr; +reg [9:0] rd_addr; +reg [9:0] rd_addr_reg; +reg ef, ff, aff, afe; +wire [8:0] rd_addr_temp; + +// select the old address during fifo empty. This application is +// used for the special ECP ram model with read clock enable input +assign rd_addr_temp[8:0] = (ef) ? rd_addr_reg[8:0] : rd_addr[8:0]; + + +// ASSIGN +assign wr_en = csw & (~ff); +assign rd_en = csr & (~ef); +assign ram_rd_en = csr | ef; +assign wr_adr[8:0] = wr_addr[8:0]; + +// select the input read address with register mode or without register mode +//assign rd_adr[8:0] = (RAM_MODE == "REG") ? rd_addr[8:0] : rd_addr_reg[8:0]; +assign rd_adr[8:0] = (RAM_MODE == "REG") ? rd_addr_temp[8:0] : rd_addr_reg[8:0]; + +// select the SYNC mode or ASYNC mode +assign wcnt[9:0] = (SYNC_MODE == "SYNC")? sync_wcnt[9:0] : async_wcnt[9:0]; +assign rcnt[9:0] = (SYNC_MODE == "SYNC")? sync_rcnt[9:0] : async_rcnt[9:0]; + +assign sync_wcnt[9:0] = {rd_addr_reg[9]^wr_addr[9], wr_addr[8:0]} - rd_addr_reg[8:0]; +assign sync_rcnt[9:0] = {wr_addr[9]^rd_addr_reg[9], wr_addr[8:0]} - rd_addr_reg[8:0]; + +// DECLARATIONS +reg [9:0] wr_addr_gc; +reg [9:0] wr2_addr; + +// wire [9:0] wr1_addr; +// assign wr1_addr[9:0] = wr_addr[9:0]+1; +// wr2_addr is the same logic function as wr1_addr +// use wr2_addr replace wr1_addr for improve timing. +//assign wr1_addr[9:0] = wr_addr[9:0]+1 after wr_addr +// increased by 1 and wr2_addr[9:0] = wr_addr[9:0]+ 2 +// at the same time wr_addr increase by 1; + + +// generate write address +always @(posedge ckw or negedge rst_wr) begin + if (~rst_wr) begin + wr_addr[9:0] <= 10'd0; + wr_addr_gc[9:0] <= 10'd0; + wr2_addr[9:0] <= 10'd0; + end // if + else begin + if(ckw_en == 1) begin + if(wr_en == 1) begin + wr_addr[9:0] <= wr_addr[9:0] + 1; + wr2_addr[9:0] <= wr_addr[9:0] + 2; + wr_addr_gc[0] <= wr2_addr[0]^wr2_addr[1]; + wr_addr_gc[1] <= wr2_addr[1]^wr2_addr[2]; + wr_addr_gc[2] <= wr2_addr[2]^wr2_addr[3]; + wr_addr_gc[3] <= wr2_addr[3]^wr2_addr[4]; + wr_addr_gc[4] <= wr2_addr[4]^wr2_addr[5]; + wr_addr_gc[5] <= wr2_addr[5]^wr2_addr[6]; + wr_addr_gc[6] <= wr2_addr[6]^wr2_addr[7]; + wr_addr_gc[7] <= wr2_addr[7]^wr2_addr[8]; + wr_addr_gc[8] <= wr2_addr[8]^wr2_addr[9]; + wr_addr_gc[9] <= wr2_addr[9]; + end // if + end // if + end // else +end // always + +// DECLARATIONS +reg [9:0] rd_addr_gc; +reg [9:0] rd2_addr; + +// wire [9:0] rd1_addr; +// assign rd1_addr[9:0] = rd_addr[9:0]+1; +// rd2_addr is the same logic function as rd1_addr +// use rd2_addr replace rd1_addr for improve timing. +// assign rd1_addr[9:0] = rd_addr[9:0]+1 after rd_addr +// increased by 1 and rd2_addr[9:0] = rd_addr[9:0]+ 2 +// at the same time rd_addr increase by 1; + +// generate read address +always @(posedge ckr or negedge rst_rd) begin + if (~rst_rd) begin + rd_addr[9:0] <= 10'd1; + rd_addr_reg[9:0] <= 10'd0; + rd_addr_gc[9:0] <= 10'd0; + rd2_addr[9:0] <= 10'd0; + end // if + else begin + if(ckr_en == 1) begin + if(rd_en == 1) begin + rd_addr[9:0] <= rd_addr[9:0] + 1; + rd_addr_reg[9:0] <= rd_addr[9:0]; + rd2_addr[9:0] <= rd_addr_reg[9:0] + 2; + rd_addr_gc[0] <= rd2_addr[0]^rd2_addr[1]; + rd_addr_gc[1] <= rd2_addr[1]^rd2_addr[2]; + rd_addr_gc[2] <= rd2_addr[2]^rd2_addr[3]; + rd_addr_gc[3] <= rd2_addr[3]^rd2_addr[4]; + rd_addr_gc[4] <= rd2_addr[4]^rd2_addr[5]; + rd_addr_gc[5] <= rd2_addr[5]^rd2_addr[6]; + rd_addr_gc[6] <= rd2_addr[6]^rd2_addr[7]; + rd_addr_gc[7] <= rd2_addr[7]^rd2_addr[8]; + rd_addr_gc[8] <= rd2_addr[8]^rd2_addr[9]; + rd_addr_gc[9] <= rd2_addr[9]; + end // if + end // if + end // else +end // always + +reg [9:0] rd_addr_gcf; + +// convert read address to write clock domain +always @(posedge ckw or negedge rst_wr) begin + if (~rst_wr) begin + rd_addr_gcf[9:0] <= 10'd0; + end // if + else begin + if(ckw_en == 1) begin + rd_addr_gcf[9:0] <= rd_addr_gc[9:0]; + end // if + end // else +end // always + +reg [9:0] wr_addr_gcf; + +// convert write address to read clock domain +always @(posedge ckr or negedge rst_rd) begin + if (~rst_rd) begin + wr_addr_gcf[9:0] <= 10'd0; + end // if + else begin + if(ckr_en == 1) begin + wr_addr_gcf[9:0] <= wr_addr_gc[9:0]; + end // if + end // else +end // always + +// convert write address gray code back to binary code + +/* +wire [9:0] wr_addr_bin_ckr; +assign wr_addr_bin_ckr[0] = wr_addr_gcf[0]^wr_addr_gcf[1]^wr_addr_gcf[2] + ^wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[1] = wr_addr_gcf[1]^wr_addr_gcf[2]^wr_addr_gcf[3] + ^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[2] = wr_addr_gcf[2]^wr_addr_gcf[3]^wr_addr_gcf[4] + ^wr_addr_gcf[5]^wr_addr_gcf[6]^wr_addr_gcf[7] + ^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[3] = wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5] + ^wr_addr_gcf[6]^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[4] = wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[5] = wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[6] = wr_addr_gcf[6]^wr_addr_gcf[7] + ^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[7] = wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[8] = wr_addr_gcf[8]^wr_addr_gcf[9]; +assign wr_addr_bin_ckr[9] = wr_addr_gcf[9]; +*/ + +// for timing reason convert wire to register +// the design will add one clock delay for the write counter +// before compare to the read counter + +reg [9:0] wr_addr_bin_ckr; +always @(posedge ckr or negedge rst_rd) begin + if (~rst_rd) begin + wr_addr_bin_ckr[9:0] <= 10'd0; + end // if + else begin + if(ckr_en == 1) begin + wr_addr_bin_ckr[0] <= wr_addr_gcf[0]^wr_addr_gcf[1]^wr_addr_gcf[2] + ^wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[1] <= wr_addr_gcf[1]^wr_addr_gcf[2]^wr_addr_gcf[3] + ^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[2] <= wr_addr_gcf[2]^wr_addr_gcf[3]^wr_addr_gcf[4] + ^wr_addr_gcf[5]^wr_addr_gcf[6]^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[3] <= wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5] + ^wr_addr_gcf[6]^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[4] <= wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[5] <= wr_addr_gcf[5]^wr_addr_gcf[6] + ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[6] <= wr_addr_gcf[6]^wr_addr_gcf[7] + ^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[7] <= wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[8] <= wr_addr_gcf[8]^wr_addr_gcf[9]; + wr_addr_bin_ckr[9] <= wr_addr_gcf[9]; + end //if + end // else +end // always + +assign async_rcnt[9:0] = {wr_addr_bin_ckr[9]^rd_addr_reg[9], wr_addr_bin_ckr[8:0]} + - rd_addr_reg[8:0]; + +/* +wire [9:0] rd_addr_bin_ckw; +assign rd_addr_bin_ckw[0] = rd_addr_gcf[0]^rd_addr_gcf[1]^rd_addr_gcf[2] + ^rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[1] = rd_addr_gcf[1]^rd_addr_gcf[2]^rd_addr_gcf[3] + ^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[2] = rd_addr_gcf[2]^rd_addr_gcf[3]^rd_addr_gcf[4] + ^rd_addr_gcf[5]^rd_addr_gcf[6]^rd_addr_gcf[7] + ^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[3] = rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5] + ^rd_addr_gcf[6]^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[4] = rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[5] = rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[6] = rd_addr_gcf[6]^rd_addr_gcf[7] + ^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[7] = rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[8] = rd_addr_gcf[8]^rd_addr_gcf[9]; +assign rd_addr_bin_ckw[9] = rd_addr_gcf[9]; +*/ + +// for timing reason convert wire to register +// the design will add one clock delay for the read counter +// before compare to the write counter + +reg [9:0] rd_addr_bin_ckw; +always @(posedge ckw or negedge rst_wr) begin + if (~rst_wr) begin + rd_addr_bin_ckw[9:0] <= 10'd0; + end // if + else begin + if(ckw_en == 1) begin + rd_addr_bin_ckw[0] <= rd_addr_gcf[0]^rd_addr_gcf[1]^rd_addr_gcf[2] + ^rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[1] <= rd_addr_gcf[1]^rd_addr_gcf[2]^rd_addr_gcf[3] + ^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[2] <= rd_addr_gcf[2]^rd_addr_gcf[3]^rd_addr_gcf[4] + ^rd_addr_gcf[5]^rd_addr_gcf[6]^rd_addr_gcf[7] + ^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[3] <= rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5] + ^rd_addr_gcf[6]^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[4] <= rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[5] <= rd_addr_gcf[5]^rd_addr_gcf[6] + ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[6] <= rd_addr_gcf[6]^rd_addr_gcf[7] + ^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[7] <= rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[8] <= rd_addr_gcf[8]^rd_addr_gcf[9]; + rd_addr_bin_ckw[9] <= rd_addr_gcf[9]; + end // if + end // else +end // always + +assign async_wcnt[9:0] = {rd_addr_bin_ckw[9]^wr_addr[9], wr_addr[8:0]} - rd_addr_bin_ckw[8:0]; + +// detect the fifo full +always @(posedge ckw or negedge rst_wr) begin + if (~rst_wr) begin + ff <= 1'b0; + aff <= 1'b0; + end // if + else begin + if(ckw_en == 1) begin + if(wcnt[9:0] >= 511 | ((wcnt[9:0] == 510) && (wr_en == 1))) begin + ff <= 1'b1; + end // if + else begin + ff <= 1'b0; + end // if + + // this extra bit is used to take care of SPYGLASS warning messages + if(wcnt[9:0] >= {1'b0,aff_thrhd[8:0]}) begin + aff <= 1'b1; + end // if + else begin + aff <= 1'b0; + end // else + end // if + end // else +end // always + +// detect the fifo empty +always @(posedge ckr or negedge rst_rd) begin + if (~rst_rd) begin + ef <= 1'b1; + afe <= 1'b1; + end // if + else begin + if(ckr_en == 1) begin + if((rcnt[9:0] == 0) || ((rcnt[9:0] == 1) && (rd_en == 1))) begin + ef <= 1'b1; + end // if + else begin + ef <= 1'b0; + end // else + + // this extra bit is used to take care of SPYGLASS warning messages + if(rcnt[9:0] <= {1'b0,afe_thrhd[8:0]}) begin + afe <= 1'b1; + end // if + else begin + afe <= 1'b0; + end // else + end // if + end // else +end // always +endmodule // end of rfifo_ctl diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/oddrx_soft.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/oddrx_soft.v new file mode 100644 index 0000000..dfce8d2 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/oddrx_soft.v @@ -0,0 +1,56 @@ + +// ==================================================================== +// File Details +// ==================================================================== +// Project : TSMAC IP Core For EC2 +// Filename : ODDRX_SFT.v +// Author : lattice Semiconductor +//===================================================================== +// +//* Notes: +//* +//* # Soft ODDR model for TSMAC +//* + +module oddrx_soft +( +// Primary I/O +DA, DB, RST, CLK_I, CLK_IX2, Q +); + +input DA; +input DB; +input CLK_I; +input CLK_IX2; +input RST; +output Q; + +reg DA_f; +reg DB_f; +reg Q; +wire MUX_OUT; + + + assign MUX_OUT = CLK_I ? DA_f:DB_f; + + always @(posedge CLK_I or posedge RST) begin + if (RST) begin + DA_f <= 1'b0; + DB_f <= 1'b0; + end + else begin + DA_f <= DA; + DB_f <= DB; + end + end + + always @(negedge CLK_IX2 or posedge RST) begin + if (RST) begin + Q <= 1'b0; + end + else begin + Q <= MUX_OUT; + end + end + +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/orcastra.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/orcastra.v new file mode 100644 index 0000000..64ed991 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/orcastra.v @@ -0,0 +1,424 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: orcastra.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + + + +//`timescale 1ns/100ps + + +module orcastra ( + //---------------------- + // inputs to orcastra_intf + //---------------------- + // + //************ + // resets + //************ + reset_n, + //************ + // clocks + //************ + hclk, + pc_clk, + //************************ + // from pc parallel port + //************************ + pc_datain, + pc_ready, + //**************** + // from host bus + //**************** + hdataout, + hready_n, + //***************** + //from reg_intf + //***************** + us_rdata, + us_ack, + //***************** + //---------------------------- + // outputs from orcastra_intf + //---------------------------- + // + //***************** + //to reg_intf + //***************** + us_wdata, + us_rdy, + us_wr, + us_addr, + us_size, + //******************** + // to MAC Host bus intf + //******************** + hdatain, + hcs_n, + hread_n, + hwrite_n, + haddr, + //******************** + // to pc parallel port + //******************** + pc_dataout, + pc_error, + pc_retry, + pc_ack ); + + +//--------- +// INPUTS +//--------- +//************ +// resets +//************ +input reset_n; +//************ +// clocks +//************ +input hclk; +input pc_clk; +//************************ +// from pc parallel port +//************************ +input pc_datain; +input pc_ready; +//*************** +// from host bus +//*************** +input [7:0] hdataout; +input hready_n; +//***************** +//from reg_intf +//***************** +input [7:0] us_rdata; +input us_ack; +//***************** +//--------- +// OUTPUTS +//--------- +//***************** +//to reg_intf +//***************** +output [7:0] us_wdata; +output us_rdy; +output us_wr; +output [17:0] us_addr; +output [1:0] us_size; +//******************** +// to MAC Host bus intf +//******************** +output [7:0] hdatain; +output hcs_n; +output hread_n; +output hwrite_n; +output [7:0] haddr; +//******************** +// to pc parallel port +//******************** +output pc_dataout; +output pc_error; +output pc_retry; +output pc_ack; + + +//------------------- +// SIGNAL assignments +//------------------- +wire [7:0] us_wdata; +reg us_rdy; +reg us_wr; +wire [17:0] us_addr; +wire [1:0] us_size; +wire [7:0] hdatain; +reg hcs_n; +reg hread_n; +reg hwrite_n; +wire [7:0] haddr; +reg pc_dataout; +reg pc_error; +wire pc_retry; +reg pc_ack; + +wire orc_ack; +reg [7:0] sreg_do; +reg [25:0] sreg_di; +reg [25:0] reg_di; +reg [2:0] rdwr_st; +reg pc_ready_1d; +reg pc_ready_2d; +reg pc_ready_3d; +reg orc_ack_1d; +reg orc_ack_2d; +reg orc_ack_3d; +reg pc_rdy_pulse; +wire [7:0] mux_dout; +wire tstl_regs; + +reg gate_clk_ctl1; +reg gate_clk_ctl2; +wire gate_clk; +reg [8:0] timeout_cnt; +wire timeout; + +// PARAMETERS + +parameter [1:0] + SIZE = 2'b00; + +parameter [2:0] + IDLE = 3'b000, // IDLE State + READ = 3'b001, // READ State + WRITE = 3'b010, // WRITE State + WAIT1 = 3'b011, // WAIT1 State + WAIT2 = 3'b100; // WAIT2 State + + assign gate_clk_ctl = gate_clk_ctl1 & gate_clk_ctl2; + assign gate_clk = gate_clk_ctl ? hclk:pc_clk; + assign mux_dout = tstl_regs ? us_rdata:hdataout; + + assign tstl_regs = (reg_di[17:6] == 12'h200) ? 1'b1:1'b0; + + assign us_size[1:0] = SIZE; + assign pc_retry = 1'b0; + assign timeout = (timeout_cnt[8:0] == 9'h000) ? 1'b1:1'b0; + assign orc_ack = (!hready_n | us_ack); + + + //------------------------------------------------------------------- + // Pipeline pc_ready and orc_ack and + // Edge detector for pc_ready signal - generates a one clk wide + // "pc_rdy_pulse" on a L->H transition of pc_ready + //------------------------------------------------------------------- + always @(posedge hclk or negedge reset_n) begin + if (~reset_n) begin + pc_ready_1d <= #1 1'b0; + pc_ready_2d <= #1 1'b0; + pc_ready_3d <= #1 1'b0; + orc_ack_1d <= #1 1'b0; + orc_ack_2d <= #1 1'b0; + orc_ack_3d <= #1 1'b0; + pc_rdy_pulse <= #1 1'b0; + end + else begin + pc_ready_1d <= #1 pc_ready; + pc_ready_2d <= #1 pc_ready_1d; + pc_ready_3d <= #1 pc_ready_2d; + orc_ack_1d <= #1 orc_ack; + orc_ack_2d <= #1 orc_ack_1d; + orc_ack_3d <= #1 orc_ack_2d; + pc_rdy_pulse <= (~pc_ready_3d & pc_ready_2d); + end // else + end // always + + + // --------------------------------------------------------------------------- + // gclk gate control2 on falling edge to prevent runt + // --------------------------------------------------------------------------- + always @(negedge hclk or negedge reset_n) begin + if (~reset_n) begin + gate_clk_ctl2 <= #1 1'b1; + end + else begin + gate_clk_ctl2 <= #1 !orc_ack_1d; + end + end // always + + // --------------------------------------------------------------------------- + // shift reg - sreg_di - shift data and address in + // --------------------------------------------------------------------------- + always @(negedge pc_clk or negedge reset_n) begin + if (~reset_n) begin + sreg_di[25:0] <= #1 26'h0000000; + end + else begin + sreg_di <= sreg_di << 1; // Shift Left + sreg_di[0] <= pc_datain; + end + end // always + + //------------------------------------------------------------------- + // Latch data and address into internal reg clocked by hclk + //------------------------------------------------------------------- + always @(posedge hclk or negedge reset_n) begin + if (~reset_n) begin + reg_di[25:0] <= #1 26'h0000000; + end + else begin + if (pc_rdy_pulse) begin + reg_di[25:0] <= #1 sreg_di[25:0]; + end + end // else + end // always + + assign us_wdata[7] = reg_di[18]; + assign us_wdata[6] = reg_di[19]; + assign us_wdata[5] = reg_di[20]; + assign us_wdata[4] = reg_di[21]; + assign us_wdata[3] = reg_di[22]; + assign us_wdata[2] = reg_di[23]; + assign us_wdata[1] = reg_di[24]; + assign us_wdata[0] = reg_di[25]; + + assign hdatain[7] = reg_di[18]; + assign hdatain[6] = reg_di[19]; + assign hdatain[5] = reg_di[20]; + assign hdatain[4] = reg_di[21]; + assign hdatain[3] = reg_di[22]; + assign hdatain[2] = reg_di[23]; + assign hdatain[1] = reg_di[24]; + assign hdatain[0] = reg_di[25]; + + assign haddr[7:0] = reg_di[7:0]; + assign us_addr[17:0] = reg_di[17:0]; + + + // --------------------------------------------------------------------------- + // Latch output read data to 8 bit shift reg - sreg_do + // --------------------------------------------------------------------------- + always @(negedge gate_clk or negedge reset_n) begin + if (~reset_n) begin + sreg_do[7:0] <= #1 8'h00; + pc_dataout <= #1 1'b0; + end + else begin + if (orc_ack_1d) begin + sreg_do[7:0] <= mux_dout[7:0]; + end + else begin + sreg_do <= sreg_do >> 1; // shift Left + sreg_do[7] <= 1; + end + pc_dataout <= sreg_do[0]; + end + end // always + + + // --------------------------------------------------------------------------- + + + // --------------------------------------------------------------------------- + // Read/Write FSM + // --------------------------------------------------------------------------- + + always @(posedge hclk or negedge reset_n) begin + if (~reset_n) begin + rdwr_st <= #1 IDLE; + gate_clk_ctl1 <= #1 1'b0; + us_rdy <= #1 1'b0; + us_wr <= #1 1'b0; + hcs_n <= #1 1'b1; + hread_n <= #1 1'b1; + hwrite_n <= #1 1'b1; + pc_ack <= #1 1'b0; + pc_error <= #1 1'b0; + timeout_cnt <= #1 9'h1ff; + end + else begin + // default values + us_rdy <= #1 1'b0; + + case (rdwr_st) + + IDLE: + begin + us_wr <= #1 1'b0; + hcs_n <= #1 1'b1; + hread_n <= #1 1'b1; + hwrite_n <= #1 1'b1; + gate_clk_ctl1 <= #1 1'b0; + timeout_cnt <= #1 9'h1ff; + pc_ack <= #1 1'b0; + pc_error <= #1 1'b0; + + if (pc_rdy_pulse) begin + if (pc_datain == 1'b0) begin // Write + rdwr_st <= #1 WRITE; + end + else begin // read + rdwr_st <= #1 READ; + gate_clk_ctl1 <= #1 1'b1; + end + end + end + READ: + begin + if (tstl_regs) begin + us_rdy <= #1 1'b1; + us_wr <= #1 1'b0; + end + else begin + hcs_n <= #1 1'b0; + hread_n <= #1 1'b0; + hwrite_n <= #1 1'b1; + end + + rdwr_st <= #1 WAIT1; + end + WRITE: + begin + if (tstl_regs) begin + us_rdy <= #1 1'b1; + us_wr <= #1 1'b1; + end + else begin + hcs_n <= #1 1'b0; + hread_n <= #1 1'b1; + hwrite_n <= #1 1'b0; + end + + rdwr_st <= #1 WAIT1; + end + WAIT1: + begin + // timeout_cnt <= #1 timeout_cnt - 1; + // if (timeout) begin + // pc_ack <= #1 1'b1; + // pc_error <= #1 1'b1; + // rdwr_st <= #1 WAIT2; + // end + // else begin + if (orc_ack) begin + us_wr <= #1 1'b0; + hcs_n <= #1 1'b1; + hread_n <= #1 1'b1; + hwrite_n <= #1 1'b1; + pc_ack <= #1 1'b1; + rdwr_st <= #1 WAIT2; + end + // end + end + WAIT2: + begin + gate_clk_ctl1 <= #1 1'b0; + if (pc_ready_3d == 1'b0) begin + pc_ack <= #1 1'b0; + pc_error <= #1 1'b0; + rdwr_st <= #1 IDLE; + end + end + default: + begin + rdwr_st <= #1 IDLE; + gate_clk_ctl1 <= #1 1'b0; + us_rdy <= #1 1'b0; + us_wr <= #1 1'b0; + hcs_n <= #1 1'b1; + hread_n <= #1 1'b1; + hwrite_n <= #1 1'b1; + pc_ack <= #1 1'b0; + pc_error <= #1 1'b0; + timeout_cnt <= #1 9'h1ff; + end + endcase + end + end // always + + +endmodule // orcastra + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/reg_intf.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/reg_intf.v new file mode 100644 index 0000000..bbcbf9d --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/reg_intf.v @@ -0,0 +1,1790 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: reg_intf.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + + +//`timescale 1ns/100ps + + +module reg_intf ( + //---------------------- + // inputs to Reg_intf + //---------------------- + // + //************ + // resets + //************ + reset_n, + //************ + // clocks + //************ + hclk, + rxc_clk, + txc_clk, + //******************* + // USI related inputs + // (User Slave Interface) + //******************* + us_wdata, + us_rdy, + us_wr, + us_addr, + us_size, + //**************** + // from tst_logic + //**************** + rx_error_ri, + rx_fifo_error_ri, + tx_disfrm_ri, + tx_fifo_full_ri, + //***************** + //from MAC Stat intf + //***************** + rx_stat_vec, + rx_stat_en, + tx_stat_vec, + tx_stat_en, + //***************** + //---------------------------- + // outputs from Reg_intf + //---------------------------- + // + //***************** + //to tst_logic + //***************** + pkt_add_swap_ri, + pkt_loop_enb_ri, + pkt_loop_clksel_ri, + phy_reset_n_ri, + tx_sndpaustim_ri, + tx_sndpausreq_ri, + tx_fifoctrl_ri, + rx_fifo_full_ri, + tx_fifo_empty_ri, + ignore_next_pkt_ri, + aff_thrhd, + afe_thrhd, + //******************** + // usi related outputs + //******************** + us_err, + us_irq, + us_ack, + us_rdata ); + + + +//--------- +// INPUTS +//--------- +//************ +// resets +//************ +input reset_n; // system reset +//************ +// clocks +//************ +input hclk; +input rxc_clk; +input txc_clk; +//**************** +input [1:0] us_size; // Transfer size 00-byte +input us_rdy; // Active high ready respose from USI +input [7:0] us_wdata; // register's input data from usi +input us_wr; // write/read enable wr=high, read=low +input [17:0] us_addr; // 18 bit address +//*********** +// tst_logic +//*********** +input rx_error_ri; +input rx_fifo_error_ri; +input tx_disfrm_ri; +input tx_fifo_full_ri; +//***************** +//from MAC Stat intf +//***************** +input [31:0] rx_stat_vec; +input rx_stat_en; +input [30:0] tx_stat_vec; +input tx_stat_en; +//***************** +//---------------------------- +// outputs from Reg_intf +//---------------------------- +// +//***************** +//to tst_logic +//***************** +output pkt_add_swap_ri; +output pkt_loop_enb_ri; +output pkt_loop_clksel_ri; +output phy_reset_n_ri; +output [15:0] tx_sndpaustim_ri; +output tx_sndpausreq_ri; +output tx_fifoctrl_ri; +output rx_fifo_full_ri; +output tx_fifo_empty_ri; +output ignore_next_pkt_ri; +output [8:0] aff_thrhd; +output [8:0] afe_thrhd; +//************* +//usi related +//************* +output us_err; +output us_irq; // active high interrupt out to mpu +output us_ack; // active high acknowledge for reads and writes +output [7:0] us_rdata; // register's output data to usi + + + +//------------------- +// SIGNAL assignments +//------------------- +wire pkt_add_swap_ri; +wire pkt_loop_enb_ri; +wire pkt_loop_clksel_ri; +wire phy_reset_n_ri; +wire [15:0] tx_sndpaustim_ri; +wire tx_sndpausreq_ri; +wire tx_fifoctrl_ri; +wire rx_fifo_full_ri; +wire tx_fifo_empty_ri; +wire ignore_next_pkt_ri; +wire [8:0] aff_thrhd; +wire [8:0] afe_thrhd; +wire unused_ctl_0; // NOT USED +wire unused_ctl_1; // NOT USED +wire unused_ctl_2; // NOT USED +wire unused_ctl_3; // NOT USED +wire unused_ctl_4; // NOT USED + +reg us_rdy_f0; // Active high ready respose from USI pipelined once +reg us_rdy_f1; // Active high ready respose from USI pipelined twice +reg us_rdy_wide; // Active high ready respose from USI widened to 2 clks +reg [7:0] us_wdata_f; // pipelined register's input data from usi +reg [49:0] we; // register write enables-used for writes (only 9 used) +reg [49:0] re; // register read enables-used for reads +reg [7:0] us_rdata; // register's output data to usi +reg us_ack; // active high acknowledge for reads and writes +reg [2:0] cntl_fsm_st; // control reg FSM states +reg start_burst; // Start Burst signal (pulse) - NOT USED +reg ram_rst; // reset the RAM signal (pulse) - NOT USED +reg range_err; // Address Out of Range Error + +wire size_err; // Data Size Error +wire us_err; // USI Error +wire [7:0] verid_reg; // VERID reg always set to 8'ha0 +wire [1:0]ram_rst_mode; // reset RAM mode signal 00 = null, 01 = dc/idle rdy low, +wire us_irq; // active high interrupt out to mpu + + +// ----------------------------- +// General Registers +// ----------------------------- +reg [7:0] tstcntl_reg; // Test Control Register +reg [7:0] tstcntl2_reg; // Test Control Register 2 - NOT USED +reg [7:0] maccntl_reg; // MAC control Register +reg [7:0] paustmrl_reg; // Pause timer register low byte +reg [7:0] paustmrh_reg; // Pause timer register high byte +reg [7:0] fifoaftl_reg; // FIFO Almost full Threshold register low byte +reg [7:0] fifoafth_reg; // FIFO Almost full Threshold register high byte +reg [7:0] fifoaetl_reg; // FIFO Almost Empty Threshold register low byte +reg [7:0] fifoaeth_reg; // FIFO Almost Empty Threshold register high byte +reg [7:0] rxstatus_reg; // RX Status Register +reg [7:0] txstatus_reg; // TX Status Register + +// ----------------------------- +// Statistics Counters Registers +// ----------------------------- +reg [15:0] rxpicnt_reg; // Rx packets ignored counter +reg [15:0] rxlcecnt_reg; // Rx length check error counter +reg [15:0] rxlfcnt_reg; // Rx long frames counter +reg [15:0] rxsfcnt_reg; // Rx short frames counter +reg [15:0] rxipgcnt_reg; // Rx ipg violations counter +reg [15:0] rxcrccnt_reg; // Rx crc errors counter +reg [15:0] rxokcnt_reg; // Rx ok packets counter +reg [15:0] rxcfcnt_reg; // Rx control frames counter +reg [15:0] rxpfcnt_reg; // Rx pause frames counter +reg [15:0] rxmfcnt_reg; // Rx Multicast frames counter +reg [15:0] rxbfcnt_reg; // Rx broadcast frames counter +reg [15:0] rxvfcnt_reg; // Rx vlan tagged frames counter + +reg [15:0] txufcnt_reg; // Tx unicast frames counter +reg [15:0] txpfcnt_reg; // Tx pause frames counter +reg [15:0] txmfcnt_reg; // Tx Multicast frames counter +reg [15:0] txbfcnt_reg; // Tx broadcast frames counter +reg [15:0] txvfcnt_reg; // Tx vlan tagged frames counter +reg [15:0] txbfccnt_reg; // Tx bad FCS frames counter +reg [15:0] txjfcnt_reg; // Tx jumbo frames counter + + +reg re10_dly; // re[10] pipelined once +reg re11_dly; // re[11] pipelined once +reg re12_dly; // re[12] pipelined once +reg re14_dly; // re[14] pipelined once +reg re16_dly; // re[16] pipelined once +reg re18_dly; // re[18] pipelined once +reg re20_dly; // re[20] pipelined once +reg re22_dly; // re[22] pipelined once +reg re24_dly; // re[24] pipelined once +reg re26_dly; // re[26] pipelined once +reg re28_dly; // re[28] pipelined once +reg re30_dly; // re[30] pipelined once +reg re32_dly; // re[32] pipelined once +reg re34_dly; // re[34] pipelined once +reg re36_dly; // re[36] pipelined once +reg re38_dly; // re[38] pipelined once +reg re40_dly; // re[40] pipelined once +reg re42_dly; // re[42] pipelined once +reg re44_dly; // re[44] pipelined once +reg re46_dly; // re[46] pipelined once +reg re48_dly; // re[48] pipelined once +reg clear_delay; // Clear the clear on read bit +reg [6:0] clear_count; // Counter used to generate clear_delay bit + + +//-------------------------- +// dbus0 related +//-------------------------- +wire [7:0] reg0_tdrive0_data; +wire [7:0] reg1_tdrive0_data; +wire [7:0] reg2_tdrive0_data; +wire [7:0] reg3_tdrive0_data; +wire [7:0] reg4_tdrive0_data; +wire [7:0] reg5_tdrive0_data; +wire [7:0] reg6_tdrive0_data; +wire [7:0] reg7_tdrive0_data; +wire [7:0] reg8_tdrive0_data; +wire [7:0] reg9_tdrive0_data; +wire [7:0] reg10_tdrive0_data; +wire [7:0] reg11_tdrive0_data; +wire [7:0] buskeep0_tdrive0_data; +wire reg0_tdrive0_en; +wire reg1_tdrive0_en; +wire reg2_tdrive0_en; +wire reg3_tdrive0_en; +wire reg4_tdrive0_en; +wire reg5_tdrive0_en; +wire reg6_tdrive0_en; +wire reg7_tdrive0_en; +wire reg8_tdrive0_en; +wire reg9_tdrive0_en; +wire reg10_tdrive0_en; +wire reg11_tdrive0_en; +wire buskeep0_tdrive0_en; +//-------------------------- + +//-------------------------- +// dbus1 related +//-------------------------- +wire [7:0] reg12_tdrive1_data; +wire [7:0] reg13_tdrive1_data; +wire [7:0] reg14_tdrive1_data; +wire [7:0] reg15_tdrive1_data; +wire [7:0] reg16_tdrive1_data; +wire [7:0] reg17_tdrive1_data; +wire [7:0] reg18_tdrive1_data; +wire [7:0] reg19_tdrive1_data; +wire [7:0] reg20_tdrive1_data; +wire [7:0] reg21_tdrive1_data; +wire [7:0] reg22_tdrive1_data; +wire [7:0] reg23_tdrive1_data; +wire [7:0] buskeep1_tdrive1_data; +wire reg12_tdrive1_en; +wire reg13_tdrive1_en; +wire reg14_tdrive1_en; +wire reg15_tdrive1_en; +wire reg16_tdrive1_en; +wire reg17_tdrive1_en; +wire reg18_tdrive1_en; +wire reg19_tdrive1_en; +wire reg20_tdrive1_en; +wire reg21_tdrive1_en; +wire reg22_tdrive1_en; +wire reg23_tdrive1_en; +wire buskeep1_tdrive1_en; +//-------------------------- + +//-------------------------- +// dbus2 related +//-------------------------- +wire [7:0] reg24_tdrive2_data; +wire [7:0] reg25_tdrive2_data; +wire [7:0] reg26_tdrive2_data; +wire [7:0] reg27_tdrive2_data; +wire [7:0] reg28_tdrive2_data; +wire [7:0] reg29_tdrive2_data; +wire [7:0] reg30_tdrive2_data; +wire [7:0] reg31_tdrive2_data; +wire [7:0] reg32_tdrive2_data; +wire [7:0] reg33_tdrive2_data; +wire [7:0] reg34_tdrive2_data; +wire [7:0] reg35_tdrive2_data; +wire [7:0] buskeep2_tdrive2_data; +wire reg24_tdrive2_en; +wire reg25_tdrive2_en; +wire reg26_tdrive2_en; +wire reg27_tdrive2_en; +wire reg28_tdrive2_en; +wire reg29_tdrive2_en; +wire reg30_tdrive2_en; +wire reg31_tdrive2_en; +wire reg32_tdrive2_en; +wire reg33_tdrive2_en; +wire reg34_tdrive2_en; +wire reg35_tdrive2_en; +wire buskeep2_tdrive2_en; +//-------------------------- + +//-------------------------- +// dbus3 related +//-------------------------- +wire [7:0] reg36_tdrive3_data; +wire [7:0] reg37_tdrive3_data; +wire [7:0] reg38_tdrive3_data; +wire [7:0] reg39_tdrive3_data; +wire [7:0] reg40_tdrive3_data; +wire [7:0] reg41_tdrive3_data; +wire [7:0] reg42_tdrive3_data; +wire [7:0] reg43_tdrive3_data; +wire [7:0] reg44_tdrive3_data; +wire [7:0] reg45_tdrive3_data; +wire [7:0] reg46_tdrive3_data; +wire [7:0] reg47_tdrive3_data; +wire [7:0] reg48_tdrive3_data; +wire [7:0] reg49_tdrive3_data; +wire [7:0] buskeep3_tdrive3_data; +wire reg36_tdrive3_en; +wire reg37_tdrive3_en; +wire reg38_tdrive3_en; +wire reg39_tdrive3_en; +wire reg40_tdrive3_en; +wire reg41_tdrive3_en; +wire reg42_tdrive3_en; +wire reg43_tdrive3_en; +wire reg44_tdrive3_en; +wire reg45_tdrive3_en; +wire reg46_tdrive3_en; +wire reg47_tdrive3_en; +wire reg48_tdrive3_en; +wire reg49_tdrive3_en; +wire buskeep3_tdrive3_en; + + + +wire [7:0] keep0; // bus keeper values for tdrive0 +wire [7:0] keep1; // bus keeper values for tdrive1 +wire [7:0] keep2; // bus keeper values for tdrive2 +wire [7:0] keep3; // bus keeper values for tdrive3 + +wire bkenb0; // bus keeper enable for tdrive0 +wire bkenb1; // bus keeper enable for tdrive1 +wire bkenb2; // bus keeper enable for tdrive2 +wire bkenb3; // bus keeper enable for tdrive3 + +wire [3:0] grpsel; // group select sigs used by add decoder sel between dbus0-dbus3 + +reg [7:0] dbus; // register's output data to usi +tri [7:0] dbus0; // data bus 0 +tri [7:0] dbus1; // data bus 1 +tri [7:0] dbus2; // data bus 2 +tri [7:0] dbus3; // data bus 3 + +wire us_clk; // tied to hclk + +// PARAMETERS + +parameter [1:0] + SIZE = 2'b00; // Size for byte transfers + +parameter [7:0] + VERID = 8'ha2; + +parameter [1:0] + IDLE = 2'b00, // IDLE State + DELAY = 2'b01, // DELAY State + PULSE1 = 2'b10, // PULSE1 State + PULSE2 = 2'b11; // PULSE2 State + + + assign us_clk = hclk; + assign us_irq = 1'b0; + + assign size_err = (us_size[1:0] != SIZE) ? 1'b1:1'b0; + assign us_err = (size_err || range_err) ? 1'b1:1'b0; + + + // ------------------------------------------- + // generate grpsel signals for address decoder + // ------------------------------------------- + + assign grpsel[0] = (re[0] | re[1] | re[2] | re[3] | re[4] | re[5] | re[6] | + re[7] | re[8] | re[9] | re[10] | re[11]); + + assign grpsel[1] = (re[12] | re[13] | re[14] | re[15] | re[16] | re[17] | + re[18] | re[19] | re[20] | re[21] | re[22] | re[23]); + + assign grpsel[2] = (re[24] | re[25] | re[26] | re[27] | re[28] | re[29] | + re[30] | re[31] | re[32] | re[33] | re[34] | re[35]); + + assign grpsel[3] = (re[36] | re[37] | re[38] | re[39] | re[40] | re[41] | re[42] | + re[43] | re[44] | re[45] | re[46] | re[47] | re[48] | re[49]); + + // set bus keeper signals to high state + + assign keep0 = 8'b11111111; + assign keep1 = 8'b11111111; + assign keep2 = 8'b11111111; + assign keep3 = 8'b11111111; + + // decode bus keeper enable signals + + assign bkenb0 = !grpsel[0]; + assign bkenb1 = !grpsel[1]; + assign bkenb2 = !grpsel[2]; + assign bkenb3 = !grpsel[3]; + + + // -------------------------- + // mux selected Register bank + // -------------------------- + + always @(grpsel[3:0] or dbus0 or dbus1 or dbus2 or dbus3) + begin + if (grpsel[0]) begin + dbus <= dbus0; + end + else if (grpsel[1]) begin + dbus <= dbus1; + end + else if (grpsel[2]) begin + dbus <= dbus2; + end + else if (grpsel[3]) begin + dbus <= dbus3; + end + else + dbus <= 8'hff; + end + // -------------------------- + + + + // Latch register output to us_rdata usi port + // --------------------------------------------------------------------------- + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + us_rdata[7:0] <= #1 8'hff; + end + else begin + if (us_rdy_wide && !us_wr) begin + us_rdata[7:0] <= dbus[7:0]; + end + end + end // always + + // --------------------------------------------------------------------------- + + + + // ======================================== + // Register outs - wire assignments + // ======================================== + + // --------------------------------------- + // VERID + // --------------------------------------- + assign verid_reg = VERID; + + // --------------------------------------- + // TSTCNTL + // --------------------------------------- + assign pkt_add_swap_ri = tstcntl_reg[0]; + assign pkt_loop_enb_ri = tstcntl_reg[1]; + assign phy_reset_n_ri = tstcntl_reg[2]; + assign pkt_loop_clksel_ri = tstcntl_reg[3]; + + + // --------------------------------------- + // SMCNTL + // --------------------------------------- + assign unused_ctl_0 = tstcntl2_reg[0]; + assign unused_ctl_1 = tstcntl2_reg[1]; + assign unused_ctl_2 = tstcntl2_reg[2]; + assign unused_ctl_3 = tstcntl2_reg[3]; + assign unused_ctl_4 = tstcntl2_reg[4]; + + // --------------------------------------- + // MACCNTL + // --------------------------------------- + assign tx_sndpausreq_ri = maccntl_reg[0]; + assign tx_fifoctrl_ri = maccntl_reg[1]; + assign rx_fifo_full_ri = maccntl_reg[2]; + assign tx_fifo_empty_ri = maccntl_reg[3]; + assign ignore_next_pkt_ri = maccntl_reg[4]; + + // --------------------------------------- + // PAUSTMRL + // --------------------------------------- + assign tx_sndpaustim_ri[0] = paustmrl_reg[0]; + assign tx_sndpaustim_ri[1] = paustmrl_reg[1]; + assign tx_sndpaustim_ri[2] = paustmrl_reg[2]; + assign tx_sndpaustim_ri[3] = paustmrl_reg[3]; + assign tx_sndpaustim_ri[4] = paustmrl_reg[4]; + assign tx_sndpaustim_ri[5] = paustmrl_reg[5]; + assign tx_sndpaustim_ri[6] = paustmrl_reg[6]; + assign tx_sndpaustim_ri[7] = paustmrl_reg[7]; + + // --------------------------------------- + // PAUSTMRH + // --------------------------------------- + assign tx_sndpaustim_ri[8] = paustmrh_reg[0]; + assign tx_sndpaustim_ri[9] = paustmrh_reg[1]; + assign tx_sndpaustim_ri[10] = paustmrh_reg[2]; + assign tx_sndpaustim_ri[11] = paustmrh_reg[3]; + assign tx_sndpaustim_ri[12] = paustmrh_reg[4]; + assign tx_sndpaustim_ri[13] = paustmrh_reg[5]; + assign tx_sndpaustim_ri[14] = paustmrh_reg[6]; + assign tx_sndpaustim_ri[15] = paustmrh_reg[7]; + + // --------------------------------------- + // FIFOAFTH and FIFOAETH + // --------------------------------------- + assign aff_thrhd[7:0] = fifoaftl_reg[7:0]; + assign aff_thrhd[8] = fifoafth_reg[0]; + assign afe_thrhd[7:0] = fifoaetl_reg[7:0]; + assign afe_thrhd[8] = fifoaeth_reg[0]; + + // --------------------------------------- + // RXSTATUS and TXSTATUS + // --------------------------------------- + // RO bits out of reg - see code below + + // --------------------------------------- + // COUNTER REGISTERS + // --------------------------------------- + // RO bits out of reg - see code below + + // ----------------------------------------- + // ***************************************** + // assign register bits to output TS-drivers + // ----------------------------------------- + // ***************************************** + + //---------------------------------------- + // dbus0 related + //---------------------------------------- + assign reg0_tdrive0_data = verid_reg; + assign reg0_tdrive0_en = re[0]; + + assign reg1_tdrive0_data = tstcntl_reg; + assign reg1_tdrive0_en = re[1]; + + assign reg2_tdrive0_data = tstcntl2_reg; + assign reg2_tdrive0_en = re[2]; + + assign reg3_tdrive0_data = maccntl_reg; + assign reg3_tdrive0_en = re[3]; + + assign reg4_tdrive0_data = paustmrl_reg; + assign reg4_tdrive0_en = re[4]; + + assign reg5_tdrive0_data = paustmrh_reg; + assign reg5_tdrive0_en = re[5]; + + assign reg6_tdrive0_data = fifoaftl_reg; + assign reg6_tdrive0_en = re[6]; + + assign reg7_tdrive0_data = fifoafth_reg; + assign reg7_tdrive0_en = re[7]; + + assign reg8_tdrive0_data = fifoaetl_reg; + assign reg8_tdrive0_en = re[8]; + + assign reg9_tdrive0_data = fifoaeth_reg; + assign reg9_tdrive0_en = re[9]; + + assign reg10_tdrive0_data = rxstatus_reg; + assign reg10_tdrive0_en = re[10]; + + assign reg11_tdrive0_data = txstatus_reg; + assign reg11_tdrive0_en = re[11]; + + assign buskeep0_tdrive0_data = keep0; + assign buskeep0_tdrive0_en = bkenb0; + //---------------------------------------- + + //---------------------------------------- + // dbus1 related + //---------------------------------------- + assign reg12_tdrive1_data = rxpicnt_reg[7:0]; + assign reg12_tdrive1_en = re[12]; + + assign reg13_tdrive1_data = rxpicnt_reg[15:8]; + assign reg13_tdrive1_en = re[13]; + + assign reg14_tdrive1_data = rxlcecnt_reg[7:0]; + assign reg14_tdrive1_en = re[14]; + + assign reg15_tdrive1_data = rxlcecnt_reg[15:8]; + assign reg15_tdrive1_en = re[15]; + + assign reg16_tdrive1_data = rxlfcnt_reg[7:0]; + assign reg16_tdrive1_en = re[16]; + + assign reg17_tdrive1_data = rxlfcnt_reg[15:8]; + assign reg17_tdrive1_en = re[17]; + + assign reg18_tdrive1_data = rxsfcnt_reg[7:0]; + assign reg18_tdrive1_en = re[18]; + + assign reg19_tdrive1_data = rxsfcnt_reg[15:8]; + assign reg19_tdrive1_en = re[19]; + + assign reg20_tdrive1_data = rxipgcnt_reg[7:0]; + assign reg20_tdrive1_en = re[20]; + + assign reg21_tdrive1_data = rxipgcnt_reg[15:8]; + assign reg21_tdrive1_en = re[21]; + + assign reg22_tdrive1_data = rxcrccnt_reg[7:0]; + assign reg22_tdrive1_en = re[22]; + + assign reg23_tdrive1_data = rxcrccnt_reg[15:8]; + assign reg23_tdrive1_en = re[23]; + + assign buskeep1_tdrive1_data = keep1; + assign buskeep1_tdrive1_en = bkenb1; + //---------------------------------------- + + //---------------------------------------- + // dbus2 related + //---------------------------------------- + assign reg24_tdrive2_data = rxokcnt_reg[7:0]; + assign reg24_tdrive2_en = re[24]; + + assign reg25_tdrive2_data = rxokcnt_reg[15:8]; + assign reg25_tdrive2_en = re[25]; + + assign reg26_tdrive2_data = rxcfcnt_reg[7:0]; + assign reg26_tdrive2_en = re[26]; + + assign reg27_tdrive2_data = rxcfcnt_reg[15:8]; + assign reg27_tdrive2_en = re[27]; + + assign reg28_tdrive2_data = rxpfcnt_reg[7:0]; + assign reg28_tdrive2_en = re[28]; + + assign reg29_tdrive2_data = rxpfcnt_reg[15:8]; + assign reg29_tdrive2_en = re[29]; + + assign reg30_tdrive2_data = rxmfcnt_reg[7:0]; + assign reg30_tdrive2_en = re[30]; + + assign reg31_tdrive2_data = rxmfcnt_reg[15:8]; + assign reg31_tdrive2_en = re[31]; + + assign reg32_tdrive2_data = rxbfcnt_reg[7:0]; + assign reg32_tdrive2_en = re[32]; + + assign reg33_tdrive2_data = rxbfcnt_reg[15:8]; + assign reg33_tdrive2_en = re[33]; + + assign reg34_tdrive2_data = rxvfcnt_reg[7:0]; + assign reg34_tdrive2_en = re[34]; + + assign reg35_tdrive2_data = rxvfcnt_reg[15:8]; + assign reg35_tdrive2_en = re[35]; + + assign buskeep2_tdrive2_data = keep2; + assign buskeep2_tdrive2_en = bkenb2; + //---------------------------------------- + + + //---------------------------------------- + // dbus3 related + //---------------------------------------- + assign reg36_tdrive3_data = txufcnt_reg[7:0]; + assign reg36_tdrive3_en = re[36]; + + assign reg37_tdrive3_data = txufcnt_reg[15:8]; + assign reg37_tdrive3_en = re[37]; + + assign reg38_tdrive3_data = txpfcnt_reg[7:0]; + assign reg38_tdrive3_en = re[38]; + + assign reg39_tdrive3_data = txpfcnt_reg[15:8]; + assign reg39_tdrive3_en = re[39]; + + assign reg40_tdrive3_data = txmfcnt_reg[7:0]; + assign reg40_tdrive3_en = re[40]; + + assign reg41_tdrive3_data = txmfcnt_reg[15:8]; + assign reg41_tdrive3_en = re[41]; + + assign reg42_tdrive3_data = txbfcnt_reg[7:0]; + assign reg42_tdrive3_en = re[42]; + + assign reg43_tdrive3_data = txbfcnt_reg[15:8]; + assign reg43_tdrive3_en = re[43]; + + assign reg44_tdrive3_data = txvfcnt_reg[7:0]; + assign reg44_tdrive3_en = re[44]; + + assign reg45_tdrive3_data = txvfcnt_reg[15:8]; + assign reg45_tdrive3_en = re[45]; + + assign reg46_tdrive3_data = txbfccnt_reg[7:0]; + assign reg46_tdrive3_en = re[46]; + + assign reg47_tdrive3_data = txbfccnt_reg[15:8]; + assign reg47_tdrive3_en = re[47]; + + assign reg48_tdrive3_data = txjfcnt_reg[7:0]; + assign reg48_tdrive3_en = re[48]; + + assign reg49_tdrive3_data = txjfcnt_reg[15:8]; + assign reg49_tdrive3_en = re[49]; + + assign buskeep3_tdrive3_data = keep3; + assign buskeep3_tdrive3_en = bkenb3; + //---------------------------------------- + + + + // instantiate tristate drivers for each register's data Muxing + // ------------------------------------------------------------- + assign dbus0 = (reg0_tdrive0_en) ? reg0_tdrive0_data:8'bz; + assign dbus0 = (reg1_tdrive0_en) ? reg1_tdrive0_data:8'bz; + assign dbus0 = (reg2_tdrive0_en) ? reg2_tdrive0_data:8'bz; + assign dbus0 = (reg3_tdrive0_en) ? reg3_tdrive0_data:8'bz; + assign dbus0 = (reg4_tdrive0_en) ? reg4_tdrive0_data:8'bz; + assign dbus0 = (reg5_tdrive0_en) ? reg5_tdrive0_data:8'bz; + assign dbus0 = (reg6_tdrive0_en) ? reg6_tdrive0_data:8'bz; + assign dbus0 = (reg7_tdrive0_en) ? reg7_tdrive0_data:8'bz; + assign dbus0 = (reg8_tdrive0_en) ? reg8_tdrive0_data:8'bz; + assign dbus0 = (reg9_tdrive0_en) ? reg9_tdrive0_data:8'bz; + assign dbus0 = (reg10_tdrive0_en) ? reg10_tdrive0_data:8'bz; + assign dbus0 = (reg11_tdrive0_en) ? reg11_tdrive0_data:8'bz; + assign dbus0 = (buskeep0_tdrive0_en) ? buskeep0_tdrive0_data:8'bz; + + // ---------------------------------------------------------------- + + assign dbus1 = (reg12_tdrive1_en) ? reg12_tdrive1_data:8'bz; + assign dbus1 = (reg13_tdrive1_en) ? reg13_tdrive1_data:8'bz; + assign dbus1 = (reg14_tdrive1_en) ? reg14_tdrive1_data:8'bz; + assign dbus1 = (reg15_tdrive1_en) ? reg15_tdrive1_data:8'bz; + assign dbus1 = (reg16_tdrive1_en) ? reg16_tdrive1_data:8'bz; + assign dbus1 = (reg17_tdrive1_en) ? reg17_tdrive1_data:8'bz; + assign dbus1 = (reg18_tdrive1_en) ? reg18_tdrive1_data:8'bz; + assign dbus1 = (reg19_tdrive1_en) ? reg19_tdrive1_data:8'bz; + assign dbus1 = (reg20_tdrive1_en) ? reg20_tdrive1_data:8'bz; + assign dbus1 = (reg21_tdrive1_en) ? reg21_tdrive1_data:8'bz; + assign dbus1 = (reg22_tdrive1_en) ? reg22_tdrive1_data:8'bz; + assign dbus1 = (reg23_tdrive1_en) ? reg23_tdrive1_data:8'bz; + assign dbus1 = (buskeep1_tdrive1_en) ? buskeep1_tdrive1_data:8'bz; + + // ---------------------------------------------------------------- + + assign dbus2 = (reg24_tdrive2_en) ? reg24_tdrive2_data:8'bz; + assign dbus2 = (reg25_tdrive2_en) ? reg25_tdrive2_data:8'bz; + assign dbus2 = (reg26_tdrive2_en) ? reg26_tdrive2_data:8'bz; + assign dbus2 = (reg27_tdrive2_en) ? reg27_tdrive2_data:8'bz; + assign dbus2 = (reg28_tdrive2_en) ? reg28_tdrive2_data:8'bz; + assign dbus2 = (reg29_tdrive2_en) ? reg29_tdrive2_data:8'bz; + assign dbus2 = (reg30_tdrive2_en) ? reg30_tdrive2_data:8'bz; + assign dbus2 = (reg31_tdrive2_en) ? reg31_tdrive2_data:8'bz; + assign dbus2 = (reg32_tdrive2_en) ? reg32_tdrive2_data:8'bz; + assign dbus2 = (reg33_tdrive2_en) ? reg33_tdrive2_data:8'bz; + assign dbus2 = (reg34_tdrive2_en) ? reg34_tdrive2_data:8'bz; + assign dbus2 = (reg35_tdrive2_en) ? reg35_tdrive2_data:8'bz; + assign dbus2 = (buskeep2_tdrive2_en) ? buskeep2_tdrive2_data:8'bz; + + // ---------------------------------------------------------------- + + assign dbus3 = (reg36_tdrive3_en) ? reg36_tdrive3_data:8'bz; + assign dbus3 = (reg37_tdrive3_en) ? reg37_tdrive3_data:8'bz; + assign dbus3 = (reg38_tdrive3_en) ? reg38_tdrive3_data:8'bz; + assign dbus3 = (reg39_tdrive3_en) ? reg39_tdrive3_data:8'bz; + assign dbus3 = (reg40_tdrive3_en) ? reg40_tdrive3_data:8'bz; + assign dbus3 = (reg41_tdrive3_en) ? reg41_tdrive3_data:8'bz; + assign dbus3 = (reg42_tdrive3_en) ? reg42_tdrive3_data:8'bz; + assign dbus3 = (reg43_tdrive3_en) ? reg43_tdrive3_data:8'bz; + assign dbus3 = (reg44_tdrive3_en) ? reg44_tdrive3_data:8'bz; + assign dbus3 = (reg45_tdrive3_en) ? reg45_tdrive3_data:8'bz; + assign dbus3 = (reg46_tdrive3_en) ? reg46_tdrive3_data:8'bz; + assign dbus3 = (reg47_tdrive3_en) ? reg47_tdrive3_data:8'bz; + assign dbus3 = (reg48_tdrive3_en) ? reg48_tdrive3_data:8'bz; + assign dbus3 = (reg49_tdrive3_en) ? reg49_tdrive3_data:8'bz; + assign dbus3 = (buskeep3_tdrive3_en) ? buskeep3_tdrive3_data:8'bz; + + // ---------------------------------------------------------------- + + + // --------------------------------------------------------------------------- + // Stretch out us_rdy and Generate us_ack + // us_ack - is just us_rdy pipelined three times and returned + // --------------------------------------------------------------------------- + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + us_rdy_f0 <= #1 1'b0; + us_rdy_f1 <= #1 1'b0; + us_ack <= #1 1'b0; + us_rdy_wide <= #1 1'b0; + end + else begin + us_rdy_f0 <= #1 us_rdy; + us_rdy_f1 <= #1 us_rdy_f0; + us_rdy_wide <= #1 (us_rdy_f0 | us_rdy_f1); + us_ack <= #1 us_rdy_f1; + end + end // always + // --------------------------------------------------------------------------- + + + + // --------------------------------------------------------------------------------- + // ********************************************************************************* + // ADDRESS DECODER + // --------------------------------------------------------------------------------- + // ********************************************************************************* + always @(us_addr or us_wr or us_rdy_wide) + begin + + // default assignment of we, and re signals + we <= 0; + re <= 0; + range_err <= 0; + + if (us_rdy_wide == 1'b1) begin + + if (us_addr[17:6] == 12'h200) begin + + case (us_addr[5:0]) + + 6'd0 : // VERID + begin + if (!us_wr) + re[0] <= 1; + else + re[0] <= 0; + end + 6'd1 : // TSTCNTL + begin + if (us_wr) begin + we[1] <= 1; + re[1] <= 0; + end + else begin + we[1] <= 0; + re[1] <= 1; + end + end + 6'd2 : // TSTCNTL2 + begin + if (us_wr) begin + we[2] <= 1; + re[2] <= 0; + end + else begin + we[2] <= 0; + re[2] <= 1; + end + end + 6'd3 : // MACCNTL + begin + if (us_wr) begin + we[3] <= 1; + re[3] <= 0; + end + else begin + we[3] <= 0; + re[3] <= 1; + end + end + 6'd4 : // PAUSTMRL + begin + if (us_wr) begin + we[4] <= 1; + re[4] <= 0; + end + else begin + we[4] <= 0; + re[4] <= 1; + end + end + 6'd5 : // PAUSTMRH + begin + if (us_wr) begin + we[5] <= 1; + re[5] <= 0; + end + else begin + we[5] <= 0; + re[5] <= 1; + end + end + 6'd6 : // FIFOAFTL + begin + if (us_wr) begin + we[6] <= 1; + re[6] <= 0; + end + else begin + we[6] <= 0; + re[6] <= 1; + end + end + 6'd7 : // FIFOAFTH + begin + if (us_wr) begin + we[7] <= 1; + re[7] <= 0; + end + else begin + we[7] <= 0; + re[7] <= 1; + end + end + 6'd8 : // FIFOAETL + begin + if (us_wr) begin + we[8] <= 1; + re[8] <= 0; + end + else begin + we[8] <= 0; + re[8] <= 1; + end + end + 6'd9 : // FIFOAETH + begin + if (us_wr) begin + we[9] <= 1; + re[9] <= 0; + end + else begin + we[9] <= 0; + re[9] <= 1; + end + end + 6'd10 : // RXSTATUS + begin + if (!us_wr) + re[10] <= 1; + else + re[10] <= 0; + end + 6'd11 : // TXSTATUS + begin + if (!us_wr) + re[11] <= 1; + else + re[11] <= 0; + end + 6'd12 : // RXPICNT_L + begin + if (!us_wr) + re[12] <= 1; + else + re[12] <= 0; + end + 6'd13 : // RXPICNT_H + begin + if (!us_wr) + re[13] <= 1; + else + re[13] <= 0; + end + 6'd14 : // RXLCECNT_L + begin + if (!us_wr) + re[14] <= 1; + else + re[14] <= 0; + end + 6'd15 : // RXLCECNT_H + begin + if (!us_wr) + re[15] <= 1; + else + re[15] <= 0; + end + 6'd16 : // RXLFCNT_L + begin + if (!us_wr) + re[16] <= 1; + else + re[16] <= 0; + end + 6'd17 : // RXLFCNT_H + begin + if (!us_wr) + re[17] <= 1; + else + re[17] <= 0; + end + 6'd18 : // RXSFCNT_L + begin + if (!us_wr) + re[18] <= 1; + else + re[18] <= 0; + end + 6'd19 : // RXSFCNT_H + begin + if (!us_wr) + re[19] <= 1; + else + re[19] <= 0; + end + 6'd20 : // RXIPGFCNT_L + begin + if (!us_wr) + re[20] <= 1; + else + re[20] <= 0; + end + 6'd21 : // RXIPGFCNT_H + begin + if (!us_wr) + re[21] <= 1; + else + re[21] <= 0; + end + 6'd22 : // RXCRCCNT_L + begin + if (!us_wr) + re[22] <= 1; + else + re[22] <= 0; + end + 6'd23 : // RXCRCCNT_H + begin + if (!us_wr) + re[23] <= 1; + else + re[23] <= 0; + end + 6'd24 : // RXOKFCNT_L + begin + if (!us_wr) + re[24] <= 1; + else + re[24] <= 0; + end + 6'd25 : // RXOKFCNT_H + begin + if (!us_wr) + re[25] <= 1; + else + re[25] <= 0; + end + 6'd26 : // RXCFCNT_L + begin + if (!us_wr) + re[26] <= 1; + else + re[26] <= 0; + end + 6'd27 : // RXCFCNT_H + begin + if (!us_wr) + re[27] <= 1; + else + re[27] <= 0; + end + 6'd28 : // RXPFCNT_L + begin + if (!us_wr) + re[28] <= 1; + else + re[28] <= 0; + end + 6'd29 : // RXPFCNT_H + begin + if (!us_wr) + re[29] <= 1; + else + re[29] <= 0; + end + 6'd30 : // RXMFCNT_L + begin + if (!us_wr) + re[30] <= 1; + else + re[30] <= 0; + end + 6'd31 : // RXMFCNT_H + begin + if (!us_wr) + re[31] <= 1; + else + re[31] <= 0; + end + 6'd32 : // RXBFCNT_L + begin + if (!us_wr) + re[32] <= 1; + else + re[32] <= 0; + end + 6'd33 : // RXBFCNT_H + begin + if (!us_wr) + re[33] <= 1; + else + re[33] <= 0; + end + 6'd34 : // RXVFCNT_L + begin + if (!us_wr) + re[34] <= 1; + else + re[34] <= 0; + end + 6'd35 : // RXVFCNT_H + begin + if (!us_wr) + re[35] <= 1; + else + re[35] <= 0; + end + 6'd36 : // TXUFCNT_L + begin + if (!us_wr) + re[36] <= 1; + else + re[36] <= 0; + end + 6'd37 : // TXUFCNT_H + begin + if (!us_wr) + re[37] <= 1; + else + re[37] <= 0; + end + 6'd38 : // TXPFCNT_L + begin + if (!us_wr) + re[38] <= 1; + else + re[38] <= 0; + end + 6'd39 : // TXPFCNT_H + begin + if (!us_wr) + re[39] <= 1; + else + re[39] <= 0; + end + 6'd40 : // TXMFCNT_L + begin + if (!us_wr) + re[40] <= 1; + else + re[40] <= 0; + end + 6'd41 : // TXMFCNT_H + begin + if (!us_wr) + re[41] <= 1; + else + re[41] <= 0; + end + 6'd42 : // TXBFCNT_L + begin + if (!us_wr) + re[42] <= 1; + else + re[42] <= 0; + end + 6'd43 : // TXBFCNT_H + begin + if (!us_wr) + re[43] <= 1; + else + re[43] <= 0; + end + 6'd44 : // TXVFCNT_L + begin + if (!us_wr) + re[44] <= 1; + else + re[44] <= 0; + end + 6'd45 : // TXVFCNT_H + begin + if (!us_wr) + re[45] <= 1; + else + re[45] <= 0; + end + 6'd46 : // TXBFCCNT_L + begin + if (!us_wr) + re[46] <= 1; + else + re[46] <= 0; + end + 6'd47 : // TXBFCCNT_H + begin + if (!us_wr) + re[47] <= 1; + else + re[47] <= 0; + end + 6'd48 : // TXJFCNT_L + begin + if (!us_wr) + re[48] <= 1; + else + re[48] <= 0; + end + 6'd49 : // TXJFCNT_H + begin + if (!us_wr) + re[49] <= 1; + else + re[49] <= 0; + end + + default: + begin + re <= 0; + we <= 0; + range_err <= 1'b0; + end + + endcase + + end // (us_addr[17:6] == 12'h2000) + + + end // (us_rdy == 1) + + else begin // (us_rdy == 0) + we <= 0; + re <= 0; + end + + end //always + // --------------------------------------------------------------------------------- + // ********************************************************************************* + + + // --------------------------------------------------------------------------- + // Delay re[10] - re[48] by 2 clks to use for Clear on Read + // --------------------------------------------------------------------------- + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + re10_dly <= #1 1'b0; + re11_dly <= #1 1'b0; + re12_dly <= #1 1'b0; + re14_dly <= #1 1'b0; + re16_dly <= #1 1'b0; + re18_dly <= #1 1'b0; + re20_dly <= #1 1'b0; + re22_dly <= #1 1'b0; + re24_dly <= #1 1'b0; + re26_dly <= #1 1'b0; + re28_dly <= #1 1'b0; + re30_dly <= #1 1'b0; + re32_dly <= #1 1'b0; + re34_dly <= #1 1'b0; + re36_dly <= #1 1'b0; + re38_dly <= #1 1'b0; + re40_dly <= #1 1'b0; + re42_dly <= #1 1'b0; + re44_dly <= #1 1'b0; + re46_dly <= #1 1'b0; + re48_dly <= #1 1'b0; + clear_delay <= #1 1'b0; + clear_count <= #1 7'b0000000; + end + else begin + if (us_rdy_wide & !us_wr) begin + clear_count <= 127; + end else if (clear_count != 0) begin + clear_count <= clear_count - 1; + end + + if (clear_count == 7'b0000001) begin + clear_delay <= 1; + end else begin + clear_delay <= 0; + end + + if (re[10]) begin + re10_dly <= 1; + end else if (clear_delay) begin + re10_dly <= 0; + end + + if (re[11]) begin + re11_dly <= 1; + end else if (clear_delay) begin + re11_dly <= 0; + end + + if (re[12]) begin + re12_dly <= 1; + end else if (clear_delay) begin + re12_dly <= 0; + end + + if (re[14]) begin + re14_dly <= 1; + end else if (clear_delay) begin + re14_dly <= 0; + end + + if (re[16]) begin + re16_dly <= 1; + end else if (clear_delay) begin + re16_dly <= 0; + end + + if (re[18]) begin + re18_dly <= 1; + end else if (clear_delay) begin + re18_dly <= 0; + end + + if (re[20]) begin + re20_dly <= 1; + end else if (clear_delay) begin + re20_dly <= 0; + end + + if (re[22]) begin + re22_dly <= 1; + end else if (clear_delay) begin + re22_dly <= 0; + end + + if (re[24]) begin + re24_dly <= 1; + end else if (clear_delay) begin + re24_dly <= 0; + end + + if (re[26]) begin + re26_dly <= 1; + end else if (clear_delay) begin + re26_dly <= 0; + end + + if (re[28]) begin + re28_dly <= 1; + end else if (clear_delay) begin + re28_dly <= 0; + end + + if (re[30]) begin + re30_dly <= 1; + end else if (clear_delay) begin + re30_dly <= 0; + end + + if (re[32]) begin + re32_dly <= 1; + end else if (clear_delay) begin + re32_dly <= 0; + end + + if (re[34]) begin + re34_dly <= 1; + end else if (clear_delay) begin + re34_dly <= 0; + end + + if (re[36]) begin + re36_dly <= 1; + end else if (clear_delay) begin + re36_dly <= 0; + end + + if (re[38]) begin + re38_dly <= 1; + end else if (clear_delay) begin + re38_dly <= 0; + end + + if (re[40]) begin + re40_dly <= 1; + end else if (clear_delay) begin + re40_dly <= 0; + end + + if (re[42]) begin + re42_dly <= 1; + end else if (clear_delay) begin + re42_dly <= 0; + end + + if (re[44]) begin + re44_dly <= 1; + end else if (clear_delay) begin + re44_dly <= 0; + end + + if (re[46]) begin + re46_dly <= 1; + end else if (clear_delay) begin + re46_dly <= 0; + end + + if (re[48]) begin + re48_dly <= 1; + end else if (clear_delay) begin + re48_dly <= 0; + end + end + end // always + + + // --------------------------------------------------------------------------------- + // WRITE TO REGISTERS LOGIC + // --------------------------------------------------------------------------------- + + + // --------------------------------------------------------------------------- + // PIPELINE us_wdata + // --------------------------------------------------------------------------- + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + us_wdata_f[7:0] <= #1 8'h00; + end + else begin + us_wdata_f[7:0] <= #1 us_wdata[7:0]; + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // TSTCNTL REGISTER + // --------------------------------------------------------------------------- + // FSM to generate pulses if tstcntl_reg[3] or tstcntl_reg[4] are written to "1" + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + cntl_fsm_st <= #1 IDLE; + start_burst <= #1 1'b0; + ram_rst <= #1 1'b0; + end + else begin + + case (cntl_fsm_st) + + IDLE: + begin + start_burst <= #1 1'b0; + ram_rst <= #1 1'b0; + + if (we[1] == 1) + cntl_fsm_st <= #1 DELAY; + else + cntl_fsm_st <= #1 IDLE; + end + DELAY: + begin + if (us_wdata_f[3] == 1) + cntl_fsm_st <= #1 PULSE1; + else if (us_wdata_f[4] == 1) + cntl_fsm_st <= #1 PULSE2; + else + cntl_fsm_st <= #1 IDLE; + end + PULSE1: + begin + start_burst <= #1 1'b1; + cntl_fsm_st <= #1 IDLE; + end + PULSE2: + begin + ram_rst <= #1 1'b1; + cntl_fsm_st <= #1 IDLE; + end + default: + begin + cntl_fsm_st <= #1 IDLE; + start_burst <= #1 1'b0; + ram_rst <= #1 1'b0; + end + endcase + end + end // always + + // --------------------------------------------------------------------------- + // Write data into TSTCNTL bits [3:0] + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + tstcntl_reg[7:0] <= #1 8'h00; + end + else begin + if (we[1] == 1) begin + tstcntl_reg[3:0] <= #1 us_wdata_f[3:0]; + tstcntl_reg[7:4] <= #1 4'b0000; + end + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // Write data into TSTCNTL2 - unused + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + tstcntl2_reg[7:0] <= #1 8'h00; + end + else begin + if (we[2] == 1) + tstcntl2_reg[7:0] <= #1 us_wdata_f[7:0]; + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // Write data into MACCNTL + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + maccntl_reg[7:0] <= #1 8'h00; + end + else begin + if (we[3] == 1) + maccntl_reg[7:0] <= #1 us_wdata_f[7:0]; + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // Write data into PAUSTMR_L, and PAUSTMR_H + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + paustmrl_reg[7:0] <= #1 8'h00; + paustmrh_reg[7:0] <= #1 8'h00; + end + else begin + if (we[4] == 1) + paustmrl_reg[7:0] <= #1 us_wdata_f[7:0]; + if (we[5] == 1) + paustmrh_reg[7:0] <= #1 us_wdata_f[7:0]; + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // Write data into FIFOAFTL, and FIFOAFTH + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + fifoaftl_reg[7:0] <= #1 8'hc1; + fifoafth_reg[7:0] <= #1 8'h01; + end + else begin + if (we[6] == 1) + fifoaftl_reg[7:0] <= #1 us_wdata_f[7:0]; + if (we[7] == 1) + fifoafth_reg[7:0] <= #1 us_wdata_f[7:0]; + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // Write data into FIFOAETL, and FIFOAETH + // --------------------------------------------------------------------------- + + always @(posedge us_clk or negedge reset_n) begin + if (~reset_n) begin + fifoaetl_reg[7:0] <= #1 8'h05; + fifoaeth_reg[7:0] <= #1 8'h00; + end + else begin + if (we[8] == 1) + fifoaetl_reg[7:0] <= #1 us_wdata_f[7:0]; + if (we[9] == 1) + fifoaeth_reg[7:0] <= #1 us_wdata_f[7:0]; + end + end // always + // --------------------------------------------------------------------------- + + // --------------------------------------------------------------------------- + // Write to RXSTATUS Reg from system side + // --------------------------------------------------------------------------- + always @(posedge rxc_clk or negedge reset_n) begin + if (~reset_n) begin + rxstatus_reg[7:0] <= #1 8'h00; + end + else begin + if (re10_dly & !us_rdy_wide) + rxstatus_reg[7:0] <= #1 8'h00; + else begin + if (rx_error_ri == 1'b1) + rxstatus_reg[0] <= #1 1'b1; + if (rx_fifo_error_ri == 1'b1) + rxstatus_reg[1] <= #1 1'b1; + end + end + end // always + + // --------------------------------------------------------------------------- + // Write to TXSTATUS Reg from system side + // --------------------------------------------------------------------------- + always @(posedge txc_clk or negedge reset_n) begin + if (~reset_n) begin + txstatus_reg[7:0] <= #1 8'h00; + end + else begin + if (re11_dly & !us_rdy_wide) + txstatus_reg[7:0] <= #1 8'h00; + else begin + if (tx_disfrm_ri == 1'b1) + txstatus_reg[0] <= #1 1'b1; + if (tx_fifo_full_ri == 1'b1) + txstatus_reg[1] <= #1 1'b1; + end + end + end // always + + // --------------------------------------------------------------------------- + // RX STAT COUNTERS + // --------------------------------------------------------------------------- + always @(posedge rxc_clk or negedge reset_n) begin + if (~reset_n) begin + rxpicnt_reg <= #1 16'h0000; + rxlcecnt_reg <= #1 16'h0000; + rxlfcnt_reg <= #1 16'h0000; + rxsfcnt_reg <= #1 16'h0000; + rxipgcnt_reg <= #1 16'h0000; + rxcrccnt_reg <= #1 16'h0000; + rxokcnt_reg <= #1 16'h0000; + rxcfcnt_reg <= #1 16'h0000; + rxpfcnt_reg <= #1 16'h0000; + rxmfcnt_reg <= #1 16'h0000; + rxbfcnt_reg <= #1 16'h0000; + rxvfcnt_reg <= #1 16'h0000; + end + else begin + if (re12_dly & !us_rdy_wide) + rxpicnt_reg <= #1 16'h0000; + if (re14_dly & !us_rdy_wide) + rxlcecnt_reg <= #1 16'h0000; + if (re16_dly & !us_rdy_wide) + rxlfcnt_reg <= #1 16'h0000; + if (re18_dly & !us_rdy_wide) + rxsfcnt_reg <= #1 16'h0000; + if (re20_dly & !us_rdy_wide) + rxipgcnt_reg <= #1 16'h0000; + if (re22_dly & !us_rdy_wide) + rxcrccnt_reg <= #1 16'h0000; + if (re24_dly & !us_rdy_wide) + rxokcnt_reg <= #1 16'h0000; + if (re26_dly & !us_rdy_wide) + rxcfcnt_reg <= #1 16'h0000; + if (re28_dly & !us_rdy_wide) + rxpfcnt_reg <= #1 16'h0000; + if (re30_dly & !us_rdy_wide) + rxmfcnt_reg <= #1 16'h0000; + if (re32_dly & !us_rdy_wide) + rxbfcnt_reg <= #1 16'h0000; + if (re34_dly & !us_rdy_wide) + rxvfcnt_reg <= #1 16'h0000; + else begin + if (rx_stat_en == 1'b1) begin + if (rx_stat_vec[26] == 1'b1) + rxpicnt_reg <= #1 rxpicnt_reg + 1; + if (rx_stat_vec[24] == 1'b1) + rxlcecnt_reg <= #1 rxlcecnt_reg + 1; + if (rx_stat_vec[31] == 1'b1) + rxlfcnt_reg <= #1 rxlfcnt_reg + 1; + if (rx_stat_vec[30] == 1'b1) + rxsfcnt_reg <= #1 rxsfcnt_reg + 1; + if (rx_stat_vec[29] == 1'b1) + rxipgcnt_reg <= #1 rxipgcnt_reg + 1; + if (rx_stat_vec[25] == 1'b1) + rxcrccnt_reg <= #1 rxcrccnt_reg + 1; + if (rx_stat_vec[23] == 1'b1) + rxokcnt_reg <= #1 rxokcnt_reg + 1; + if (rx_stat_vec[18] == 1'b1) + rxcfcnt_reg <= #1 rxcfcnt_reg + 1; + if (rx_stat_vec[17] == 1'b1) + rxpfcnt_reg <= #1 rxpfcnt_reg + 1; + if (rx_stat_vec[22] == 1'b1) + rxmfcnt_reg <= #1 rxmfcnt_reg + 1; + if (rx_stat_vec[21] == 1'b1) + rxbfcnt_reg <= #1 rxbfcnt_reg + 1; + if (rx_stat_vec[16] == 1'b1) + rxvfcnt_reg <= #1 rxvfcnt_reg + 1; + end + end + end + end // always + + + // --------------------------------------------------------------------------- + // TX STAT COUNTERS + // --------------------------------------------------------------------------- + always @(posedge txc_clk or negedge reset_n) begin + if (~reset_n) begin + txufcnt_reg <= #1 16'h0000; + txpfcnt_reg <= #1 16'h0000; + txmfcnt_reg <= #1 16'h0000; + txbfcnt_reg <= #1 16'h0000; + txvfcnt_reg <= #1 16'h0000; + txbfccnt_reg <= #1 16'h0000; + txjfcnt_reg <= #1 16'h0000; + end + else begin + if (re36_dly & !us_rdy_wide) + txufcnt_reg <= #1 16'h0000; + if (re38_dly & !us_rdy_wide) + txpfcnt_reg <= #1 16'h0000; + if (re40_dly & !us_rdy_wide) + txmfcnt_reg <= #1 16'h0000; + if (re42_dly & !us_rdy_wide) + txbfcnt_reg <= #1 16'h0000; + if (re44_dly & !us_rdy_wide) + txvfcnt_reg <= #1 16'h0000; + if (re46_dly & !us_rdy_wide) + txbfccnt_reg <= #1 16'h0000; + if (re48_dly & !us_rdy_wide) + txjfcnt_reg <= #1 16'h0000; + else begin + if (tx_stat_en == 1'b1) begin + if (tx_stat_vec[0] == 1'b1) + txufcnt_reg <= #1 txufcnt_reg + 1; + if (tx_stat_vec[6] == 1'b1) + txpfcnt_reg <= #1 txpfcnt_reg + 1; + if (tx_stat_vec[1] == 1'b1) + txmfcnt_reg <= #1 txmfcnt_reg + 1; + if (tx_stat_vec[2] == 1'b1) + txbfcnt_reg <= #1 txbfcnt_reg + 1; + if (tx_stat_vec[7] == 1'b1) + txvfcnt_reg <= #1 txvfcnt_reg + 1; + if (tx_stat_vec[3] == 1'b1) + txbfccnt_reg <= #1 txbfccnt_reg + 1; + if (tx_stat_vec[4] == 1'b1) + txjfcnt_reg <= #1 txjfcnt_reg + 1; + end + end + end + end // always + + +endmodule // reg_intf + + + + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/rx_loopbk.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/rx_loopbk.v new file mode 100644 index 0000000..8c844d5 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/rx_loopbk.v @@ -0,0 +1,300 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: rx_loopbk.v +// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +//`timescale 1ns/100ps + + +// DEFINES + + +module rx_loopbk( + clk, + reset_n, + rxmac_clk_en, + add_swap, + loop_enb, + rx_dbout, + rx_write, + rx_eof, + tx_dbin, + tx_write, + tx_eof + ); + + + input clk; // rx fifo clock + input reset_n; // active low global reset + input rxmac_clk_en; // rx clk enable + + input add_swap; // address swap control bit from reg + input loop_enb; // loop back enable control bit from reg + + input [7:0] rx_dbout; // rxdata input to Rx FIFO + input rx_eof; // rxdata EOF input to Rx FIFO + input rx_write; // Rx FIFO write enable + + output [7:0] tx_dbin; // txdata input to Tx FIFO + reg [7:0] tx_dbin; // + + output tx_eof; // txdata EOF input to Tx FIFO + reg tx_eof; // + + output tx_write; // Tx FIFO write enable + reg tx_write; // + + + reg [7:0] rx_dbout_1f; // rxdata input to Rx FIFO flopped 1 time + reg rx_eof_1f; // rxdata EOF input to Rx FIFO flopped 1 time + reg rx_write_1f; // Rx FIFO write enable flopped 1 time + + reg [7:0] rx_dbout_2f; // rxdata input to Rx FIFO flopped 2 times + reg rx_eof_2f; // rxdata EOF input to Rx FIFO flopped 2 times + reg rx_write_2f; // Rx FIFO write enable flopped 2 times + + reg [7:0] rx_dbout_3f; // rxdata input to Rx FIFO flopped 3 times + reg rx_eof_3f; // rxdata EOF input to Rx FIFO flopped 3 times + reg rx_write_3f; // Rx FIFO write enable flopped 3 times + + reg [7:0] rx_dbout_4f; // rxdata input to Rx FIFO flopped 4 times + reg rx_eof_4f; // rxdata EOF input to Rx FIFO flopped 4 times + reg rx_write_4f; // Rx FIFO write enable flopped 4 times + + reg [7:0] rx_dbout_5f; // rxdata input to Rx FIFO flopped 5 times + reg rx_eof_5f; // rxdata EOF input to Rx FIFO flopped 5 times + reg rx_write_5f; // Rx FIFO write enable flopped 5 times + + reg [7:0] rx_dbout_6f; // rxdata input to Rx FIFO flopped 6 times + reg rx_eof_6f; // rxdata EOF input to Rx FIFO flopped 6 times + reg rx_write_6f; // Rx FIFO write enable flopped 6 times + + reg [7:0] rx_dbout_7f; // rxdata input to Rx FIFO flopped 7 times + reg rx_eof_7f; // rxdata EOF input to Rx FIFO flopped 7 times + reg rx_write_7f; // Rx FIFO write enable flopped 7 times + + reg [7:0] rx_dbout_8f; // rxdata input to Rx FIFO flopped 8 times + reg rx_eof_8f; // rxdata EOF input to Rx FIFO flopped 8 times + reg rx_write_8f; // Rx FIFO write enable flopped 8 times + + reg [7:0] rx_dbout_9f; // rxdata input to Rx FIFO flopped 9 times + reg [7:0] rx_dbout_10f; // rxdata input to Rx FIFO flopped 10 times + reg [7:0] rx_dbout_11f; // rxdata input to Rx FIFO flopped 11 times + reg [7:0] rx_dbout_12f; // rxdata input to Rx FIFO flopped 12 times + reg [7:0] rx_dbout_13f; // rxdata input to Rx FIFO flopped 13 times + + reg [7:0] add_swap_data; // data from add swap mux flopped once + + reg mx_ctl_1f; // mux control flopped 1 time + reg mx_ctl_2f; // mux control flopped 2 times + reg mx_ctl_3f; // mux control flopped 3 times + reg mx_ctl_4f; // mux control flopped 4 times + reg mx_ctl_5f; // mux control flopped 5 times + reg mx_ctl_6f; // mux control flopped 6 times + reg mx_ctl_7f; // mux control flopped 7 time + reg mx_ctl_8f; // mux control flopped 8 times + reg mx_ctl_9f; // mux control flopped 9 times + reg mx_ctl_10f; // mux control flopped 10 times + reg mx_ctl_11f; // mux control flopped 11 times + reg mx_ctl_12f; // mux control flopped 12 times + reg addr_detect_en; // address detect enable + + reg [1:0] mux_ctl; // address swap mux control bits + + parameter + NO_WRITE = 1'b0; // write enable low + + parameter [7:0] + NULL_DATA = 8'h00; // NULL DATA + + parameter + NULL_EOF = 1'b0; // NO EOF + + parameter [1:0] // ADD SWAP MUX SELECTIONS + DATA_D7 = 2'b00, + DATA_D1 = 2'b01, + DATA_D13 = 2'b10, + NO_SWAP = 2'b11; + + + + + //------------------------------------------------------------------- + // Pipeline rx_dbout, rx_eof and rx_write + //------------------------------------------------------------------- + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + rx_dbout_1f <= 8'h00; + rx_eof_1f <= 1'b0; + rx_write_1f <= 1'b0; + + rx_dbout_2f <= 8'h00; + rx_eof_2f <= 1'b0; + rx_write_2f <= 1'b0; + + rx_dbout_3f <= 8'h00; + rx_eof_3f <= 1'b0; + rx_write_3f <= 1'b0; + + rx_dbout_4f <= 8'h00; + rx_eof_4f <= 1'b0; + rx_write_4f <= 1'b0; + + rx_dbout_5f <= 8'h00; + rx_eof_5f <= 1'b0; + rx_write_5f <= 1'b0; + + rx_dbout_6f <= 8'h00; + rx_eof_6f <= 1'b0; + rx_write_6f <= 1'b0; + + rx_dbout_7f <= 8'h00; + rx_eof_7f <= 1'b0; + rx_write_7f <= 1'b0; + + rx_dbout_8f <= 8'h00; + rx_eof_8f <= 1'b0; + rx_write_8f <= 1'b0; + + rx_dbout_9f <= 8'h00; + rx_dbout_10f <= 8'h00; + rx_dbout_11f <= 8'h00; + rx_dbout_12f <= 8'h00; + rx_dbout_13f <= 8'h00; + end + else if (rxmac_clk_en) begin + rx_dbout_1f <= rx_dbout; + rx_eof_1f <= rx_eof; + rx_write_1f <= rx_write; + + rx_dbout_2f <= rx_dbout_1f; + rx_eof_2f <= rx_eof_1f; + rx_write_2f <= rx_write_1f; + + rx_dbout_3f <= rx_dbout_2f; + rx_eof_3f <= rx_eof_2f; + rx_write_3f <= rx_write_2f; + + rx_dbout_4f <= rx_dbout_3f; + rx_eof_4f <= rx_eof_3f; + rx_write_4f <= rx_write_3f; + + rx_dbout_5f <= rx_dbout_4f; + rx_eof_5f <= rx_eof_4f; + rx_write_5f <= rx_write_4f; + + rx_dbout_6f <= rx_dbout_5f; + rx_eof_6f <= rx_eof_5f; + rx_write_6f <= rx_write_5f; + + rx_dbout_7f <= rx_dbout_6f; + rx_eof_7f <= rx_eof_6f; + rx_write_7f <= rx_write_6f; + + rx_write_8f <= rx_write_7f; + rx_eof_8f <= rx_eof_7f; + rx_dbout_8f <= rx_dbout_7f; + + rx_dbout_9f <= rx_dbout_8f; + rx_dbout_10f <= rx_dbout_9f; + rx_dbout_11f <= rx_dbout_10f; + rx_dbout_12f <= rx_dbout_11f; + rx_dbout_13f <= rx_dbout_12f; + end // else + end // always + + //------------------------------------------------------------------- + // Pipelined mux control bits + //------------------------------------------------------------------- + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + mx_ctl_1f <= 1'b0; + mx_ctl_2f <= 1'b0; + mx_ctl_3f <= 1'b0; + mx_ctl_4f <= 1'b0; + mx_ctl_5f <= 1'b0; + mx_ctl_6f <= 1'b0; + mx_ctl_7f <= 1'b0; + mx_ctl_8f <= 1'b0; + mx_ctl_9f <= 1'b0; + mx_ctl_10f <= 1'b0; + mx_ctl_11f <= 1'b0; + mx_ctl_12f <= 1'b0; + addr_detect_en <= 1'b1; + end + else if (rxmac_clk_en) begin + if (rx_write_1f & rx_write_7f) begin + addr_detect_en <= 0; + end else if (rx_write_7f & rx_eof_7f) begin + addr_detect_en <= 1; + end + mx_ctl_1f <= (rx_write_1f & !rx_write_7f & addr_detect_en); + mx_ctl_2f <= mx_ctl_1f; + mx_ctl_3f <= mx_ctl_2f; + mx_ctl_4f <= mx_ctl_3f; + mx_ctl_5f <= mx_ctl_4f; + mx_ctl_6f <= mx_ctl_5f; + mx_ctl_7f <= mx_ctl_6f; + mx_ctl_8f <= mx_ctl_7f; + mx_ctl_9f <= mx_ctl_8f; + mx_ctl_10f <= mx_ctl_9f; + mx_ctl_11f <= mx_ctl_10f; + mx_ctl_12f <= mx_ctl_11f; + end // else + end // always + + always @(add_swap, mx_ctl_12f, mx_ctl_6f) begin + if (add_swap) begin + mux_ctl[0] <= mx_ctl_6f; + mux_ctl[1] <= mx_ctl_12f; + end + else begin + mux_ctl <= NO_SWAP; + end + end // always + + + //------------------------------------------------------------------- + // Pipelined address swap mux + //------------------------------------------------------------------- + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + add_swap_data <= 8'h00; + end + else if (rxmac_clk_en) begin + case (mux_ctl) + DATA_D7: add_swap_data <= rx_dbout_7f; + DATA_D1: add_swap_data <= rx_dbout_1f; + DATA_D13: add_swap_data <= rx_dbout_13f; + NO_SWAP: add_swap_data <= rx_dbout_7f; + endcase + end // else + end // always + + //------------------------------------------------------------------- + // Pipelined muxes - loopback rx data or Null data (place holder + // for a frame buffer etc.) + //------------------------------------------------------------------- + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + tx_dbin <= 8'h00; + tx_write <= 1'b0; + tx_eof <= 1'b0; + end + else if (rxmac_clk_en) begin + if (loop_enb) begin + tx_dbin <= add_swap_data; + tx_write <= rx_write_8f ; + tx_eof <= rx_eof_8f; + end + else begin + tx_dbin <= NULL_DATA; + tx_write <= NO_WRITE; + tx_eof <= NULL_EOF; + end + end // else + end // always + + +endmodule// diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/tst_logic.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/tst_logic.v new file mode 100644 index 0000000..6e2daf6 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/tst_logic.v @@ -0,0 +1,295 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: tst_logic.v +// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== + +//`timescale 1ns/100ps + +module tst_logic ( + + // ------- + // inputs + // ------- + + // from IO + reset_n, + txmac_clk, + rxmac_clk, + txmac_clk_en, + rxmac_clk_en, + + // from tsmac core + rx_write, + rx_dbout, + rx_eof, + rx_error, + rx_fifo_error, + tx_macread, + tx_done, + tx_disfrm, +//gbit_en, + + // from reg_intf + pkt_add_swap_ri, + pkt_loop_enb_ri, + tx_sndpaustim_ri, + tx_sndpausreq_ri, + tx_fifoctrl_ri, + rx_fifo_full_ri, + tx_fifo_empty_ri, + ignore_next_pkt_ri, + aff_thrhd, + afe_thrhd, + + // ------- + // outputs + // ------- + + // to tsmac core + tx_fifodata, + tx_fifoeof, + tx_fifoavail, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + rx_fifo_full, + ignore_next_pkt, + + // to reg_intf + rxc_clk, + txc_clk, + rx_error_ri, + rx_fifo_error_ri, + tx_disfrm_ri, + tx_fifo_full_ri + ); + + //====================== + // inputs and outputs + //====================== + input reset_n; // active low global reset + input txmac_clk; + input rxmac_clk; + input txmac_clk_en; + input rxmac_clk_en; + + // from tsmac core + input rx_write; + input [7:0] rx_dbout; + input rx_eof; + input rx_error; + input rx_fifo_error; + input tx_macread; + input tx_done; + input tx_disfrm; +// input gbit_en; + + // from reg_intf + input pkt_add_swap_ri; + input pkt_loop_enb_ri; + input [15:0] tx_sndpaustim_ri; + input tx_sndpausreq_ri; + input tx_fifoctrl_ri; + input rx_fifo_full_ri; + input tx_fifo_empty_ri; + input ignore_next_pkt_ri; + input [8:0] aff_thrhd; // almost full threshold from reg intf + input [8:0] afe_thrhd; // almost empty threshold from reg intf + + // to tsmac core + output [7:0] tx_fifodata; + output tx_fifoeof; + output tx_fifoavail; + output tx_fifoempty; + output [15:0] tx_sndpaustim; + output tx_sndpausreq; + output tx_fifoctrl; + output rx_fifo_full; + output ignore_next_pkt; + + // to reg_intf + output rx_error_ri; + output rx_fifo_error_ri; + output tx_disfrm_ri; + output tx_fifo_full_ri; + output rxc_clk; // MAC Client side Rx clock + output txc_clk; // MAC Client side Tx clock + +parameter pdevice_family = "EC"; + + //====================== + // Regs and wires + //====================== + wire tx_fifoempty; + reg [15:0] tx_sndpaustim; + reg tx_sndpausreq; + reg tx_fifoctrl; + reg ignore_next_pkt; + reg write_eof_rxclk; + reg [1:0] clr_write_eof_rxclk; + reg [2:0] write_eof_txclk; + reg flop_tx_macread; + reg flop_flop_tx_macread; + reg flop_tx_fifo_eof; + reg [3:0] frames_present; + + reg rx_error_ri; + reg rx_fifo_error_ri; + reg tx_disfrm_ri; + reg tx_fifo_full_ri; + reg tx_fifo_empty_f; // tx fifo empty pipelined and synced with clk_enb + + wire rxc_clk; // MAC Client side Rx clock + wire txc_clk; // MAC Client side Tx clock + + wire [7:0] tx_fifodata; + wire tx_fifoeof; + reg tx_fifoavail; + reg tx_fifoavail_int; + wire rx_fifo_full; + + wire [8:0] tx_fifo_dout; // data out of tx_fifo + wire tx_fifo_full; // tx fifo full + wire tx_fifo_afull; // tx fifo almost full + wire tx_fifo_empty; // tx fifo empty + wire tx_fifo_aempty; // tx fifo almost empty + + wire [7:0] tx_dbin; + wire tx_write; + wire tx_eof; + + //------------------------------------------------------------------- + // glue logic + //------------------------------------------------------------------- + assign rxc_clk = rxmac_clk; + assign txc_clk = txmac_clk; + assign tx_fifodata[7:0] = tx_fifo_dout[7:0]; + assign tx_fifoeof = tx_fifo_dout[8]; + assign rx_fifo_full = (tx_fifo_full | rx_fifo_full_ri); + + assign tx_fifoempty = (tx_fifo_empty|tx_fifo_empty_ri); + + always @(posedge rxmac_clk or negedge reset_n) begin + if (~reset_n) begin + ignore_next_pkt <= 1'b0; + tx_fifoavail <= 1'b0; + tx_fifoavail_int <= 1'b0; + write_eof_rxclk <= 1'b0; + clr_write_eof_rxclk <= 2'b00; + tx_fifo_empty_f <= 1'b1; + end + else if (rxmac_clk_en) begin + tx_fifo_empty_f <= tx_fifo_empty; + ignore_next_pkt <= ignore_next_pkt_ri; + + tx_fifoavail_int <= (|frames_present) | (~tx_fifo_aempty); + tx_fifoavail <= tx_fifoavail_int; + + clr_write_eof_rxclk[1] <= clr_write_eof_rxclk[0]; + clr_write_eof_rxclk[0] <= write_eof_rxclk; + if (rx_write & rx_eof) begin + write_eof_rxclk <= 1; + end else if (clr_write_eof_rxclk[1]) begin + write_eof_rxclk <= 0; + end + end // else + end // always + + always @(posedge txmac_clk or negedge reset_n) begin + if (~reset_n) begin + tx_sndpausreq <= 1'b0; + tx_fifo_full_ri <= 1'b0; + tx_sndpaustim[15:0] <= 16'h0000; + tx_disfrm_ri <= 1'b0; + tx_fifoctrl <= 1'b0; + rx_error_ri <= 1'b0; + rx_fifo_error_ri <= 1'b0; + write_eof_txclk <= 1'b0; + flop_tx_macread <= 1'b0; + flop_flop_tx_macread <= 1'b0; + flop_tx_fifo_eof <= 1'b0; + frames_present <= 1'b0; + end + else if (txmac_clk_en) begin + if (tx_sndpausreq_ri == 1) begin + tx_sndpausreq <= 1; + end else if (tx_macread == 1) begin + if (tx_fifo_afull) begin + tx_sndpausreq <= 1; + end else begin + tx_sndpausreq <= 0; + end + end else begin + tx_sndpausreq <= 0; + end + tx_sndpaustim[15:0] <= tx_sndpaustim_ri[15:0]; + tx_fifoctrl <= tx_fifoctrl_ri; + + tx_disfrm_ri <= tx_disfrm; // an error condition -fifo underun etc. + rx_error_ri <= rx_error; + rx_fifo_error_ri <= rx_fifo_error; + + tx_fifo_full_ri <= tx_fifo_full; + + write_eof_txclk[2] <= write_eof_txclk[1]; + write_eof_txclk[1] <= write_eof_txclk[0]; + write_eof_txclk[0] <= write_eof_rxclk; + flop_tx_macread <= tx_macread; + flop_flop_tx_macread <= flop_tx_macread; + flop_tx_fifo_eof <= tx_fifo_dout[8]; + if (tx_fifo_empty == 1) begin + frames_present <= 0; // When fifo is empty clear frames present + end else if ((write_eof_txclk[1] & !write_eof_txclk[2]) + && !(flop_flop_tx_macread & flop_tx_fifo_eof)) begin + frames_present <= frames_present + 4'b0001; // Increment # frames + end else if (!(write_eof_txclk[1] & !write_eof_txclk[2]) + && (flop_flop_tx_macread & flop_tx_fifo_eof)) begin + frames_present <= frames_present - 4'b0001; // Dec # frames in buf + end + end // else + end // always + + //------------------------------------------------------------------- + // instanciate modules + //------------------------------------------------------------------- + + rx_loopbk rx_loopbk( + .clk(rxmac_clk), + .reset_n(reset_n), + .rxmac_clk_en(rxmac_clk_en), + .add_swap(pkt_add_swap_ri), + .loop_enb(pkt_loop_enb_ri), + .rx_dbout(rx_dbout[7:0]), + .rx_write(rx_write), + .rx_eof(rx_eof), + .tx_dbin(tx_dbin), + .tx_write(tx_write), + .tx_eof(tx_eof) + ); + + //defparam tx_fifo.ff_ctl.SYNC_MODE = "ASYNC"; + //defparam tx_fifo.ff_ctl.RAM_MODE = "NOREG"; + fifo_2048x9 #(.pdevice_family(pdevice_family)) + tx_fifo ( + // INPUTS + .wclk(rxmac_clk), + .wren(tx_write), + .datain({tx_eof,tx_dbin}), + .reset(reset_n), + .rclk(txmac_clk), + .rden(tx_macread), + .aff_thrhd(aff_thrhd), + .afe_thrhd(afe_thrhd), + .wclk_en(rxmac_clk_en), + .rclk_en(txmac_clk_en), + + // OUTPUTS + .daout(tx_fifo_dout[8:0]), + .empty(tx_fifo_empty), + .almost_full(tx_fifo_afull), + .almost_empty(tx_fifo_aempty), + .full(tx_fifo_full) + ); +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.v new file mode 100644 index 0000000..320160c --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.v @@ -0,0 +1,216 @@ +//============================================================================= +// Verilog module generated by IPExpress +// Filename: USERNAME.v +// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. +//============================================================================= + +/* WARNING - Changes to this file should be performed by re-running IPexpress +or modifying the .LPC file and regenerating the core. Other changes may lead +to inconsistent simulation and/or implemenation results */ +module ts_mac_core_only_top ( + // clock and reset + hclk, + txmac_clk, + rxmac_clk, + reset_n, + txmac_clk_en, + rxmac_clk_en, + + // Input signals to the GMII + rxd, + rx_dv, + rx_er, + col, + crs, + + // Input signals to the CPU Interface + haddr, + hdatain, + hcs_n, + hwrite_n, + hread_n, + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + + // Input signals to the Rx MAC FIFO Interface + rx_fifo_full, + ignore_pkt, + + // Output signals from the GMII + txd, + tx_en, + tx_er, + + // Output signals from the CPU Interface + hdataout, + hdataout_en_n, + hready_n, + cpu_if_gbit_en, + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + tx_macread, + tx_discfrm, + tx_staten, + tx_statvec, + tx_done, + + // Output signals from the Rx MAC FIFO Interface + rx_fifo_error, + rx_stat_vector, + rx_dbout, + rx_write, + rx_stat_en, + rx_eof, + rx_error + ); + + // ------------------------- clock and reset inputs --------------------- + input hclk; // clock to the CPU I/F + input txmac_clk; // clock to the Tx MAC + input rxmac_clk; // clock to the RX MAC + input reset_n; // Global reset + + input txmac_clk_en; // clock enable to the Tx MAC + input rxmac_clk_en; // clock enable to the RX MAC + + // ----------------------- Input signals to the GMII ------------------- + input [7:0] rxd; // Receive data + input rx_dv; // Receive data valid + input rx_er; // Receive data error + + input col; // Collision detect + input crs; // Carrier Sense + + // -------------------- Input signals to the CPU I/F ------------------- + input [7:0] haddr; // Address Bus + input [7:0] hdatain; // Input data Bus + input hcs_n; // Chip select + input hwrite_n; // Register write + input hread_n; // Register read + + // -------------------- Input signals to the MII I/F ------------------- + + + // ---------------- Input signals to the Tx MAC FIFO I/F --------------- + input [7:0] tx_fifodata; // Data Input from FIFO + input tx_fifoavail; // Data Available in FIFO + input tx_fifoeof; // End of Frame + input tx_fifoempty; // FIFO Empty + input [15:0] tx_sndpaustim; // Pause frame parameter + input tx_sndpausreq; // Transmit PAUSE frame + input tx_fifoctrl; // Control frame or Not + + // ---------------- Input signals to the Rx MAC FIFO I/F --------------- + input rx_fifo_full; // Receive FIFO Full + input ignore_pkt; // Ignore the frame + + // -------------------- Output signals from the GMII ----------------------- + output [7:0] txd; // Transmit data + output tx_en; // Transmit Enable + output tx_er; // Transmit Error + + // -------------------- Output signals from the CPU I/F ------------------- + output [7:0] hdataout; // Output data Bus + output hdataout_en_n; // Data Out Enable + output hready_n; // Ready signal + output cpu_if_gbit_en; // Gig or 10/100 mode + + // -------------------- Output signals from the MII I/F ------------------- + + + // ---------------- Output signals from the Tx MAC FIFO I/F --------------- + output tx_macread; // Read FIFO + output tx_discfrm; // Discard Frame + output tx_staten; // Status Vector Valid + output tx_done; // Transmit of Frame done + output [30:0] tx_statvec; // Tx Status Vector + + // ---------------- Output signals from the Rx MAC FIFO I/F --------------- + output rx_fifo_error; // FIFO full detected + output [31:0] rx_stat_vector; // Rx Status Vector + output [7:0] rx_dbout; // Data Output to FIFO + output rx_write; // Write FIFO + output rx_stat_en; // Status Vector Valid + output rx_eof; // Entire frame written + output rx_error; // Erroneous frame + + tsmac U1_ts_mac_core_only_core ( + + // clock and reset + .hclk(hclk), + .txmac_clk(txmac_clk), + .rxmac_clk(rxmac_clk), + .reset_n(reset_n), + .txmac_clk_en(txmac_clk_en), + .rxmac_clk_en(rxmac_clk_en), + + + // Input signals to the GMII + .rxd(rxd), + .rx_dv(rx_dv), + .rx_er(rx_er), + .col(col), + .crs(crs), + // Input signals to the CPU Interface + .haddr(haddr), + .hdatain(hdatain), + .hcs_n(hcs_n), + .hwrite_n(hwrite_n), + .hread_n(hread_n), + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + .tx_fifodata(tx_fifodata), + .tx_fifoavail(tx_fifoavail), + .tx_fifoeof(tx_fifoeof), + .tx_fifoempty(tx_fifoempty), + .tx_sndpaustim(tx_sndpaustim), + .tx_sndpausreq(tx_sndpausreq), + .tx_fifoctrl(tx_fifoctrl), + + // Input signals to the Rx MAC FIFO Interface + .rx_fifo_full(rx_fifo_full), + .ignore_pkt(ignore_pkt), + + // Output signals from the GMII + .txd(txd), + .tx_en(tx_en), + .tx_er(tx_er), + + // Output signals from the CPU Interface + .hdataout(hdataout), + .hdataout_en_n(hdataout_en_n), + .hready_n(hready_n), + .cpu_if_gbit_en(cpu_if_gbit_en), + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + .tx_macread(tx_macread), + .tx_discfrm(tx_discfrm), + .tx_staten(tx_staten), + .tx_statvec(tx_statvec), + .tx_done(tx_done), + + // Output signals from the Rx MAC FIFO Interface + .rx_fifo_error(rx_fifo_error), + .rx_stat_vector(rx_stat_vector), + .rx_dbout(rx_dbout), + .rx_write(rx_write), + .rx_stat_en(rx_stat_en), + .rx_eof(rx_eof), + .rx_error(rx_error) + ); +endmodule diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.vhd b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.vhd new file mode 100644 index 0000000..328d770 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.vhd @@ -0,0 +1,201 @@ +------------------------------------------------------------------------------- +-- Verilog module generated by IPExpress +-- Filename: ts_mac_core_only_top.vhd +-- Copyright(c) 2005 Lattice Semiconductor Corporation. All rights reserved. +------------------------------------------------------------------------------- + +--WARNING - Changes to this file should be performed by re-running IPexpress +--or modifying the .LPC file and regenerating the core. Other changes may lead +--to inconsistent simulation and/or implemenation results +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ts_mac_core_only_top is +port( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + -------------------- Input signals to the Tx MAC FIFO Interface---- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + + -------------------- Input signals to the Rx MAC FIFO Interface ---- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic + + ); +end ts_mac_core_only_top; + +architecture ts_mac_core_only_top_a of ts_mac_core_only_top is +component tsmac + port ( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic + ); +end component; + +begin + +U1_ts_mac_core_only_core : tsmac +port map ( + hclk => hclk, + txmac_clk => txmac_clk, + rxmac_clk => rxmac_clk, + reset_n => reset_n, + txmac_clk_en =>txmac_clk_en, + rxmac_clk_en =>rxmac_clk_en, + rxd => rxd, + rx_dv => rx_dv, + rx_er => rx_er, + col => col, + crs => crs, + + haddr => haddr, + hdatain => hdatain, + hcs_n => hcs_n, + hwrite_n => hwrite_n, + hread_n => hread_n, + + + tx_fifodata => tx_fifodata, + tx_fifoavail => tx_fifoavail, + tx_fifoeof => tx_fifoeof, + tx_fifoempty => tx_fifoempty, + tx_sndpaustim => tx_sndpaustim, + tx_sndpausreq => tx_sndpausreq, + tx_fifoctrl => tx_fifoctrl, + rx_fifo_full => rx_fifo_full, + ignore_pkt => ignore_pkt, + txd => txd, + tx_en => tx_en, + tx_er => tx_er, + hdataout => hdataout, + hdataout_en_n => hdataout_en_n, + hready_n => hready_n, + cpu_if_gbit_en => cpu_if_gbit_en, + + tx_macread => tx_macread, + tx_discfrm => tx_discfrm, + tx_staten => tx_staten , + tx_statvec => tx_statvec, + tx_done => tx_done, + rx_fifo_error => rx_fifo_error, + rx_stat_vector => rx_stat_vector, + rx_dbout => rx_dbout, + rx_write => rx_write, + rx_stat_en => rx_stat_en, + rx_eof => rx_eof, + rx_error => rx_error + ); + +end ts_mac_core_only_top_a; + diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_top.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_top.v new file mode 100644 index 0000000..c795296 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_top.v @@ -0,0 +1,544 @@ +// =========================================================================== +// Verilog module generated by IPexpress +// Filename: ts_mac_top.v +// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved. +// =========================================================================== +// + +`timescale 1 ns/ 1ns +module ts_mac_top ( + + // clock, clock enables and reset + gtx_clk, + tx_clk, + + txmac_clk_en, + rxmac_clk_en, + + sys_clk, + hclk, + rx_clk, + rxmac_clk, + txmac_clk, + reset_n, + + // Input signals to the GMII + rx_dv, + rx_er, + rxd, + col, + crs, + + // orcastra interface + pc_clk, + pc_datain, + pc_ready, + pc_dataout, + pc_error, + pc_retry, + pc_ack, + jtag_present, + jtag_parallel, + // JTAG Port + tdi, + tck, + tms, + tdo, + + // Output signals from the MII Management Interface + + // Output signals from the GMII + tx_en, + tx_er, + txd, + + // These are test points on the evaluation board + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpausreq, + tx_fifoctrl, + tx_fifo_full_ri, + tx_macread, + tx_discfrm, + tx_staten, + tx_done, + gbit_en, + phy_reset_n +); + +// ---------------- clock, clock enables and reset inputs ----------------- +output gtx_clk; // Gigabit Transmit clock +output rxmac_clk; // Rx_clock out to App I/F +output txmac_clk; // Tx_clock out to App I/F +input tx_clk; // Transmit clock + +input txmac_clk_en; +input rxmac_clk_en; + + +input sys_clk; // system clock +input rx_clk; // Receive clock +input reset_n; // Global reset + +// ----------------------- Input signals to the GMII ------------------- +input [7:0] rxd /* synthesis syn_useioff=0 */; // Receive data +input rx_dv/* synthesis syn_useioff=0 */; // Receive data valid +input rx_er/* synthesis syn_useioff=0 */; // Receive data error + +input col; // Collision detect +input crs; // Carrier Sense +// ------------------ Input/ouputs signals to the Orcastra Interface ---- +input pc_clk; +input pc_datain; +input pc_ready; +output pc_dataout; +output pc_error; +output pc_retry; +output pc_ack; +output jtag_present; +input jtag_parallel; +// ------------------ Input/output signals to the JTAG Port -------------- +input tdi; +input tck; +input tms; +output tdo; + +// -------------------- Output signals from the GMII ----------------------- +output [7:0] txd; // Transmit data +output tx_en; // Transmit Enable +output tx_er; // Transmit Error + +// These are test points on the evaluation board +output [7:0] tx_fifodata; +output tx_fifoavail; +output tx_fifoeof; +output tx_fifoempty; +output tx_sndpausreq; +output tx_fifoctrl; +output tx_fifo_full_ri; +output tx_macread; +output tx_discfrm; +output tx_staten; +output tx_done; +output gbit_en; + +// -------------------- Input signals to the CPU I/F ------------------- +input hclk; // Clock + +// -------------------- Input/Output signals from the MII I/F ---------------- + +// -------------------- Misc Output signals to be used with eval board only -- +output phy_reset_n; // used to reset PHY device +parameter pdevice_family = "ECP5UM"; +////////////////////////////////////////////////////////////////////////////// +// Internal wires related to fifo client interfaces and host bus interface +////////////////////////////////////////////////////////////////////////////// + +// -------------------- Input signals to the CPU I/F ------------------- +wire [7:0] haddr; // Address Bus +wire [7:0] hdatain; // Input data Bus +wire hcs_n; // Chip select +wire hwrite_n; // Register write +wire hread_n; // Register read + +// -------------------- Output signals from the CPU I/F ------------------- +wire [7:0] hdataout; // Output data Bus +wire hdataout_en_n; // Data Out Enable +wire hready_n; // Ready signal + +// ---------------- Input signals to the Tx MAC FIFO I/F --------------- +wire [7:0] tx_fifodata; // Data Input from FIFO +wire tx_fifoavail; // Data Available in FIFO +wire tx_fifoeof; // End of Frame +wire tx_fifoempty; // FIFO Empty +wire [15:0] tx_sndpaustim; // Pause frame parameter +wire tx_sndpausreq; // Transmit PAUSE frame +wire tx_fifoctrl; // Control frame or Not + +// ---------------- Input signals to the Rx MAC FIFO I/F --------------- +wire rx_fifo_full; // Receive FIFO Full +wire ignore_pkt; // Ignore the frame + +// ---------------- Output signals from the Tx MAC FIFO I/F --------------- +wire tx_macread; // Read FIFO +wire tx_discfrm; // Discard Frame +wire tx_staten; // Status Vector Valid +wire tx_done; // Transmit of Frame done +wire [30:0] tx_statvec; // Tx Status Vector + +// ---------------- Output signals from the Rx MAC FIFO I/F --------------- +wire rx_fifo_error; // FIFO full detected +wire [31:0] rx_stat_vector; // Rx Status Vector +wire [7:0] rx_dbout; // Data Output to FIFO +wire rx_write; // Write FIFO +wire rx_stat_en; // Status Vector Valid +wire rx_eof; // Entire frame written +wire rx_error; // Erroneous frame + +wire rx_write_e; // Write FIFO conditioned with rx enable +wire tx_macread_e; // Read FIFO conditioned with tx enable +////////////////////////////////////////////////////////////////////////////// +// internal wires related to register interface, and orcastra interface +////////////////////////////////////////////////////////////////////////////// + +wire pkt_add_swap_ri; +wire pkt_loop_enb_ri; +wire pkt_loop_clksel_ri; +wire phy_reset_n_ri; +wire [15:0] tx_sndpaustim_ri; +wire tx_sndpausreq_ri; +wire tx_fifoctrl_ri; +wire rx_fifo_full_ri; +wire tx_fifo_empty_ri; +wire ignore_next_pkt_ri; +wire [8:0] aff_thrhd; +wire [8:0] afe_thrhd; + +wire [7:0] us_rdata; +wire us_ack; +wire [7:0] us_wdata; +wire us_rdy; +wire us_wr; +wire [17:0] us_addr; +wire [1:0] us_size; + +wire rxc_clk; +wire txc_clk; + +// from MAC to status reg bits in reg_intf +wire rx_error_ri; +wire rx_fifo_error_ri; +wire tx_disfrm_ri; +wire tx_fifo_full_ri; + +wire gbit_en_wire /*synthesis syn_keep=1 */; // 1G enable - MAC clock select + +// ------------------ signals related to the Orcastra Interface ------- +wire pc_clk_jtag; +wire pc_clk_mux /*synthesis syn_keep=1 */; +wire pc_datain_jtag; +wire pc_datain_mux; +wire pc_ready_jtag; +wire pc_ready_mux; + +assign phy_reset_n = phy_reset_n_ri; // this output is used only when user is using an eval board. +assign gbit_en = gbit_en_wire; + + +////////////////////////////////////////////////////////////////////////////// +// Internal wires related to GMII I/O +reg [7:0] rxd_pos; +reg [3:0] rxd_neg; +reg rx_dv_pos; +reg rx_dv_neg; +reg rx_er_pos; +reg rx_er_neg; +wire [7:0] txd_pos; +wire [3:0] txd_neg; +wire tx_en_d; +wire tx_er_d; + +reg [7:4] txd_pos_x; +reg tx_en_d_x; +reg tx_er_d_x; +wire [3:0] txd_int; +reg [3:0] txd_10_100; +reg tx_en_10_100; +reg tx_er_10_100; +reg [7:0] txd_1g; +reg tx_en_1g; +reg tx_er_1g; + +// Internal wires related to clock synthesis +reg tx_clk_div2; // tx_clk divided by 2 +reg rx_clk_div2; // rx_clk divided by 2 +wire txmac_clk_c /*synthesis syn_keep=1 */; // Internal txmac_clk +wire rxmac_clk_c /*synthesis syn_keep=1 */; // Internal rxmac_clk +wire gtx_clk_src; // for 1GBE +wire txmac_clk_1g; // +wire txmac_ref /*synthesis syn_keep=1 */; + + +////////////////////////////////////////////////////////////////////////////// +// Instantiate PLLs, DCS Muxes, and other buffers + + assign rx_write_e = rx_write & rxmac_clk_en; + assign tx_macread_e = tx_macread & txmac_clk_en; + +// SGMII_TSMAC or GBE_MAC +assign rxmac_clk_c = rx_clk; + +// This mux is added to allow a selection of the txmac_clk source +assign txmac_clk_c = pkt_loop_clksel_ri ? rx_clk : sys_clk; +assign gtx_clk_src = txmac_clk_c; +assign rxmac_clk = rxmac_clk_c; +assign txmac_clk = txmac_clk_c; + + +// GMII inputs RXD[3:0], RX_DV RX_ER are sampled on +// both clock edges of rxmac_clk_c +// These flip-flops must be placed close to the associated I/O pins. +// They are given a COMP name here and located in a specific component +// in the preference file. + +always @(posedge rxmac_clk_c or negedge reset_n) begin + if (~reset_n) begin + rx_dv_pos <= 1'b0; + rx_er_pos <= 1'b0; + rxd_pos[7:0] <= 8'h00; + end + else begin + rx_dv_pos <= rx_dv; + rx_er_pos <= rx_er; + rxd_pos[7:0] <= rxd[7:0]; + end +end + +always @(negedge rxmac_clk_c or negedge reset_n) begin + if (~reset_n) begin + rx_dv_neg <= 1'b0; + rx_er_neg <= 1'b0; + rxd_neg[3:0] <= 4'h0; + end + else begin + rx_dv_neg <= rx_dv; + rx_er_neg <= rx_er; + rxd_neg[3:0] <= rxd[3:0]; + end +end + +// GBE_MAC OR SGMII_TSMAC +always @(posedge txmac_clk_c or negedge reset_n) begin + if (~reset_n) begin + txd_1g <= 8'h00; + tx_en_1g <= 1'b0; + tx_er_1g <= 1'b0; + end + else begin + txd_1g <= txd_pos; + tx_en_1g <= tx_en_d; + tx_er_1g <= tx_er_d; + end +end + +assign txd = txd_1g; +assign tx_en = tx_en_1g; +assign tx_er = tx_er_1g; + +//Note: User may need to invert clock to adjust timing +assign gtx_clk = gtx_clk_src; + +assign pc_datain_mux = (jtag_parallel) ? pc_datain_jtag : pc_datain; +assign pc_ready_mux = (jtag_parallel) ? pc_ready_jtag : pc_ready; +assign pc_clk_mux = (jtag_parallel) ? pc_clk_jtag : pc_clk; + +//////////////////////////////////////////////////////////////////////////// +// Instantiate modules +ts_mac_core_only_top U1_ts_mac_core ( + // clock and reset + .hclk(hclk), + .txmac_clk(txmac_clk_c), + .rxmac_clk(rxmac_clk_c), + .reset_n(reset_n), + .txmac_clk_en(txmac_clk_en), + .rxmac_clk_en(rxmac_clk_en), + + // Input signals to the GMII + .rxd(rxd_pos), + .rx_dv(rx_dv_pos), + .rx_er(rx_er_pos), + .col(col), + .crs(crs), + + // Input signals to the CPU Interface + .haddr(haddr), + .hdatain(hdatain), + .hcs_n(hcs_n), + .hwrite_n(hwrite_n), + .hread_n(hread_n), + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + .tx_fifodata(tx_fifodata), + .tx_fifoavail(tx_fifoavail), + .tx_fifoeof(tx_fifoeof), + .tx_fifoempty(tx_fifoempty), + .tx_sndpaustim(tx_sndpaustim), + .tx_sndpausreq(tx_sndpausreq), + .tx_fifoctrl(tx_fifoctrl), + + // Input signals to the Rx MAC FIFO Interface + .rx_fifo_full(rx_fifo_full), + .ignore_pkt(ignore_pkt), + + // Output signals from the GMII + .txd(txd_pos), + .tx_en(tx_en_d), + .tx_er(tx_er_d), + + // Output signals from the CPU Interface + .hdataout(hdataout), + .hdataout_en_n(hdataout_en_n), + .hready_n(hready_n), + .cpu_if_gbit_en(gbit_en_wire), + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + .tx_macread(tx_macread), + .tx_discfrm(tx_discfrm), + .tx_staten(tx_staten), + .tx_statvec(tx_statvec), + .tx_done(tx_done), + + // Output signals from the Rx MAC FIFO Interface + .rx_fifo_error(rx_fifo_error), + .rx_stat_vector(rx_stat_vector), + .rx_dbout(rx_dbout), + .rx_write(rx_write), + .rx_stat_en(rx_stat_en), + .rx_eof(rx_eof), + .rx_error(rx_error) +); + + +tst_logic #(.pdevice_family(pdevice_family)) + u1_tst_logic ( + // ------- + // inputs + // ------- + // Clock and Reset + .reset_n (reset_n), + .txmac_clk (txmac_clk_c), + .rxmac_clk (rxmac_clk_c), + // Clock enables + .txmac_clk_en (txmac_clk_en), + .rxmac_clk_en (rxmac_clk_en), + // from tsmac core + .rx_write (rx_write_e), + .tx_macread (tx_macread_e), + .rx_dbout (rx_dbout), + .rx_eof (rx_eof), + .rx_error (rx_error), + .rx_fifo_error (rx_fifo_error), + .tx_done (tx_done), + .tx_disfrm (tx_discfrm), + // from reg_intf + .pkt_add_swap_ri (pkt_add_swap_ri), + .pkt_loop_enb_ri (pkt_loop_enb_ri), + .tx_sndpaustim_ri (tx_sndpaustim_ri), + .tx_sndpausreq_ri (tx_sndpausreq_ri), + .tx_fifoctrl_ri (tx_fifoctrl_ri), + .rx_fifo_full_ri (rx_fifo_full_ri), + .tx_fifo_empty_ri (tx_fifo_empty_ri), + .ignore_next_pkt_ri (ignore_next_pkt_ri), + .aff_thrhd (aff_thrhd[8:0]), + .afe_thrhd (afe_thrhd[8:0]), + // ------- + // outputs + // ------- + // to tsmac core + .tx_fifodata (tx_fifodata), + .tx_fifoeof (tx_fifoeof), + .tx_fifoavail (tx_fifoavail), + .tx_fifoempty (tx_fifoempty), + .tx_sndpaustim (tx_sndpaustim), + .tx_sndpausreq (tx_sndpausreq), + .tx_fifoctrl (tx_fifoctrl), + .rx_fifo_full (rx_fifo_full), + .ignore_next_pkt (ignore_pkt), + // to reg_intf + .rxc_clk (rxc_clk), + .txc_clk (txc_clk), + .rx_error_ri (rx_error_ri), + .rx_fifo_error_ri (rx_fifo_error_ri), + .tx_disfrm_ri (tx_disfrm_ri), + .tx_fifo_full_ri (tx_fifo_full_ri) +); + +orcastra orcastra ( + .reset_n (reset_n), + .hclk (hclk), + .pc_clk (pc_clk_mux), + .pc_datain (pc_datain_mux), + .pc_ready (pc_ready_mux), + .hdataout (hdataout), + .hready_n (hready_n), + .us_rdata (us_rdata), + .us_ack (us_ack), + .us_wdata (us_wdata), + .us_rdy (us_rdy), + .us_wr (us_wr), + .us_addr (us_addr), + .us_size (us_size), + .hdatain (hdatain), + .hcs_n (hcs_n), + .hread_n (hread_n), + .hwrite_n (hwrite_n), + .haddr (haddr), + .pc_dataout (pc_dataout), + .pc_error (pc_error), + .pc_retry (pc_retry), + .pc_ack (pc_ack) +); + +reg_intf reg_intf ( + .reset_n (reset_n), + .hclk (hclk), + .rxc_clk (rxc_clk), + .txc_clk (txc_clk), + .us_wdata (us_wdata), + .us_rdy (us_rdy), + .us_wr (us_wr), + .us_addr (us_addr), + .us_size (us_size), + .rx_error_ri (rx_error_ri), + .rx_fifo_error_ri (rx_fifo_error_ri), + .tx_disfrm_ri (tx_disfrm_ri), + .tx_fifo_full_ri (tx_fifo_full_ri), + .rx_stat_vec (rx_stat_vector[31:0]), + .rx_stat_en (rx_stat_en), + .tx_stat_vec (tx_statvec[30:0]), + .tx_stat_en (tx_staten), + .pkt_add_swap_ri (pkt_add_swap_ri), + .pkt_loop_enb_ri (pkt_loop_enb_ri), + .pkt_loop_clksel_ri (pkt_loop_clksel_ri), + .phy_reset_n_ri (phy_reset_n_ri), + .tx_sndpaustim_ri (tx_sndpaustim_ri), + .tx_sndpausreq_ri (tx_sndpausreq_ri), + .tx_fifoctrl_ri (tx_fifoctrl_ri), + .rx_fifo_full_ri (rx_fifo_full_ri), + .tx_fifo_empty_ri (tx_fifo_empty_ri), + .ignore_next_pkt_ri (ignore_next_pkt_ri), + .aff_thrhd (aff_thrhd[8:0]), + .afe_thrhd (afe_thrhd[8:0]), + .us_err (), //no_connect + .us_irq (), //no_connect + .us_ack (us_ack), + .us_rdata (us_rdata) +); + + + +JTAG_ECP5UM JTAG_ECP5UM + ( + .grst_ni (reset_n), + .tck (tck), + .tms (tms), + .tdi (tdi), + .tdo (tdo), + .PC_Clk (pc_clk_jtag), + .PC_Data_In (pc_datain_jtag), + .PC_Ready (pc_ready_jtag), + .PC_Reset (), + .Cnt (), + .PC_Data_Out (pc_dataout), + .PC_Ack (pc_ack), + .PC_Error (pc_error) +); + + +endmodule diff --git a/gbe/cores/sgmii/tsmac/tsmac.fdc b/gbe/cores/sgmii/tsmac/tsmac.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/tsmac.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/gbe/cores/sgmii/tsmac/tsmac.lpc b/gbe/cores/sgmii/tsmac/tsmac.lpc new file mode 100644 index 0000000..5c8ae17 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/tsmac.lpc @@ -0,0 +1,37 @@ +[Device] +Family=sa5p00m +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=Tri-Speed Ethernet MAC +CoreRevision=4.1 +ModuleName=tsmac +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/29/2019 +Time=13:44:50 + +[Parameters] +MIIM=No +MODE=SGMII easy connect +MODS_TOOL=1 +ALDC_TOOL=0 +MULT_WB=NO +LOOPBACK=NO +STAT_REGS=NO +CORE_SYNP=1 + +[Files] +Synthesis= +Simulation= +Logical= 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zb&HV=nZAYWjwZIZk=;E=EkSl4S+^9~HyGL8LG~?HD)!3pFqy_)IUXg`*el25Wg2_s zc%qi;Vy_%OBGcF_$J1pRd*%4*^^3i7Y?5j0mE)IH?ufl|{Dzi_y>cwi1$xI`IbI>t z*ek~$c{q)|a=cL#d*yhmh3#Wx?=(>BkZl*ONA})$()3P7wo9Q>kewZeruPP9=b5OD z$UYW_ruQevE-+D>kj;zL^tK}Vw6x90tCH*YDRQpYbKMr?+$`FPoZHN7+mQ1>kopWc gQ&nm^a%PJ@N6w3)FOXGh<#Y$K&uOWh$i8CwKazk$z5oCK literal 0 HcmV?d00001 diff --git a/gbe/cores/sgmii/tsmac/tsmac.v b/gbe/cores/sgmii/tsmac/tsmac.v new file mode 100644 index 0000000..569c933 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/tsmac.v @@ -0,0 +1,212 @@ +//============================================================================= +// Verilog module generated by IPExpress +// Filename: USERNAME.v +// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. +//============================================================================= + +/* WARNING - Changes to this file should be performed by re-running IPexpress +or modifying the .LPC file and regenerating the core. Other changes may lead +to inconsistent simulation and/or implemenation results */ +`timescale 1 ns/ 1ns +module tsmac ( + // clock and reset + hclk, + txmac_clk, + rxmac_clk, + reset_n, + txmac_clk_en, + rxmac_clk_en, + + // Input signals to the GMII + rxd, + rx_dv, + rx_er, + col, + crs, + // Input signals to the CPU Interface + haddr, + hdatain, + hcs_n, + hwrite_n, + hread_n, + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + + // Input signals to the Rx MAC FIFO Interface + rx_fifo_full, + ignore_pkt, + + // Output signals from the GMII + txd, + tx_en, + tx_er, + + // Output signals from the CPU Interface + hdataout, + hdataout_en_n, + hready_n, + cpu_if_gbit_en, + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + tx_macread, + tx_discfrm, + tx_staten, + tx_statvec, + tx_done, + + // Output signals from the Rx MAC FIFO Interface + rx_fifo_error, + rx_stat_vector, + rx_dbout, + rx_write, + rx_stat_en, + rx_eof, + rx_error + ); + + // ------------------------- clock and reset inputs --------------------- + input hclk; // clock to the CPU I/F + input txmac_clk; // clock to the Tx MAC + input rxmac_clk; // clock to the RX MAC + input reset_n; // Global reset + input txmac_clk_en; // clock enable to the Tx MAC + input rxmac_clk_en; // clock enable to the RX MAC + + // ----------------------- Input signals to the GMII ------------------- + input [7:0] rxd; // Receive data + input rx_dv; // Receive data valid + input rx_er; // Receive data error + input col; // Collision detect + input crs; // Carrier Sense + // -------------------- Input signals to the CPU I/F ------------------- + input [7:0] haddr; // Address Bus + input [7:0] hdatain; // Input data Bus + input hcs_n; // Chip select + input hwrite_n; // Register write + input hread_n; // Register read + + // -------------------- Input signals to the MII I/F ------------------- + + + // ---------------- Input signals to the Tx MAC FIFO I/F --------------- + input [7:0] tx_fifodata; // Data Input from FIFO + input tx_fifoavail; // Data Available in FIFO + input tx_fifoeof; // End of Frame + input tx_fifoempty; // FIFO Empty + input [15:0] tx_sndpaustim; // Pause frame parameter + input tx_sndpausreq; // Transmit PAUSE frame + input tx_fifoctrl; // Control frame or Not + + // ---------------- Input signals to the Rx MAC FIFO I/F --------------- + input rx_fifo_full; // Receive FIFO Full + input ignore_pkt; // Ignore the frame + + // -------------------- Output signals from the GMII ----------------------- + output [7:0] txd; // Transmit data + output tx_en; // Transmit Enable + output tx_er; // Transmit Error + + // -------------------- Output signals from the CPU I/F ------------------- + output [7:0] hdataout; // Output data Bus + output hdataout_en_n; // Data Out Enable + output hready_n; // Ready signal + output cpu_if_gbit_en; // Gig or 10/100 mode + + // -------------------- Output signals from the MII I/F ------------------- + + + // ---------------- Output signals from the Tx MAC FIFO I/F --------------- + output tx_macread; // Read FIFO + output tx_discfrm; // Discard Frame + output tx_staten; // Status Vector Valid + output tx_done; // Transmit of Frame done + output [30:0] tx_statvec; // Tx Status Vector + + // ---------------- Output signals from the Rx MAC FIFO I/F --------------- + output rx_fifo_error; // FIFO full detected + output [31:0] rx_stat_vector; // Rx Status Vector + output [7:0] rx_dbout; // Data Output to FIFO + output rx_write; // Write FIFO + output rx_stat_en; // Status Vector Valid + output rx_eof; // Entire frame written + output rx_error; // Erroneous frame + + tsmac_core U1_LSC_ts_mac_core ( + + // clock and reset + .hclk(hclk), + .txmac_clk(txmac_clk), + .rxmac_clk(rxmac_clk), + .reset_n(reset_n), + .txmac_clk_en(txmac_clk_en), + .rxmac_clk_en(rxmac_clk_en), + + // Input signals to the GMII + .rxd(rxd), + .rx_dv(rx_dv), + .rx_er(rx_er), + .col(col), + .crs(crs), + // Input signals to the CPU Interface + .haddr(haddr), + .hdatain(hdatain), + .hcs_n(hcs_n), + .hwrite_n(hwrite_n), + .hread_n(hread_n), + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + .tx_fifodata(tx_fifodata), + .tx_fifoavail(tx_fifoavail), + .tx_fifoeof(tx_fifoeof), + .tx_fifoempty(tx_fifoempty), + .tx_sndpaustim(tx_sndpaustim), + .tx_sndpausreq(tx_sndpausreq), + .tx_fifoctrl(tx_fifoctrl), + + // Input signals to the Rx MAC FIFO Interface + .rx_fifo_full(rx_fifo_full), + .ignore_pkt(ignore_pkt), + + // Output signals from the GMII + .txd(txd), + .tx_en(tx_en), + .tx_er(tx_er), + + // Output signals from the CPU Interface + .hdataout(hdataout), + .hdataout_en_n(hdataout_en_n), + .hready_n(hready_n), + .cpu_if_gbit_en(cpu_if_gbit_en), + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + .tx_macread(tx_macread), + .tx_discfrm(tx_discfrm), + .tx_staten(tx_staten), + .tx_statvec(tx_statvec), + .tx_done(tx_done), + + // Output signals from the Rx MAC FIFO Interface + .rx_fifo_error(rx_fifo_error), + .rx_stat_vector(rx_stat_vector), + .rx_dbout(rx_dbout), + .rx_write(rx_write), + .rx_stat_en(rx_stat_en), + .rx_eof(rx_eof), + .rx_error(rx_error) + ); +endmodule diff --git a/gbe/cores/sgmii/tsmac/tsmac_bb.v b/gbe/cores/sgmii/tsmac/tsmac_bb.v new file mode 100644 index 0000000..4cee903 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/tsmac_bb.v @@ -0,0 +1,145 @@ +//============================================================================= +// Verilog module generated by IPExpress +// Filename: USERNAME_bb.v +// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. +//============================================================================= + +/* WARNING - Changes to this file should be performed by re-running IPexpress +or modifying the .LPC file and regenerating the core. Other changes may lead +to inconsistent simulation and/or implemenation results */ +module tsmac ( + // clock and reset + hclk, + txmac_clk, + rxmac_clk, + reset_n, + txmac_clk_en, + rxmac_clk_en, + + // Input signals to the GMII + rxd, + rx_dv, + rx_er, + col, + crs, + + // Input signals to the CPU Interface + haddr, + hdatain, + hcs_n, + hwrite_n, + hread_n, + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + + // Input signals to the Rx MAC FIFO Interface + rx_fifo_full, + ignore_pkt, + + // Output signals from the GMII + txd, + tx_en, + tx_er, + + // Output signals from the CPU Interface + hdataout, + hdataout_en_n, + hready_n, + cpu_if_gbit_en, + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + tx_macread, + tx_discfrm, + tx_staten, + tx_statvec, + tx_done, + + // Output signals from the Rx MAC FIFO Interface + rx_fifo_error, + rx_stat_vector, + rx_dbout, + rx_write, + rx_stat_en, + rx_eof, + rx_error + ); + + // ------------------------- clock and reset inputs --------------------- + input hclk; // clock to the CPU I/F + input txmac_clk; // clock to the Tx MAC + input rxmac_clk; // clock to the RX MAC + input reset_n; // Global reset + input txmac_clk_en; // clock enable to the Tx MAC + input rxmac_clk_en; // clock enable to the RX MAC + + // ----------------------- Input signals to the GMII ------------------- + input [7:0] rxd; // Receive data + input rx_dv; // Receive data valid + input rx_er; // Receive data error + input col; // Collision detect + input crs; // Carrier Sense + // -------------------- Input signals to the CPU I/F ------------------- + input [7:0] haddr; // Address Bus + input [7:0] hdatain; // Input data Bus + input hcs_n; // Chip select + input hwrite_n; // Register write + input hread_n; // Register read + + // -------------------- Input signals to the MII I/F ------------------- + + + // ---------------- Input signals to the Tx MAC FIFO I/F --------------- + input [7:0] tx_fifodata; // Data Input from FIFO + input tx_fifoavail; // Data Available in FIFO + input tx_fifoeof; // End of Frame + input tx_fifoempty; // FIFO Empty + input [15:0] tx_sndpaustim; // Pause frame parameter + input tx_sndpausreq; // Transmit PAUSE frame + input tx_fifoctrl; // Control frame or Not + + // ---------------- Input signals to the Rx MAC FIFO I/F --------------- + input rx_fifo_full; // Receive FIFO Full + input ignore_pkt; // Ignore the frame + + // -------------------- Output signals from the GMII ----------------------- + output [7:0] txd; // Transmit data + output tx_en; // Transmit Enable + output tx_er; // Transmit Error + + // -------------------- Output signals from the CPU I/F ------------------- + output [7:0] hdataout; // Output data Bus + output hdataout_en_n; // Data Out Enable + output hready_n; // Ready signal + output cpu_if_gbit_en; // Gig or 10/100 mode + + // -------------------- Output signals from the MII I/F ------------------- + + + // ---------------- Output signals from the Tx MAC FIFO I/F --------------- + output tx_macread; // Read FIFO + output tx_discfrm; // Discard Frame + output tx_staten; // Status Vector Valid + output tx_done; // Transmit of Frame done + output [30:0] tx_statvec; // Tx Status Vector + + // ---------------- Output signals from the Rx MAC FIFO I/F --------------- + output rx_fifo_error; // FIFO full detected + output [31:0] rx_stat_vector; // Rx Status Vector + output [7:0] rx_dbout; // Data Output to FIFO + output rx_write; // Write FIFO + output rx_stat_en; // Status Vector Valid + output rx_eof; // Entire frame written + output rx_error; // Erroneous frame + +endmodule diff --git a/gbe/cores/sgmii/tsmac/tsmac_beh.v b/gbe/cores/sgmii/tsmac/tsmac_beh.v new file mode 100644 index 0000000..c5f1d57 --- /dev/null +++ b/gbe/cores/sgmii/tsmac/tsmac_beh.v @@ -0,0 +1,6022 @@ +//============================================================================= +// Verilog module generated by IPExpress +// Filename: USERNAME.v +// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. +//============================================================================= + +/* WARNING - Changes to this file should be performed by re-running IPexpress +or modifying the .LPC file and regenerating the core. Other changes may lead +to inconsistent simulation and/or implemenation results */ +`timescale 1 ns/ 1ns +module tsmac ( + // clock and reset + hclk, + txmac_clk, + rxmac_clk, + reset_n, + txmac_clk_en, + rxmac_clk_en, + + // Input signals to the GMII + rxd, + rx_dv, + rx_er, + col, + crs, + // Input signals to the CPU Interface + haddr, + hdatain, + hcs_n, + hwrite_n, + hread_n, + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + + // Input signals to the Rx MAC FIFO Interface + rx_fifo_full, + ignore_pkt, + + // Output signals from the GMII + txd, + tx_en, + tx_er, + + // Output signals from the CPU Interface + hdataout, + hdataout_en_n, + hready_n, + cpu_if_gbit_en, + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + tx_macread, + tx_discfrm, + tx_staten, + tx_statvec, + tx_done, + + // Output signals from the Rx MAC FIFO Interface + rx_fifo_error, + rx_stat_vector, + rx_dbout, + rx_write, + rx_stat_en, + rx_eof, + rx_error + ); + + // ------------------------- clock and reset inputs --------------------- + input hclk; // clock to the CPU I/F + input txmac_clk; // clock to the Tx MAC + input rxmac_clk; // clock to the RX MAC + input reset_n; // Global reset + input txmac_clk_en; // clock enable to the Tx MAC + input rxmac_clk_en; // clock enable to the RX MAC + + // ----------------------- Input signals to the GMII ------------------- + input [7:0] rxd; // Receive data + input rx_dv; // Receive data valid + input rx_er; // Receive data error + input col; // Collision detect + input crs; // Carrier Sense + // -------------------- Input signals to the CPU I/F ------------------- + input [7:0] haddr; // Address Bus + input [7:0] hdatain; // Input data Bus + input hcs_n; // Chip select + input hwrite_n; // Register write + input hread_n; // Register read + + // -------------------- Input signals to the MII I/F ------------------- + + + // ---------------- Input signals to the Tx MAC FIFO I/F --------------- + input [7:0] tx_fifodata; // Data Input from FIFO + input tx_fifoavail; // Data Available in FIFO + input tx_fifoeof; // End of Frame + input tx_fifoempty; // FIFO Empty + input [15:0] tx_sndpaustim; // Pause frame parameter + input tx_sndpausreq; // Transmit PAUSE frame + input tx_fifoctrl; // Control frame or Not + + // ---------------- Input signals to the Rx MAC FIFO I/F --------------- + input rx_fifo_full; // Receive FIFO Full + input ignore_pkt; // Ignore the frame + + // -------------------- Output signals from the GMII ----------------------- + output [7:0] txd; // Transmit data + output tx_en; // Transmit Enable + output tx_er; // Transmit Error + + // -------------------- Output signals from the CPU I/F ------------------- + output [7:0] hdataout; // Output data Bus + output hdataout_en_n; // Data Out Enable + output hready_n; // Ready signal + output cpu_if_gbit_en; // Gig or 10/100 mode + + // -------------------- Output signals from the MII I/F ------------------- + + + // ---------------- Output signals from the Tx MAC FIFO I/F --------------- + output tx_macread; // Read FIFO + output tx_discfrm; // Discard Frame + output tx_staten; // Status Vector Valid + output tx_done; // Transmit of Frame done + output [30:0] tx_statvec; // Tx Status Vector + + // ---------------- Output signals from the Rx MAC FIFO I/F --------------- + output rx_fifo_error; // FIFO full detected + output [31:0] rx_stat_vector; // Rx Status Vector + output [7:0] rx_dbout; // Data Output to FIFO + output rx_write; // Write FIFO + output rx_stat_en; // Status Vector Valid + output rx_eof; // Entire frame written + output rx_error; // Erroneous frame + + tsmac_core U1_LSC_ts_mac_core ( + + // clock and reset + .hclk(hclk), + .txmac_clk(txmac_clk), + .rxmac_clk(rxmac_clk), + .reset_n(reset_n), + .txmac_clk_en(txmac_clk_en), + .rxmac_clk_en(rxmac_clk_en), + + // Input signals to the GMII + .rxd(rxd), + .rx_dv(rx_dv), + .rx_er(rx_er), + .col(col), + .crs(crs), + // Input signals to the CPU Interface + .haddr(haddr), + .hdatain(hdatain), + .hcs_n(hcs_n), + .hwrite_n(hwrite_n), + .hread_n(hread_n), + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + .tx_fifodata(tx_fifodata), + .tx_fifoavail(tx_fifoavail), + .tx_fifoeof(tx_fifoeof), + .tx_fifoempty(tx_fifoempty), + .tx_sndpaustim(tx_sndpaustim), + .tx_sndpausreq(tx_sndpausreq), + .tx_fifoctrl(tx_fifoctrl), + + // Input signals to the Rx MAC FIFO Interface + .rx_fifo_full(rx_fifo_full), + .ignore_pkt(ignore_pkt), + + // Output signals from the GMII + .txd(txd), + .tx_en(tx_en), + .tx_er(tx_er), + + // Output signals from the CPU Interface + .hdataout(hdataout), + .hdataout_en_n(hdataout_en_n), + .hready_n(hready_n), + .cpu_if_gbit_en(cpu_if_gbit_en), + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + .tx_macread(tx_macread), + .tx_discfrm(tx_discfrm), + .tx_staten(tx_staten), + .tx_statvec(tx_statvec), + .tx_done(tx_done), + + // Output signals from the Rx MAC FIFO Interface + .rx_fifo_error(rx_fifo_error), + .rx_stat_vector(rx_stat_vector), + .rx_dbout(rx_dbout), + .rx_write(rx_write), + .rx_stat_en(rx_stat_en), + .rx_eof(rx_eof), + .rx_error(rx_error) + ); +endmodule +// ts_mac_core_beh.v generated by Lattice IP Model Creator version 1 +// created on Fri, May 23, 2014 10:35:39 AM +// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved +// obfuscator_exe version 1.mar0807 + +// top + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +`timescale 1 ns / 100 ps +module kdd67f2 ( + rxmac_clk, + reset_n, + rxmac_clk_en, + + + mrf282b, + tj9415c, + + + lfa0ae7, + aa573e, + + + aa2b9f0, + yk5cf81, + yxe7c08, + ec3e045 +); +parameter mef0229 = 8; +input rxmac_clk; +input reset_n; +input rxmac_clk_en; +input mrf282b; +input lfa0ae7; +input aa573e; +input [mef0229-1:0] tj9415c; +output yk5cf81; +output yxe7c08; +output ec3e045; +output [mef0229-1:0] aa2b9f0; +reg yk5cf81; +reg yxe7c08; +reg ec3e045; +reg [mef0229-1:0] aa2b9f0; +reg gd26f72; +parameter tj37b95 = 2; +parameter vkbdcae = 2'b01; +parameter tuee573 = 2'b10; +parameter qg72b9a = 0; +parameter yz95cd0 = 1; +parameter uxae684 = 8'hd5; +parameter zk73424 = 8'h55; +wire wl9a123; +wire hod091c; +reg ph848e2; +reg uk24717; +reg an238b9; +reg [tj37b95-1:0] uve2e6f; +reg [2:0] an1737d; +reg [tj37b95-1:0] vvcdf61; +reg wj6fb0f; +reg [mef0229 - 1 : 0] xjec3e9; +reg dz61f4f; +reg oufa7e; +reg me7d3f0; +reg xje9f80; +reg zx4fc06; +reg zx7e036; +reg ykf01b7; +reg kf80db8; +reg [tj37b95 - 1 : 0] wl36e2e; +reg [2 : 0] twb7174; +reg [tj37b95 - 1 : 0] zkc5d1b; +reg [2047:0] wy2e8db; +wire [12:0] vv746d9; + +localparam ksa36ce = 13,tw1b670 = 32'hfdffc68b; +localparam [31:0] icdb382 = tw1b670; +localparam mece084 = tw1b670 & 4'hf; +localparam [11:0] ou8210c = 'h7ff; +wire [(1 << mece084) -1:0] db84308; +reg [ksa36ce-1:0] dbc230; +reg [mece084-1:0] kf8c37 [0:1]; +reg [mece084-1:0] hq30de9; +reg hq86f4b; +integer hd37a5a; +integer dobd2d6; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin aa2b9f0 <= 0; end else if (rxmac_clk_en) begin if (wj6fb0f) begin aa2b9f0 <= xjec3e9; end end +end + + + + +assign wl9a123 = xjec3e9[7:0] == uxae684; +assign hod091c = xjec3e9[7:0] == zk73424; + + + + + + +always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin vvcdf61 <= vkbdcae; an1737d <= 3'b0; yk5cf81 <= 1'b0; ec3e045 <= 1'b0; gd26f72 <= 1'b0; yxe7c08 <= 1'b0; end else if (rxmac_clk_en) begin vvcdf61 <= wl36e2e; gd26f72 <= zx7e036; yxe7c08 <= me7d3f0; yk5cf81 <= 1'b0; + an1737d <= kf80db8 ? 3'h1 : (|twb7174) ? (twb7174+3'h1) : zkc5d1b[qg72b9a] ? 3'h0 : twb7174; + if (ykf01b7) begin ec3e045 <= 1'b1; end else if (oufa7e) begin ec3e045 <= 1'b0; end else if (dz61f4f) begin ec3e045 <= 1'b0; end end +end + + +always @(zkc5d1b or dz61f4f or zx4fc06 or xje9f80 or twb7174) begin case(zkc5d1b) vkbdcae : begin if (dz61f4f && xje9f80) begin uve2e6f = vkbdcae; ph848e2 = 1'b1; uk24717 = 1'b0; an238b9 = 1'b0; end else if (dz61f4f && zx4fc06) begin uve2e6f = tuee573; ph848e2 = 1'b0; uk24717 = 1'b0; an238b9 = 1'b1; end else if (dz61f4f && !xje9f80 && !zx4fc06) begin uve2e6f = vkbdcae; ph848e2 = 1'b0; uk24717 = 1'b1; an238b9 = 1'b0; end + else begin uve2e6f = vkbdcae; ph848e2 = 1'b0; uk24717 = 1'b0; an238b9 = 1'b0; end end + tuee573 : begin if (xje9f80) begin uve2e6f = vkbdcae; ph848e2 = 1'b1; uk24717 = 1'b0; an238b9 = 1'b0; end else if (~|twb7174 & ~zx4fc06) begin uve2e6f = vkbdcae; ph848e2 = 1'b0; uk24717 = 1'b1; an238b9 = 1'b0; end else begin uve2e6f = tuee573; ph848e2 = 1'b0; uk24717 = 1'b0; an238b9 = 1'b0; end + end + default : begin uve2e6f = vkbdcae; ph848e2 = 1'b0; uk24717 = 1'b0; an238b9 = 1'b0; end endcase +end + +always@* begin wj6fb0f<=vv746d9[0];xjec3e9<={tj9415c>>1,vv746d9[1]};dz61f4f<=vv746d9[2];oufa7e<=vv746d9[3];me7d3f0<=vv746d9[4];xje9f80<=vv746d9[5];zx4fc06<=vv746d9[6];zx7e036<=vv746d9[7];ykf01b7<=vv746d9[8];kf80db8<=vv746d9[9];wl36e2e<={uve2e6f>>1,vv746d9[10]};twb7174<={an1737d>>1,vv746d9[11]};zkc5d1b<={vvcdf61>>1,vv746d9[12]};end +always@* begin wy2e8db[2047]<=tj9415c[0];wy2e8db[2046]<=lfa0ae7;wy2e8db[2044]<=aa573e;wy2e8db[2040]<=gd26f72;wy2e8db[2032]<=wl9a123;wy2e8db[2017]<=hod091c;wy2e8db[1987]<=ph848e2;wy2e8db[1926]<=uk24717;wy2e8db[1805]<=an238b9;wy2e8db[1562]<=uve2e6f[0];wy2e8db[1076]<=an1737d[0];wy2e8db[1023]<=mrf282b;wy2e8db[104]<=vvcdf61[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};godee70<=vv746d9[1];oufa7e<=vv746d9[2];ksb9c0d<=vv746d9[3];wj70349<={su43606>>1,vv746d9[4]};sjd267<={tw1b031>>1,vv746d9[5]};ui499e3<={ldd818a>>1,vv746d9[6]};ay678c9<={byc0c57>>1,vv746d9[7]};zxe324c<={ph62bb>>1,vv746d9[8]};czc9337<={uk315df>>1,vv746d9[9]};me4cde1<={ep8aef8>>1,vv746d9[10]};fp3784b<={lq577c4>>1,vv746d9[11]};vie12f0<={uxbbe22>>1,vv746d9[12]};jr9783<=vv746d9[13];al4bc1e<=vv746d9[14];gb5e0f4<=vv746d9[15];ls83d20<={hd228a8>>1,vv746d9[16]};ls1e902<=vv746d9[17];byf4813<=vv746d9[18];mta409b<=vv746d9[19];ng204dd<=vv746d9[20];wl26eb<=vv746d9[21];bn1375d<=vv746d9[22];tj9baee<=vv746d9[23];pfdd777<=vv746d9[24];dm5ddfb<={fca828a>>1,vv746d9[25]};ic77ed3<={iea29c>>1,vv746d9[26]};ntbf698<=vv746d9[27];hofb4c7<=vv746d9[28];lqda63b<=vv746d9[29];yxd31da<=vv746d9[30];sw98ed4<=vv746d9[31];dzc76a0<=vv746d9[32];co3b507<=vv746d9[33];xwda839<=vv746d9[34];dba0e59<={hb5aa5d>>1,vv746d9[35]};ep39675<={yma977b>>1,vv746d9[36]};iccb3ac<=vv746d9[37];ui59d61<=vv746d9[38];en75840<={vv7b310>>1,vv746d9[39]};ieac205<=vv746d9[40];nr61029<=vv746d9[41];wl814f<=vv746d9[42];bl40a7c<=vv746d9[43];mg53e7<=vv746d9[44];bl4f9c4<={jce4005>>1,vv746d9[45]};ipe7133<={ks15b>>1,vv746d9[46]};fp3899c<=vv746d9[47];uic4ce7<=vv746d9[48];kf26739<=vv746d9[49];ux339cc<=vv746d9[50];do9ce64<=vv746d9[51];mre7322<=vv746d9[52];kf39914<=vv746d9[53];kdcc8a5<=vv746d9[54];nr6452d<=vv746d9[55];xl2296f<=vv746d9[56];xy14b7f<=vv746d9[57];end +always@* begin wy2e8db[2047]<=yxe7c08;wy2e8db[2046]<=aa573e;wy2e8db[2044]<=fnc86c0;wy2e8db[2040]<=su43606[0];wy2e8db[2032]<=tw1b031[0];wy2e8db[2017]<=ldd818a[0];wy2e8db[1987]<=byc0c57[0];wy2e8db[1980]<=ec2b608;wy2e8db[1963]<=me6d2d5;wy2e8db[1942]<=th409c4;wy2e8db[1926]<=ph62bb[0];wy2e8db[1921]<=do14d41;wy2e8db[1913]<=cz5b040;wy2e8db[1903]<=su621e4;wy2e8db[1879]<=rg696a9;wy2e8db[1837]<=ba4e27;wy2e8db[1805]<=uk315df[0];wy2e8db[1795]<=gqa6a0a;wy2e8db[1783]<=ks15b[0];wy2e8db[1778]<=fnd8204;wy2e8db[1758]<=ec10f20;wy2e8db[1710]<=hb5aa5d[0];wy2e8db[1679]<=hd228a8[0];wy2e8db[1627]<=ph2713b;wy2e8db[1562]<=ep8aef8[0];wy2e8db[1543]<=fca828a[0];wy2e8db[1519]<=coad8;wy2e8db[1509]<=eac1027;wy2e8db[1499]<=uvd9887;wy2e8db[1469]<=ou87900;wy2e8db[1398]<=ho5decc;wy2e8db[1373]<=yma977b[0];wy2e8db[1310]<=zk73e4c;wy2e8db[1207]<=jr389de;wy2e8db[1144]<=dzf9314;wy2e8db[1076]<=lq577c4[0];wy2e8db[1039]<=iea29c[0];wy2e8db[1023]<=ne52e43[0];wy2e8db[990]<=uk56c1;wy2e8db[981]<=uxda5a;wy2e8db[971]<=ir8138;wy2e8db[960]<=os629a8;wy2e8db[951]<=shcc43c;wy2e8db[891]<=jce4005[0];wy2e8db[839]<=uic4515;wy2e8db[749]<=vv7b310[0];wy2e8db[699]<=kd4bbd9;wy2e8db[572]<=sj9f262;wy2e8db[490]<=xwe1b4b;wy2e8db[480]<=yk4c535;wy2e8db[419]<=shf88a2;wy2e8db[245]<=ri9c369;wy2e8db[240]<=czc98a6;wy2e8db[209]<=hodf114;wy2e8db[122]<=ui5386d;wy2e8db[104]<=uxbbe22[0];wy2e8db[61]<=ir8a70d;wy2e8db[30]<=wj514e1;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6= 7'h42); + + +assign kqd4ee3 = uxb1e05 & ~rg79e44; +assign jcda9dc = mg8dfce & ~nr71b79 & ~qt7f38d & ~hbf9c6d; + + +assign yma9e3c = sj236bc & hd91bf9[18]; + + + + + + +assign kf3c1ce = (mg8dfce | rx_write) & hoc0b68 & ~nr71b79 & ~qt7f38d; + +always@* begin uxb1e05<=vv746d9[0];ir8f02d<=vv746d9[1];ui7816d<={zm9985b>>1,vv746d9[2]};hoc0b68<=vv746d9[3];tj2da19<={dz616d4>>1,vv746d9[4]};ww68671<={mgacec5>>1,vv746d9[5]};vx19c49<={ie3b140>>1,vv746d9[6]};vv71271<={qvbe6c1>>1,vv746d9[7]};os49c72<={jr9b06f>>1,vv746d9[8]};sh4e391<=vv746d9[9];zx71c8d<=vv746d9[10];xl8e46f<=vv746d9[11];hd91bf9<={cm6dd4f>>1,vv746d9[12]};mg8dfce<=vv746d9[13];cz6fe71<=vv746d9[14];qt7f38d<=vv746d9[15];hbf9c6d<=vv746d9[16];kqce36f<=vv746d9[17];nr71b79<=vv746d9[18];co8dbcf<=vv746d9[19];gb6f3c8<={yz73a0>>1,vv746d9[20]};rg79e44<=vv746d9[21];jc7911b<={nr74168>>1,vv746d9[22]};cz446d7<={ym5a36>>1,vv746d9[23]};sj236bc<=vv746d9[24];fc1b5e4<=vv746d9[25];bydaf22<=vv746d9[26];bld7913<=vv746d9[27];end +always@* begin wy2e8db[2047]<=tu7330b;wy2e8db[2046]<=zm9985b[0];wy2e8db[2044]<=rx_fifo_full;wy2e8db[2040]<=dz616d4[0];wy2e8db[2032]<=mgacec5[0];wy2e8db[2017]<=ie3b140[0];wy2e8db[1987]<=qvbe6c1[0];wy2e8db[1926]<=jr9b06f[0];wy2e8db[1804]<=kqc1bf7;wy2e8db[1803]<=ym5a36[0];wy2e8db[1560]<=irdfb9;wy2e8db[1558]<=rv2d1b1;wy2e8db[1550]<=hb4f1e0;wy2e8db[1072]<=wj6fdcd;wy2e8db[1069]<=ea68d8f;wy2e8db[1052]<=me78f07;wy2e8db[1023]<=lse661;wy2e8db[901]<=nr74168[0];wy2e8db[775]<=yma9e3c;wy2e8db[450]<=qv39d05;wy2e8db[387]<=al753c7;wy2e8db[225]<=yz73a0[0];wy2e8db[193]<=nr6ea78;wy2e8db[183]<=cb363c0;wy2e8db[112]<=kf3c1ce;wy2e8db[96]<=cm6dd4f[0];wy2e8db[91]<=ay46c78;wy2e8db[56]<=blc7839;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};oufa7e<=vv746d9[1];fpbfe8f<=vv746d9[2];ksb9c0d<=vv746d9[3];eafa3f1<=vv746d9[4];cb8fc48<={ep90e3c>>1,vv746d9[5]};xj7e244<=vv746d9[6];jcf1227<=vv746d9[7];by489d2<={vie1324>>1,vv746d9[8]};sh44e93<=vv746d9[9];vx2749d<=vv746d9[10];do3a4ee<=vv746d9[11];hbd2773<=vv746d9[12];ng93b9e<=vv746d9[13];mg9dcf3<=vv746d9[14];faee798<=vv746d9[15];jc73cc2<=vv746d9[16];vx9e612<=vv746d9[17];ks984b7<={rtf63e4>>1,vv746d9[18]};vvc25b9<=vv746d9[19];sj12dcf<=vv746d9[20];ba96e7d<=vv746d9[21];vkb73eb<=vv746d9[22];pscfad9<={rv3d8d7>>1,vv746d9[23]};xy14b7f<=vv746d9[24];end +always@* begin wy2e8db[2047]<=aa573e;wy2e8db[2046]<=yk78487;wy2e8db[2044]<=fnc86c0;wy2e8db[2041]<=wl121c7;wy2e8db[2034]<=ep90e3c[0];wy2e8db[2021]<=medb299;wy2e8db[2017]<=by7c9ec;wy2e8db[1995]<=fca2a3b;wy2e8db[1986]<=pse4f63;wy2e8db[1943]<=vie1324[0];wy2e8db[1925]<=rv3d8d7[0];wy2e8db[1855]<=tj9efb1;wy2e8db[1838]<=neeb0b5;wy2e8db[1803]<=jr389de;wy2e8db[1662]<=off7d8f;wy2e8db[1628]<=vi585aa;wy2e8db[1487]<=ntaa7be;wy2e8db[1276]<=rtf63e4[0];wy2e8db[1209]<=fnc2d53;wy2e8db[1023]<=ne52e43[0];wy2e8db[1008]<=gd8f93d;wy2e8db[927]<=ui53df6;wy2e8db[743]<=vxb54f7;wy2e8db[504]<=kfb1f27;wy2e8db[371]<=rv16a9e;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};nec54d1<=vv746d9[1];ba2a68a<=vv746d9[2];cm53452<=vv746d9[3];an9a290<=vv746d9[4];med1484<={lq42166>>1,vv746d9[5]};gd8a421<={yk4962f>>1,vv746d9[6]};fa5210d<={rgc5e2a>>1,vv746d9[7]};yz9086a<={ls2f153>>1,vv746d9[8]};end +always@* begin wy2e8db[2047]<=mee0e42;wy2e8db[2046]<=kf7210;wy2e8db[2044]<=ir39085;wy2e8db[2040]<=rtc842c;wy2e8db[2032]<=lq42166[0];wy2e8db[2017]<=yk4962f[0];wy2e8db[1987]<=rgc5e2a[0];wy2e8db[1926]<=ls2f153[0];wy2e8db[1023]<=lq7c1c8[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6= 14'd64); + + + + +assign tu7330b = ((~vk96e34) ? (aa573e & ~wla11ec) : 1'b0) | (an18b41 & ~nec5a0c) | (ayd163b & ~ph8b1d9) | (xy1b700 & vk48b0 & aa573e) | (zz9e5b8 & aa573e); + +assign zmad7ab = godee70 | (ou10c51 & uvf8bdc); + + +assign th6bd5b = wl121c7; +assign wj5eadf = wl121c7 & wy98ff3; + + +assign cbab7e8 = (~ng833f6) ? mg8862d -14'd4 : qi1f373; + +assign mecb116 = 32'hffffffff; + +assign hd22c50 = lfa0ae7; +assign ir39085 = ~hd3d96a & mrd6847; + +assign zm14547 = godee70 | al6afa7; + + + +assign ld5f545 = zmb71a3 & fpb067e & nt2d5f4 & wla11ec & ~(ng1bcce | osdb802); + +always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin rt5ac95 <= 1'b0; en4b592 <= 1'b0; twb257c <= 14'b0; ie2b213 <= 14'b0; pfc84c1 <= 14'b0; vi4260e <= 1'b0; fn617ab <= 1'b0; pua8b83 <= 1'b0; lsb88ce <= 1'b0; qgc4673 <= 1'b0; an23398 <= 1'b0; tj19cc4 <= 1'b0; wwfaa2e <= 1'b0; uka5df <= 1'b0; xjd7119 <= 1'b0; by73c4b <= 14'd0; yz95f19 <= 14'd0; ri99b0a <= 9'd0; vvcd852 <= 1'b0; icce626 <= 1'b0; ph2713b <= 1'b0; end else if (rxmac_clk_en) begin vvcd852 <= pu2f72b & ~bld7913; if (pu2f72b && !bld7913) ri99b0a <= mg98e8b; wwfaa2e <= ir39085; uka5df <= wj65abe; if (gq8d22a) xjd7119 <= gq8d22a; else if (lfa0ae7 && !gq8d22a) xjd7119 <= 1'b0; else if (an18b41) xjd7119 <= 1'b0; else xjd7119 <= xweb8de; tj19cc4 <= ~jr3d71b; if (ir7674 & wj6fb0f) an23398 <= ir7674; else if (pu2f72b) an23398 <= 1'b0; else an23398 <= ng1bcce; if (zkf4f5c) qgc4673 <= zkf4f5c; else if (pu2f72b) qgc4673 <= 1'b0; else qgc4673 <= the3799; ph2713b <= godee70; if (xl2296f) lsb88ce <= gbd9d29; if (nr614bb) icce626 <= ay4c1fc; pua8b83 <= godee70 | (al6afa7 & wj6fb0f); twb257c <= pu1bcbb; en4b592 <= zk57d3d; rt5ac95 <= kdf2ed8; if (ou10c51 && !pf4541b) fn617ab <= jpc7f98; vi4260e <= pf4541b; if (ou10c51 && !pf4541b) ie2b213 <= ym8218a; if (pf4541b) begin pfc84c1 <= ym8218a + 14'd1; end else pfc84c1 <= 14'd0; if (dz506f2 && ng833f6 && uk98c9f) yz95f19 <= qi1f373 + 14'd1; if (ri2a0de && !ng833f6 && uvf8bdc) by73c4b <= mg8862d + 14'd1; else if (ww43168) by73c4b <= 14'd0; end +end + + + +assign nr614bb = ww43168; + + +assign nr45c1a = qi24583 ? (os46086 > (uvc68db + 14'd4)) : os46086 > uvc68db; +assign ec2e0d7 = (os46086 < 14'd64); +assign cz706b8 = do11a45; + +assign mr5bf44 = (os46086[6:0] != 7'd64); +assign jcdfa25 = (jr160cf != fpc7cd); +assign pu835c4 = gdbe9eb ? 1'b0 : vk48b0 | ng833f6 ? gode5db : hd19fb3 ? 1'b0 : cm6831f; + +assign uk1ae23 = ~(ng1bcce | osdb802 | vka7ae3); +assign zma8cd1[31] = hd2d063; +assign zma8cd1[30] = gdbe9eb; +assign zma8cd1[29] = ay5c6f3; +assign zma8cd1[28] = nrf3398; +assign zma8cd1[27] = the3799; +assign zma8cd1[26] = xweb8de; +assign zma8cd1[25] = osdb802; +assign zma8cd1[24] = vka7ae3; +assign zma8cd1[23] = jr3d71b; +assign zma8cd1[22] = je3f824; +assign zma8cd1[21] = zxfc122; +assign zma8cd1[20] = qi3b3a5; +assign zma8cd1[19] = rgcfd9e; +assign zma8cd1[18] = vk48b0; +assign zma8cd1[17] = fpb067e; +assign zma8cd1[16] = qi24583; +assign zma8cd1[15:14] = 2'b00; +assign zma8cd1[13:0] = os46086; + +assign kf262c1[0] = fpb067e; +assign kf262c1[1] = osdb802; +assign kf262c1[2] = ng1bcce; +assign kf262c1[3] = hd2d063; +assign kf262c1[4] = gdbe9eb; +assign kf262c1[5] = ay5c6f3; +assign kf262c1[6] = je3f824; +assign kf262c1[7] = zxfc122; +assign kf262c1[8] = qi24583; + +always@* begin wj6fb0f<=vv746d9[0];cz60ece<=vv746d9[1];ir7674<=vv746d9[2];qi3b3a5<=vv746d9[3];gbd9d29<=vv746d9[4];uk3bdce<={ne52e43>>1,vv746d9[5]};godee70<=vv746d9[6];ep2983f<=vv746d9[7];ay4c1fc<=vv746d9[8];gb60fe0<=vv746d9[9];oh7f04<=vv746d9[10];je3f824<=vv746d9[11];zxfc122<=vv746d9[12];uie0916<=vv746d9[13];vk48b0<=vv746d9[14];qi24583<=vv746d9[15];jr160cf<={ec21fab>>1,vv746d9[16]};fpb067e<=vv746d9[17];ng833f6<=vv746d9[18];hd19fb3<=vv746d9[19];rgcfd9e<=vv746d9[20];nr7ecf2<=vv746d9[21];qib3cb7<={bl7eac0>>1,vv746d9[22]};zz9e5b8<=vv746d9[23];gbf2dc6<=vv746d9[24];vk96e34<=vv746d9[25];zmb71a3<=vv746d9[26];uvc68db<={dz6b175>>1,vv746d9[27]};ec346dc<=vv746d9[28];eca36e0<=vv746d9[29];xy1b700<=vv746d9[30];osdb802<=vv746d9[31];qge008d<={ecb9836>>1,vv746d9[32]};sw469<=vv746d9[33];qv2348<=vv746d9[34];do11a45<=vv746d9[35];gq8d22a<=vv746d9[36];by69150<=vv746d9[37];ho48a83<=vv746d9[38];pf4541b<=vv746d9[39];ri2a0de<=vv746d9[40];dz506f2<=vv746d9[41];pu1bcbb<={cbab7e8>>1,vv746d9[42]};gode5db<=vv746d9[43];kdf2ed8<=vv746d9[44];kfbb620<={wje895c>>1,vv746d9[45]};icdb105<=vv746d9[46];bld8828<=vv746d9[47];uic4146<={sw2b92b>>1,vv746d9[48]};fc20a30<=vv746d9[49];ec5182<=vv746d9[50];os46086<={ie2b213>>1,vv746d9[51]};ym8218a<={pfc84c1>>1,vv746d9[52]};ou10c51<=vv746d9[53];ri86288<=vv746d9[54];ks31443<=vv746d9[55];cb8a218<=vv746d9[56];mg8862d<={by73c4b>>1,vv746d9[57]};ww43168<=vv746d9[58];an18b41<=vv746d9[59];nec5a0c<=vv746d9[60];hd2d063<=vv746d9[61];cm6831f<=vv746d9[62];fpc7cd<={twb257c>>1,vv746d9[63]};qi1f373<={yz95f19>>1,vv746d9[64]};nrf9b98<=vv746d9[65];jpcdcc7<=vv746d9[66];fn6e63f<=vv746d9[67];jc731fe<=vv746d9[68];wy98ff3<=vv746d9[69];jpc7f98<=vv746d9[70];vk3fcc6<=vv746d9[71];zxf3193<={ksb6a15>>1,vv746d9[72]};uk98c9f<=vv746d9[73];shc64f8<=vv746d9[74];vx327c5<=vv746d9[75];ep9f17b<={zma8cd1>>1,vv746d9[76]};uvf8bdc<=vv746d9[77];lqc5ee5<=vv746d9[78];pu2f72b<=vv746d9[79];bld7913<=vv746d9[80];endcad6<=vv746d9[81];sue56b4<=vv746d9[82];jp5ad08<={dz61b0b>>1,vv746d9[83]};mrd6847<=vv746d9[84];gdb423d<=vv746d9[85];wla11ec<=vv746d9[86];qv8f65<=vv746d9[87];ho47b2d<={al5eafa>>1,vv746d9[88]};hd3d96a<=vv746d9[89];xl2296f<=vv746d9[90];wj65abe<=vv746d9[91];nt2d5f4<=vv746d9[92];al6afa7<=vv746d9[93];zk57d3d<=vv746d9[94];gdbe9eb<=vv746d9[95];zkf4f5c<=vv746d9[96];vka7ae3<=vv746d9[97];jr3d71b<=vv746d9[98];xweb8de<=vv746d9[99];ay5c6f3<=vv746d9[100];the3799<=vv746d9[101];ng1bcce<=vv746d9[102];qgde673<=vv746d9[103];nrf3398<=vv746d9[104];do99cc7<=vv746d9[105];kqce63a<=vv746d9[106];mg98e8b<={kf262c1>>1,vv746d9[107]};hbc7458<={sw3160c>>1,vv746d9[108]};je3a2c7<=vv746d9[109];ayd163b<=vv746d9[110];ph8b1d9<=vv746d9[111];end +always@* begin wy2e8db[2047]<=xy304af;wy2e8db[2046]<=aa8257a;wy2e8db[2045]<=ui675b5;wy2e8db[2044]<=gd12bd1;wy2e8db[2043]<=vk3ada8;wy2e8db[2041]<=kf95e8d;wy2e8db[2038]<=ksb6a15[0];wy2e8db[2035]<=ne52e43[0];wy2e8db[2029]<=by73c4b[0];wy2e8db[2028]<=dbb50a8;wy2e8db[2022]<=yxe7c08;wy2e8db[2011]<=jr9e25a;wy2e8db[2009]<=xya8546;wy2e8db[1996]<=ec3e045;wy2e8db[1986]<=icce626;wy2e8db[1974]<=hof12d6;wy2e8db[1971]<=by42a33;wy2e8db[1945]<=yk5cf81;wy2e8db[1943]<=me5c959;wy2e8db[1924]<=vi73131;wy2e8db[1922]<=thddac5;wy2e8db[1901]<=do896b2;wy2e8db[1895]<=zma8cd1[0];wy2e8db[1857]<=qvd85e;wy2e8db[1842]<=ie151db;wy2e8db[1839]<=fae4ac8;wy2e8db[1800]<=ou9898b;wy2e8db[1797]<=kded62e;wy2e8db[1791]<=pfe333a;wy2e8db[1784]<=qgc4673;wy2e8db[1778]<=qt44ae4;wy2e8db[1776]<=bl7eac0[0];wy2e8db[1759]<=yz95f19[0];wy2e8db[1755]<=en4b592;wy2e8db[1742]<=yz33451;wy2e8db[1677]<=nr45c1a;wy2e8db[1667]<=ho6c2f5;wy2e8db[1652]<=cb363c0;wy2e8db[1637]<=zma8ed9;wy2e8db[1631]<=ie2b213[0];wy2e8db[1622]<=ux3c87e;wy2e8db[1552]<=kf262c1[0];wy2e8db[1546]<=dz6b175[0];wy2e8db[1535]<=jr199d6;wy2e8db[1531]<=ec9839e;wy2e8db[1520]<=an23398;wy2e8db[1509]<=do25725;wy2e8db[1504]<=uk2b76b;wy2e8db[1471]<=vxaf8cc;wy2e8db[1468]<=rv846fb;wy2e8db[1463]<=rt5ac95;wy2e8db[1437]<=oh9a28d;wy2e8db[1391]<=cbab030;wy2e8db[1312]<=bn6c64;wy2e8db[1307]<=ec2e0d7;wy2e8db[1286]<=fn617ab;wy2e8db[1256]<=yx51b0d;wy2e8db[1226]<=ne476ca;wy2e8db[1215]<=pfc84c1[0];wy2e8db[1197]<=lqe43f5;wy2e8db[1153]<=gdb1935;wy2e8db[1135]<=pu835c4;wy2e8db[1057]<=sw3160c[0];wy2e8db[1050]<=al5eafa[0];wy2e8db[1044]<=tu58bae;wy2e8db[1037]<=zmad7ab;wy2e8db[1023]<=mrf282b;wy2e8db[1022]<=ipcceb6;wy2e8db[1014]<=wwc1cf1;wy2e8db[993]<=tj19cc4;wy2e8db[971]<=sw2b92b[0];wy2e8db[961]<=ignore_pkt;wy2e8db[928]<=dz61b0b[0];wy2e8db[895]<=lq7c667;wy2e8db[892]<=lsb88ce;wy2e8db[889]<=wje895c[0];wy2e8db[888]<=wyfd58;wy2e8db[879]<=twb257c[0];wy2e8db[838]<=pua8b83;wy2e8db[826]<=uid146c;wy2e8db[811]<=zxc790f;wy2e8db[765]<=tj13073;wy2e8db[734]<=lq58184;wy2e8db[695]<=kqf5606;wy2e8db[656]<=of60d8c;wy2e8db[576]<=kf36326;wy2e8db[567]<=cz706b8;wy2e8db[525]<=jebd5f;wy2e8db[518]<=tw35af5;wy2e8db[464]<=sw8d86c;wy2e8db[446]<=xjd7119;wy2e8db[444]<=jcdfa25;wy2e8db[419]<=wwfaa2e;wy2e8db[405]<=ec3b653;wy2e8db[382]<=vi4260e;wy2e8db[347]<=ec21fab[0];wy2e8db[328]<=ecb9836[0];wy2e8db[269]<=icc183b;wy2e8db[259]<=dz64d6b;wy2e8db[223]<=uk1ae23;wy2e8db[222]<=mr5bf44;wy2e8db[209]<=ld5f545;wy2e8db[164]<=ecf839;wy2e8db[134]<=zk58307;wy2e8db[111]<=cbab7e8[0];wy2e8db[104]<=ph2713b;wy2e8db[82]<=ym2eb93;wy2e8db[67]<=ph8b060;wy2e8db[55]<=wj5eadf;wy2e8db[52]<=qgf57d5;wy2e8db[41]<=jcc5d72;wy2e8db[27]<=th6bd5b;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[3]};ir7674<=vv746d9[4];qi3b3a5<=vv746d9[5];gbd9d29<=vv746d9[6];wj70349<={su43606>>1,vv746d9[7]};sjd267<={tw1b031>>1,vv746d9[8]};ui499e3<={ldd818a>>1,vv746d9[9]};ay678c9<={byc0c57>>1,vv746d9[10]};zxe324c<={ph62bb>>1,vv746d9[11]};czc9337<={uk315df>>1,vv746d9[12]};me4cde1<={ep8aef8>>1,vv746d9[13]};fp3784b<={lq577c4>>1,vv746d9[14]};vie12f0<={uxbbe22>>1,vv746d9[15]};jr9783<=vv746d9[16];al4bc1e<=vv746d9[17];gb5e0f4<=vv746d9[18];cb8fc48<={ep90e3c>>1,vv746d9[19]};vk96e34<=vv746d9[20];zmb71a3<=vv746d9[21];uvc68db<={dz6b175>>1,vv746d9[22]};ec346dc<=vv746d9[23];eca36e0<=vv746d9[24];xy1b700<=vv746d9[25];hoc0b68<=vv746d9[26];gbf2dc6<=vv746d9[27];dob70ad<={gq88cbf>>1,vv746d9[28]};nrc2b5a<={nt32fc9>>1,vv746d9[29]};aa15ad6<=vv746d9[30];jead6b0<=vv746d9[31];vv6b583<=vv746d9[32];jp5ac1e<=vv746d9[33];mrd60f7<=vv746d9[34];xy83de6<={mt8fd6f>>1,vv746d9[35]};do1ef32<=vv746d9[36];qtf7993<=vv746d9[37];wybcc9c<=vv746d9[38];dze64e1<=vv746d9[39];rv3270e<=vv746d9[40];hq9c3bb<={ym3155e>>1,vv746d9[41]};doeeda<={jp55784>>1,vv746d9[42]};uxbb691<={mr5e13d>>1,vv746d9[43]};kqdb48d<=vv746d9[44];psda468<=vv746d9[45];fnd2342<=vv746d9[46];zz91a16<=vv746d9[47];aa8d0b6<=vv746d9[48];ea685b0<=vv746d9[49];fa42d81<=vv746d9[50];rv16c0a<=vv746d9[51];swb6057<=vv746d9[52];tjb02b9<=vv746d9[53];xl815ce<=vv746d9[54];coae76<=vv746d9[55];vi573b0<=vv746d9[56];ukb9d82<=vv746d9[57];ho76088<={db3398>>1,vv746d9[58]};jrb0443<=vv746d9[59];sw8221e<=vv746d9[60];ie8878b<={wy98f8b>>1,vv746d9[61]};qg43c58<=vv746d9[62];zm1e2c0<=vv746d9[63];ph8b012<={wl8aea8>>1,vv746d9[64]};jcc04bb<={dbbaa22>>1,vv746d9[65]};an12ed5<={vka88b3>>1,vv746d9[66]};cbbb568<={ph22cd4>>1,vv746d9[67]};xwdab45<=vv746d9[68];tud5a2b<=vv746d9[69];me68ad3<={osd4f8d>>1,vv746d9[70]};end +always@* begin wy2e8db[2047]<=mrf282b;wy2e8db[2046]<=xy304af;wy2e8db[2044]<=tj9415c[0];wy2e8db[2040]<=aa8257a;wy2e8db[2033]<=gd12bd1;wy2e8db[2019]<=kf95e8d;wy2e8db[1999]<=mt8fd6f[0];wy2e8db[1991]<=su43606[0];wy2e8db[1981]<=mr7fff0;wy2e8db[1958]<=ph84019;wy2e8db[1950]<=zx7eb7c;wy2e8db[1947]<=jp55784[0];wy2e8db[1934]<=tw1b031[0];wy2e8db[1914]<=uifff84;wy2e8db[1892]<=thddac5;wy2e8db[1868]<=ri200ce;wy2e8db[1852]<=uif5be6;wy2e8db[1851]<=uxbbe22[0];wy2e8db[1847]<=mr5e13d[0];wy2e8db[1820]<=ldd818a[0];wy2e8db[1783]<=hbec3ff;wy2e8db[1780]<=goffc20;wy2e8db[1737]<=kded62e;wy2e8db[1689]<=db3398[0];wy2e8db[1657]<=hqadf31;wy2e8db[1654]<=hodf114;wy2e8db[1647]<=eaf09ec;wy2e8db[1610]<=jcc5d72;wy2e8db[1608]<=wl8aea8[0];wy2e8db[1593]<=byc0c57[0];wy2e8db[1523]<=mrc9c7e;wy2e8db[1519]<=fn61fff;wy2e8db[1513]<=zkfe100;wy2e8db[1426]<=dz6b175[0];wy2e8db[1404]<=zzbf271;wy2e8db[1330]<=fp19cc7;wy2e8db[1267]<=al6f98a;wy2e8db[1260]<=shf88a2;wy2e8db[1246]<=lf84f61;wy2e8db[1225]<=wy98f8b[0];wy2e8db[1199]<=gq88cbf[0];wy2e8db[1173]<=ym2eb93;wy2e8db[1169]<=dbbaa22[0];wy2e8db[1163]<=nt166a7;wy2e8db[1139]<=ph62bb[0];wy2e8db[1023]<=reset_n;wy2e8db[999]<=cz4e3f5;wy2e8db[990]<=ecfffe;wy2e8db[979]<=ykf0803;wy2e8db[973]<=ym3155e[0];wy2e8db[946]<=ep90e3c[0];wy2e8db[925]<=lq577c4[0];wy2e8db[891]<=db3d87f;wy2e8db[805]<=tu58bae;wy2e8db[804]<=uk3e2c6;wy2e8db[761]<=blf938f;wy2e8db[702]<=ym97e4e;wy2e8db[612]<=ayce63e;wy2e8db[599]<=ignore_pkt;wy2e8db[581]<=ph22cd4[0];wy2e8db[556]<=osd4f8d[0];wy2e8db[486]<=zk7cc55;wy2e8db[473]<=uic4515;wy2e8db[462]<=ep8aef8[0];wy2e8db[445]<=rv27b0f;wy2e8db[402]<=jpc7c58;wy2e8db[351]<=nt32fc9[0];wy2e8db[299]<=rx_fifo_full;wy2e8db[290]<=vka88b3[0];wy2e8db[278]<=ieb353e;wy2e8db[231]<=uk315df[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[1]};qg43b47<=vv746d9[2];an1da38<=vv746d9[3];ofed1c4<={zm9368d>>1,vv746d9[4]};go68e25<={db9b46a>>1,vv746d9[5]};rg47128<=vv746d9[6];nt38943<={gd90143>>1,vv746d9[7]};end +always@* begin wy2e8db[2047]<=osce1dd[0];wy2e8db[2046]<=qi3e4da;wy2e8db[2044]<=gbf26d1;wy2e8db[2040]<=zm9368d[0];wy2e8db[2032]<=db9b46a[0];wy2e8db[2016]<=lqda356;wy2e8db[1985]<=gd90143[0];wy2e8db[1023]<=oh39c3b;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};nec54d1<=vv746d9[1];an9a290<=vv746d9[2];med1484<={lq42166>>1,vv746d9[3]};gd8a421<={yk4962f>>1,vv746d9[4]};fa5210d<={rgc5e2a>>1,vv746d9[5]};end +always@* begin wy2e8db[2047]<=mee0e42;wy2e8db[2046]<=rtc842c;wy2e8db[2044]<=lq42166[0];wy2e8db[2040]<=yk4962f[0];wy2e8db[2033]<=rgc5e2a[0];wy2e8db[1023]<=lq7c1c8[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[1]};cz6561a<=vv746d9[2];ks2b0d5<=vv746d9[3];uvc3543<={ui7d18f>>1,vv746d9[4]};dmd50e9<={go463c4>>1,vv746d9[5]};lsa874b<=vv746d9[6];ic43a5b<=vv746d9[7];oh1d2d8<=vv746d9[8];ip4b62f<={xw483d3>>1,vv746d9[9]};jpd8bec<={ip7a6a9>>1,vv746d9[10]};hoc5f66<=vv746d9[11];end +always@* begin wy2e8db[2047]<=yza464e[0];wy2e8db[2046]<=gd23275;wy2e8db[2044]<=ph193ac;wy2e8db[2040]<=ui7d18f[0];wy2e8db[2032]<=go463c4[0];wy2e8db[2017]<=aa31e21;wy2e8db[1987]<=os7884d;wy2e8db[1927]<=osc4269;wy2e8db[1806]<=xw483d3[0];wy2e8db[1565]<=ip7a6a9[0];wy2e8db[1082]<=uvd354d;wy2e8db[1023]<=fp948c9;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[6]};tj9bfdb<={dz7e8f3>>1,vv746d9[7]};qgff6fb<={byf479e>>1,vv746d9[8]};fafb7d9<=vv746d9[9];uidbecb<=vv746d9[10];vidf659<=vv746d9[11];zkfb2ca<=vv746d9[12];qgcb29d<={off22b6>>1,vv746d9[13]};go594e9<=vv746d9[14];neca749<=vv746d9[15];ym9d259<={me56d7c>>1,vv746d9[16]};dze92c9<=vv746d9[17];ww4964f<=vv746d9[18];ic593c5<={jraf847>>1,vv746d9[19]};enc9e29<=vv746d9[20];rt4f14d<=vv746d9[21];os78a6f<=vv746d9[22];psc5379<=vv746d9[23];sj29bca<=vv746d9[24];jc4de54<=vv746d9[25];en6f2a3<=vv746d9[26];ic43a5b<={os7884d>>1,vv746d9[27]};oh1d2d8<={osc4269>>1,vv746d9[28]};qt54712<=vv746d9[29];ksa3895<=vv746d9[30];kde254f<={ph94fba>>1,vv746d9[31]};sj953e5<={mg3eeb3>>1,vv746d9[32]};xj4f968<={zzbacc5>>1,vv746d9[33]};ho7cb46<=vv746d9[34];kqe5a33<=vv746d9[35];vx2d198<=vv746d9[36];kq68cc7<=vv746d9[37];ww46638<=vv746d9[38];an331c1<=vv746d9[39];co98e0d<={osceb0e>>1,vv746d9[40]};fnc7068<={of75870>>1,vv746d9[41]};vx38347<=vv746d9[42];osc1a3e<=vv746d9[43];ohd1f1<=vv746d9[44];me68f8c<=vv746d9[45];ne47c60<=vv746d9[46];aa3e302<=vv746d9[47];hq8c08b<={zk4d8a8>>1,vv746d9[48]};kd6045a<=vv746d9[49];yz22d5<=vv746d9[50];pu116ad<=vv746d9[51];fp8b56b<={wjc9655>>1,vv746d9[52]};zx5ab5f<=vv746d9[53];jcd5aff<=vv746d9[54];doad7fa<={dmcab29>>1,vv746d9[55]};zx6bfd3<=vv746d9[56];th5fe9f<=vv746d9[57];meff4ff<=vv746d9[58];ykfa7f9<=vv746d9[59];shd3fc9<=vv746d9[60];cb9fe4d<=vv746d9[61];goff26d<=vv746d9[62];fnf9369<=vv746d9[63];shc9b4e<=vv746d9[64];xw4da75<={th710a3>>1,vv746d9[65]};kq6d3ab<={uk8851e>>1,vv746d9[66]};by69d59<={jc428f0>>1,vv746d9[67]};en4eaca<=vv746d9[68];mr75654<=vv746d9[69];sjab2a4<=vv746d9[70];end +always@* begin wy2e8db[2047]<=dze6fa5;wy2e8db[2046]<=vx37d2f;wy2e8db[2044]<=mtbe97e;wy2e8db[2040]<=vif4bf4;wy2e8db[2033]<=rva5fa3;wy2e8db[2019]<=xy2fd1e[0];wy2e8db[1991]<=dz7e8f3[0];wy2e8db[1934]<=byf479e[0];wy2e8db[1929]<=oh95362;wy2e8db[1898]<=oh8adaf;wy2e8db[1821]<=gqa3cf2;wy2e8db[1810]<=zk4d8a8[0];wy2e8db[1749]<=me56d7c[0];wy2e8db[1707]<=jraf847[0];wy2e8db[1666]<=osc4269[0];wy2e8db[1630]<=of75870[0];wy2e8db[1617]<=th710a3[0];wy2e8db[1595]<=ri1e791;wy2e8db[1572]<=lsa86c9;wy2e8db[1506]<=ip4e764;wy2e8db[1450]<=ecb6be1;wy2e8db[1440]<=kdd3a99;wy2e8db[1428]<=sj2647d;wy2e8db[1384]<=ipc9d67;wy2e8db[1370]<=oh8fd3;wy2e8db[1366]<=tu7c23f;wy2e8db[1308]<=yma3c13;wy2e8db[1284]<=zx7eca7;wy2e8db[1212]<=ksac385;wy2e8db[1202]<=cobc75c;wy2e8db[1187]<=uk8851e[0];wy2e8db[1174]<=wyaca56;wy2e8db[1170]<=ic59565;wy2e8db[1142]<=tx_fifoavail;wy2e8db[1125]<=qv8675;wy2e8db[1097]<=ic4364b;wy2e8db[1041]<=ph94fba[0];wy2e8db[1023]<=wl3cdf4;wy2e8db[964]<=vi73b25;wy2e8db[949]<=nt915b5;wy2e8db[853]<=wj4eb3d;wy2e8db[833]<=os7884d[0];wy2e8db[815]<=osceb0e[0];wy2e8db[808]<=ep8fb3e;wy2e8db[753]<=ir29cec;wy2e8db[720]<=kqfa753;wy2e8db[714]<=yk59132;wy2e8db[692]<=sh70ee9;wy2e8db[685]<=zke11fa;wy2e8db[654]<=vk14782;wy2e8db[601]<=kf23de3;wy2e8db[587]<=fn5594a;wy2e8db[585]<=al4b2ac;wy2e8db[568]<=fc1e099;wy2e8db[562]<=th74219;wy2e8db[520]<=xjf653e;wy2e8db[474]<=off22b6[0];wy2e8db[407]<=xl19d61;wy2e8db[376]<=dz61c29;wy2e8db[357]<=ux7ac8;wy2e8db[327]<=jc428f0[0];wy2e8db[300]<=sj84dc;wy2e8db[293]<=dmcab29[0];wy2e8db[292]<=wjc9655[0];wy2e8db[281]<=mg2e843;wy2e8db[237]<=nt9e456;wy2e8db[203]<=cm433ac;wy2e8db[146]<=ri1b259;wy2e8db[140]<=byc5d08;wy2e8db[70]<=zzbacc5[0];wy2e8db[35]<=mg3eeb3[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[3]};nrec8cd<=vv746d9[4];xj6466e<=vv746d9[5];db19bbc<={th4059a>>1,vv746d9[6]};fafb7d9<=vv746d9[7];ld6ef37<=vv746d9[8];ic779bf<=vv746d9[9];ksbcdf8<=vv746d9[10];lde6fc1<=vv746d9[11];hd37e0f<=vv746d9[12];fpbf07e<=vv746d9[13];wjf83f7<=vv746d9[14];wwc1fbc<=vv746d9[15];ymfde1<=vv746d9[16];rt7ef08<=vv746d9[17];kdf7846<=vv746d9[18];aabc234<=vv746d9[19];dme11a0<=vv746d9[20];ux8d03<=vv746d9[21];zz28768<={osce1dd>>1,vv746d9[22]};pha0740<=vv746d9[23];nt3a07<=vv746d9[24];cb1d03e<=vv746d9[25];ipe81f5<=vv746d9[26];nr40fad<=vv746d9[27];wy3eb7c<={je434b>>1,vv746d9[28]};wwf5be0<=vv746d9[29];yx6f80a<={zk69684>>1,vv746d9[30]};jc7c055<=vv746d9[31];wwe02aa<=vv746d9[32];pu1551<=vv746d9[33];qiaa8a<=vv746d9[34];fn55450<=vv746d9[35];dbaa287<=vv746d9[36];uv5143e<=vv746d9[37];sj8a1f5<=vv746d9[38];zx50fad<=vv746d9[39];aa87d6e<=vv746d9[40];aa3eb70<=vv746d9[41];cmf5b80<=vv746d9[42];twadc01<=vv746d9[43];th6e00a<=vv746d9[44];sh70056<=vv746d9[45];oh802b4<=vv746d9[46];je15a4<=vv746d9[47];ukad22<=vv746d9[48];ic56910<=vv746d9[49];anb4881<=vv746d9[50];epa440d<=vv746d9[51];ou1036e<={kq53e55>>1,vv746d9[52]};xl81b71<=vv746d9[53];irdb8f<=vv746d9[54];ui6dc7d<=vv746d9[55];bl6e3e8<=vv746d9[56];fn71f46<=vv746d9[57];sj8fa37<=vv746d9[58];su7d1bc<=vv746d9[59];she8de0<=vv746d9[60];ic46f04<=vv746d9[61];ph37820<=vv746d9[62];end +always@* begin wy2e8db[2047]<=dze6fa5;wy2e8db[2046]<=tx_sndpausreq;wy2e8db[2044]<=tx_sndpaustim[0];wy2e8db[2040]<=psfe9c0;wy2e8db[2033]<=tuf4e02;wy2e8db[2019]<=th4059a[0];wy2e8db[1994]<=cz41436;wy2e8db[1990]<=gqa3cf2;wy2e8db[1981]<=co9810d;wy2e8db[1965]<=zz84772;wy2e8db[1940]<=qia1b4;wy2e8db[1939]<=ou9d4cd;wy2e8db[1933]<=nec04d6;wy2e8db[1914]<=je434b[0];wy2e8db[1883]<=neee5ac;wy2e8db[1832]<=jp50da1;wy2e8db[1831]<=pu99a40;wy2e8db[1819]<=qtd698d;wy2e8db[1785]<=co1f20a;wy2e8db[1781]<=uk21a5a;wy2e8db[1778]<=cz41332;wy2e8db[1740]<=kf18629;wy2e8db[1719]<=ui72d62;wy2e8db[1634]<=ww53d13;wy2e8db[1616]<=do86d0e;wy2e8db[1615]<=tx_discfrm;wy2e8db[1591]<=gq8db41;wy2e8db[1522]<=fnf9050;wy2e8db[1515]<=zk69684[0];wy2e8db[1508]<=ay6d048;wy2e8db[1470]<=os620f9;wy2e8db[1432]<=lq6c518;wy2e8db[1391]<=ntb5883;wy2e8db[1286]<=qv18d0c;wy2e8db[1271]<=vka72b6;wy2e8db[1221]<=of7a593;wy2e8db[1184]<=an36872;wy2e8db[1182]<=ea53348;wy2e8db[1135]<=ea6da09;wy2e8db[1051]<=nt27c53;wy2e8db[1023]<=wl3cdf4;wy2e8db[997]<=thc8286;wy2e8db[990]<=ep395b2;wy2e8db[982]<=fad08ee;wy2e8db[969]<=db9444a;wy2e8db[892]<=xy83e41;wy2e8db[889]<=tu48266;wy2e8db[870]<=aaf97d;wy2e8db[817]<=eacb16f;wy2e8db[735]<=coac41f;wy2e8db[643]<=wy24634;wy2e8db[635]<=vx94e56;wy2e8db[525]<=ng209f1;wy2e8db[495]<=go56ec6;wy2e8db[444]<=yk68241;wy2e8db[435]<=mg31165;wy2e8db[394]<=bn9b02c;wy2e8db[321]<=epa48c6;wy2e8db[317]<=osce1dd[0];wy2e8db[222]<=kd41209;wy2e8db[217]<=ay4c3c3;wy2e8db[108]<=iec4c;wy2e8db[54]<=kq53e55[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[2]};anbecbb<={zz28f06>>1,vv746d9[3]};fnf65dc<={ne47836>>1,vv746d9[4]};ic43a5b<=vv746d9[5];oh1d2d8<=vv746d9[6];qvbb9d0<=vv746d9[7];end +always@* begin wy2e8db[2047]<=fp271f5;wy2e8db[2046]<=hd38fae[0];wy2e8db[2044]<=zz28f06[0];wy2e8db[2040]<=ne47836[0];wy2e8db[2032]<=os7884d;wy2e8db[2017]<=osc4269;wy2e8db[1987]<=gd36506;wy2e8db[1023]<=qt44e3e;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[1]};vk99763<=vv746d9[2];cmcbb1b<=vv746d9[3];vi5d8d8<=vv746d9[4];kdf7846<=vv746d9[5];vk1b0ba<={yz36b29>>1,vv746d9[6]};blc2e97<={mgaca67>>1,vv746d9[7]};ntba5f4<={ep299c5>>1,vv746d9[8]};gq97d3f<={ic67161>>1,vv746d9[9]};faf4fcc<={vic5847>>1,vv746d9[10]};ba3f31b<={pf611dd>>1,vv746d9[11]};ofcc6df<={by4777d>>1,vv746d9[12]};ri1b7e2<={xjddf58>>1,vv746d9[13]};fadf891<={go7d631>>1,vv746d9[14]};ipe245e<={ne58c42>>1,vv746d9[15]};rv917a4<={mg31095>>1,vv746d9[16]};sh5e93e<={dm42540>>1,vv746d9[17]};sja4fab<={ux9501d>>1,vv746d9[18]};ym3eae7<={hb4076b>>1,vv746d9[19]};sjab9c0<={gd1daf6>>1,vv746d9[20]};me5ce05<=vv746d9[21];gbe7028<=vv746d9[22];end +always@* begin wy2e8db[2047]<=tx_fifodata[0];wy2e8db[2046]<=tx_fifoeof;wy2e8db[2044]<=tx_fifoempty;wy2e8db[2040]<=tx_fifoctrl;wy2e8db[2032]<=ou9d4cd;wy2e8db[2016]<=yz36b29[0];wy2e8db[1985]<=mgaca67[0];wy2e8db[1922]<=ep299c5[0];wy2e8db[1796]<=ic67161[0];wy2e8db[1544]<=vic5847[0];wy2e8db[1302]<=kded7b4;wy2e8db[1105]<=dm42540[0];wy2e8db[1041]<=pf611dd[0];wy2e8db[1023]<=tx_discfrm;wy2e8db[651]<=gd1daf6[0];wy2e8db[557]<=dz6bda5;wy2e8db[552]<=mg31095[0];wy2e8db[325]<=hb4076b[0];wy2e8db[276]<=ne58c42[0];wy2e8db[162]<=ux9501d[0];wy2e8db[138]<=go7d631[0];wy2e8db[69]<=xjddf58[0];wy2e8db[34]<=by4777d[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[5]};qv8f33b<={me68ae0>>1,vv746d9[6]};tj9bfdb<={dz7e8f3>>1,vv746d9[7]};zk732ec<={tx_fifodata>>1,vv746d9[8]};vk99763<=vv746d9[9];cmcbb1b<=vv746d9[10];vidf659<=vv746d9[11];uvfd919<={tx_sndpaustim>>1,vv746d9[12]};ps63f64<=vv746d9[13];vi5d8d8<=vv746d9[14];godbbe9<=vv746d9[15];cmefa4e<={go49e10>>1,vv746d9[16]};pf5039b<=vv746d9[17];hoca073<=vv746d9[18];qgff6fb<={byf479e>>1,vv746d9[19]};ym9d259<={me56d7c>>1,vv746d9[20]};ic593c5<={jraf847>>1,vv746d9[21]};enc9e29<=vv746d9[22];db19bbc<={th4059a>>1,vv746d9[23]};qgcb29d<={off22b6>>1,vv746d9[24]};zz28768<={osce1dd>>1,vv746d9[25]};ic779bf<=vv746d9[26];aab6476<=vv746d9[27];db91d8b<={czc621c>>1,vv746d9[28]};zk762f6<={co88728>>1,vv746d9[29]};end +always@* begin wy2e8db[2047]<=wl3cdf4;wy2e8db[2046]<=dze6fa5;wy2e8db[2044]<=mtbe97e;wy2e8db[2040]<=vx37d2f;wy2e8db[2032]<=ou8d15c[0];wy2e8db[2016]<=me68ae0[0];wy2e8db[1985]<=dz7e8f3[0];wy2e8db[1922]<=tx_fifodata[0];wy2e8db[1796]<=tx_fifoeof;wy2e8db[1544]<=tx_fifoempty;wy2e8db[1316]<=mtb4c6d;wy2e8db[1169]<=co88728[0];wy2e8db[1106]<=th4059a[0];wy2e8db[1041]<=rva5fa3;wy2e8db[1040]<=tx_fifoavail;wy2e8db[1023]<=zxc8e70;wy2e8db[658]<=qtd698d;wy2e8db[584]<=czc621c[0];wy2e8db[553]<=tu7c23f;wy2e8db[520]<=go49e10[0];wy2e8db[329]<=osce1dd[0];wy2e8db[276]<=jraf847[0];wy2e8db[260]<=kq493c2;wy2e8db[164]<=off22b6[0];wy2e8db[138]<=me56d7c[0];wy2e8db[130]<=tx_fifoctrl;wy2e8db[69]<=byf479e[0];wy2e8db[65]<=tx_sndpausreq;wy2e8db[34]<=vif4bf4;wy2e8db[32]<=tx_sndpaustim[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};en5e01d<={hdatain>>1,vv746d9[1]};suf00ec<=vv746d9[2];oh80760<=vv746d9[3];lf3b04<=vv746d9[4];mt1d826<=vv746d9[5];en609a7<={sw10140>>1,vv746d9[6]};xy4d3c<=vv746d9[7];gq34f1d<={ri99b0a>>1,vv746d9[8]};zma78e9<=vv746d9[9];oh3c74b<=vv746d9[10];nre3a5c<=vv746d9[11];wl1d2e7<=vv746d9[12];nre973d<=vv746d9[13];al4b9ef<=vv746d9[14];uve7be0<={wy31bf1>>1,vv746d9[15]};osef82f<={en6fc49>>1,vv746d9[16]};goe0bca<={lqf126f>>1,vv746d9[17]};xy2f281<={yk49bd2>>1,vv746d9[18]};xw7940a<=vv746d9[19];zx50293<={ou2ef80>>1,vv746d9[20]};eca4fe<={wlbe008>>1,vv746d9[21]};zm93f8a<={an80228>>1,vv746d9[22]};nefe29d<={kf8a22>>1,vv746d9[23]};ep8a75a<={db288ae>>1,vv746d9[24]};os53ad5<={uv44576>>1,vv746d9[25]};uk9d6a9<=vv746d9[26];jp5aa4a<={uxaed38>>1,vv746d9[27]};wya92bb<={yzb4e2a>>1,vv746d9[28]};vv4aec8<={tj38aaa>>1,vv746d9[29]};qvbb232<={zm2aaba>>1,vv746d9[30]};pfc8cad<={lfaae9f>>1,vv746d9[31]};rv32b79<={fpba7fa>>1,vv746d9[32]};fcade74<={ir9febd>>1,vv746d9[33]};xw79d14<={wwfaf69>>1,vv746d9[34]};icce8a3<=vv746d9[35];th74518<=vv746d9[36];hq14633<={tu691dd>>1,vv746d9[37]};qv18cd8<={vi4775b>>1,vv746d9[38]};yz33625<={dzdd6d8>>1,vv746d9[39]};fnd896e<={mr5b63a>>1,vv746d9[40]};fc25bb1<={vvd8ea0>>1,vv746d9[41]};bl6ec56<={ng3a837>>1,vv746d9[42]};irb15bb<={fpa0dd1>>1,vv746d9[43]};ww56ee4<={hd37476>>1,vv746d9[44]};hqb7721<={jrba3b7>>1,vv746d9[45]};qtdc85c<={lf8edf8>>1,vv746d9[46]};ec21723<={pub7e32>>1,vv746d9[47]};bab919<=vv746d9[48];me5c8ca<=vv746d9[49];fae4650<=vv746d9[50];vx1941c<={qi92f6f>>1,vv746d9[51]};dmca0e7<=vv746d9[52];jp5073b<=vv746d9[53];end +always@* begin wy2e8db[2047]<=hdatain[0];wy2e8db[2046]<=hread_n;wy2e8db[2044]<=hwrite_n;wy2e8db[2040]<=hcs_n;wy2e8db[2032]<=dzc2191;wy2e8db[2017]<=sw10140[0];wy2e8db[1987]<=cb80a01;wy2e8db[1963]<=qi92f6f[0];wy2e8db[1950]<=jrba3b7[0];wy2e8db[1926]<=ri99b0a[0];wy2e8db[1878]<=ks97b79;wy2e8db[1853]<=lf8edf8[0];wy2e8db[1839]<=vi4775b[0];wy2e8db[1818]<=kf8a22[0];wy2e8db[1804]<=vvcd852;wy2e8db[1708]<=pubdbc9;wy2e8db[1707]<=tj38aaa[0];wy2e8db[1658]<=pub7e32[0];wy2e8db[1630]<=dzdd6d8[0];wy2e8db[1614]<=en6fc49[0];wy2e8db[1589]<=db288ae[0];wy2e8db[1561]<=ba93361;wy2e8db[1511]<=fpa0dd1[0];wy2e8db[1483]<=fcbda47;wy2e8db[1394]<=wwfaf69[0];wy2e8db[1372]<=fpba7fa[0];wy2e8db[1367]<=zm2aaba[0];wy2e8db[1269]<=rvbf192;wy2e8db[1251]<=ou2ef80[0];wy2e8db[1212]<=mr5b63a[0];wy2e8db[1180]<=lqf126f[0];wy2e8db[1130]<=uv44576[0];wy2e8db[1074]<=qg56946;wy2e8db[1023]<=haddr[0];wy2e8db[981]<=qtc64bd;wy2e8db[975]<=hd37476[0];wy2e8db[919]<=tu691dd[0];wy2e8db[909]<=an80228[0];wy2e8db[853]<=yzb4e2a[0];wy2e8db[807]<=wy31bf1[0];wy2e8db[755]<=ng3a837[0];wy2e8db[741]<=zxd7b48;wy2e8db[697]<=ir9febd[0];wy2e8db[686]<=lfaae9f[0];wy2e8db[625]<=ui5cbbe;wy2e8db[490]<=off8c97;wy2e8db[454]<=wlbe008[0];wy2e8db[426]<=uxaed38[0];wy2e8db[403]<=zz28c6f;wy2e8db[377]<=vvd8ea0[0];wy2e8db[312]<=yk49bd2[0];wy2e8db[213]<=hd22bb4;wy2e8db[201]<=xla518d;wy2e8db[100]<=mtb4a31;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};ui43460<={jc63498>>1,vv746d9[1]};ie1a301<=vv746d9[2];ykd1808<=vv746d9[3];tw8c040<=vv746d9[4];ls1015<={nt6092>>1,vv746d9[5]};zx40554<={mg824ba>>1,vv746d9[6]};ec15534<={sw92e8c>>1,vv746d9[7]};mr54d0f<={lfba308>>1,vv746d9[8]};uk343e1<={hq8c238>>1,vv746d9[9]};wyf844<={gd8e17>>1,vv746d9[10]};vie1102<={vx385eb>>1,vv746d9[11]};wj4409d<={ir17af6>>1,vv746d9[12]};ir2763<={viebdaa>>1,vv746d9[13]};ie9d8ef<={ldf6a9d>>1,vv746d9[14]};blec778<=vv746d9[15];ho63bc7<=vv746d9[16];an1de3b<=vv746d9[17];meef1dc<=vv746d9[18];me78ee0<=vv746d9[19];end +always@* begin wy2e8db[2047]<=jc63498[0];wy2e8db[2046]<=rtd2610;wy2e8db[2044]<=mdi;wy2e8db[2040]<=ls20830;wy2e8db[2032]<=nt6092[0];wy2e8db[2016]<=mg824ba[0];wy2e8db[1985]<=sw92e8c[0];wy2e8db[1922]<=lfba308[0];wy2e8db[1867]<=byeed88;wy2e8db[1797]<=hq8c238[0];wy2e8db[1547]<=gd8e17[0];wy2e8db[1490]<=ea53bb6;wy2e8db[1047]<=vx385eb[0];wy2e8db[1023]<=ui4c693[0];wy2e8db[933]<=sw9ddb1;wy2e8db[745]<=lfaa776;wy2e8db[372]<=lfb54ee;wy2e8db[186]<=ldf6a9d[0];wy2e8db[93]<=viebdaa[0];wy2e8db[46]<=ir17af6[0];end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[0]};xl6c56<=vv746d9[1];ep362b6<=vv746d9[2];kfb15b5<=vv746d9[3];ec346dc<=vv746d9[4];ui56d64<=vv746d9[5];qib6b21<=vv746d9[6];zzb5908<=vv746d9[7];ukac847<=vv746d9[8];bl64238<={rxd_pos>>1,vv746d9[9]};co211c7<={rxd_neg>>1,vv746d9[10]};mt8e39<=vv746d9[11];by471cd<=vv746d9[12];ph38e6b<=vv746d9[13];zxc735f<=vv746d9[14];yz39aff<=vv746d9[15];thcd7fd<=vv746d9[16];dz6bfee<=vv746d9[17];zx5ff77<=vv746d9[18];icffbbf<=vv746d9[19];qtfddf8<=vv746d9[20];me77e2b<={ng83b46>>1,vv746d9[21]};enf8ac7<={ened194>>1,vv746d9[22]};aa2b1ea<={ay46528>>1,vv746d9[23]};blc7a82<={ph283b7>>1,vv746d9[24]};meea0b6<={doedfd>>1,vv746d9[25]};pf505b0<=vv746d9[26];co82d87<=vv746d9[27];tj16c38<=vv746d9[28];ieb61c7<=vv746d9[29];rvb0e39<=vv746d9[30];ie871cf<=vv746d9[31];tj38e79<=vv746d9[32];fnc73cf<=vv746d9[33];ux39e7f<=vv746d9[34];lqcf3fd<=vv746d9[35];dmcff5b<={qgf0b9c>>1,vv746d9[36]};en7fada<=vv746d9[37];kdfd6d4<=vv746d9[38];faeb6a4<=vv746d9[39];kd5b522<=vv746d9[40];psda914<=vv746d9[41];god48a3<=vv746d9[42];gda4518<=vv746d9[43];tj228c5<=vv746d9[44];swa317b<={qv9a85e>>1,vv746d9[45]};gd18bd8<=vv746d9[46];zm2f623<={pubd4d>>1,vv746d9[47]};pf7b11a<={wj5ea6a>>1,vv746d9[48]};zxd88d7<={kqf5355>>1,vv746d9[49]};eac46be<=vv746d9[50];ir235f0<=vv746d9[51];co1af84<=vv746d9[52];jpd7c21<=vv746d9[53];irbe10f<=vv746d9[54];suf087d<=vv746d9[55];tj843e9<=vv746d9[56];wy21f4e<=vv746d9[57];ksfa70<=vv746d9[58];end +always@* begin wy2e8db[2047]<=ph8edd2;wy2e8db[2046]<=vi76e96;wy2e8db[2044]<=tuf131a;wy2e8db[2040]<=tu58bae;wy2e8db[2033]<=rx_dv_pos;wy2e8db[2019]<=rx_dv_neg;wy2e8db[1994]<=uxd09a;wy2e8db[1990]<=rx_er_pos;wy2e8db[1981]<=dbbfa92;wy2e8db[1965]<=lf8b9eb;wy2e8db[1940]<=ic684d4;wy2e8db[1939]<=jebdab0;wy2e8db[1933]<=rx_er_neg;wy2e8db[1914]<=czfd496;wy2e8db[1883]<=os5cf5e;wy2e8db[1832]<=lq426a1;wy2e8db[1831]<=qt6ac1d;wy2e8db[1819]<=rxd_pos[0];wy2e8db[1785]<=zk73868;wy2e8db[1781]<=jc525a0;wy2e8db[1778]<=do11ded;wy2e8db[1740]<=ec15ef4;wy2e8db[1719]<=rv3d785;wy2e8db[1616]<=qv9a85e[0];wy2e8db[1615]<=ww560ed;wy2e8db[1591]<=rxd_neg[0];wy2e8db[1522]<=ri9c342;wy2e8db[1515]<=co92d02;wy2e8db[1508]<=jr8ef6a;wy2e8db[1470]<=cb85ce1;wy2e8db[1432]<=rvaf7a0;wy2e8db[1391]<=jcebc2e;wy2e8db[1286]<=kqf5355[0];wy2e8db[1271]<=ph283b7[0];wy2e8db[1184]<=osd42f5;wy2e8db[1182]<=ng83b46[0];wy2e8db[1135]<=sudbb02;wy2e8db[1051]<=vi4d540;wy2e8db[1023]<=hq11dba[0];wy2e8db[997]<=xwe1a13;wy2e8db[990]<=xyb7f52;wy2e8db[982]<=tw1173d;wy2e8db[969]<=yk77b56;wy2e8db[892]<=uk2e70d;wy2e8db[889]<=qv23bd;wy2e8db[870]<=ux2bde;wy2e8db[735]<=qgf0b9c[0];wy2e8db[643]<=wj5ea6a[0];wy2e8db[635]<=ay46528[0];wy2e8db[525]<=aaa9aa8;wy2e8db[495]<=doedfd[0];wy2e8db[444]<=thec08e;wy2e8db[435]<=zx4057b;wy2e8db[321]<=pubd4d[0];wy2e8db[317]<=ened194[0];wy2e8db[222]<=hbdd811;wy2e8db[217]<=doa80af;wy2e8db[108]<=pf55015;wy2e8db[54]<=sh6aa02;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6>1,vv746d9[1]};en5e01d<={hdatain>>1,vv746d9[2]};lf3b04<=vv746d9[3];oh80760<=vv746d9[4];suf00ec<=vv746d9[5];zk732ec<={tx_fifodata>>1,vv746d9[6]};vidf659<=vv746d9[7];vk99763<=vv746d9[8];cmcbb1b<=vv746d9[9];uvfd919<={tx_sndpaustim>>1,vv746d9[10]};ps63f64<=vv746d9[11];vi5d8d8<=vv746d9[12];hoc0b68<=vv746d9[13];gbf2dc6<=vv746d9[14];jccae98<={hod0a7b>>1,vv746d9[15]};zk574c2<=vv746d9[16];dbba612<=vv746d9[17];gq34f1d<={ri99b0a>>1,vv746d9[18]};zma78e9<=vv746d9[19];zxc25e1<={fada93f>>1,vv746d9[20]};yz12f0f<=vv746d9[21];wy9787d<=vv746d9[22];gqbc3e9<={rv27ec4>>1,vv746d9[23]};zke1f48<=vv746d9[24];iefa42<=vv746d9[25];qg7d210<=vv746d9[26];dze9080<=vv746d9[27];xw48407<=vv746d9[28];ho4203a<={qi3b78e>>1,vv746d9[29]};ie101d3<=vv746d9[30];an80e99<=vv746d9[31];gd74cd<=vv746d9[32];ba3a66d<=vv746d9[33];qtd336b<=vv746d9[34];hq99b5c<=vv746d9[35];thcdae2<=vv746d9[36];ea6d717<=vv746d9[37];hb6b8b9<=vv746d9[38];cm5c5cf<={zkfe481>>1,vv746d9[39]};ipe2e79<={alf240b>>1,vv746d9[40]};ir173cd<={co9205d>>1,vv746d9[41]};ukb9e6c<={an902e8>>1,vv746d9[42]};lqcf361<={ph81745>>1,vv746d9[43]};tu79b0b<={riba2e>>1,vv746d9[44]};fncd85b<={lq5d172>>1,vv746d9[45]};xw6c2df<={cze8b93>>1,vv746d9[46]};dz616fb<={nr45c9c>>1,vv746d9[47]};twb7df<={ec2e4e7>>1,vv746d9[48]};gb5befb<={ay72738>>1,vv746d9[49]};nedf7dd<={do939c1>>1,vv746d9[50]};nefbeea<={ls9ce0b>>1,vv746d9[51]};dmdf752<=vv746d9[52];lqfba92<={db382d4>>1,vv746d9[53]};pfdd492<=vv746d9[54];goea497<=vv746d9[55];rg524b8<=vv746d9[56];ou925c2<=vv746d9[57];qi92e10<=vv746d9[58];ks97081<=vv746d9[59];lsb8408<=vv746d9[60];pfc2042<=vv746d9[61];uk10217<={mt12115>>1,vv746d9[62]};tj810b9<={cb908ac>>1,vv746d9[63]};yz85ce<=vv746d9[64];ps42e74<=vv746d9[65];sj173a2<=vv746d9[66];wyb9d14<=vv746d9[67];ayce8a1<={fn64dc0>>1,vv746d9[68]};hb74508<={gd26e06>>1,vv746d9[69]};end +always@* begin wy2e8db[2047]<=haddr[0];wy2e8db[2046]<=hdatain[0];wy2e8db[2044]<=hcs_n;wy2e8db[2041]<=db382d4[0];wy2e8db[2040]<=hwrite_n;wy2e8db[2035]<=ayc16a6;wy2e8db[2033]<=hread_n;wy2e8db[2024]<=ead49fb;wy2e8db[2022]<=bab530;wy2e8db[2018]<=tx_fifodata[0];wy2e8db[2001]<=qva4fd8;wy2e8db[1997]<=th5a983;wy2e8db[1988]<=tx_fifoavail;wy2e8db[1954]<=rv27ec4[0];wy2e8db[1946]<=med4c1f;wy2e8db[1929]<=tx_fifoeof;wy2e8db[1874]<=ng890fe;wy2e8db[1860]<=ba3f627;wy2e8db[1851]<=fn64dc0[0];wy2e8db[1845]<=aaa60f8;wy2e8db[1811]<=tx_fifoempty;wy2e8db[1789]<=ri99b0a[0];wy2e8db[1721]<=cb908ac[0];wy2e8db[1700]<=fa487f2;wy2e8db[1673]<=psfb13b;wy2e8db[1655]<=gd26e06[0];wy2e8db[1643]<=ri307c0;wy2e8db[1574]<=tx_sndpaustim[0];wy2e8db[1530]<=vvcd852;wy2e8db[1486]<=ec15937;wy2e8db[1395]<=bn84564;wy2e8db[1353]<=su43f92;wy2e8db[1317]<=zkfe481[0];wy2e8db[1311]<=nr45c9c[0];wy2e8db[1299]<=zxd89db;wy2e8db[1258]<=hof1c48;wy2e8db[1247]<=hod0a7b[0];wy2e8db[1239]<=xwc0484;wy2e8db[1187]<=riba2e[0];wy2e8db[1172]<=co9205d[0];wy2e8db[1151]<=ay72738[0];wy2e8db[1102]<=nt276f1;wy2e8db[1101]<=tx_sndpausreq;wy2e8db[1023]<=reset_n;wy2e8db[1020]<=yxe705a;wy2e8db[1012]<=fada93f[0];wy2e8db[937]<=fn7121f;wy2e8db[925]<=ouac9b8;wy2e8db[894]<=kf29ed4;wy2e8db[860]<=mt12115[0];wy2e8db[743]<=lf22b26;wy2e8db[658]<=ou1fc90;wy2e8db[655]<=cze8b93[0];wy2e8db[629]<=wwde389;wy2e8db[623]<=ignore_pkt;wy2e8db[593]<=ph81745[0];wy2e8db[586]<=alf240b[0];wy2e8db[575]<=ec2e4e7[0];wy2e8db[551]<=eac4ede;wy2e8db[510]<=ls9ce0b[0];wy2e8db[468]<=jr8e243;wy2e8db[447]<=oh853da;wy2e8db[430]<=ep2422;wy2e8db[327]<=lq5d172[0];wy2e8db[314]<=eadbc71;wy2e8db[311]<=rx_fifo_full;wy2e8db[296]<=an902e8[0];wy2e8db[255]<=do939c1[0];wy2e8db[157]<=qi3b78e[0];wy2e8db[155]<=tx_fifoctrl;end assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6X*ncdl$xf6eXJ|Vl`_kC~P%)EJ1c5k(Ips>Eu ztElq$-)526FNe`pS?~Nsot@dabGoa%$ml%>2#WN!S9O<{FY+Sef13oQYktS^4pV6bq%?yfw_aIw&E&dF4c+dM!)>OyCe>P#ZLOPF)6$xn*yKeL=_CZ{ zwz~T2?Btr}mb%6UFA~3>K!vuZn#b3)W+qm9k>oo%9$1N=xyt0HnllqTZi9`=Q2fjn zj+{3HZlV$BqJpbY29qS3KLnnjJ%&Wc7&jEWc&TaYQ#^0;)sf^21(YyxlWp(r?w}ho{8bL*r7L=}%a>;7bkYBMj+-$ClBy_4BFnle zvK`CX7iJgtWP5t&_H@vHmu4%o<-|A&j508~=PX`Ex*eVK=4C5jB3s3bs=Tt%vvBdk zY{zUa;`q5ei?g#A2?vs(kdex4Hz@PwcFdnk+MQ&7Toj_^?VU^8v(WFQLiUZFI<>iK9~Me2^&&rEJ=EUIwYJ5h}$?M&P@rm0bEDj9X?RI!^Gsa26( zx}sMMBC=Htg}@fZ5O-{~&!)EO=)nLAl*U7eJR^tE`uf0Vmjj~)`fkeXMI6#;FsNiQ zvaHi?)tYEgF-BKyAchNK;Gs9t5ELs|jIHtcqLg;w+k~PFVWGCDoU1k=N(G3j@xTva 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zzzUQeq6rG2^azD2QF^RXY*i>V_CwVuZIck2j?&W>Yk5Ye7&<7}eNEh@WN@pnBM<|`G+O9`wAR*q5Q94i6`vj$LsVJYK zbg5IkpP_VxU(n|$E%FKa0;OfD?UyL65)-~cY1k|9Ym~-3f|4k$*983srSAjBlZX8&LXrK+r~%e(e{u38mjA1#L#@7KflMDBb20^c_l5UP0fZ^e0`=R+Rp# z3EGCzKRtr}i?RZ@pzSDY85FbwW%~vMrBHT2O3)7|JH#nyC(4fS3;Gdd#{T6el(kNX z?Prvoqzl@GveUeRenHt;s<&TJcCIG2-%xgbP|$9awHJWjQFfV2;2$V+2L%0zvMz2x zdr;O@7xWj(y89T>Ia8TO>J=2A>?UPvhO(Re;%$MlTM~j=qU=_WpuJEw)Gugnl-=PK zv=7QgDBHd$8>MWmP&Uya-u+N^zw+*nvZ)FkfU<{D;yn;$k1BK!%4P?}=0I6Mp@UKO zw2E>F%AQl`P?WvsmwJbx>=j+m;V65Qsy4a3GS*=3Hqil_e(i&y!eBwO;Wr?I9C(1rl=tPu#s_LDDvM=1?ZG$p3!U|4C z**AW%or*Fw!U|49*;du!bd>Gzi1!SX{pc2SCdzgxbT-QVQvIHT@`L>1ZHw|_9fHn9 z`SD3XE|j0>6m%ZS+h~H?q5QOfpz~3Fi9#2k{IZ1DE<|}pm!OMK-boj9G0MBBdhJnu zjZ$YpgMw&w(;*6tLB$b@%UDz#qtHF5XsuX{L&Zr7jYq|)3Qa)8nF>ur zMOzMsf_qVMUP90$RH&m>!F{Oc;1%2bsJL9A$*Ab0&=gc$6$GV%2T*aXLQ_$3y+VFe z^mK`L8Y+70f*wRgKL#jx2o(bZf~KRwr}}*u72_0o1Qqux^e8H(IHcYTR7_LoF;qOP z&`eZ3rqC=@%u#4IDxP#pi#e#67ZCI~D&{Ni6R3E>DYgJAUQ7sj5*4p0G#3@>+^66v zRJ`RC?>tl#rUX5Wie;+aGpJahi|tudto8_+kBSnPpyyCgmK5|nDndR%FQB5@EocEM zYE+aLQ4#Tq?Il#iQi5JaMV(&|%?n)T5%dbeEfsndVReiucn#qLeBxb*@WBebj_~2C z-kbDY3%7U|A>2AB=q-d#QfM*4r?CkIg$SSJ6|@B5wthiN5pJh!%MiZEA-3fRcVWO^ zs}J{b3tEBjOOIVij#DQGt$ZJmOCN8~(R z&>x6gkQDSMA|2d<_MmWrvi*g~6@r@4TY@|3>}^(nNEc;mMsMa8R&?7k(%m867KrrF z1hquu#()dR#x@)Lu5oiZ2KcJ$|dLkM8-M< z9f*iJ{x&-Zkx8na1Cc2{@g9uGG>@P|5SgA5bSNS-+=326WR^?N;V68@FX#wF0!cwf zA~H`GbQB`<6*?M`1wpYLgGf->jzwglLdPMpNO_N^?~3?Asab18G_Rl&5Lq1*u}dUzN8V3P%S(soD7`?9BkpE^ejzIK|c-(MeuG*CVR-#m#O&)UV?8pqCk{dLBd{ zRj4PTGn3My7ov}=dN(3ES9yCQ`m{nfA!;bp2hjy?Y0($amvuomBdU(h&H5p_*d@09 zh%QYE8i42ukD!5wsv~i;TM#W}6PgV|v_iEQjA)f6HZP*J%6lt)T}^q1AX=9c?`?>_ z?GQ8+(S$;`BlhoIO-Bl>$lkPp#4PC;W3D^T^uBG!UUXm$@`dnE;pL#&nZjz{bOHlf)B z#2jux6A?QkA?RMj4p;RiA$DX^Z1*8{ibv4>h@H*=%_bvuW>U};`bvUV&;y8F5D+vK zvGzVee#DHCI1RCm39&th*p-@~hY-6)*`_0Qow7ZQSdV~sA3^L!pP)w(>+2CT1F-?h z_84M=m2DsKx|b~ zYzq)8RZ(6?hq}ZzH%{pE|)rg}55(6}=LHuOD zpfKX6F+j6g#Em^`1o5+jVv8bvu2WD9@pcT*EKaZe@C#al_{9v+td8Dq;S^Ml_+>#s zYZ33LZ0qRt4QxWQw-N8+7xWI|*SH0}i}49md*gir0)})|M5g+Om^cmuJxCMQV_?^0-FAyK8Y+usj zu3oWyh4`4Hpsx`hr)){YC%VPT)7+cw1C)W!B+#232-ZAW~Gvh6^8c~ERA z#8)~6{eXCpL(opdOZyAan^i(e40QT2XByjIntM_bx+ zH8k5TkJB*vT^^-jL{Bhu)Cr*3pWsJm810cKW*E^~-yd$aHK*U^yCntDLlidz1<`XS zy}W{&%abkyo41e$TNt&J=U5o+1%7OW(cbcu3L|=E;7+I5_LXN)*wzaC$O)tUz)zSk z+Fu?hVRV2zKf>rhd0d3iLGpA6BZoW;!suXm_Jh$O@~8)+L*>a1Mu*9R9E|8$n?m|e z=m>dcgVB-lyaprs-BcavnjbCCX|U}Wc}9cLvGRNdBl_L+OFscLKVF{8VANWk$zXJX zJdeT1DbHdsqURpg%9?3@l00d_wl?x$1*4PYISNLn$YT?XPL-!57@Z~$MKC&Do`GO= zhCK4X=uCOSfzes=Km#Ls4(Vsr+d1;M0^8`Zr9V9c(EMC^7=e*Xo;_f6o;+&6sGU4n z!03GNg9MB&kmm*%T_}$UFuF*d3SdM}F`S?gK=bzUGytOx@+1JGOXMj4MwiMH0E{k^ z+5e0#mzn>Ju8>*(j5^AUe@1SZ?a!!_%=Bl}S!Ve&x>9ENGorh6uLcO9`BgHrpAp@q z3p&Mijm+q0TUVLQ&*)m2$*+4hWXm6`U8hR7^?Mz_ffdqzWLc0Hrp zWoA92VKS?p(H%0Qp3!ibP0#2~nMu!Rgv_F6beGJaXEah~&ojDPX3jGjC9~!kjg}en zjC?X%p3xYYDbHvuc$Pe)dt`<@qj54jp3!)j8P8~f%!+3;QD($5x>shyGnynb;Thd0 zv)~!sFEij7O_tg3jHbxUcSiKUO}(1{nopG(?~MF1+nv!gnd#2xL7C;w=pmWm&S<*K zZfEqc%xq`$h|Fqd^r*~eXEZ}*vom^3X0kJyDYMua&5{}HjAqO1bw+b!<~pOtW!5^Q zCuGJtBQ;x{(UUS$ozYzIEOkat$qaQy^JI29qo-wNI-_S~Ryw0+Wkx!q`7#@w(Q`5r zoze3$3!TvmG6S8_0-1fz=tY@%&gdnXbcWp+8E*TFN(8NDI1${D>WGs+n)lG)^p-jbQ*j26o*az=$RgPhS4nLW;EsmvT_ wv`l7=Gg>Y)#u;fcTb$7fnJLa_rOXm%v`S`(Gg>XP!x"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b000",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH1_CDR_MAX_RATE=>"2", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103, + CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103, + CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103, + CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103, + CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103, + CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103, + CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103, + CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103, + D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2), + D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5), + D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0), + D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3), + D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual, + D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103, + CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn, + D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103, + CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44, + D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44, + D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44, + D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44, + D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44, + CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6, + CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8, + CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c, + CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1), + CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3), + CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5), + CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7), + CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0), + CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66, + CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69, + CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73, + CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77, + CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81, + CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85, + CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89, + CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91, + CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c, + CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94, + CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s, + CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97, + CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c, + CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100, + CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19, + D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23, + D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29, + D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35, + D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40, + D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n103 <= '0' ; + n102 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n112 <= 'Z' ; + rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122, + rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122, + rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122, + rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116, + rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n111 <= '1' ; + n110 <= '0' ; + n122 <= '0' ; + n121 <= '1' ; + n113 <= 'Z' ; + n114 <= 'Z' ; + n115 <= 'Z' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n124 <= '1' ; + n123 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_ngd.asd b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v new file mode 100644 index 0000000..69a023d --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module sgmii_ecp5rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_ecp5sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/.recordref b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_CMD_.CML b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_CMD_.CML new file mode 100644 index 0000000..9b9aad5 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs -top sgmii_ecp5 -hdllog /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/ -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib -v2001 -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -lib work /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_cmd._cml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_cmd._cml new file mode 100644 index 0000000..369b52b --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top sgmii_ecp5 -osyn /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.srs \ No newline at end of file diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/dm/layer0.xdm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..44e72f3 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/dm/layer0.xdm @@ -0,0 +1,551 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +SS1SS1SS1S +SF<1kCsOR"b=/lEFCF/#VD0/NH00O8C/HFNlMd8/3_4jG/nc#b$MLCN#/LDH/8PE/bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S> 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+1,76 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/run_options.txt +#-- Written on Fri May 10 11:58:54 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "sgmii_ecp5" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./sgmii_ecp5.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf" +impl -active "syn_results" diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scemi_cfg.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs new file mode 100644 index 0000000..b221cbd --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs @@ -0,0 +1,74 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "sgmii_ecp5" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf" +impl -active "syn_results" diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr new file mode 100644 index 0000000..270aaa7 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr @@ -0,0 +1,97 @@ +---------------------------------------------------------------------- +Report for cell sgmii_ecp5.v1 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + CCU2C 113 100.0 + DCUA 1 100.0 + FD1P3BX 20 100.0 + FD1P3DX 92 100.0 + FD1S3BX 12 100.0 + FD1S3DX 97 100.0 + GSR 1 100.0 + INV 3 100.0 + ORCALUT4 153 100.0 + PFUMX 2 100.0 + PUR 1 100.0 + VHI 6 100.0 + VLO 6 100.0 +SUB MODULES + sgmii_ecp5rsl_core_Z2_layer1 1 100.0 + sgmii_ecp5sll_core_Z1_layer1 1 100.0 + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 512 +---------------------------------------------------------------------- +Report for cell sgmii_ecp5rsl_core_Z2_layer1.netlist + Instance path: rsl_inst + Cell usage: + cell count Res Usage(%) + CCU2C 51 45.1 + FD1P3BX 4 20.0 + FD1P3DX 74 80.4 + FD1S3BX 12 100.0 + FD1S3DX 37 38.1 + ORCALUT4 99 64.7 + PFUMX 2 100.0 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 281 +---------------------------------------------------------------------- +Report for cell sgmii_ecp5sll_core_Z1_layer1.netlist + Instance path: sll_inst + Cell usage: + cell count Res Usage(%) + CCU2C 62 54.9 + FD1P3BX 16 80.0 + FD1P3DX 18 19.6 + FD1S3DX 60 61.9 + INV 3 100.0 + ORCALUT4 54 35.3 + VHI 4 66.7 + VLO 4 66.7 +SUB MODULES + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 224 +---------------------------------------------------------------------- +Report for cell sync_0s_0.netlist + Original Cell name sync_0s + Instance path: sll_inst.pdiff_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s_6.netlist + Original Cell name sync_0s + Instance path: sll_inst.rtc_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s.netlist + Original Cell name sync_0s + Instance path: sll_inst.phb_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.fse b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.fse new file mode 100644 index 0000000..cc147f0 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.fse @@ -0,0 +1,12 @@ + +fsm_encoding {61801018011} sequential + +fsm_state_encoding {61801018011} LPLL_LOSS_ST {00} + +fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01} + +fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10} + +fsm_state_encoding {61801018011} LPLL_LOCK_ST {11} + +fsm_registers {61801018011} {sll_state[1]} {sll_state[0]} diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.htm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.htm new file mode 100644 index 0000000..31d89ed --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.htm @@ -0,0 +1,9 @@ + + + syntmp/sgmii_ecp5_srr.htm log file + + + + + + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj new file mode 100644 index 0000000..ef8c3fe --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj @@ -0,0 +1,47 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj +#-- Written on Fri May 10 11:58:54 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -constraint {"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc"} + +#-- top module name +set_option -top_module sgmii_ecp5 + +#-- set result format/file last +project -result_file "sgmii_ecp5.edn" + +#-- error message log file +project -log_file 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uFcr64Cl;2s_1c1YFeM4VoBsy@0RR8ua!}v`00030{{sN(WK}5mfCT^vCytT; literal 0 HcmV?d00001 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf new file mode 100644 index 0000000..a063791 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf @@ -0,0 +1,1144 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 11:58:54 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000010011 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111 + PPCLK_TC=32'b00000000000000010000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:57 2019 + +###########################################################] +Pre-mapping Report + +# Fri May 10 11:58:57 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 11:58:58 2019 + +###########################################################] +Map & Optimize Report + +# Fri May 10 11:58:58 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.36ns 154 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 11:59:02 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.184 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.700 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +======================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[7] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[7] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[7] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 153 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 11:59:02 2019 + +###########################################################] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srm new file mode 100644 index 0000000000000000000000000000000000000000..bacca77869981b665c22adfb6d504b929f58e1d7 GIT binary patch literal 31347 zcmaI7cT`hP&^NB4pj4IKMUdWm4JuXXBE3uRASDS^1VQOV=>(+r-bv`ah28>$-a~-U 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z)(1uVKW%SfN12``S^pe=CosjCa-71QX$Kul5A8YmHW1Q%Dd@i-&k=954f-7c|6b-C zXFxzJ@F2whTd@0j=z)XtD%x~-&FDLt{A>o(uS4hFQ_?n0ssI2|NjF3 LeHchIs-*z{BHI1d literal 0 HcmV?d00001 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr new file mode 100644 index 0000000..a063791 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr @@ -0,0 +1,1144 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 11:58:54 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000010011 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111 + PPCLK_TC=32'b00000000000000010000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:57 2019 + +###########################################################] +Pre-mapping Report + +# Fri May 10 11:58:57 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 11:58:58 2019 + +###########################################################] +Map & Optimize Report + +# Fri May 10 11:58:58 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.36ns 154 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 11:59:02 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.184 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.700 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +======================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[7] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[7] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[7] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 153 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 11:59:02 2019 + +###########################################################] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..26e7e9585d11b6aa8d19cde718e5ee796ef31ef8 GIT binary patch literal 40960 zcmeHQU2q)PRi4r4-x|&C+K%xWvv;-GU2CyN-90@cX}k-OwUTjSt$!rP>y@3R)qQ8C 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    xdK4^MW~B?+FkvMCk*T(zZ?=|Imxp5&;&t@`wF^+O*u`B%;lHsdP# z5F`krC-ezpS&fYkv~NMbvi9gj$K@ZTT7JxJ6iMm}WSB(KA{SGdF6EB&mkiXYW(vQg zJ5@1@3Nq?7BidR;9$fT`YGzYGUF15^DluN+o%|K=ewDY@#yd5`FNxyg7xNmQC!7C5 z_5#0Ec5?w=U8x>NRoTCA&*HLc?XpYeSF7G4{m`mY{V6|Z+4K|X-};HvgwJ5Ba=U1a ze57Wy%f4`UoUFzc;h3TDXH6fJ%MnBU3D2q!UB*`S1Y1G9jGaFpg-PLn-g*$^uv_t8Q^LIcMCX@r-;t|1KiXneH%;_`?ENC1wz_%HBR%W>Y}PmWRzILlKHqD5 zk&gS<&+X_KsRz9gOFErO5DwY2s+SXw=_>jX)Fk7%LDRGv9~IRme64cX>UjESs^a2a zrd_@6yEtd+$m_JfYE}8Zwk!0vf>(V_$LW_YubygqBjI4|2;JkQ4h|}MX7s{+I!)_y z(PyTI2eY=PI-q4@$g43SWTC{ydnqzJc)2ZzFRHhfy}Ym^=B9`SE&L52HW66VI)l$2sc5 zsMjvqMUHV#sDH?dC_Zh18!#Sdl`$)ak;_)TD*Lo_X|K9BNOf3C`FEui0b535i z4ceyq@g*eD^d&U6HQLykQM|8SrjdDy>l)5`^pB4=T5@zegzxpdiMja;^T6>#d#}aK zS+?ZZ{Rio3aXEgx96w^6K=A0AT0>s*cucCbO~D%*^DSqza#S3H_a6mjnJ=DJR%I!76FU!nNgvN#DCo`ux4rWHykK zgnkYO#n7~cJrMaju>VrH-1k=w3pe84wOk0qxNp;K5@6OpYz=&NZE05cz#P}!+hLCP zsB}cIT{aXI{@D?gM_0_>^&i?-weuJ>ZpXnDy`M*)V&~B|TyWt*ru*UioVWcbx~Jz- zwXx#9+0d}~xoM)sg4m_|E3)-A7^XMgZ%M-ciuvL`k!SI9*C?M8+qN@2ouA;oK)?Sb z!kXUr1{V81F1{PYF@JtX&%#0_i06hoKgsj}zP)xlJBY7BWA4uR^CJZFZPZg3T*b7m z0F=;;jrqeI{Iv~UU^`bv7`rf^6F$EWhdkU3-T51XA1YQ%cd6*PmI48b?a-ztVTz@= zp|_8VXTi5&m)nqje~R01vE(+S_sD-`Ll*bN(uQ)~hV&Z=CmS+Ya~skFy4;5J8!YE{ z;rZ_th{5pU9fb8Gb1T=w;2k$a}@PzI3^kB zePfcn@&3_Ux)|KhdH&?L{BQglyO4?fJDFHrCW0@1N9hg3Hu&=FW&vNEH~a-W9h~F- zL-0trX)|tzrfnYs)P>(2*0VD>U;Hr zw}r-Te&fISP{5HNIk_#^(75LQNxu#8c%92zeXpgB<{M}@rv29TK3OjN`8OIC0na1# z-yM+O2ES=HoG-n%e!~4_?(pM#mnpfP;xKmT9yrMxUx)XK@ABWP2o3siMn^g6Ftp DATA_P1, + CK => pll_refclki, + CD => sli_rst, + Q => pdiff_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => ppul_sync, + CK => pll_refclki, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_6 is +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic); +end sync_0s_6; + +architecture beh of sync_0s_6 is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => tx_pclk, + CD => sli_rst, + Q => ppul_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => rtc_pul, + CK => tx_pclk, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s is +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic); +end sync_0s; + +architecture beh of sync_0s is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN_0 : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN_0 : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( +D => DATA_P1, +CK => pll_refclki, +CD => sli_rst, +Q => rhb_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( +D => phb, +CK => pll_refclki, +CD => sli_rst, +Q => DATA_P1); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5rsl_core_Z2_layer1 is +port( +rx_pcs_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rsl_disable : in std_logic; +rx_serdes_rst_c : in std_logic; +rst_dual_c : in std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic); +end sgmii_ecp5rsl_core_Z2_layer1; + +architecture beh of sgmii_ecp5rsl_core_Z2_layer1 is +signal RXS_CNT : std_logic_vector(1 downto 0); +signal RXS_CNT_3 : std_logic_vector(1 downto 0); +signal RXPR_APPD_RNO : std_logic_vector(0 to 0); +signal PLOL0_CNT : std_logic_vector(2 downto 0); +signal PLOL0_CNT_3 : std_logic_vector(2 downto 0); +signal RXSR_APPD : std_logic_vector(0 to 0); +signal RXS_CNT_QN : std_logic_vector(1 downto 0); +signal RLOS_DB_CNT : std_logic_vector(3 downto 0); +signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOLS0_CNT_S : std_logic_vector(17 downto 0); +signal RLOLS0_CNT : std_logic_vector(17 downto 0); +signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0); +signal RLOL_DB_CNT : std_logic_vector(3 downto 0); +signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOL1_CNT_S : std_logic_vector(18 downto 0); +signal RLOL1_CNT : std_logic_vector(18 downto 0); +signal RLOL1_CNT_QN : std_logic_vector(18 downto 0); +signal RXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal RXR_WT_CNT : std_logic_vector(11 downto 0); +signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal RXSR_APPD_QN : std_logic_vector(0 to 0); +signal RXPR_APPD : std_logic_vector(0 to 0); +signal RXPR_APPD_QN : std_logic_vector(0 to 0); +signal TXS_CNT : std_logic_vector(1 downto 0); +signal TXS_CNT_QN : std_logic_vector(1 downto 0); +signal TXS_CNT_RNO : std_logic_vector(1 to 1); +signal TXP_CNT : std_logic_vector(1 downto 0); +signal TXP_CNT_QN : std_logic_vector(1 downto 0); +signal TXP_CNT_RNO : std_logic_vector(1 to 1); +signal PLOL_CNT_S : std_logic_vector(19 downto 0); +signal PLOL_CNT : std_logic_vector(19 downto 0); +signal PLOL_CNT_QN : std_logic_vector(19 downto 0); +signal PLOL0_CNT_QN : std_logic_vector(2 downto 0); +signal TXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal TXR_WT_CNT : std_logic_vector(11 downto 0); +signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal TXPR_APPD : std_logic_vector(0 to 0); +signal TXPR_APPD_QN : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17); +signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal PLOL_CNT_CRY : std_logic_vector(18 downto 0); +signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19); +signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19); +signal RXS_RST : std_logic ; +signal VCC : std_logic ; +signal RSL_SERDES_RST_DUAL_C_10 : std_logic ; +signal RSL_RX_SERDES_RST_C_9 : std_logic ; +signal RLOS_DB_P1 : std_logic ; +signal RLOS_DB : std_logic ; +signal RXP_RST25 : std_logic ; +signal RLOL_DB : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ; +signal PLOL0_CNT9 : std_logic ; +signal WAITA_PLOL0 : std_logic ; +signal RX_ANY_RST : std_logic ; +signal UN3_RX_ALL_WELL_2 : std_logic ; +signal UN17_RXR_WT_TC : std_logic ; +signal RX_ALL_WELL : std_logic ; +signal UN3_RX_ALL_WELL_1 : std_logic ; +signal RXR_WT_CNT9 : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_I : std_logic ; +signal RLOL1_CNT_TC_1 : std_logic ; +signal \RLOL1_CNT_\ : std_logic ; +signal RXR_WT_EN : std_logic ; +signal RXR_WT_CNTE : std_logic ; +signal UN18_TXR_WT_TC : std_logic ; +signal TX_ANY_RST : std_logic ; +signal PLL_LOL_P2 : std_logic ; +signal UN2_PLOL_FEDGE_5_I : std_logic ; +signal N_2160_0 : std_logic ; +signal WAITA_RLOLS06 : std_logic ; +signal UN1_RLOLS0_CNT_TC : std_logic ; +signal WAITA_RLOLS0 : std_logic ; +signal WAITA_RLOLS0_QN : std_logic ; +signal WAIT_CALIB_RNO : std_logic ; +signal UN1_RLOS_FEDGE_1 : std_logic ; +signal WAIT_CALIB : std_logic ; +signal WAIT_CALIB_QN : std_logic ; +signal RXS_RST6 : std_logic ; +signal UN1_RXS_CNT_TC : std_logic ; +signal RXS_RST_QN : std_logic ; +signal UN2_RLOS_REDGE_1_I : std_logic ; +signal RXP_RST2 : std_logic ; +signal RXP_RST2_QN : std_logic ; +signal RLOS_P1 : std_logic ; +signal RLOS_P2 : std_logic ; +signal RLOS_P2_QN : std_logic ; +signal RLOS_P1_QN : std_logic ; +signal RLOS_DB_P1_QN : std_logic ; +signal RLOS_DB_CNT_AXB_0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOS_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOS_DB_CNT_MAX : std_logic ; +signal RLOS_DB_QN : std_logic ; +signal RLOLS0_CNTE : std_logic ; +signal RLOL_P1 : std_logic ; +signal RLOL_P2 : std_logic ; +signal RLOL_P2_QN : std_logic ; +signal RLOL_P1_QN : std_logic ; +signal RLOL_DB_P1 : std_logic ; +signal RLOL_DB_P1_QN : std_logic ; +signal RLOL_DB_CNT_AXB_0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOL_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOL_DB_CNT_MAX : std_logic ; +signal RLOL_DB_QN : std_logic ; +signal RLOL1_CNTE : std_logic ; +signal RXSDR_APPD_2 : std_logic ; +signal RXSDR_APPD : std_logic ; +signal RXSDR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ; +signal RXR_WT_EN_QN : std_logic ; +signal RXDPR_APPD : std_logic ; +signal RXDPR_APPD_QN : std_logic ; +signal RSL_RX_RDY_8 : std_logic ; +signal RUO_RX_RDYR_QN : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ; +signal PLOL_FEDGE : std_logic ; +signal UN1_PLOL0_CNT_TC_1_I : std_logic ; +signal WAITA_PLOL0_QN : std_logic ; +signal UN1_PLOL_CNT_TC : std_logic ; +signal UN2_PLOL_CNT_TC : std_logic ; +signal TXS_RST : std_logic ; +signal TXS_RST_QN : std_logic ; +signal N_10_I : std_logic ; +signal UN9_PLOL0_CNT_TC : std_logic ; +signal UN1_PLOL0_CNT_TC_1 : std_logic ; +signal TXP_RST : std_logic ; +signal TXP_RST_QN : std_logic ; +signal N_11_I : std_logic ; +signal PLL_LOL_P3 : std_logic ; +signal PLL_LOL_P3_QN : std_logic ; +signal PLL_LOL_P1 : std_logic ; +signal PLL_LOL_P2_QN : std_logic ; +signal PLL_LOL_P1_QN : std_logic ; +signal TXSR_APPD_2 : std_logic ; +signal TXSR_APPD : std_logic ; +signal TXSR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ; +signal TXR_WT_EN : std_logic ; +signal TXR_WT_EN_QN : std_logic ; +signal TXR_WT_CNTE : std_logic ; +signal UN2_PLOL_FEDGE_2 : std_logic ; +signal UN2_PLOL_FEDGE_3_I : std_logic ; +signal TXDPR_APPD : std_logic ; +signal TXDPR_APPD_QN : std_logic ; +signal UN2_PLOL_FEDGE_5_1 : std_logic ; +signal RSL_TX_RDY_7 : std_logic ; +signal RUO_TX_RDYR_QN : std_logic ; +signal UN2_PLOL_FEDGE_8_I : std_logic ; +signal RLOLS0_CNT_TC_1 : std_logic ; +signal RLOS_REDGE : std_logic ; +signal RLOLS0_CNT11_0 : std_logic ; +signal RSL_TX_SERDES_RST_C_6 : std_logic ; +signal \PLOL_CNT_\ : std_logic ; +signal \RLOLS0_CNT_\ : std_logic ; +signal UN8_RXS_CNT_TC : std_logic ; +signal UN1_TXSR_APPD : std_logic ; +signal UN1_DUAL_OR_RSERD_RST_2_0 : std_logic ; +signal UN1_RXSDR_OR_SR_APPD : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_1_1 : std_logic ; +signal RLOLS0_CNT_TC_1_10 : std_logic ; +signal RLOLS0_CNT_TC_1_11 : std_logic ; +signal RLOLS0_CNT_TC_1_12 : std_logic ; +signal RLOLS0_CNT_TC_1_13 : std_logic ; +signal RLOL1_CNT_TC_1_11 : std_logic ; +signal RLOL1_CNT_TC_1_12 : std_logic ; +signal RLOL1_CNT_TC_1_13 : std_logic ; +signal RLOL1_CNT_TC_1_14 : std_logic ; +signal UN1_PLOL_CNT_TC_11 : std_logic ; +signal UN1_PLOL_CNT_TC_12 : std_logic ; +signal UN1_PLOL_CNT_TC_13 : std_logic ; +signal UN1_PLOL_CNT_TC_14 : std_logic ; +signal CO0_2 : std_logic ; +signal TXSR_APPD_4 : std_logic ; +signal RSL_TX_PCS_RST_C_5 : std_logic ; +signal UN17_RXR_WT_TC_6 : std_logic ; +signal UN17_RXR_WT_TC_7 : std_logic ; +signal UN17_RXR_WT_TC_8 : std_logic ; +signal RSL_RX_PCS_RST_C_4 : std_logic ; +signal UN18_TXR_WT_TC_6 : std_logic ; +signal UN18_TXR_WT_TC_7 : std_logic ; +signal UN18_TXR_WT_TC_8 : std_logic ; +signal RXSDR_APPD_4 : std_logic ; +signal RLOLS0_CNT_TC_1_9 : std_logic ; +signal UN1_PLOL_CNT_TC_10 : std_logic ; +signal RLOL1_CNT_TC_1_10 : std_logic ; +signal \TXR_WT_CNT_\ : std_logic ; +signal RLOS_DB_CNT_CRY_0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOS_DB_CNT_CRY_2 : std_logic ; +signal RLOS_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOS_DB_CNT_S_3_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_2 : std_logic ; +signal RLOL_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOL_DB_CNT_S_3_0_S1 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_6 : std_logic ; +signal N_7 : std_logic ; +begin +\GENBLK2.RXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"2626" +) +port map ( +A => RXS_RST, +B => RXS_CNT(0), +C => RXS_CNT(1), +D => VCC, +Z => RXS_CNT_3(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => RSL_RX_SERDES_RST_C_9, +C => rx_los_low_s, +D => rx_cdr_lol_s, +Z => RXPR_APPD_RNO(0)); +\GENBLK2.RXP_RST2_RNO\: LUT4 +generic map( + init => X"EFEE" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => RSL_RX_SERDES_RST_C_9, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => RXP_RST25); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => RSL_RX_SERDES_RST_C_9, +C => RLOS_DB, +D => RLOL_DB, +Z => UN1_RUI_RST_DUAL_C_1_1); +\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 +generic map( + init => X"1222" +) +port map ( +A => PLOL0_CNT(1), +B => PLOL0_CNT9, +C => WAITA_PLOL0, +D => PLOL0_CNT(0), +Z => PLOL0_CNT_3(1)); +\GENBLK2.GENBLK3.RUO_RX_RDYR_RNO\: LUT4 +generic map( + init => X"0101" +) +port map ( +A => RX_ANY_RST, +B => RLOS_DB, +C => RLOL_DB, +D => VCC, +Z => UN3_RX_ALL_WELL_2); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0100" +) +port map ( +A => UN17_RXR_WT_TC, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_RX_SERDES_RST_C_9, +D => RX_ALL_WELL, +Z => UN3_RX_ALL_WELL_1); +RX_ANY_RST_RNIFD021: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RX_ANY_RST, +B => UN17_RXR_WT_TC, +C => RLOS_DB, +D => RLOL_DB, +Z => RXR_WT_CNT9); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO_0\: LUT4 +generic map( + init => X"FEFF" +) +port map ( +A => rst_dual_c, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_RX_SERDES_RST_C_9, +D => RX_ALL_WELL, +Z => UN1_RUI_RST_DUAL_C_1_I); +\GENBLK2.RLOS_DB_P1_RNIS0OP\: LUT4 +generic map( + init => X"1011" +) +port map ( +A => RLOL1_CNT_TC_1, +B => RXS_RST, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => \RLOL1_CNT_\); +\GENBLK2.GENBLK3.RXR_WT_EN_RNIQF0H1\: LUT4 +generic map( + init => X"FFEF" +) +port map ( +A => RXR_WT_EN, +B => RX_ANY_RST, +C => RX_ALL_WELL, +D => UN17_RXR_WT_TC, +Z => RXR_WT_CNTE); +\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => UN18_TXR_WT_TC, +B => TX_ANY_RST, +C => PLL_LOL_P2, +D => VCC, +Z => UN2_PLOL_FEDGE_5_I); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RXSR_APPD(0), +B => rx_serdes_rst_c, +C => RXS_RST, +D => rsl_disable, +Z => N_2160_0); +\GENBLK2.WAITA_RLOLS0_REG_Z616\: FD1P3DX port map ( +D => WAITA_RLOLS06, +SP => UN1_RLOLS0_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => WAITA_RLOLS0); +\GENBLK2.WAIT_CALIB_REG_Z618\: FD1P3BX port map ( +D => WAIT_CALIB_RNO, +SP => UN1_RLOS_FEDGE_1, +CK => rxrefclk, +PD => rsl_rst, +Q => WAIT_CALIB); +\GENBLK2.RXS_RST_REG_Z620\: FD1P3DX port map ( +D => RXS_RST6, +SP => UN1_RXS_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_RST); +\GENBLK2.RXS_CNT[0]_REG_Z622\: FD1S3DX port map ( +D => RXS_CNT_3(0), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(0)); +\GENBLK2.RXS_CNT[1]_REG_Z624\: FD1S3DX port map ( +D => RXS_CNT_3(1), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(1)); +\GENBLK2.RXP_RST2_REG_Z626\: FD1P3BX port map ( +D => RXP_RST25, +SP => UN2_RLOS_REDGE_1_I, +CK => rxrefclk, +PD => rsl_rst, +Q => RXP_RST2); +\GENBLK2.RLOS_P2_REG_Z628\: FD1S3DX port map ( +D => RLOS_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P2); +\GENBLK2.RLOS_P1_REG_Z630\: FD1S3DX port map ( +D => rx_los_low_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P1); +\GENBLK2.RLOS_DB_P1_REG_Z632\: FD1S3BX port map ( +D => RLOS_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_P1); +\GENBLK2.RLOS_DB_CNT[0]_REG_Z634\: FD1S3BX port map ( +D => RLOS_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(0)); +\GENBLK2.RLOS_DB_CNT[1]_REG_Z636\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(1)); +\GENBLK2.RLOS_DB_CNT[2]_REG_Z638\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(2)); +\GENBLK2.RLOS_DB_CNT[3]_REG_Z640\: FD1S3BX port map ( +D => RLOS_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(3)); +\GENBLK2.RLOS_DB_REG_Z642\: FD1P3BX port map ( +D => RLOS_DB_CNT(1), +SP => UN1_RLOS_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB); +\GENBLK2.RLOLS0_CNT[0]_REG_Z644\: FD1P3DX port map ( +D => RLOLS0_CNT_S(0), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(0)); +\GENBLK2.RLOLS0_CNT[1]_REG_Z646\: FD1P3DX port map ( +D => RLOLS0_CNT_S(1), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(1)); +\GENBLK2.RLOLS0_CNT[2]_REG_Z648\: FD1P3DX port map ( +D => RLOLS0_CNT_S(2), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(2)); +\GENBLK2.RLOLS0_CNT[3]_REG_Z650\: FD1P3DX port map ( +D => RLOLS0_CNT_S(3), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(3)); +\GENBLK2.RLOLS0_CNT[4]_REG_Z652\: FD1P3DX port map ( +D => RLOLS0_CNT_S(4), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(4)); +\GENBLK2.RLOLS0_CNT[5]_REG_Z654\: FD1P3DX port map ( +D => RLOLS0_CNT_S(5), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(5)); +\GENBLK2.RLOLS0_CNT[6]_REG_Z656\: FD1P3DX port map ( +D => RLOLS0_CNT_S(6), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(6)); +\GENBLK2.RLOLS0_CNT[7]_REG_Z658\: FD1P3DX port map ( +D => RLOLS0_CNT_S(7), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(7)); +\GENBLK2.RLOLS0_CNT[8]_REG_Z660\: FD1P3DX port map ( +D => RLOLS0_CNT_S(8), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(8)); +\GENBLK2.RLOLS0_CNT[9]_REG_Z662\: FD1P3DX port map ( +D => RLOLS0_CNT_S(9), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(9)); +\GENBLK2.RLOLS0_CNT[10]_REG_Z664\: FD1P3DX port map ( +D => RLOLS0_CNT_S(10), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(10)); +\GENBLK2.RLOLS0_CNT[11]_REG_Z666\: FD1P3DX port map ( +D => RLOLS0_CNT_S(11), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(11)); +\GENBLK2.RLOLS0_CNT[12]_REG_Z668\: FD1P3DX port map ( +D => RLOLS0_CNT_S(12), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(12)); +\GENBLK2.RLOLS0_CNT[13]_REG_Z670\: FD1P3DX port map ( +D => RLOLS0_CNT_S(13), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(13)); +\GENBLK2.RLOLS0_CNT[14]_REG_Z672\: FD1P3DX port map ( +D => RLOLS0_CNT_S(14), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(14)); +\GENBLK2.RLOLS0_CNT[15]_REG_Z674\: FD1P3DX port map ( +D => RLOLS0_CNT_S(15), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(15)); +\GENBLK2.RLOLS0_CNT[16]_REG_Z676\: FD1P3DX port map ( +D => RLOLS0_CNT_S(16), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(16)); +\GENBLK2.RLOLS0_CNT[17]_REG_Z678\: FD1P3DX port map ( +D => RLOLS0_CNT_S(17), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(17)); +\GENBLK2.RLOL_P2_REG_Z680\: FD1S3DX port map ( +D => RLOL_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P2); +\GENBLK2.RLOL_P1_REG_Z682\: FD1S3DX port map ( +D => rx_cdr_lol_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P1); +\GENBLK2.RLOL_DB_P1_REG_Z684\: FD1S3BX port map ( +D => RLOL_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_P1); +\GENBLK2.RLOL_DB_CNT[0]_REG_Z686\: FD1S3BX port map ( +D => RLOL_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(0)); +\GENBLK2.RLOL_DB_CNT[1]_REG_Z688\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(1)); +\GENBLK2.RLOL_DB_CNT[2]_REG_Z690\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(2)); +\GENBLK2.RLOL_DB_CNT[3]_REG_Z692\: FD1S3BX port map ( +D => RLOL_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(3)); +\GENBLK2.RLOL_DB_REG_Z694\: FD1P3BX port map ( +D => RLOL_DB_CNT(1), +SP => UN1_RLOL_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB); +\GENBLK2.RLOL1_CNT[0]_REG_Z696\: FD1P3DX port map ( +D => RLOL1_CNT_S(0), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(0)); +\GENBLK2.RLOL1_CNT[1]_REG_Z698\: FD1P3DX port map ( +D => RLOL1_CNT_S(1), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(1)); +\GENBLK2.RLOL1_CNT[2]_REG_Z700\: FD1P3DX port map ( +D => RLOL1_CNT_S(2), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(2)); +\GENBLK2.RLOL1_CNT[3]_REG_Z702\: FD1P3DX port map ( +D => RLOL1_CNT_S(3), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(3)); +\GENBLK2.RLOL1_CNT[4]_REG_Z704\: FD1P3DX port map ( +D => RLOL1_CNT_S(4), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(4)); +\GENBLK2.RLOL1_CNT[5]_REG_Z706\: FD1P3DX port map ( +D => RLOL1_CNT_S(5), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(5)); +\GENBLK2.RLOL1_CNT[6]_REG_Z708\: FD1P3DX port map ( +D => RLOL1_CNT_S(6), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(6)); +\GENBLK2.RLOL1_CNT[7]_REG_Z710\: FD1P3DX port map ( +D => RLOL1_CNT_S(7), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(7)); +\GENBLK2.RLOL1_CNT[8]_REG_Z712\: FD1P3DX port map ( +D => RLOL1_CNT_S(8), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(8)); +\GENBLK2.RLOL1_CNT[9]_REG_Z714\: FD1P3DX port map ( +D => RLOL1_CNT_S(9), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(9)); +\GENBLK2.RLOL1_CNT[10]_REG_Z716\: FD1P3DX port map ( +D => RLOL1_CNT_S(10), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(10)); +\GENBLK2.RLOL1_CNT[11]_REG_Z718\: FD1P3DX port map ( +D => RLOL1_CNT_S(11), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(11)); +\GENBLK2.RLOL1_CNT[12]_REG_Z720\: FD1P3DX port map ( +D => RLOL1_CNT_S(12), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(12)); +\GENBLK2.RLOL1_CNT[13]_REG_Z722\: FD1P3DX port map ( +D => RLOL1_CNT_S(13), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(13)); +\GENBLK2.RLOL1_CNT[14]_REG_Z724\: FD1P3DX port map ( +D => RLOL1_CNT_S(14), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(14)); +\GENBLK2.RLOL1_CNT[15]_REG_Z726\: FD1P3DX port map ( +D => RLOL1_CNT_S(15), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(15)); +\GENBLK2.RLOL1_CNT[16]_REG_Z728\: FD1P3DX port map ( +D => RLOL1_CNT_S(16), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(16)); +\GENBLK2.RLOL1_CNT[17]_REG_Z730\: FD1P3DX port map ( +D => RLOL1_CNT_S(17), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(17)); +\GENBLK2.RLOL1_CNT[18]_REG_Z732\: FD1P3DX port map ( +D => RLOL1_CNT_S(18), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(18)); +\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z734\: FD1S3BX port map ( +D => RXSDR_APPD_2, +CK => rxrefclk, +PD => rsl_rst, +Q => RXSDR_APPD); +\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z736\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_1, +SP => UN1_DUAL_OR_RSERD_RST_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_EN); +\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z738\: FD1P3DX port map ( +D => RXR_WT_CNT_S(0), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z740\: FD1P3DX port map ( +D => RXR_WT_CNT_S(1), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(1)); +\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z742\: FD1P3DX port map ( +D => RXR_WT_CNT_S(2), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z744\: FD1P3DX port map ( +D => RXR_WT_CNT_S(3), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(3)); +\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z746\: FD1P3DX port map ( +D => RXR_WT_CNT_S(4), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z748\: FD1P3DX port map ( +D => RXR_WT_CNT_S(5), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(5)); +\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z750\: FD1P3DX port map ( +D => RXR_WT_CNT_S(6), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z752\: FD1P3DX port map ( +D => RXR_WT_CNT_S(7), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(7)); +\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z754\: FD1P3DX port map ( +D => RXR_WT_CNT_S(8), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z756\: FD1P3DX port map ( +D => RXR_WT_CNT_S(9), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(9)); +\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z758\: FD1P3DX port map ( +D => RXR_WT_CNT_S(10), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z760\: FD1P3DX port map ( +D => RXR_WT_CNT_S(11), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(11)); +\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z762\: FD1P3DX port map ( +D => UN1_RUI_RST_DUAL_C_1_1, +SP => UN1_RUI_RST_DUAL_C_1_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXDPR_APPD); +\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z764\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_2, +SP => RXR_WT_CNT9, +CK => rxrefclk, +CD => rsl_rst, +Q => RSL_RX_RDY_8); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z766\: FD1S3DX port map ( +D => N_2160_0, +CK => rxrefclk, +CD => rsl_rst, +Q => RXSR_APPD(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z768\: FD1P3DX port map ( +D => RXPR_APPD_RNO(0), +SP => UN2_RDO_SERDES_RST_DUAL_C_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXPR_APPD(0)); +\GENBLK1.WAITA_PLOL0_REG_Z770\: FD1P3DX port map ( +D => PLOL_FEDGE, +SP => UN1_PLOL0_CNT_TC_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => WAITA_PLOL0); +\GENBLK1.TXS_RST_REG_Z772\: FD1P3DX port map ( +D => UN1_PLOL_CNT_TC, +SP => UN2_PLOL_CNT_TC, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_RST); +\GENBLK1.TXS_CNT[0]_REG_Z774\: FD1S3DX port map ( +D => N_10_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(0)); +\GENBLK1.TXS_CNT[1]_REG_Z776\: FD1S3DX port map ( +D => TXS_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(1)); +\GENBLK1.TXP_RST_REG_Z778\: FD1P3DX port map ( +D => UN9_PLOL0_CNT_TC, +SP => UN1_PLOL0_CNT_TC_1, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_RST); +\GENBLK1.TXP_CNT[0]_REG_Z780\: FD1S3DX port map ( +D => N_11_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(0)); +\GENBLK1.TXP_CNT[1]_REG_Z782\: FD1S3DX port map ( +D => TXP_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(1)); +\GENBLK1.PLOL_CNT[0]_REG_Z784\: FD1S3DX port map ( +D => PLOL_CNT_S(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(0)); +\GENBLK1.PLOL_CNT[1]_REG_Z786\: FD1S3DX port map ( +D => PLOL_CNT_S(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(1)); +\GENBLK1.PLOL_CNT[2]_REG_Z788\: FD1S3DX port map ( +D => PLOL_CNT_S(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(2)); +\GENBLK1.PLOL_CNT[3]_REG_Z790\: FD1S3DX port map ( +D => PLOL_CNT_S(3), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(3)); +\GENBLK1.PLOL_CNT[4]_REG_Z792\: FD1S3DX port map ( +D => PLOL_CNT_S(4), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(4)); +\GENBLK1.PLOL_CNT[5]_REG_Z794\: FD1S3DX port map ( +D => PLOL_CNT_S(5), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(5)); +\GENBLK1.PLOL_CNT[6]_REG_Z796\: FD1S3DX port map ( +D => PLOL_CNT_S(6), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(6)); +\GENBLK1.PLOL_CNT[7]_REG_Z798\: FD1S3DX port map ( +D => PLOL_CNT_S(7), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(7)); +\GENBLK1.PLOL_CNT[8]_REG_Z800\: FD1S3DX port map ( +D => PLOL_CNT_S(8), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(8)); +\GENBLK1.PLOL_CNT[9]_REG_Z802\: FD1S3DX port map ( +D => PLOL_CNT_S(9), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(9)); +\GENBLK1.PLOL_CNT[10]_REG_Z804\: FD1S3DX port map ( +D => PLOL_CNT_S(10), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(10)); +\GENBLK1.PLOL_CNT[11]_REG_Z806\: FD1S3DX port map ( +D => PLOL_CNT_S(11), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(11)); +\GENBLK1.PLOL_CNT[12]_REG_Z808\: FD1S3DX port map ( +D => PLOL_CNT_S(12), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(12)); +\GENBLK1.PLOL_CNT[13]_REG_Z810\: FD1S3DX port map ( +D => PLOL_CNT_S(13), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(13)); +\GENBLK1.PLOL_CNT[14]_REG_Z812\: FD1S3DX port map ( +D => PLOL_CNT_S(14), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(14)); +\GENBLK1.PLOL_CNT[15]_REG_Z814\: FD1S3DX port map ( +D => PLOL_CNT_S(15), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(15)); +\GENBLK1.PLOL_CNT[16]_REG_Z816\: FD1S3DX port map ( +D => PLOL_CNT_S(16), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(16)); +\GENBLK1.PLOL_CNT[17]_REG_Z818\: FD1S3DX port map ( +D => PLOL_CNT_S(17), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(17)); +\GENBLK1.PLOL_CNT[18]_REG_Z820\: FD1S3DX port map ( +D => PLOL_CNT_S(18), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(18)); +\GENBLK1.PLOL_CNT[19]_REG_Z822\: FD1S3DX port map ( +D => PLOL_CNT_S(19), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(19)); +\GENBLK1.PLOL0_CNT[0]_REG_Z824\: FD1S3DX port map ( +D => PLOL0_CNT_3(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(0)); +\GENBLK1.PLOL0_CNT[1]_REG_Z826\: FD1S3DX port map ( +D => PLOL0_CNT_3(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(1)); +\GENBLK1.PLOL0_CNT[2]_REG_Z828\: FD1S3DX port map ( +D => PLOL0_CNT_3(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(2)); +\GENBLK1.PLL_LOL_P3_REG_Z830\: FD1S3DX port map ( +D => PLL_LOL_P2, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P3); +\GENBLK1.PLL_LOL_P2_REG_Z832\: FD1S3DX port map ( +D => PLL_LOL_P1, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P2); +\GENBLK1.PLL_LOL_P1_REG_Z834\: FD1S3DX port map ( +D => pll_lock_i, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P1); +\GENBLK1.GENBLK2.TXSR_APPD_REG_Z836\: FD1S3BX port map ( +D => TXSR_APPD_2, +CK => pll_refclki, +PD => rsl_rst, +Q => TXSR_APPD); +\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z838\: FD1P3DX port map ( +D => UN1_DUAL_OR_SERD_RST_1_1, +SP => UN1_DUAL_OR_SERD_RST_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_EN); +\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z840\: FD1P3DX port map ( +D => TXR_WT_CNT_S(0), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z842\: FD1P3DX port map ( +D => TXR_WT_CNT_S(1), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(1)); +\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z844\: FD1P3DX port map ( +D => TXR_WT_CNT_S(2), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z846\: FD1P3DX port map ( +D => TXR_WT_CNT_S(3), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(3)); +\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z848\: FD1P3DX port map ( +D => TXR_WT_CNT_S(4), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z850\: FD1P3DX port map ( +D => TXR_WT_CNT_S(5), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(5)); +\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z852\: FD1P3DX port map ( +D => TXR_WT_CNT_S(6), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z854\: FD1P3DX port map ( +D => TXR_WT_CNT_S(7), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(7)); +\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z856\: FD1P3DX port map ( +D => TXR_WT_CNT_S(8), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z858\: FD1P3DX port map ( +D => TXR_WT_CNT_S(9), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(9)); +\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z860\: FD1P3DX port map ( +D => TXR_WT_CNT_S(10), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z862\: FD1P3DX port map ( +D => TXR_WT_CNT_S(11), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(11)); +\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z864\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_3_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXDPR_APPD); +\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z866\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_5_1, +SP => UN2_PLOL_FEDGE_5_I, +CK => pll_refclki, +CD => rsl_rst, +Q => RSL_TX_RDY_7); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z868\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_8_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXPR_APPD(0)); +\GENBLK1.TXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXS_CNT(0), +B => TXS_RST, +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => N_10_I); +\GENBLK1.TXS_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => TXS_RST, +D => UN1_PLOL_CNT_TC, +Z => TXS_CNT_RNO(1)); +\GENBLK2.RXP_RST2_RNO_0\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RLOLS0_CNT_TC_1, +B => RLOS_REDGE, +C => RSL_RX_SERDES_RST_C_9, +D => RSL_SERDES_RST_DUAL_C_10, +Z => UN2_RLOS_REDGE_1_I); +\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0F2F" +) +port map ( +A => TXPR_APPD(0), +B => PLL_LOL_P2, +C => UN1_DUAL_OR_SERD_RST_1_1, +D => RSL_TX_RDY_7, +Z => UN1_DUAL_OR_SERD_RST_1_I); +\GENBLK2.RXS_RST6\: LUT4 +generic map( + init => X"2020" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => RXS_RST6); +\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RXS_RST, +B => WAIT_CALIB, +C => RLOL1_CNT_TC_1, +D => RLOS_REDGE, +Z => RLOL1_CNTE); +\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS0, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => RLOLS0_CNTE); +\GENBLK1.PLOL_CNT11_I\: LUT4 +generic map( + init => X"0202" +) +port map ( +A => PLL_LOL_P2, +B => UN1_PLOL_CNT_TC, +C => RSL_TX_SERDES_RST_C_6, +D => VCC, +Z => \PLOL_CNT_\); +\GENBLK2.RLOLS0_CNT11_I\: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOLS0_CNT11_0, +B => RLOLS0_CNT_TC_1, +C => VCC, +D => VCC, +Z => \RLOLS0_CNT_\); +\GENBLK2.UN1_RXS_CNT_TC\: LUT4 +generic map( + init => X"FEFC" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => UN8_RXS_CNT_TC, +D => RLOL1_CNT_TC_1, +Z => UN1_RXS_CNT_TC); +\GENBLK2.WAIT_CALIB_RNO\: LUT4 +generic map( + init => X"A3A3" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => WAIT_CALIB_RNO); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => UN1_TXSR_APPD, +B => PLL_LOL_P2, +C => RSL_SERDES_RST_DUAL_C_10, +D => RSL_TX_SERDES_RST_C_6, +Z => UN2_PLOL_FEDGE_8_I); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 +generic map( + init => X"FFFB" +) +port map ( +A => UN17_RXR_WT_TC, +B => UN1_DUAL_OR_RSERD_RST_2_0, +C => RSL_RX_SERDES_RST_C_9, +D => RSL_SERDES_RST_DUAL_C_10, +Z => UN1_DUAL_OR_RSERD_RST_2_I); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO_0[0]\: LUT4 +generic map( + init => X"FFFB" +) +port map ( +A => UN1_RXSDR_OR_SR_APPD, +B => UN2_RDO_SERDES_RST_DUAL_C_1_1, +C => RSL_RX_SERDES_RST_C_9, +D => RSL_SERDES_RST_DUAL_C_10, +Z => UN2_RDO_SERDES_RST_DUAL_C_2_I); +\GENBLK1.GENBLK2.TXR_WT_EN_RNICEBT\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => TXR_WT_EN, +B => UN18_TXR_WT_TC, +C => TX_ANY_RST, +D => VCC, +Z => TXR_WT_CNTE); +\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => UN2_PLOL_CNT_TC); +\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => UN1_RLOS_FEDGE_1); +\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS06, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => UN1_RLOLS0_CNT_TC); +\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_TX_SERDES_RST_C_6, +D => rst_dual_c, +Z => UN2_PLOL_FEDGE_3_I); +\GENBLK1.TXP_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXP_CNT(0), +B => TXP_RST, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => N_11_I); +\GENBLK1.TXP_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => TXP_RST, +D => UN9_PLOL0_CNT_TC, +Z => TXP_CNT_RNO(1)); +UN1_DUAL_OR_SERD_RST_1_1_Z890: LUT4 +generic map( + init => X"0101" +) +port map ( +A => UN18_TXR_WT_TC, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_TX_SERDES_RST_C_6, +D => VCC, +Z => UN1_DUAL_OR_SERD_RST_1_1); +UN2_PLOL_FEDGE_5_1_Z891: LUT4 +generic map( + init => X"1111" +) +port map ( +A => PLL_LOL_P2, +B => TX_ANY_RST, +C => VCC, +D => VCC, +Z => UN2_PLOL_FEDGE_5_1); +RLOLS0_CNT_TC_1_Z892: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOLS0_CNT_TC_1_10, +B => RLOLS0_CNT_TC_1_11, +C => RLOLS0_CNT_TC_1_12, +D => RLOLS0_CNT_TC_1_13, +Z => RLOLS0_CNT_TC_1); +RLOL1_CNT_TC_1_Z893: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL1_CNT_TC_1_11, +B => RLOL1_CNT_TC_1_12, +C => RLOL1_CNT_TC_1_13, +D => RLOL1_CNT_TC_1_14, +Z => RLOL1_CNT_TC_1); +\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => UN1_PLOL_CNT_TC_11, +B => UN1_PLOL_CNT_TC_12, +C => UN1_PLOL_CNT_TC_13, +D => UN1_PLOL_CNT_TC_14, +Z => UN1_PLOL_CNT_TC); +\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOL_DB_CNT(0), +B => UN1_RLOL_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOL_DB_CNT_AXB_0); +\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOS_DB_CNT(0), +B => UN1_RLOS_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOS_DB_CNT_AXB_0); +\GENBLK1.WAITA_PLOL0_RNO\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1_I); +\GENBLK1.PLOL0_CNT_3[2]\: LUT4 +generic map( + init => X"1320" +) +port map ( +A => CO0_2, +B => PLOL0_CNT9, +C => PLOL0_CNT(1), +D => PLOL0_CNT(2), +Z => PLOL0_CNT_3(2)); +\GENBLK1.PLOL0_CNT_3[0]\: LUT4 +generic map( + init => X"1414" +) +port map ( +A => PLOL0_CNT9, +B => PLOL0_CNT(0), +C => WAITA_PLOL0, +D => VCC, +Z => PLOL0_CNT_3(0)); +\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => TXSR_APPD_4, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_TX_SERDES_RST_C_6, +D => VCC, +Z => TXSR_APPD_2); +\GENBLK1.GENBLK2.MFOR[0].UN1_TXSR_APPD\: LUT4 +generic map( + init => X"C8C8" +) +port map ( +A => TXDPR_APPD, +B => TXSR_APPD_4, +C => RSL_TX_PCS_RST_C_5, +D => VCC, +Z => UN1_TXSR_APPD); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN17_RXR_WT_TC_6, +B => UN17_RXR_WT_TC_7, +C => UN17_RXR_WT_TC_8, +D => VCC, +Z => UN17_RXR_WT_TC); +RX_ANY_RST_Z903: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RSL_RX_PCS_RST_C_4, +B => RSL_RX_SERDES_RST_C_9, +C => RSL_SERDES_RST_DUAL_C_10, +D => rst_dual_c, +Z => RX_ANY_RST); +TX_ANY_RST_Z904: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => RSL_TX_PCS_RST_C_5, +C => RSL_TX_SERDES_RST_C_6, +D => rst_dual_c, +Z => TX_ANY_RST); +UN2_PLOL_FEDGE_2_Z905: LUT4 +generic map( + init => X"0101" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_TX_SERDES_RST_C_6, +D => VCC, +Z => UN2_PLOL_FEDGE_2); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN18_TXR_WT_TC_6, +B => UN18_TXR_WT_TC_7, +C => UN18_TXR_WT_TC_8, +D => VCC, +Z => UN18_TXR_WT_TC); +\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z907\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_BM(0)); +\UN1_RLOL_DB_CNT_ZERO[0]_Z908\: PFUMX port map ( +ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0), +C0 => RLOL_P2, +Z => UN1_RLOL_DB_CNT_ZERO(0)); +\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z909\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_BM(0)); +\UN1_RLOS_DB_CNT_ZERO[0]_Z910\: PFUMX port map ( +ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0), +C0 => RLOS_P2, +Z => UN1_RLOS_DB_CNT_ZERO(0)); +\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_MAX); +\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_MAX); +\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1); +\GENBLK2.WAITA_RLOLS06\: LUT4 +generic map( + init => X"0504" +) +port map ( +A => RLOL_DB, +B => RLOL_DB_P1, +C => RLOS_DB, +D => RLOS_DB_P1, +Z => WAITA_RLOLS06); +\RXS_CNT_3[1]_Z915\: LUT4 +generic map( + init => X"6464" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => RXS_RST, +D => VCC, +Z => RXS_CNT_3(1)); +\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD\: LUT4 +generic map( + init => X"3200" +) +port map ( +A => RXSR_APPD(0), +B => RX_ALL_WELL, +C => RXSDR_APPD_4, +D => RSL_RX_PCS_RST_C_4, +Z => UN1_RXSDR_OR_SR_APPD); +RLOLS0_CNT_TC_1_13_Z917: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RLOLS0_CNT(16), +B => RLOLS0_CNT(17), +C => RLOLS0_CNT_TC_1_9, +D => VCC, +Z => RLOLS0_CNT_TC_1_13); +\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 +generic map( + init => X"0100" +) +port map ( +A => PLOL_CNT(4), +B => PLOL_CNT(5), +C => PLOL_CNT(18), +D => UN1_PLOL_CNT_TC_10, +Z => UN1_PLOL_CNT_TC_14); +RLOL1_CNT_TC_1_14_Z919: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(11), +B => RLOL1_CNT(12), +C => RLOL1_CNT(18), +D => RLOL1_CNT_TC_1_10, +Z => RLOL1_CNT_TC_1_14); +UN1_DUAL_OR_RSERD_RST_2_0_Z920: LUT4 +generic map( + init => X"F010" +) +port map ( +A => RXPR_APPD(0), +B => RXDPR_APPD, +C => RX_ALL_WELL, +D => RSL_RX_RDY_8, +Z => UN1_DUAL_OR_RSERD_RST_2_0); +RDO_TX_SERDES_RST_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXS_RST, +C => tx_serdes_rst_c, +D => VCC, +Z => RSL_TX_SERDES_RST_C_6); +RDO_SERDES_RST_DUAL_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => rsl_rst, +C => serdes_rst_dual_c, +D => VCC, +Z => RSL_SERDES_RST_DUAL_C_10); +\RDO_TX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXP_RST, +C => tx_pcs_rst_c, +D => VCC, +Z => RSL_TX_PCS_RST_C_5); +\RDO_RX_SERDES_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXS_RST, +C => rx_serdes_rst_c, +D => VCC, +Z => RSL_RX_SERDES_RST_C_9); +\RDO_RX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXP_RST2, +C => rx_pcs_rst_c, +D => VCC, +Z => RSL_RX_PCS_RST_C_4); +\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 +generic map( + init => X"1010" +) +port map ( +A => PLOL0_CNT(0), +B => PLOL0_CNT(1), +C => PLOL0_CNT(2), +D => VCC, +Z => UN9_PLOL0_CNT_TC); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => TXR_WT_CNT(0), +B => TXR_WT_CNT(8), +C => TXR_WT_CNT(9), +D => TXR_WT_CNT(11), +Z => UN18_TXR_WT_TC_6); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => TXR_WT_CNT(3), +B => TXR_WT_CNT(4), +C => TXR_WT_CNT(5), +D => TXR_WT_CNT(7), +Z => UN18_TXR_WT_TC_7); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => TXR_WT_CNT(1), +B => TXR_WT_CNT(2), +C => TXR_WT_CNT(6), +D => TXR_WT_CNT(10), +Z => UN18_TXR_WT_TC_8); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RXR_WT_CNT(0), +B => RXR_WT_CNT(8), +C => RXR_WT_CNT(9), +D => RXR_WT_CNT(11), +Z => UN17_RXR_WT_TC_6); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RXR_WT_CNT(3), +B => RXR_WT_CNT(4), +C => RXR_WT_CNT(5), +D => RXR_WT_CNT(7), +Z => UN17_RXR_WT_TC_7); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RXR_WT_CNT(1), +B => RXR_WT_CNT(2), +C => RXR_WT_CNT(6), +D => RXR_WT_CNT(10), +Z => UN17_RXR_WT_TC_8); +RLOLS0_CNT_TC_1_9_Z933: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(1), +B => RLOLS0_CNT(2), +C => RLOLS0_CNT(3), +D => RLOLS0_CNT(4), +Z => RLOLS0_CNT_TC_1_9); +RLOLS0_CNT_TC_1_10_Z934: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RLOLS0_CNT(0), +B => RLOLS0_CNT(10), +C => RLOLS0_CNT(14), +D => RLOLS0_CNT(15), +Z => RLOLS0_CNT_TC_1_10); +RLOLS0_CNT_TC_1_11_Z935: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(9), +B => RLOLS0_CNT(11), +C => RLOLS0_CNT(12), +D => RLOLS0_CNT(13), +Z => RLOLS0_CNT_TC_1_11); +RLOLS0_CNT_TC_1_12_Z936: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(5), +B => RLOLS0_CNT(6), +C => RLOLS0_CNT(7), +D => RLOLS0_CNT(8), +Z => RLOLS0_CNT_TC_1_12); +\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 +generic map( + init => X"1000" +) +port map ( +A => PLOL_CNT(2), +B => PLOL_CNT(3), +C => PLOL_CNT(17), +D => PLOL_CNT(19), +Z => UN1_PLOL_CNT_TC_10); +\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(13), +B => PLOL_CNT(14), +C => PLOL_CNT(15), +D => PLOL_CNT(16), +Z => UN1_PLOL_CNT_TC_11); +\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(7), +B => PLOL_CNT(8), +C => PLOL_CNT(9), +D => PLOL_CNT(11), +Z => UN1_PLOL_CNT_TC_12); +\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 +generic map( + init => X"0008" +) +port map ( +A => PLOL_CNT(1), +B => PLOL_CNT(6), +C => PLOL_CNT(10), +D => PLOL_CNT(12), +Z => UN1_PLOL_CNT_TC_13); +RLOL1_CNT_TC_1_10_Z941: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(7), +B => RLOL1_CNT(8), +C => RLOL1_CNT(9), +D => RLOL1_CNT(10), +Z => RLOL1_CNT_TC_1_10); +RLOL1_CNT_TC_1_11_Z942: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(3), +B => RLOL1_CNT(4), +C => RLOL1_CNT(5), +D => RLOL1_CNT(6), +Z => RLOL1_CNT_TC_1_11); +RLOL1_CNT_TC_1_12_Z943: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(0), +B => RLOL1_CNT(1), +C => RLOL1_CNT(2), +D => RLOL1_CNT(17), +Z => RLOL1_CNT_TC_1_12); +RLOL1_CNT_TC_1_13_Z944: LUT4 +generic map( + init => X"0040" +) +port map ( +A => RLOL1_CNT(13), +B => RLOL1_CNT(14), +C => RLOL1_CNT(15), +D => RLOL1_CNT(16), +Z => RLOL1_CNT_TC_1_13); +\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PLOL0_CNT(0), +B => WAITA_PLOL0, +C => VCC, +D => VCC, +Z => CO0_2); +PLOL_FEDGE_Z946: LUT4 +generic map( + init => X"4444" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => VCC, +D => VCC, +Z => PLOL_FEDGE); +RX_ALL_WELL_Z947: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => VCC, +D => VCC, +Z => RX_ALL_WELL); +\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RXSDR_APPD_4, +B => serdes_rst_dual_c, +C => VCC, +D => VCC, +Z => RXSDR_APPD_2); +\GENBLK2.UN8_RXS_CNT_TC\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => VCC, +D => VCC, +Z => UN8_RXS_CNT_TC); +RLOS_REDGE_Z950: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => VCC, +D => VCC, +Z => RLOS_REDGE); +UN2_RDO_SERDES_RST_DUAL_C_1_1_Z951: LUT4 +generic map( + init => X"1111" +) +port map ( +A => rx_cdr_lol_s, +B => rx_los_low_s, +C => VCC, +D => VCC, +Z => UN2_RDO_SERDES_RST_DUAL_C_1_1); +\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z952\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_AM(0)); +\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z953\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_AM(0)); +\GENBLK1.PLOL0_CNT9\: LUT4 +generic map( + init => X"AAAE" +) +port map ( +A => PLL_LOL_P2, +B => PLOL0_CNT(2), +C => PLOL0_CNT(1), +D => PLOL0_CNT(0), +Z => PLOL0_CNT9); +\GENBLK2.RLOLS0_CNT11_0\: LUT4 +generic map( + init => X"4F44" +) +port map ( +A => RLOL_DB_P1, +B => RLOL_DB, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => RLOLS0_CNT11_0); +\GENBLK1.GENBLK2.TXR_WT_CNT9_I\: LUT4 +generic map( + init => X"1555" +) +port map ( +A => TX_ANY_RST, +B => UN18_TXR_WT_TC_8, +C => UN18_TXR_WT_TC_7, +D => UN18_TXR_WT_TC_6, +Z => \TXR_WT_CNT_\); +\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOL1_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_7, +COUT => RLOL1_CNT_CRY(0), +S0 => RLOL1_CNT_CRY_0_S0(0), +S1 => RLOL1_CNT_S(0)); +\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(0), +COUT => RLOL1_CNT_CRY(2), +S0 => RLOL1_CNT_S(1), +S1 => RLOL1_CNT_S(2)); +\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(2), +COUT => RLOL1_CNT_CRY(4), +S0 => RLOL1_CNT_S(3), +S1 => RLOL1_CNT_S(4)); +\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(4), +COUT => RLOL1_CNT_CRY(6), +S0 => RLOL1_CNT_S(5), +S1 => RLOL1_CNT_S(6)); +\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(6), +COUT => RLOL1_CNT_CRY(8), +S0 => RLOL1_CNT_S(7), +S1 => RLOL1_CNT_S(8)); +\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(8), +COUT => RLOL1_CNT_CRY(10), +S0 => RLOL1_CNT_S(9), +S1 => RLOL1_CNT_S(10)); +\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(10), +COUT => RLOL1_CNT_CRY(12), +S0 => RLOL1_CNT_S(11), +S1 => RLOL1_CNT_S(12)); +\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(12), +COUT => RLOL1_CNT_CRY(14), +S0 => RLOL1_CNT_S(13), +S1 => RLOL1_CNT_S(14)); +\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(14), +COUT => RLOL1_CNT_CRY(16), +S0 => RLOL1_CNT_S(15), +S1 => RLOL1_CNT_S(16)); +\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"800a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(16), +COUT => RLOL1_CNT_CRY_0_COUT(17), +S0 => RLOL1_CNT_S(17), +S1 => RLOL1_CNT_S(18)); +\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOLS0_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_6, +COUT => RLOLS0_CNT_CRY(0), +S0 => RLOLS0_CNT_CRY_0_S0(0), +S1 => RLOLS0_CNT_S(0)); +\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(0), +COUT => RLOLS0_CNT_CRY(2), +S0 => RLOLS0_CNT_S(1), +S1 => RLOLS0_CNT_S(2)); +\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(2), +COUT => RLOLS0_CNT_CRY(4), +S0 => RLOLS0_CNT_S(3), +S1 => RLOLS0_CNT_S(4)); +\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(4), +COUT => RLOLS0_CNT_CRY(6), +S0 => RLOLS0_CNT_S(5), +S1 => RLOLS0_CNT_S(6)); +\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(6), +COUT => RLOLS0_CNT_CRY(8), +S0 => RLOLS0_CNT_S(7), +S1 => RLOLS0_CNT_S(8)); +\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(8), +COUT => RLOLS0_CNT_CRY(10), +S0 => RLOLS0_CNT_S(9), +S1 => RLOLS0_CNT_S(10)); +\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(10), +COUT => RLOLS0_CNT_CRY(12), +S0 => RLOLS0_CNT_S(11), +S1 => RLOLS0_CNT_S(12)); +\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(12), +COUT => RLOLS0_CNT_CRY(14), +S0 => RLOLS0_CNT_S(13), +S1 => RLOLS0_CNT_S(14)); +\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(14), +COUT => RLOLS0_CNT_CRY(16), +S0 => RLOLS0_CNT_S(15), +S1 => RLOLS0_CNT_S(16)); +\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(16), +COUT => RLOLS0_CNT_S_0_COUT(17), +S0 => RLOLS0_CNT_S(17), +S1 => RLOLS0_CNT_S_0_S1(17)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \TXR_WT_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => TXR_WT_CNT_CRY(0), +S0 => TXR_WT_CNT_CRY_0_S0(0), +S1 => TXR_WT_CNT_S(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(0), +COUT => TXR_WT_CNT_CRY(2), +S0 => TXR_WT_CNT_S(1), +S1 => TXR_WT_CNT_S(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(2), +COUT => TXR_WT_CNT_CRY(4), +S0 => TXR_WT_CNT_S(3), +S1 => TXR_WT_CNT_S(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(4), +COUT => TXR_WT_CNT_CRY(6), +S0 => TXR_WT_CNT_S(5), +S1 => TXR_WT_CNT_S(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(6), +COUT => TXR_WT_CNT_CRY(8), +S0 => TXR_WT_CNT_S(7), +S1 => TXR_WT_CNT_S(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \TXR_WT_CNT_\, +B1 => TXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(8), +COUT => TXR_WT_CNT_CRY(10), +S0 => TXR_WT_CNT_S(9), +S1 => TXR_WT_CNT_S(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \TXR_WT_CNT_\, +B0 => TXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(10), +COUT => TXR_WT_CNT_S_0_COUT(11), +S0 => TXR_WT_CNT_S(11), +S1 => TXR_WT_CNT_S_0_S1(11)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => RXR_WT_CNT9, +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RXR_WT_CNT_CRY(0), +S0 => RXR_WT_CNT_CRY_0_S0(0), +S1 => RXR_WT_CNT_S(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(0), +COUT => RXR_WT_CNT_CRY(2), +S0 => RXR_WT_CNT_S(1), +S1 => RXR_WT_CNT_S(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(2), +COUT => RXR_WT_CNT_CRY(4), +S0 => RXR_WT_CNT_S(3), +S1 => RXR_WT_CNT_S(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(4), +COUT => RXR_WT_CNT_CRY(6), +S0 => RXR_WT_CNT_S(5), +S1 => RXR_WT_CNT_S(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(6), +COUT => RXR_WT_CNT_CRY(8), +S0 => RXR_WT_CNT_S(7), +S1 => RXR_WT_CNT_S(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(8), +COUT => RXR_WT_CNT_CRY(10), +S0 => RXR_WT_CNT_S(9), +S1 => RXR_WT_CNT_S(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(10), +COUT => RXR_WT_CNT_S_0_COUT(11), +S0 => RXR_WT_CNT_S(11), +S1 => RXR_WT_CNT_S_0_S1(11)); +\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \PLOL_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => PLOL_CNT_CRY(0), +S0 => PLOL_CNT_CRY_0_S0(0), +S1 => PLOL_CNT_S(0)); +\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(0), +COUT => PLOL_CNT_CRY(2), +S0 => PLOL_CNT_S(1), +S1 => PLOL_CNT_S(2)); +\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(2), +COUT => PLOL_CNT_CRY(4), +S0 => PLOL_CNT_S(3), +S1 => PLOL_CNT_S(4)); +\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(4), +COUT => PLOL_CNT_CRY(6), +S0 => PLOL_CNT_S(5), +S1 => PLOL_CNT_S(6)); +\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(6), +COUT => PLOL_CNT_CRY(8), +S0 => PLOL_CNT_S(7), +S1 => PLOL_CNT_S(8)); +\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(8), +COUT => PLOL_CNT_CRY(10), +S0 => PLOL_CNT_S(9), +S1 => PLOL_CNT_S(10)); +\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(10), +COUT => PLOL_CNT_CRY(12), +S0 => PLOL_CNT_S(11), +S1 => PLOL_CNT_S(12)); +\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(12), +COUT => PLOL_CNT_CRY(14), +S0 => PLOL_CNT_S(13), +S1 => PLOL_CNT_S(14)); +\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(14), +COUT => PLOL_CNT_CRY(16), +S0 => PLOL_CNT_S(15), +S1 => PLOL_CNT_S(16)); +\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(16), +COUT => PLOL_CNT_CRY(18), +S0 => PLOL_CNT_S(17), +S1 => PLOL_CNT_S(18)); +\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(19), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(18), +COUT => PLOL_CNT_S_0_COUT(19), +S0 => PLOL_CNT_S(19), +S1 => PLOL_CNT_S_0_S1(19)); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOS_DB_CNT(0), +B1 => UN1_RLOS_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => RLOS_DB_CNT_CRY_0, +S0 => RLOS_DB_CNT_CRY_0_0_S0, +S1 => RLOS_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOS_DB_CNT_ZERO(0), +B0 => RLOS_P2, +C0 => RLOS_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOS_DB_CNT_ZERO(0), +B1 => RLOS_P2, +C1 => RLOS_DB_CNT(2), +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_0, +COUT => RLOS_DB_CNT_CRY_2, +S0 => RLOS_DB_CNT_CRY_1_0_S0, +S1 => RLOS_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOS_DB_CNT(3), +B0 => RLOS_P2, +C0 => UN1_RLOS_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_2, +COUT => RLOS_DB_CNT_S_3_0_COUT, +S0 => RLOS_DB_CNT_S_3_0_S0, +S1 => RLOS_DB_CNT_S_3_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOL_DB_CNT(0), +B1 => UN1_RLOL_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => RLOL_DB_CNT_CRY_0, +S0 => RLOL_DB_CNT_CRY_0_0_S0, +S1 => RLOL_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOL_DB_CNT_ZERO(0), +B0 => RLOL_P2, +C0 => RLOL_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOL_DB_CNT_ZERO(0), +B1 => RLOL_P2, +C1 => RLOL_DB_CNT(2), +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_0, +COUT => RLOL_DB_CNT_CRY_2, +S0 => RLOL_DB_CNT_CRY_1_0_S0, +S1 => RLOL_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOL_DB_CNT(3), +B0 => RLOL_P2, +C0 => UN1_RLOL_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_2, +COUT => RLOL_DB_CNT_S_3_0_COUT, +S0 => RLOL_DB_CNT_S_3_0_S0, +S1 => RLOL_DB_CNT_S_3_0_S1); +RXSDR_APPD_4 <= RXSDR_APPD; +TXSR_APPD_4 <= TXSR_APPD; +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_4; +rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_5; +rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_6; +rsl_tx_rdy <= RSL_TX_RDY_7; +rsl_rx_rdy <= RSL_RX_RDY_8; +rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_9; +rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_10; +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5sll_core_Z1_layer1 is +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic); +end sgmii_ecp5sll_core_Z1_layer1; + +architecture beh of sgmii_ecp5sll_core_Z1_layer1 is +signal PHB_CNT : std_logic_vector(2 downto 0); +signal PHB_CNT_I : std_logic_vector(2 downto 0); +signal RCOUNT : std_logic_vector(15 downto 0); +signal PCOUNT : std_logic_vector(21 downto 0); +signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0); +signal SLL_STATE : std_logic_vector(1 downto 0); +signal SLL_STATE_QN : std_logic_vector(1 downto 0); +signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0); +signal RCOUNT_S : std_logic_vector(15 downto 0); +signal RCOUNT_QN : std_logic_vector(15 downto 0); +signal PHB_CNT_QN : std_logic_vector(2 downto 0); +signal PHB_CNT_RNO : std_logic_vector(2 downto 1); +signal PCOUNT_S : std_logic_vector(21 downto 0); +signal PCOUNT_QN : std_logic_vector(21 downto 0); +signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0); +signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2); +signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2); +signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0); +signal PCOUNT_CRY : std_logic_vector(20 downto 0); +signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21); +signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21); +signal RCOUNT_CRY : std_logic_vector(14 downto 0); +signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15); +signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15); +signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0); +signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7); +signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7); +signal PLL_LOCK : std_logic ; +signal RTC_CTRL4_0_A3_1 : std_logic ; +signal UN13_LOCK_20 : std_logic ; +signal PPUL_SYNC_P2 : std_logic ; +signal PPUL_SYNC_P1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ; +signal UN13_LOCK_19 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ; +signal UN13_LOCK_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ; +signal UN13_LOCK_17 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_17 : std_logic ; +signal UN13_LOCK_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0 : std_logic ; +signal UN13_LOCK_15 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ; +signal UN13_LOCK_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ; +signal UN13_LOCK_13 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ; +signal UN13_LOCK_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ; +signal UN13_LOCK_11 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ; +signal UN13_LOCK_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ; +signal UN13_LOCK_9 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ; +signal UN13_LOCK_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ; +signal UN13_LOCK_7 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ; +signal UN13_LOCK_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ; +signal UN13_LOCK_5 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ; +signal UN13_LOCK_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ; +signal UN13_LOCK_3 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ; +signal UN13_LOCK_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ; +signal UN13_LOCK_1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ; +signal UN13_LOCK_21 : std_logic ; +signal PPUL_SYNC_P3 : std_logic ; +signal N_7 : std_logic ; +signal UN13_LOCK_0 : std_logic ; +signal RTC_CTRL4 : std_logic ; +signal RTC_CTRL : std_logic ; +signal VCC : std_logic ; +signal N_2121_0 : std_logic ; +signal UNLOCK_5 : std_logic ; +signal UNLOCK_1_SQMUXA_I : std_logic ; +signal UNLOCK : std_logic ; +signal UNLOCK_QN : std_logic ; +signal N_95_I : std_logic ; +signal N_97_I : std_logic ; +signal RTC_PUL : std_logic ; +signal RTC_PUL_P1 : std_logic ; +signal RTC_PUL_P1_QN : std_logic ; +signal RTC_PUL5 : std_logic ; +signal RTC_PUL_QN : std_logic ; +signal RTC_CTRL_QN : std_logic ; +signal RSTAT_PCLK_2 : std_logic ; +signal RSTAT_PCLK : std_logic ; +signal RSTAT_PCLK_QN : std_logic ; +signal RHB_SYNC_P1 : std_logic ; +signal RHB_SYNC_P2 : std_logic ; +signal RHB_SYNC_P2_QN : std_logic ; +signal RHB_SYNC : std_logic ; +signal RHB_SYNC_P1_QN : std_logic ; +signal PPUL_SYNC_P3_QN : std_logic ; +signal PPUL_SYNC_P2_QN : std_logic ; +signal PPUL_SYNC : std_logic ; +signal PPUL_SYNC_P1_QN : std_logic ; +signal N_53_I : std_logic ; +signal PLL_LOCK_QN : std_logic ; +signal PHB : std_logic ; +signal PHB_QN : std_logic ; +signal PDIFF_SYNC : std_logic ; +signal PDIFF_SYNC_P1 : std_logic ; +signal PDIFF_SYNC_P1_QN : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ; +signal LOCK_5 : std_logic ; +signal LOCK_1_SQMUXA_I : std_logic ; +signal LOCK : std_logic ; +signal LOCK_QN : std_logic ; +signal N_98 : std_logic ; +signal RTC_PUL5_0_O3 : std_logic ; +signal RTC_PUL5_0_A3_6 : std_logic ; +signal RTC_PUL5_0_A3_7 : std_logic ; +signal UN1_RCOUNT_1_0_A3 : std_logic ; +signal RHB_WAIT_CNT12 : std_logic ; +signal UN1_RHB_WAIT_CNT_4 : std_logic ; +signal UN1_RHB_WAIT_CNT_5 : std_logic ; +signal N_99 : std_logic ; +signal RTC_CTRL4_0_A3_12_4 : std_logic ; +signal RTC_CTRL4_0_A3_12_5 : std_logic ; +signal RTC_CTRL4_10 : std_logic ; +signal UN1_RCOUNT_1_0_A3_1 : std_logic ; +signal N_6 : std_logic ; +signal RTC_PUL5_0_A3_5 : std_logic ; +signal N_8 : std_logic ; +signal UN13_UNLOCK_CRY_21 : std_logic ; +signal UN13_LOCK_CRY_21_I : std_logic ; +signal \RHB_WAIT_CNT_\ : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ; +signal UN13_LOCK_CRY_0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S1 : std_logic ; +signal UN13_LOCK_CRY_2 : std_logic ; +signal UN13_LOCK_CRY_1_0_S0 : std_logic ; +signal UN13_LOCK_CRY_1_0_S1 : std_logic ; +signal UN13_LOCK_CRY_4 : std_logic ; +signal UN13_LOCK_CRY_3_0_S0 : std_logic ; +signal UN13_LOCK_CRY_3_0_S1 : std_logic ; +signal UN13_LOCK_CRY_6 : std_logic ; +signal UN13_LOCK_CRY_5_0_S0 : std_logic ; +signal UN13_LOCK_CRY_5_0_S1 : std_logic ; +signal UN13_LOCK_CRY_8 : std_logic ; +signal UN13_LOCK_CRY_7_0_S0 : std_logic ; +signal UN13_LOCK_CRY_7_0_S1 : std_logic ; +signal UN13_LOCK_CRY_10 : std_logic ; +signal UN13_LOCK_CRY_9_0_S0 : std_logic ; +signal UN13_LOCK_CRY_9_0_S1 : std_logic ; +signal UN13_LOCK_CRY_12 : std_logic ; +signal UN13_LOCK_CRY_11_0_S0 : std_logic ; +signal UN13_LOCK_CRY_11_0_S1 : std_logic ; +signal UN13_LOCK_CRY_14 : std_logic ; +signal UN13_LOCK_CRY_13_0_S0 : std_logic ; +signal UN13_LOCK_CRY_13_0_S1 : std_logic ; +signal UN13_LOCK_CRY_16 : std_logic ; +signal UN13_LOCK_CRY_15_0_S0 : std_logic ; +signal UN13_LOCK_CRY_15_0_S1 : std_logic ; +signal UN13_LOCK_CRY_18 : std_logic ; +signal UN13_LOCK_CRY_17_0_S0 : std_logic ; +signal UN13_LOCK_CRY_17_0_S1 : std_logic ; +signal UN13_LOCK_CRY_20 : std_logic ; +signal UN13_LOCK_CRY_19_0_S0 : std_logic ; +signal UN13_LOCK_CRY_19_0_S1 : std_logic ; +signal UN13_LOCK_CRY_21_0_COUT : std_logic ; +signal UN13_LOCK_CRY_21_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_2 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_4 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_6 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_8 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_10 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_12 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_14 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_16 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_18 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_20 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ; +signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ; +signal N_21 : std_logic ; +signal N_20 : std_logic ; +signal N_19 : std_logic ; +signal N_18 : std_logic ; +signal N_14 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_9 : std_logic ; +component sync_0s +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +component sync_0s_6 +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic ); +end component; +component sync_0s_0 +port( +ppul_sync : in std_logic; +pdiff_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +begin +PHB_RNO: INV port map ( +A => PHB_CNT(2), +Z => PHB_CNT_I(2)); +\PHB_CNT_RNO[0]\: INV port map ( +A => PHB_CNT(0), +Z => PHB_CNT_I(0)); +PLL_LOCK_RNI6JK9: INV port map ( +A => PLL_LOCK, +Z => pll_lock_i); +RTC_CTRL4_0_A3_RNO: LUT4 +generic map( + init => X"2000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => RTC_CTRL4_0_A3_1); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_20, +B => PCOUNT(20), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_20); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_19, +B => PCOUNT(19), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_19); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_18, +B => PCOUNT(18), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_18); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_17, +B => PCOUNT(17), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_17); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0_Z478: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_16, +B => PCOUNT(16), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_15, +B => PCOUNT(15), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_15); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_14, +B => PCOUNT(14), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_14); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_13, +B => PCOUNT(13), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_13); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_12, +B => PCOUNT(12), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_12); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_11, +B => PCOUNT(11), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_11); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_10, +B => PCOUNT(10), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_10); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_9, +B => PCOUNT(9), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_9); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_8, +B => PCOUNT(8), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_8); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_7, +B => PCOUNT(7), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_7); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_6, +B => PCOUNT(6), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_6); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_5, +B => PCOUNT(5), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_5); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_4, +B => PCOUNT(4), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_4); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_3, +B => PCOUNT(3), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_3); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_2, +B => PCOUNT(2), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_2); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_1, +B => PCOUNT(1), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_1); +PPUL_SYNC_P3_RNIU65C: LUT4 +generic map( + init => X"2F20" +) +port map ( +A => UN13_LOCK_21, +B => PPUL_SYNC_P3, +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => N_7); +\PCOUNT_DIFF_RNO[0]\: LUT4 +generic map( + init => X"FD20" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => PCOUNT(0), +D => UN13_LOCK_0, +Z => UN1_PCOUNT_DIFF_I(0)); +RTC_CTRL_0: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RTC_CTRL4, +B => RTC_CTRL, +C => VCC, +D => VCC, +Z => N_2121_0); +UNLOCK_REG_Z498: FD1P3DX port map ( +D => UNLOCK_5, +SP => UNLOCK_1_SQMUXA_I, +CK => pll_refclki, +CD => sli_rst, +Q => UNLOCK); +\SLL_STATE[0]_REG_Z500\: FD1S3DX port map ( +D => N_95_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(0)); +\SLL_STATE[1]_REG_Z502\: FD1S3DX port map ( +D => N_97_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(1)); +RTC_PUL_P1_REG_Z504: FD1S3DX port map ( +D => RTC_PUL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL_P1); +RTC_PUL_REG_Z506: FD1P3DX port map ( +D => RTC_PUL5, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL); +RTC_CTRL_REG_Z508: FD1S3DX port map ( +D => N_2121_0, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_CTRL); +RSTAT_PCLK_REG_Z510: FD1P3DX port map ( +D => RSTAT_PCLK_2, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RSTAT_PCLK); +\RHB_WAIT_CNT[0]_REG_Z512\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(0), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(0)); +\RHB_WAIT_CNT[1]_REG_Z514\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(1), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(1)); +\RHB_WAIT_CNT[2]_REG_Z516\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(2), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(2)); +\RHB_WAIT_CNT[3]_REG_Z518\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(3), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(3)); +\RHB_WAIT_CNT[4]_REG_Z520\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(4), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(4)); +\RHB_WAIT_CNT[5]_REG_Z522\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(5), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(5)); +\RHB_WAIT_CNT[6]_REG_Z524\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(6), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(6)); +\RHB_WAIT_CNT[7]_REG_Z526\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(7), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(7)); +RHB_SYNC_P2_REG_Z528: FD1S3DX port map ( +D => RHB_SYNC_P1, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P2); +RHB_SYNC_P1_REG_Z530: FD1S3DX port map ( +D => RHB_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P1); +\RCOUNT[0]_REG_Z532\: FD1S3DX port map ( +D => RCOUNT_S(0), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(0)); +\RCOUNT[1]_REG_Z534\: FD1S3DX port map ( +D => RCOUNT_S(1), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(1)); +\RCOUNT[2]_REG_Z536\: FD1S3DX port map ( +D => RCOUNT_S(2), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(2)); +\RCOUNT[3]_REG_Z538\: FD1S3DX port map ( +D => RCOUNT_S(3), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(3)); +\RCOUNT[4]_REG_Z540\: FD1S3DX port map ( +D => RCOUNT_S(4), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(4)); +\RCOUNT[5]_REG_Z542\: FD1S3DX port map ( +D => RCOUNT_S(5), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(5)); +\RCOUNT[6]_REG_Z544\: FD1S3DX port map ( +D => RCOUNT_S(6), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(6)); +\RCOUNT[7]_REG_Z546\: FD1S3DX port map ( +D => RCOUNT_S(7), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(7)); +\RCOUNT[8]_REG_Z548\: FD1S3DX port map ( +D => RCOUNT_S(8), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(8)); +\RCOUNT[9]_REG_Z550\: FD1S3DX port map ( +D => RCOUNT_S(9), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(9)); +\RCOUNT[10]_REG_Z552\: FD1S3DX port map ( +D => RCOUNT_S(10), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(10)); +\RCOUNT[11]_REG_Z554\: FD1S3DX port map ( +D => RCOUNT_S(11), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(11)); +\RCOUNT[12]_REG_Z556\: FD1S3DX port map ( +D => RCOUNT_S(12), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(12)); +\RCOUNT[13]_REG_Z558\: FD1S3DX port map ( +D => RCOUNT_S(13), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(13)); +\RCOUNT[14]_REG_Z560\: FD1S3DX port map ( +D => RCOUNT_S(14), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(14)); +\RCOUNT[15]_REG_Z562\: FD1S3DX port map ( +D => RCOUNT_S(15), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(15)); +PPUL_SYNC_P3_REG_Z564: FD1S3DX port map ( +D => PPUL_SYNC_P2, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P3); +PPUL_SYNC_P2_REG_Z566: FD1S3DX port map ( +D => PPUL_SYNC_P1, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P2); +PPUL_SYNC_P1_REG_Z568: FD1S3DX port map ( +D => PPUL_SYNC, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P1); +PLL_LOCK_REG_Z570: FD1S3DX port map ( +D => N_53_I, +CK => pll_refclki, +CD => sli_rst, +Q => PLL_LOCK); +\PHB_CNT[0]_REG_Z572\: FD1S3DX port map ( +D => PHB_CNT_I(0), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(0)); +\PHB_CNT[1]_REG_Z574\: FD1S3DX port map ( +D => PHB_CNT_RNO(1), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(1)); +\PHB_CNT[2]_REG_Z576\: FD1S3DX port map ( +D => PHB_CNT_RNO(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(2)); +PHB_REG_Z578: FD1S3DX port map ( +D => PHB_CNT_I(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB); +PDIFF_SYNC_P1_REG_Z580: FD1S3DX port map ( +D => PDIFF_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => PDIFF_SYNC_P1); +\PCOUNT[0]_REG_Z582\: FD1S3DX port map ( +D => PCOUNT_S(0), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(0)); +\PCOUNT_DIFF[0]_REG_Z584\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_I(0), +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_0); +\PCOUNT[1]_REG_Z586\: FD1S3DX port map ( +D => PCOUNT_S(1), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(1)); +\PCOUNT_DIFF[1]_REG_Z588\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_1); +\PCOUNT_DIFF[2]_REG_Z590\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_2); +\PCOUNT[2]_REG_Z592\: FD1S3DX port map ( +D => PCOUNT_S(2), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(2)); +\PCOUNT_DIFF[3]_REG_Z594\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_3); +\PCOUNT[3]_REG_Z596\: FD1S3DX port map ( +D => PCOUNT_S(3), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(3)); +\PCOUNT_DIFF[4]_REG_Z598\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_4); +\PCOUNT[4]_REG_Z600\: FD1S3DX port map ( +D => PCOUNT_S(4), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(4)); +\PCOUNT_DIFF[5]_REG_Z602\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_5); +\PCOUNT[5]_REG_Z604\: FD1S3DX port map ( +D => PCOUNT_S(5), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(5)); +\PCOUNT[6]_REG_Z606\: FD1S3DX port map ( +D => PCOUNT_S(6), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(6)); +\PCOUNT_DIFF[6]_REG_Z608\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_6); +\PCOUNT[7]_REG_Z610\: FD1S3DX port map ( +D => PCOUNT_S(7), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(7)); +\PCOUNT_DIFF[7]_REG_Z612\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_7); +\PCOUNT[8]_REG_Z614\: FD1S3DX port map ( +D => PCOUNT_S(8), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(8)); +\PCOUNT_DIFF[8]_REG_Z616\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_8); +\PCOUNT_DIFF[9]_REG_Z618\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_9); +\PCOUNT[9]_REG_Z620\: FD1S3DX port map ( +D => PCOUNT_S(9), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(9)); +\PCOUNT[10]_REG_Z622\: FD1S3DX port map ( +D => PCOUNT_S(10), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(10)); +\PCOUNT_DIFF[10]_REG_Z624\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_10); +\PCOUNT_DIFF[11]_REG_Z626\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_11); +\PCOUNT[11]_REG_Z628\: FD1S3DX port map ( +D => PCOUNT_S(11), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(11)); +\PCOUNT[12]_REG_Z630\: FD1S3DX port map ( +D => PCOUNT_S(12), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(12)); +\PCOUNT_DIFF[12]_REG_Z632\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_12); +\PCOUNT_DIFF[13]_REG_Z634\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_13); +\PCOUNT[13]_REG_Z636\: FD1S3DX port map ( +D => PCOUNT_S(13), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(13)); +\PCOUNT_DIFF[14]_REG_Z638\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_14); +\PCOUNT[14]_REG_Z640\: FD1S3DX port map ( +D => PCOUNT_S(14), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(14)); +\PCOUNT[15]_REG_Z642\: FD1S3DX port map ( +D => PCOUNT_S(15), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(15)); +\PCOUNT_DIFF[15]_REG_Z644\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_15); +\PCOUNT[16]_REG_Z646\: FD1S3DX port map ( +D => PCOUNT_S(16), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(16)); +\PCOUNT_DIFF[16]_REG_Z648\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_16); +\PCOUNT_DIFF[17]_REG_Z650\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_17); +\PCOUNT[17]_REG_Z652\: FD1S3DX port map ( +D => PCOUNT_S(17), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(17)); +\PCOUNT_DIFF[18]_REG_Z654\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_18); +\PCOUNT[18]_REG_Z656\: FD1S3DX port map ( +D => PCOUNT_S(18), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(18)); +\PCOUNT[19]_REG_Z658\: FD1S3DX port map ( +D => PCOUNT_S(19), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(19)); +\PCOUNT_DIFF[19]_REG_Z660\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_19); +\PCOUNT[20]_REG_Z662\: FD1S3DX port map ( +D => PCOUNT_S(20), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(20)); +\PCOUNT_DIFF[20]_REG_Z664\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_20); +\PCOUNT_DIFF[21]_REG_Z666\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_S_21_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_21); +\PCOUNT[21]_REG_Z668\: FD1S3DX port map ( +D => PCOUNT_S(21), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(21)); +LOCK_REG_Z670: FD1P3DX port map ( +D => LOCK_5, +SP => LOCK_1_SQMUXA_I, +CK => pll_refclki, +CD => sli_rst, +Q => LOCK); +\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z672\: FD1S3DX port map ( +D => VCC, +CK => pll_refclki, +CD => sli_rst, +Q => RDIFF_COMP_LOCK(2)); +\SLL_STATE_RNO[0]\: LUT4 +generic map( + init => X"E050" +) +port map ( +A => N_98, +B => LOCK, +C => RSTAT_PCLK, +D => SLL_STATE(0), +Z => N_95_I); +RTC_PUL5_0_0: LUT4 +generic map( + init => X"FF80" +) +port map ( +A => RTC_PUL5_0_O3, +B => RTC_PUL5_0_A3_6, +C => RTC_PUL5_0_A3_7, +D => UN1_RCOUNT_1_0_A3, +Z => RTC_PUL5); +RSTAT_PCLK_2_IV: LUT4 +generic map( + init => X"AEEE" +) +port map ( +A => RHB_WAIT_CNT12, +B => RSTAT_PCLK, +C => UN1_RHB_WAIT_CNT_4, +D => UN1_RHB_WAIT_CNT_5, +Z => RSTAT_PCLK_2); +\SLL_STATE_RNO[1]\: LUT4 +generic map( + init => X"8088" +) +port map ( +A => N_99, +B => RSTAT_PCLK, +C => SLL_STATE(1), +D => UNLOCK, +Z => N_97_I); +RTC_CTRL4_0_A3: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_1, +B => RTC_CTRL4_0_A3_12_4, +C => RTC_CTRL4_0_A3_12_5, +D => RTC_CTRL4_10, +Z => RTC_CTRL4); +UN1_RCOUNT_1_0_A3_Z678: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_12_4, +B => RTC_CTRL4_0_A3_12_5, +C => RTC_CTRL4_10, +D => UN1_RCOUNT_1_0_A3_1, +Z => UN1_RCOUNT_1_0_A3); +LOCK_1_SQMUXA_I_Z679: LUT4 +generic map( + init => X"7575" +) +port map ( +A => LOCK, +B => PDIFF_SYNC, +C => PDIFF_SYNC_P1, +D => VCC, +Z => LOCK_1_SQMUXA_I); +UNLOCK_1_SQMUXA_I_Z680: LUT4 +generic map( + init => X"4F4F" +) +port map ( +A => PDIFF_SYNC, +B => PDIFF_SYNC_P1, +C => UNLOCK, +D => VCC, +Z => UNLOCK_1_SQMUXA_I); +RTC_PUL5_0_O3_Z681: LUT4 +generic map( + init => X"AAAB" +) +port map ( +A => N_6, +B => RCOUNT(1), +C => RCOUNT(2), +D => RCOUNT(3), +Z => RTC_PUL5_0_O3); +RTC_PUL5_0_A3_7_Z682: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RTC_PUL5_0_A3_5, +D => VCC, +Z => RTC_PUL5_0_A3_7); +\SLL_STATE_NS_I_M4[1]\: LUT4 +generic map( + init => X"EF20" +) +port map ( +A => LOCK, +B => RTC_PUL, +C => RTC_PUL_P1, +D => SLL_STATE(1), +Z => N_99); +PLL_LOCK_RNO: LUT4 +generic map( + init => X"8888" +) +port map ( +A => SLL_STATE(0), +B => SLL_STATE(1), +C => VCC, +D => VCC, +Z => N_53_I); +\PHB_CNT_RNO[2]_Z685\: LUT4 +generic map( + init => X"7878" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => PHB_CNT(2), +D => VCC, +Z => PHB_CNT_RNO(2)); +\SLL_STATE_NS_I_O4[0]\: LUT4 +generic map( + init => X"BFBF" +) +port map ( +A => RTC_PUL, +B => RTC_PUL_P1, +C => SLL_STATE(1), +D => VCC, +Z => N_98); +RTC_CTRL4_0_A3_10: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(1), +B => RCOUNT(3), +C => RCOUNT(6), +D => RCOUNT(15), +Z => RTC_CTRL4_10); +UN1_RHB_WAIT_CNT_4_Z688: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(4), +B => RHB_WAIT_CNT(5), +C => RHB_WAIT_CNT(6), +D => RHB_WAIT_CNT(7), +Z => UN1_RHB_WAIT_CNT_4); +UN1_RHB_WAIT_CNT_5_Z689: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(0), +B => RHB_WAIT_CNT(1), +C => RHB_WAIT_CNT(2), +D => RHB_WAIT_CNT(3), +Z => UN1_RHB_WAIT_CNT_5); +RTC_CTRL4_0_A3_12_4_Z690: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(11), +B => RCOUNT(12), +C => RCOUNT(13), +D => RCOUNT(14), +Z => RTC_CTRL4_0_A3_12_4); +RTC_CTRL4_0_A3_12_5_Z691: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RCOUNT(9), +D => RCOUNT(10), +Z => RTC_CTRL4_0_A3_12_5); +RTC_PUL5_0_A3_5_Z692: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(6), +B => RCOUNT(13), +C => RCOUNT(14), +D => RCOUNT(15), +Z => RTC_PUL5_0_A3_5); +RTC_PUL5_0_A3_6_Z693: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(9), +B => RCOUNT(10), +C => RCOUNT(11), +D => RCOUNT(12), +Z => RTC_PUL5_0_A3_6); +PCOUNT10_0_O3: LUT4 +generic map( + init => X"DDDD" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => VCC, +D => VCC, +Z => N_8); +\PHB_CNT_RNO[1]_Z695\: LUT4 +generic map( + init => X"6666" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => VCC, +D => VCC, +Z => PHB_CNT_RNO(1)); +RTC_CTRL4_0_O3: LUT4 +generic map( + init => X"7777" +) +port map ( +A => RCOUNT(4), +B => RCOUNT(5), +C => VCC, +D => VCC, +Z => N_6); +UNLOCK_5_Z697: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_UNLOCK_CRY_21, +C => VCC, +D => VCC, +Z => UNLOCK_5); +LOCK_5_Z698: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_LOCK_CRY_21_I, +C => VCC, +D => VCC, +Z => LOCK_5); +RHB_WAIT_CNT12_Z699: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RHB_SYNC_P1, +B => RHB_SYNC_P2, +C => VCC, +D => VCC, +Z => RHB_WAIT_CNT12); +\UN1_PCOUNT_DIFF[0]_Z700\: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_0, +B => PCOUNT(0), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF(0)); +UN1_RCOUNT_1_0_A3_1_Z701: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => UN1_RCOUNT_1_0_A3_1); +RHB_SYNC_P2_RNIU9TG1: LUT4 +generic map( + init => X"7077" +) +port map ( +A => UN1_RHB_WAIT_CNT_5, +B => UN1_RHB_WAIT_CNT_4, +C => RHB_SYNC_P2, +D => RHB_SYNC_P1, +Z => \RHB_WAIT_CNT_\); +\PCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => N_8, +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_9, +COUT => PCOUNT_CRY(0), +S0 => PCOUNT_CRY_0_S0(0), +S1 => PCOUNT_S(0)); +\PCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(0), +COUT => PCOUNT_CRY(2), +S0 => PCOUNT_S(1), +S1 => PCOUNT_S(2)); +\PCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(2), +COUT => PCOUNT_CRY(4), +S0 => PCOUNT_S(3), +S1 => PCOUNT_S(4)); +\PCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(4), +COUT => PCOUNT_CRY(6), +S0 => PCOUNT_S(5), +S1 => PCOUNT_S(6)); +\PCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(6), +COUT => PCOUNT_CRY(8), +S0 => PCOUNT_S(7), +S1 => PCOUNT_S(8)); +\PCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(8), +COUT => PCOUNT_CRY(10), +S0 => PCOUNT_S(9), +S1 => PCOUNT_S(10)); +\PCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(10), +COUT => PCOUNT_CRY(12), +S0 => PCOUNT_S(11), +S1 => PCOUNT_S(12)); +\PCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(12), +COUT => PCOUNT_CRY(14), +S0 => PCOUNT_S(13), +S1 => PCOUNT_S(14)); +\PCOUNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(16), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(14), +COUT => PCOUNT_CRY(16), +S0 => PCOUNT_S(15), +S1 => PCOUNT_S(16)); +\PCOUNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(17), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(18), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(16), +COUT => PCOUNT_CRY(18), +S0 => PCOUNT_S(17), +S1 => PCOUNT_S(18)); +\PCOUNT_CRY_0[19]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(19), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(20), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(18), +COUT => PCOUNT_CRY(20), +S0 => PCOUNT_S(19), +S1 => PCOUNT_S(20)); +\PCOUNT_S_0[21]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(21), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(20), +COUT => PCOUNT_S_0_COUT(21), +S0 => PCOUNT_S(21), +S1 => PCOUNT_S_0_S1(21)); +\RCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => UN1_RCOUNT_1_0_A3, +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => RCOUNT_CRY(0), +S0 => RCOUNT_CRY_0_S0(0), +S1 => RCOUNT_S(0)); +\RCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(0), +COUT => RCOUNT_CRY(2), +S0 => RCOUNT_S(1), +S1 => RCOUNT_S(2)); +\RCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(2), +COUT => RCOUNT_CRY(4), +S0 => RCOUNT_S(3), +S1 => RCOUNT_S(4)); +\RCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(4), +COUT => RCOUNT_CRY(6), +S0 => RCOUNT_S(5), +S1 => RCOUNT_S(6)); +\RCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(6), +COUT => RCOUNT_CRY(8), +S0 => RCOUNT_S(7), +S1 => RCOUNT_S(8)); +\RCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(8), +COUT => RCOUNT_CRY(10), +S0 => RCOUNT_S(9), +S1 => RCOUNT_S(10)); +\RCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(10), +COUT => RCOUNT_CRY(12), +S0 => RCOUNT_S(11), +S1 => RCOUNT_S(12)); +\RCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(12), +COUT => RCOUNT_CRY(14), +S0 => RCOUNT_S(13), +S1 => RCOUNT_S(14)); +\RCOUNT_S_0[15]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(14), +COUT => RCOUNT_S_0_COUT(15), +S0 => RCOUNT_S(15), +S1 => RCOUNT_S_0_S1(15)); +\RHB_WAIT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RHB_WAIT_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RHB_WAIT_CNT_CRY(0), +S0 => RHB_WAIT_CNT_CRY_0_S0(0), +S1 => RHB_WAIT_CNT_S(0)); +\RHB_WAIT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(0), +COUT => RHB_WAIT_CNT_CRY(2), +S0 => RHB_WAIT_CNT_S(1), +S1 => RHB_WAIT_CNT_S(2)); +\RHB_WAIT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(2), +COUT => RHB_WAIT_CNT_CRY(4), +S0 => RHB_WAIT_CNT_S(3), +S1 => RHB_WAIT_CNT_S(4)); +\RHB_WAIT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RHB_WAIT_CNT_\, +B1 => RHB_WAIT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(4), +COUT => RHB_WAIT_CNT_CRY(6), +S0 => RHB_WAIT_CNT_S(5), +S1 => RHB_WAIT_CNT_S(6)); +\RHB_WAIT_CNT_S_0[7]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RHB_WAIT_CNT_\, +B0 => RHB_WAIT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(6), +COUT => RHB_WAIT_CNT_S_0_COUT(7), +S0 => RHB_WAIT_CNT_S(7), +S1 => RHB_WAIT_CNT_S_0_S1(7)); +UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500f", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF(0), +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => UN1_PCOUNT_DIFF_1_CRY_0, +S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1); +UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_1, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_2, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_0, +COUT => UN1_PCOUNT_DIFF_1_CRY_2, +S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1); +UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_2, +COUT => UN1_PCOUNT_DIFF_1_CRY_4, +S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1); +UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_4, +COUT => UN1_PCOUNT_DIFF_1_CRY_6, +S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1); +UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_6, +COUT => UN1_PCOUNT_DIFF_1_CRY_8, +S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1); +UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_8, +COUT => UN1_PCOUNT_DIFF_1_CRY_10, +S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1); +UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_10, +COUT => UN1_PCOUNT_DIFF_1_CRY_12, +S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1); +UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_12, +COUT => UN1_PCOUNT_DIFF_1_CRY_14, +S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1); +UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"b404", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => RDIFF_COMP_LOCK(2), +C1 => UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_14, +COUT => UN1_PCOUNT_DIFF_1_CRY_16, +S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1); +UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_16, +COUT => UN1_PCOUNT_DIFF_1_CRY_18, +S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1); +UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_18, +COUT => UN1_PCOUNT_DIFF_1_CRY_20, +S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1); +UN1_PCOUNT_DIFF_1_S_21_0: CCU2C +generic map( + INIT0 => X"350a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => PCOUNT(21), +B0 => UN13_LOCK_21, +C0 => N_8, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_20, +COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT, +S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0, +S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1); +UN13_LOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => UN13_LOCK_CRY_0, +S0 => UN13_LOCK_CRY_0_0_S0, +S1 => UN13_LOCK_CRY_0_0_S1); +UN13_LOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_0, +COUT => UN13_LOCK_CRY_2, +S0 => UN13_LOCK_CRY_1_0_S0, +S1 => UN13_LOCK_CRY_1_0_S1); +UN13_LOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_2, +COUT => UN13_LOCK_CRY_4, +S0 => UN13_LOCK_CRY_3_0_S0, +S1 => UN13_LOCK_CRY_3_0_S1); +UN13_LOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_4, +COUT => UN13_LOCK_CRY_6, +S0 => UN13_LOCK_CRY_5_0_S0, +S1 => UN13_LOCK_CRY_5_0_S1); +UN13_LOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_6, +COUT => UN13_LOCK_CRY_8, +S0 => UN13_LOCK_CRY_7_0_S0, +S1 => UN13_LOCK_CRY_7_0_S1); +UN13_LOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_8, +COUT => UN13_LOCK_CRY_10, +S0 => UN13_LOCK_CRY_9_0_S0, +S1 => UN13_LOCK_CRY_9_0_S1); +UN13_LOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_10, +COUT => UN13_LOCK_CRY_12, +S0 => UN13_LOCK_CRY_11_0_S0, +S1 => UN13_LOCK_CRY_11_0_S1); +UN13_LOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_12, +COUT => UN13_LOCK_CRY_14, +S0 => UN13_LOCK_CRY_13_0_S0, +S1 => UN13_LOCK_CRY_13_0_S1); +UN13_LOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_14, +COUT => UN13_LOCK_CRY_16, +S0 => UN13_LOCK_CRY_15_0_S0, +S1 => UN13_LOCK_CRY_15_0_S1); +UN13_LOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_16, +COUT => UN13_LOCK_CRY_18, +S0 => UN13_LOCK_CRY_17_0_S0, +S1 => UN13_LOCK_CRY_17_0_S1); +UN13_LOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_18, +COUT => UN13_LOCK_CRY_20, +S0 => UN13_LOCK_CRY_19_0_S0, +S1 => UN13_LOCK_CRY_19_0_S1); +UN13_LOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_20, +COUT => UN13_LOCK_CRY_21_0_COUT, +S0 => UN13_LOCK_CRY_21_0_S0, +S1 => UN13_LOCK_CRY_21_I); +UN13_UNLOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => UN13_UNLOCK_CRY_0, +S0 => UN13_UNLOCK_CRY_0_0_S0, +S1 => UN13_UNLOCK_CRY_0_0_S1); +UN13_UNLOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_0, +COUT => UN13_UNLOCK_CRY_2, +S0 => UN13_UNLOCK_CRY_1_0_S0, +S1 => UN13_UNLOCK_CRY_1_0_S1); +UN13_UNLOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_2, +COUT => UN13_UNLOCK_CRY_4, +S0 => UN13_UNLOCK_CRY_3_0_S0, +S1 => UN13_UNLOCK_CRY_3_0_S1); +UN13_UNLOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_4, +COUT => UN13_UNLOCK_CRY_6, +S0 => UN13_UNLOCK_CRY_5_0_S0, +S1 => UN13_UNLOCK_CRY_5_0_S1); +UN13_UNLOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_6, +COUT => UN13_UNLOCK_CRY_8, +S0 => UN13_UNLOCK_CRY_7_0_S0, +S1 => UN13_UNLOCK_CRY_7_0_S1); +UN13_UNLOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_8, +COUT => UN13_UNLOCK_CRY_10, +S0 => UN13_UNLOCK_CRY_9_0_S0, +S1 => UN13_UNLOCK_CRY_9_0_S1); +UN13_UNLOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_10, +COUT => UN13_UNLOCK_CRY_12, +S0 => UN13_UNLOCK_CRY_11_0_S0, +S1 => UN13_UNLOCK_CRY_11_0_S1); +UN13_UNLOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_12, +COUT => UN13_UNLOCK_CRY_14, +S0 => UN13_UNLOCK_CRY_13_0_S0, +S1 => UN13_UNLOCK_CRY_13_0_S1); +UN13_UNLOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_14, +COUT => UN13_UNLOCK_CRY_16, +S0 => UN13_UNLOCK_CRY_15_0_S0, +S1 => UN13_UNLOCK_CRY_15_0_S1); +UN13_UNLOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_16, +COUT => UN13_UNLOCK_CRY_18, +S0 => UN13_UNLOCK_CRY_17_0_S0, +S1 => UN13_UNLOCK_CRY_17_0_S1); +UN13_UNLOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_18, +COUT => UN13_UNLOCK_CRY_20, +S0 => UN13_UNLOCK_CRY_19_0_S0, +S1 => UN13_UNLOCK_CRY_19_0_S1); +UN13_UNLOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_20, +COUT => UN13_UNLOCK_CRY_21_0_COUT, +S0 => UN13_UNLOCK_CRY_21_0_S0, +S1 => UN13_UNLOCK_CRY_21); +PHB_SYNC_INST: sync_0s port map ( +phb => PHB, +rhb_sync => RHB_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +RTC_SYNC_INST: sync_0s_6 port map ( +rtc_pul => RTC_PUL, +ppul_sync => PPUL_SYNC, +sli_rst => sli_rst, +tx_pclk => tx_pclk); +PDIFF_SYNC_INST: sync_0s_0 port map ( +ppul_sync => PPUL_SYNC, +pdiff_sync => PDIFF_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sgmii_ecp5 is +port( +hdoutp : out std_logic; +hdoutn : out std_logic; +hdinp : in std_logic; +hdinn : in std_logic; +rxrefclk : in std_logic; +tx_pclk : out std_logic; +txi_clk : in std_logic; +txdata : in std_logic_vector(7 downto 0); +tx_k : in std_logic_vector(0 downto 0); +xmit : in std_logic_vector(0 downto 0); +tx_disp_correct : in std_logic_vector(0 downto 0); +rxdata : out std_logic_vector(7 downto 0); +rx_k : out std_logic_vector(0 downto 0); +rx_disp_err : out std_logic_vector(0 downto 0); +rx_cv_err : out std_logic_vector(0 downto 0); +signal_detect_c : in std_logic; +rx_los_low_s : out std_logic; +lsm_status_s : out std_logic; +ctc_urun_s : out std_logic; +ctc_orun_s : out std_logic; +rx_cdr_lol_s : out std_logic; +ctc_ins_s : out std_logic; +ctc_del_s : out std_logic; +sli_rst : in std_logic; +tx_pwrup_c : in std_logic; +rx_pwrup_c : in std_logic; +sci_wrdata : in std_logic_vector(7 downto 0); +sci_addr : in std_logic_vector(5 downto 0); +sci_rddata : out std_logic_vector(7 downto 0); +sci_en_dual : in std_logic; +sci_sel_dual : in std_logic; +sci_en : in std_logic; +sci_sel : in std_logic; +sci_rd : in std_logic; +sci_wrn : in std_logic; +sci_int : out std_logic; +cyawstn : in std_logic; +serdes_pdb : in std_logic; +pll_refclki : in std_logic; +rsl_disable : in std_logic; +rsl_rst : in std_logic; +serdes_rst_dual_c : in std_logic; +rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +pll_lol : out std_logic; +rsl_tx_rdy : out std_logic; +rx_serdes_rst_c : in std_logic; +rx_pcs_rst_c : in std_logic; +rsl_rx_rdy : out std_logic); +end sgmii_ecp5; + +architecture beh of sgmii_ecp5 is +signal TX_PCLK_11 : std_logic ; +signal RX_LOS_LOW_S_12 : std_logic ; +signal RX_CDR_LOL_S_13 : std_logic ; +signal RSL_TX_PCS_RST_C : std_logic ; +signal RSL_RX_PCS_RST_C : std_logic ; +signal RSL_RX_SERDES_RST_C : std_logic ; +signal RSL_SERDES_RST_DUAL_C : std_logic ; +signal RSL_TX_SERDES_RST_C : std_logic ; +signal N47_1 : std_logic ; +signal N48_1 : std_logic ; +signal N1_1 : std_logic ; +signal N2_1 : std_logic ; +signal N3_1 : std_logic ; +signal N4_1 : std_logic ; +signal N5_1 : std_logic ; +signal N49_1 : std_logic ; +signal N6_1 : std_logic ; +signal N50_1 : std_logic ; +signal N7_1 : std_logic ; +signal N51_1 : std_logic ; +signal N8_1 : std_logic ; +signal N52_1 : std_logic ; +signal N9_1 : std_logic ; +signal N53_1 : std_logic ; +signal N54_1 : std_logic ; +signal N55_1 : std_logic ; +signal N56_1 : std_logic ; +signal N57_1 : std_logic ; +signal N58_1 : std_logic ; +signal N59_1 : std_logic ; +signal N60_1 : std_logic ; +signal N61_1 : std_logic ; +signal N62_1 : std_logic ; +signal N63_1 : std_logic ; +signal N64_1 : std_logic ; +signal N65_1 : std_logic ; +signal N10_1 : std_logic ; +signal N66_1 : std_logic ; +signal N67_1 : std_logic ; +signal N68_1 : std_logic ; +signal N69_1 : std_logic ; +signal N70_1 : std_logic ; +signal N71_1 : std_logic ; +signal N72_1 : std_logic ; +signal N73_1 : std_logic ; +signal N74_1 : std_logic ; +signal N75_1 : std_logic ; +signal N76_1 : std_logic ; +signal N77_1 : std_logic ; +signal N78_1 : std_logic ; +signal N79_1 : std_logic ; +signal N80_1 : std_logic ; +signal N81_1 : std_logic ; +signal N82_1 : std_logic ; +signal N83_1 : std_logic ; +signal N84_1 : std_logic ; +signal N85_1 : std_logic ; +signal N86_1 : std_logic ; +signal N87_1 : std_logic ; +signal N88_1 : std_logic ; +signal N11_1 : std_logic ; +signal N89_1 : std_logic ; +signal N12_1 : std_logic ; +signal N90_1 : std_logic ; +signal N13_1 : std_logic ; +signal N91_1 : std_logic ; +signal N92_1 : std_logic ; +signal N93_1 : std_logic ; +signal N94_1 : std_logic ; +signal N95_1 : std_logic ; +signal N14_1 : std_logic ; +signal N96_1 : std_logic ; +signal N15_1 : std_logic ; +signal N97_1 : std_logic ; +signal N98_1 : std_logic ; +signal N99_1 : std_logic ; +signal N100_1 : std_logic ; +signal N101_1 : std_logic ; +signal N112_1 : std_logic ; +signal N16_1 : std_logic ; +signal N17_1 : std_logic ; +signal N18_1 : std_logic ; +signal N19_1 : std_logic ; +signal N20_1 : std_logic ; +signal N21_1 : std_logic ; +signal N22_1 : std_logic ; +signal N23_1 : std_logic ; +signal N24_1 : std_logic ; +signal N25_1 : std_logic ; +signal N26_1 : std_logic ; +signal N27_1 : std_logic ; +signal N28_1 : std_logic ; +signal N29_1 : std_logic ; +signal N30_1 : std_logic ; +signal N31_1 : std_logic ; +signal N32_1 : std_logic ; +signal N33_1 : std_logic ; +signal N34_1 : std_logic ; +signal N35_1 : std_logic ; +signal N36_1 : std_logic ; +signal N37_1 : std_logic ; +signal N38_1 : std_logic ; +signal N39_1 : std_logic ; +signal N40_1 : std_logic ; +signal N41_1 : std_logic ; +signal N42_1 : std_logic ; +signal N43_1 : std_logic ; +signal N46_1 : std_logic ; +signal TX_PCLK_I : std_logic ; +signal GND : std_logic ; +signal VCC : std_logic ; +signal \SLL_INST.PLL_LOCK_I_14\ : std_logic ; +component sgmii_ecp5sll_core_Z1_layer1 +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic ); +end component; +component sgmii_ecp5rsl_core_Z2_layer1 +port( +rx_pcs_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rsl_disable : in std_logic; +rx_serdes_rst_c : in std_logic; +rst_dual_c : in std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic ); +end component; +begin +VCC_0: VHI port map ( +Z => VCC); +GND_0: VLO port map ( +Z => GND); +PUR_INST: PUR port map ( +PUR => VCC); +GSR_INST: GSR port map ( +GSR => VCC); +TX_PCLK_11 <= TX_PCLK_I; +DCU0_INST: DCUA +generic map( + D_MACROPDB => "0b1", + D_IB_PWDNB => "0b1", + D_XGE_MODE => "0b0", + D_LOW_MARK => "0d4", + D_HIGH_MARK => "0d12", + D_BUS8BIT_SEL => "0b0", + D_CDR_LOL_SET => "0b00", + D_BITCLK_LOCAL_EN => "0b1", + D_BITCLK_ND_EN => "0b0", + D_BITCLK_FROM_ND_EN => "0b0", + D_SYNC_LOCAL_EN => "0b1", + D_SYNC_ND_EN => "0b0", + CH0_UC_MODE => "0b0", + CH0_PCIE_MODE => "0b0", + CH0_RIO_MODE => "0b0", + CH0_WA_MODE => "0b0", + CH0_INVERT_RX => "0b0", + CH0_INVERT_TX => "0b0", + CH0_PRBS_SELECTION => "0b0", + CH0_GE_AN_ENABLE => "0b0", + CH0_PRBS_LOCK => "0b0", + CH0_PRBS_ENABLE => "0b0", + CH0_ENABLE_CG_ALIGN => "0b1", + CH0_TX_GEAR_MODE => "0b0", + CH0_RX_GEAR_MODE => "0b0", + CH0_PCS_DET_TIME_SEL => "0b00", + CH0_PCIE_EI_EN => "0b0", + CH0_TX_GEAR_BYPASS => "0b0", + CH0_ENC_BYPASS => "0b0", + CH0_SB_BYPASS => "0b0", + CH0_RX_SB_BYPASS => "0b0", + CH0_WA_BYPASS => "0b0", + CH0_DEC_BYPASS => "0b0", + CH0_CTC_BYPASS => "0b0", + CH0_RX_GEAR_BYPASS => "0b0", + CH0_LSM_DISABLE => "0b0", + CH0_MATCH_2_ENABLE => "0b1", + CH0_MATCH_4_ENABLE => "0b0", + CH0_MIN_IPG_CNT => "0b11", + CH0_CC_MATCH_1 => "0x000", + CH0_CC_MATCH_2 => "0x000", + CH0_CC_MATCH_3 => "0x1BC", + CH0_CC_MATCH_4 => "0x050", + CH0_UDF_COMMA_MASK => "0x3ff", + CH0_UDF_COMMA_A => "0x283", + CH0_UDF_COMMA_B => "0x17C", + CH0_RX_DCO_CK_DIV => "0b000", + CH0_RCV_DCC_EN => "0b0", + CH0_REQ_LVL_SET => "0b00", + CH0_REQ_EN => "0b1", + CH0_RTERM_RX => "0d22", + CH0_PDEN_SEL => "0b1", + CH0_LDR_RX2CORE_SEL => "0b0", + CH0_LDR_CORE2TX_SEL => "0b0", + CH0_TPWDNB => "0b1", + CH0_RATE_MODE_TX => "0b0", + CH0_RTERM_TX => "0d19", + CH0_TX_CM_SEL => "0b00", + CH0_TDRV_PRE_EN => "0b0", + CH0_TDRV_SLICE0_SEL => "0b01", + CH0_TDRV_SLICE1_SEL => "0b00", + CH0_TDRV_SLICE2_SEL => "0b01", + CH0_TDRV_SLICE3_SEL => "0b01", + CH0_TDRV_SLICE4_SEL => "0b01", + CH0_TDRV_SLICE5_SEL => "0b01", + CH0_TDRV_SLICE0_CUR => "0b101", + CH0_TDRV_SLICE1_CUR => "0b000", + CH0_TDRV_SLICE2_CUR => "0b11", + CH0_TDRV_SLICE3_CUR => "0b11", + CH0_TDRV_SLICE4_CUR => "0b11", + CH0_TDRV_SLICE5_CUR => "0b00", + CH0_TDRV_DAT_SEL => "0b00", + CH0_TX_DIV11_SEL => "0b0", + CH0_RPWDNB => "0b1", + CH0_RATE_MODE_RX => "0b0", + CH0_RLOS_SEL => "0b1", + CH0_RX_LOS_LVL => "0b010", + CH0_RX_LOS_CEQ => "0b11", + CH0_RX_LOS_HYST_EN => "0b0", + CH0_RX_LOS_EN => "0b1", + CH0_RX_DIV11_SEL => "0b0", + CH0_SEL_SD_RX_CLK => "0b0", + CH0_FF_RX_H_CLK_EN => "0b0", + CH0_FF_RX_F_CLK_DIS => "0b0", + CH0_FF_TX_H_CLK_EN => "0b0", + CH0_FF_TX_F_CLK_DIS => "0b0", + CH0_RX_RATE_SEL => "0d8", + CH0_TDRV_POST_EN => "0b0", + CH0_TX_POST_SIGN => "0b0", + CH0_TX_PRE_SIGN => "0b0", + CH0_RXTERM_CM => "0b11", + CH0_RXIN_CM => "0b11", + CH0_LEQ_OFFSET_SEL => "0b0", + CH0_LEQ_OFFSET_TRIM => "0b000", + D_TX_MAX_RATE => "2", + CH0_CDR_MAX_RATE => "2", + CH0_TXAMPLITUDE => "0d1100", + CH0_TXDEPRE => "DISABLED", + CH0_TXDEPOST => "DISABLED", + CH0_PROTOCOL => "GBE", + D_ISETLOS => "0d0", + D_SETIRPOLY_AUX => "0b00", + D_SETICONST_AUX => "0b00", + D_SETIRPOLY_CH => "0b00", + D_SETICONST_CH => "0b00", + D_REQ_ISET => "0b000", + D_PD_ISET => "0b00", + D_DCO_CALIB_TIME_SEL => "0b00", + CH0_DCOCTLGI => "0b010", + CH0_DCOATDDLY => "0b00", + CH0_DCOATDCFG => "0b00", + CH0_DCOBYPSATD => "0b1", + CH0_DCOSCALEI => "0b00", + CH0_DCOITUNE4LSB => "0b111", + CH0_DCOIOSTUNE => "0b000", + CH0_DCODISBDAVOID => "0b0", + CH0_DCOCALDIV => "0b001", + CH0_DCONUOFLSB => "0b101", + CH0_DCOIUPDNX2 => "0b1", + CH0_DCOSTEP => "0b00", + CH0_DCOSTARTVAL => "0b000", + CH0_DCOFLTDAC => "0b01", + CH0_DCOITUNE => "0b00", + CH0_DCOFTNRG => "0b110", + CH0_CDR_CNT4SEL => "0b00", + CH0_CDR_CNT8SEL => "0b00", + CH0_BAND_THRESHOLD => "0d0", + CH0_AUTO_FACQ_EN => "0b1", + CH0_AUTO_CALIB_EN => "0b1", + CH0_CALIB_CK_MODE => "0b0", + CH0_REG_BAND_OFFSET => "0d0", + CH0_REG_BAND_SEL => "0d0", + CH0_REG_IDAC_SEL => "0d0", + CH0_REG_IDAC_EN => "0b0", + D_TXPLL_PWDNB => "0b1", + D_SETPLLRC => "0d1", + D_REFCK_MODE => "0b001", + D_TX_VCO_CK_DIV => "0b000", + D_PLL_LOL_SET => "0b00", + D_RG_EN => "0b0", + D_RG_SET => "0b00", + D_CMUSETISCL4VCO => "0b000", + D_CMUSETI4VCO => "0b00", + D_CMUSETINITVCT => "0b00", + D_CMUSETZGM => "0b000", + D_CMUSETP2AGM => "0b000", + D_CMUSETP1GM => "0b000", + D_CMUSETI4CPZ => "0d3", + D_CMUSETI4CPP => "0d3", + D_CMUSETICP4Z => "0b101", + D_CMUSETICP4P => "0b01", + D_CMUSETBIASI => "0b00" +) +port map ( +CH0_HDINP => hdinp, +CH1_HDINP => GND, +CH0_HDINN => hdinn, +CH1_HDINN => GND, +D_TXBIT_CLKP_FROM_ND => GND, +D_TXBIT_CLKN_FROM_ND => GND, +D_SYNC_ND => GND, +D_TXPLL_LOL_FROM_ND => GND, +CH0_RX_REFCLK => rxrefclk, +CH1_RX_REFCLK => GND, +CH0_FF_RXI_CLK => TX_PCLK_11, +CH1_FF_RXI_CLK => VCC, +CH0_FF_TXI_CLK => txi_clk, +CH1_FF_TXI_CLK => VCC, +CH0_FF_EBRD_CLK => TX_PCLK_11, +CH1_FF_EBRD_CLK => VCC, +CH0_FF_TX_D_0 => txdata(0), +CH1_FF_TX_D_0 => GND, +CH0_FF_TX_D_1 => txdata(1), +CH1_FF_TX_D_1 => GND, +CH0_FF_TX_D_2 => txdata(2), +CH1_FF_TX_D_2 => GND, +CH0_FF_TX_D_3 => txdata(3), +CH1_FF_TX_D_3 => GND, +CH0_FF_TX_D_4 => txdata(4), +CH1_FF_TX_D_4 => GND, +CH0_FF_TX_D_5 => txdata(5), +CH1_FF_TX_D_5 => GND, +CH0_FF_TX_D_6 => txdata(6), +CH1_FF_TX_D_6 => GND, +CH0_FF_TX_D_7 => txdata(7), +CH1_FF_TX_D_7 => GND, +CH0_FF_TX_D_8 => tx_k(0), +CH1_FF_TX_D_8 => GND, +CH0_FF_TX_D_9 => GND, +CH1_FF_TX_D_9 => GND, +CH0_FF_TX_D_10 => xmit(0), +CH1_FF_TX_D_10 => GND, +CH0_FF_TX_D_11 => tx_disp_correct(0), +CH1_FF_TX_D_11 => GND, +CH0_FF_TX_D_12 => GND, +CH1_FF_TX_D_12 => GND, +CH0_FF_TX_D_13 => GND, +CH1_FF_TX_D_13 => GND, +CH0_FF_TX_D_14 => GND, +CH1_FF_TX_D_14 => GND, +CH0_FF_TX_D_15 => GND, +CH1_FF_TX_D_15 => GND, +CH0_FF_TX_D_16 => GND, +CH1_FF_TX_D_16 => GND, +CH0_FF_TX_D_17 => GND, +CH1_FF_TX_D_17 => GND, +CH0_FF_TX_D_18 => GND, +CH1_FF_TX_D_18 => GND, +CH0_FF_TX_D_19 => GND, +CH1_FF_TX_D_19 => GND, +CH0_FF_TX_D_20 => GND, +CH1_FF_TX_D_20 => GND, +CH0_FF_TX_D_21 => GND, +CH1_FF_TX_D_21 => GND, +CH0_FF_TX_D_22 => GND, +CH1_FF_TX_D_22 => GND, +CH0_FF_TX_D_23 => GND, +CH1_FF_TX_D_23 => GND, +CH0_FFC_EI_EN => GND, +CH1_FFC_EI_EN => GND, +CH0_FFC_PCIE_DET_EN => GND, +CH1_FFC_PCIE_DET_EN => GND, +CH0_FFC_PCIE_CT => GND, +CH1_FFC_PCIE_CT => GND, +CH0_FFC_SB_INV_RX => GND, +CH1_FFC_SB_INV_RX => GND, +CH0_FFC_ENABLE_CGALIGN => GND, +CH1_FFC_ENABLE_CGALIGN => GND, +CH0_FFC_SIGNAL_DETECT => signal_detect_c, +CH1_FFC_SIGNAL_DETECT => GND, +CH0_FFC_FB_LOOPBACK => GND, +CH1_FFC_FB_LOOPBACK => GND, +CH0_FFC_SB_PFIFO_LP => GND, +CH1_FFC_SB_PFIFO_LP => GND, +CH0_FFC_PFIFO_CLR => GND, +CH1_FFC_PFIFO_CLR => GND, +CH0_FFC_RATE_MODE_RX => GND, +CH1_FFC_RATE_MODE_RX => GND, +CH0_FFC_RATE_MODE_TX => GND, +CH1_FFC_RATE_MODE_TX => GND, +CH0_FFC_DIV11_MODE_RX => GND, +CH1_FFC_DIV11_MODE_RX => GND, +CH0_FFC_RX_GEAR_MODE => GND, +CH1_FFC_RX_GEAR_MODE => GND, +CH0_FFC_TX_GEAR_MODE => GND, +CH1_FFC_TX_GEAR_MODE => GND, +CH0_FFC_DIV11_MODE_TX => GND, +CH1_FFC_DIV11_MODE_TX => GND, +CH0_FFC_LDR_CORE2TX_EN => GND, +CH1_FFC_LDR_CORE2TX_EN => GND, +CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C, +CH1_FFC_LANE_TX_RST => GND, +CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C, +CH1_FFC_LANE_RX_RST => GND, +CH0_FFC_RRST => RSL_RX_SERDES_RST_C, +CH1_FFC_RRST => GND, +CH0_FFC_TXPWDNB => tx_pwrup_c, +CH1_FFC_TXPWDNB => GND, +CH0_FFC_RXPWDNB => rx_pwrup_c, +CH1_FFC_RXPWDNB => GND, +CH0_LDR_CORE2TX => GND, +CH1_LDR_CORE2TX => GND, +D_SCIWDATA0 => sci_wrdata(0), +D_SCIWDATA1 => sci_wrdata(1), +D_SCIWDATA2 => sci_wrdata(2), +D_SCIWDATA3 => sci_wrdata(3), +D_SCIWDATA4 => sci_wrdata(4), +D_SCIWDATA5 => sci_wrdata(5), +D_SCIWDATA6 => sci_wrdata(6), +D_SCIWDATA7 => sci_wrdata(7), +D_SCIADDR0 => sci_addr(0), +D_SCIADDR1 => sci_addr(1), +D_SCIADDR2 => sci_addr(2), +D_SCIADDR3 => sci_addr(3), +D_SCIADDR4 => sci_addr(4), +D_SCIADDR5 => sci_addr(5), +D_SCIENAUX => sci_en_dual, +D_SCISELAUX => sci_sel_dual, +CH0_SCIEN => sci_en, +CH1_SCIEN => GND, +CH0_SCISEL => sci_sel, +CH1_SCISEL => GND, +D_SCIRD => sci_rd, +D_SCIWSTN => sci_wrn, +D_CYAWSTN => cyawstn, +D_FFC_SYNC_TOGGLE => GND, +D_FFC_DUAL_RST => rst_dual_c, +D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C, +D_FFC_MACROPDB => serdes_pdb, +D_FFC_TRST => RSL_TX_SERDES_RST_C, +CH0_FFC_CDR_EN_BITSLIP => GND, +CH1_FFC_CDR_EN_BITSLIP => GND, +D_SCAN_ENABLE => GND, +D_SCAN_IN_0 => GND, +D_SCAN_IN_1 => GND, +D_SCAN_IN_2 => GND, +D_SCAN_IN_3 => GND, +D_SCAN_IN_4 => GND, +D_SCAN_IN_5 => GND, +D_SCAN_IN_6 => GND, +D_SCAN_IN_7 => GND, +D_SCAN_MODE => GND, +D_SCAN_RESET => GND, +D_CIN0 => GND, +D_CIN1 => GND, +D_CIN2 => GND, +D_CIN3 => GND, +D_CIN4 => GND, +D_CIN5 => GND, +D_CIN6 => GND, +D_CIN7 => GND, +D_CIN8 => GND, +D_CIN9 => GND, +D_CIN10 => GND, +D_CIN11 => GND, +CH0_HDOUTP => hdoutp, +CH1_HDOUTP => N47_1, +CH0_HDOUTN => hdoutn, +CH1_HDOUTN => N48_1, +D_TXBIT_CLKP_TO_ND => N1_1, +D_TXBIT_CLKN_TO_ND => N2_1, +D_SYNC_PULSE2ND => N3_1, +D_TXPLL_LOL_TO_ND => N4_1, +CH0_FF_RX_F_CLK => N5_1, +CH1_FF_RX_F_CLK => N49_1, +CH0_FF_RX_H_CLK => N6_1, +CH1_FF_RX_H_CLK => N50_1, +CH0_FF_TX_F_CLK => N7_1, +CH1_FF_TX_F_CLK => N51_1, +CH0_FF_TX_H_CLK => N8_1, +CH1_FF_TX_H_CLK => N52_1, +CH0_FF_RX_PCLK => N9_1, +CH1_FF_RX_PCLK => N53_1, +CH0_FF_TX_PCLK => TX_PCLK_I, +CH1_FF_TX_PCLK => N54_1, +CH0_FF_RX_D_0 => rxdata(0), +CH1_FF_RX_D_0 => N55_1, +CH0_FF_RX_D_1 => rxdata(1), +CH1_FF_RX_D_1 => N56_1, +CH0_FF_RX_D_2 => rxdata(2), +CH1_FF_RX_D_2 => N57_1, +CH0_FF_RX_D_3 => rxdata(3), +CH1_FF_RX_D_3 => N58_1, +CH0_FF_RX_D_4 => rxdata(4), +CH1_FF_RX_D_4 => N59_1, +CH0_FF_RX_D_5 => rxdata(5), +CH1_FF_RX_D_5 => N60_1, +CH0_FF_RX_D_6 => rxdata(6), +CH1_FF_RX_D_6 => N61_1, +CH0_FF_RX_D_7 => rxdata(7), +CH1_FF_RX_D_7 => N62_1, +CH0_FF_RX_D_8 => rx_k(0), +CH1_FF_RX_D_8 => N63_1, +CH0_FF_RX_D_9 => rx_disp_err(0), +CH1_FF_RX_D_9 => N64_1, +CH0_FF_RX_D_10 => rx_cv_err(0), +CH1_FF_RX_D_10 => N65_1, +CH0_FF_RX_D_11 => N10_1, +CH1_FF_RX_D_11 => N66_1, +CH0_FF_RX_D_12 => N67_1, +CH1_FF_RX_D_12 => N68_1, +CH0_FF_RX_D_13 => N69_1, +CH1_FF_RX_D_13 => N70_1, +CH0_FF_RX_D_14 => N71_1, +CH1_FF_RX_D_14 => N72_1, +CH0_FF_RX_D_15 => N73_1, +CH1_FF_RX_D_15 => N74_1, +CH0_FF_RX_D_16 => N75_1, +CH1_FF_RX_D_16 => N76_1, +CH0_FF_RX_D_17 => N77_1, +CH1_FF_RX_D_17 => N78_1, +CH0_FF_RX_D_18 => N79_1, +CH1_FF_RX_D_18 => N80_1, +CH0_FF_RX_D_19 => N81_1, +CH1_FF_RX_D_19 => N82_1, +CH0_FF_RX_D_20 => N83_1, +CH1_FF_RX_D_20 => N84_1, +CH0_FF_RX_D_21 => N85_1, +CH1_FF_RX_D_21 => N86_1, +CH0_FF_RX_D_22 => N87_1, +CH1_FF_RX_D_22 => N88_1, +CH0_FF_RX_D_23 => N11_1, +CH1_FF_RX_D_23 => N89_1, +CH0_FFS_PCIE_DONE => N12_1, +CH1_FFS_PCIE_DONE => N90_1, +CH0_FFS_PCIE_CON => N13_1, +CH1_FFS_PCIE_CON => N91_1, +CH0_FFS_RLOS => RX_LOS_LOW_S_12, +CH1_FFS_RLOS => N92_1, +CH0_FFS_LS_SYNC_STATUS => lsm_status_s, +CH1_FFS_LS_SYNC_STATUS => N93_1, +CH0_FFS_CC_UNDERRUN => ctc_urun_s, +CH1_FFS_CC_UNDERRUN => N94_1, +CH0_FFS_CC_OVERRUN => ctc_orun_s, +CH1_FFS_CC_OVERRUN => N95_1, +CH0_FFS_RXFBFIFO_ERROR => N14_1, +CH1_FFS_RXFBFIFO_ERROR => N96_1, +CH0_FFS_TXFBFIFO_ERROR => N15_1, +CH1_FFS_TXFBFIFO_ERROR => N97_1, +CH0_FFS_RLOL => RX_CDR_LOL_S_13, +CH1_FFS_RLOL => N98_1, +CH0_FFS_SKP_ADDED => ctc_ins_s, +CH1_FFS_SKP_ADDED => N99_1, +CH0_FFS_SKP_DELETED => ctc_del_s, +CH1_FFS_SKP_DELETED => N100_1, +CH0_LDR_RX2CORE => N101_1, +CH1_LDR_RX2CORE => N112_1, +D_SCIRDATA0 => sci_rddata(0), +D_SCIRDATA1 => sci_rddata(1), +D_SCIRDATA2 => sci_rddata(2), +D_SCIRDATA3 => sci_rddata(3), +D_SCIRDATA4 => sci_rddata(4), +D_SCIRDATA5 => sci_rddata(5), +D_SCIRDATA6 => sci_rddata(6), +D_SCIRDATA7 => sci_rddata(7), +D_SCIINT => sci_int, +D_SCAN_OUT_0 => N16_1, +D_SCAN_OUT_1 => N17_1, +D_SCAN_OUT_2 => N18_1, +D_SCAN_OUT_3 => N19_1, +D_SCAN_OUT_4 => N20_1, +D_SCAN_OUT_5 => N21_1, +D_SCAN_OUT_6 => N22_1, +D_SCAN_OUT_7 => N23_1, +D_COUT0 => N24_1, +D_COUT1 => N25_1, +D_COUT2 => N26_1, +D_COUT3 => N27_1, +D_COUT4 => N28_1, +D_COUT5 => N29_1, +D_COUT6 => N30_1, +D_COUT7 => N31_1, +D_COUT8 => N32_1, +D_COUT9 => N33_1, +D_COUT10 => N34_1, +D_COUT11 => N35_1, +D_COUT12 => N36_1, +D_COUT13 => N37_1, +D_COUT14 => N38_1, +D_COUT15 => N39_1, +D_COUT16 => N40_1, +D_COUT17 => N41_1, +D_COUT18 => N42_1, +D_COUT19 => N43_1, +D_REFCLKI => pll_refclki, +D_FFS_PLOL => N46_1); +SLL_INST: sgmii_ecp5sll_core_Z1_layer1 port map ( +tx_pclk => TX_PCLK_11, +sli_rst => sli_rst, +pll_refclki => pll_refclki, +pll_lock_i => \SLL_INST.PLL_LOCK_I_14\); +RSL_INST: sgmii_ecp5rsl_core_Z2_layer1 port map ( +rx_pcs_rst_c => rx_pcs_rst_c, +tx_pcs_rst_c => tx_pcs_rst_c, +serdes_rst_dual_c => serdes_rst_dual_c, +tx_serdes_rst_c => tx_serdes_rst_c, +rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C, +rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C, +rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C, +rsl_tx_rdy => rsl_tx_rdy, +pll_lock_i => \SLL_INST.PLL_LOCK_I_14\, +pll_refclki => pll_refclki, +rsl_rx_rdy => rsl_rx_rdy, +rsl_rst => rsl_rst, +rxrefclk => rxrefclk, +rsl_disable => rsl_disable, +rx_serdes_rst_c => rx_serdes_rst_c, +rst_dual_c => rst_dual_c, +rx_cdr_lol_s => RX_CDR_LOL_S_13, +rx_los_low_s => RX_LOS_LOW_S_12, +rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C, +rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C); +tx_pclk <= TX_PCLK_11; +rx_los_low_s <= RX_LOS_LOW_S_12; +rx_cdr_lol_s <= RX_CDR_LOL_S_13; +pll_lol <= \SLL_INST.PLL_LOCK_I_14\; +end beh; + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vm new file mode 100644 index 0000000..be4d326 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vm @@ -0,0 +1,6617 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Fri May 10 11:59:01 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v " +// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v " +// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v " +// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v " +// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v " +// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh " +// file 16 "\/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v " +// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 18 "\/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc " + +`timescale 100 ps/100 ps +module sync_0s ( + phb, + rhb_sync, + sli_rst, + pll_refclki +) +; +input phb ; +output rhb_sync ; +input sli_rst ; +input pll_refclki ; +wire phb ; +wire rhb_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_0 ; +wire VCC ; +wire data_p1_QN_0 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(phb), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s */ + +module sync_0s_6 ( + rtc_pul, + ppul_sync, + sli_rst, + tx_pclk +) +; +input rtc_pul ; +output ppul_sync ; +input sli_rst ; +input tx_pclk ; +wire rtc_pul ; +wire ppul_sync ; +wire sli_rst ; +wire tx_pclk ; +wire data_p1 ; +wire data_p2_QN ; +wire VCC ; +wire data_p1_QN ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(rtc_pul), + .CK(tx_pclk), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_6 */ + +module sync_0s_0 ( + ppul_sync, + pdiff_sync, + sli_rst, + pll_refclki +) +; +input ppul_sync ; +output pdiff_sync ; +input sli_rst ; +input pll_refclki ; +wire ppul_sync ; +wire pdiff_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_1 ; +wire VCC ; +wire data_p1_QN_1 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(ppul_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_0 */ + +module sgmii_ecp5sll_core_Z1_layer1 ( + tx_pclk, + sli_rst, + pll_refclki, + pll_lock_i +) +; +input tx_pclk ; +input sli_rst ; +input pll_refclki ; +output pll_lock_i ; +wire tx_pclk ; +wire sli_rst ; +wire pll_refclki ; +wire pll_lock_i ; +wire [2:0] phb_cnt; +wire [2:0] phb_cnt_i; +wire [15:0] rcount; +wire [21:0] pcount; +wire [0:0] un1_pcount_diff_i; +wire [1:0] sll_state; +wire [1:0] sll_state_QN; +wire [7:0] rhb_wait_cnt_s; +wire [7:0] rhb_wait_cnt; +wire [7:0] rhb_wait_cnt_QN; +wire [15:0] rcount_s; +wire [15:0] rcount_QN; +wire [2:0] phb_cnt_QN; +wire [2:1] phb_cnt_RNO; +wire [21:0] pcount_s; +wire [21:0] pcount_QN; +wire [21:0] pcount_diff_QN; +wire [2:2] rdiff_comp_lock; +wire [2:2] rdiff_comp_lock_QN; +wire [0:0] un1_pcount_diff; +wire [20:0] pcount_cry; +wire [0:0] pcount_cry_0_S0; +wire [21:21] pcount_s_0_COUT; +wire [21:21] pcount_s_0_S1; +wire [14:0] rcount_cry; +wire [0:0] rcount_cry_0_S0; +wire [15:15] rcount_s_0_COUT; +wire [15:15] rcount_s_0_S1; +wire [6:0] rhb_wait_cnt_cry; +wire [0:0] rhb_wait_cnt_cry_0_S0; +wire [7:7] rhb_wait_cnt_s_0_COUT; +wire [7:7] rhb_wait_cnt_s_0_S1; +wire pll_lock ; +wire rtc_ctrl4_0_a3_1 ; +wire un13_lock_20 ; +wire ppul_sync_p2 ; +wire ppul_sync_p1 ; +wire un1_pcount_diff_1_axb_20 ; +wire un13_lock_19 ; +wire un1_pcount_diff_1_axb_19 ; +wire un13_lock_18 ; +wire un1_pcount_diff_1_axb_18 ; +wire un13_lock_17 ; +wire un1_pcount_diff_1_axb_17 ; +wire un13_lock_16 ; +wire un1_pcount_diff_1_cry_15_0_RNO_0 ; +wire un13_lock_15 ; +wire un1_pcount_diff_1_axb_15 ; +wire un13_lock_14 ; +wire un1_pcount_diff_1_axb_14 ; +wire un13_lock_13 ; +wire un1_pcount_diff_1_axb_13 ; +wire un13_lock_12 ; +wire un1_pcount_diff_1_axb_12 ; +wire un13_lock_11 ; +wire un1_pcount_diff_1_axb_11 ; +wire un13_lock_10 ; +wire un1_pcount_diff_1_axb_10 ; +wire un13_lock_9 ; +wire un1_pcount_diff_1_axb_9 ; +wire un13_lock_8 ; +wire un1_pcount_diff_1_axb_8 ; +wire un13_lock_7 ; +wire un1_pcount_diff_1_axb_7 ; +wire un13_lock_6 ; +wire un1_pcount_diff_1_axb_6 ; +wire un13_lock_5 ; +wire un1_pcount_diff_1_axb_5 ; +wire un13_lock_4 ; +wire un1_pcount_diff_1_axb_4 ; +wire un13_lock_3 ; +wire un1_pcount_diff_1_axb_3 ; +wire un13_lock_2 ; +wire un1_pcount_diff_1_axb_2 ; +wire un13_lock_1 ; +wire un1_pcount_diff_1_axb_1 ; +wire un13_lock_21 ; +wire ppul_sync_p3 ; +wire N_7 ; +wire un13_lock_0 ; +wire rtc_ctrl4 ; +wire rtc_ctrl ; +wire VCC ; +wire N_2121_0 ; +wire unlock_5 ; +wire unlock_1_sqmuxa_i ; +wire unlock ; +wire unlock_QN ; +wire N_95_i ; +wire N_97_i ; +wire rtc_pul ; +wire rtc_pul_p1 ; +wire rtc_pul_p1_QN ; +wire rtc_pul5 ; +wire rtc_pul_QN ; +wire rtc_ctrl_QN ; +wire rstat_pclk_2 ; +wire rstat_pclk ; +wire rstat_pclk_QN ; +wire rhb_sync_p1 ; +wire rhb_sync_p2 ; +wire rhb_sync_p2_QN ; +wire rhb_sync ; +wire rhb_sync_p1_QN ; +wire ppul_sync_p3_QN ; +wire ppul_sync_p2_QN ; +wire ppul_sync ; +wire ppul_sync_p1_QN ; +wire N_53_i ; +wire pll_lock_QN ; +wire phb ; +wire phb_QN ; +wire pdiff_sync ; +wire pdiff_sync_p1 ; +wire pdiff_sync_p1_QN ; +wire un1_pcount_diff_1_cry_1_0_S0 ; +wire un1_pcount_diff_1_cry_1_0_S1 ; +wire un1_pcount_diff_1_cry_3_0_S0 ; +wire un1_pcount_diff_1_cry_3_0_S1 ; +wire un1_pcount_diff_1_cry_5_0_S0 ; +wire un1_pcount_diff_1_cry_5_0_S1 ; +wire un1_pcount_diff_1_cry_7_0_S0 ; +wire un1_pcount_diff_1_cry_7_0_S1 ; +wire un1_pcount_diff_1_cry_9_0_S0 ; +wire un1_pcount_diff_1_cry_9_0_S1 ; +wire un1_pcount_diff_1_cry_11_0_S0 ; +wire un1_pcount_diff_1_cry_11_0_S1 ; +wire un1_pcount_diff_1_cry_13_0_S0 ; +wire un1_pcount_diff_1_cry_13_0_S1 ; +wire un1_pcount_diff_1_cry_15_0_S0 ; +wire un1_pcount_diff_1_cry_15_0_S1 ; +wire un1_pcount_diff_1_cry_17_0_S0 ; +wire un1_pcount_diff_1_cry_17_0_S1 ; +wire un1_pcount_diff_1_cry_19_0_S0 ; +wire un1_pcount_diff_1_cry_19_0_S1 ; +wire un1_pcount_diff_1_s_21_0_S0 ; +wire lock_5 ; +wire lock_1_sqmuxa_i ; +wire lock ; +wire lock_QN ; +wire N_98 ; +wire rtc_pul5_0_o3 ; +wire rtc_pul5_0_a3_6 ; +wire rtc_pul5_0_a3_7 ; +wire un1_rcount_1_0_a3 ; +wire rhb_wait_cnt12 ; +wire un1_rhb_wait_cnt_4 ; +wire un1_rhb_wait_cnt_5 ; +wire N_99 ; +wire rtc_ctrl4_0_a3_12_4 ; +wire rtc_ctrl4_0_a3_12_5 ; +wire rtc_ctrl4_10 ; +wire un1_rcount_1_0_a3_1 ; +wire N_6 ; +wire rtc_pul5_0_a3_5 ; +wire N_8 ; +wire un13_unlock_cry_21 ; +wire un13_lock_cry_21_i ; +wire rhb_wait_cnt_scalar ; +wire un1_pcount_diff_1_cry_0 ; +wire un1_pcount_diff_1_cry_0_0_S0 ; +wire un1_pcount_diff_1_cry_0_0_S1 ; +wire un1_pcount_diff_1_cry_2 ; +wire un1_pcount_diff_1_cry_4 ; +wire un1_pcount_diff_1_cry_6 ; +wire un1_pcount_diff_1_cry_8 ; +wire un1_pcount_diff_1_cry_10 ; +wire un1_pcount_diff_1_cry_12 ; +wire un1_pcount_diff_1_cry_14 ; +wire un1_pcount_diff_1_cry_16 ; +wire un1_pcount_diff_1_cry_18 ; +wire un1_pcount_diff_1_cry_20 ; +wire un1_pcount_diff_1_s_21_0_COUT ; +wire un1_pcount_diff_1_s_21_0_S1 ; +wire un13_lock_cry_0 ; +wire un13_lock_cry_0_0_S0 ; +wire un13_lock_cry_0_0_S1 ; +wire un13_lock_cry_2 ; +wire un13_lock_cry_1_0_S0 ; +wire un13_lock_cry_1_0_S1 ; +wire un13_lock_cry_4 ; +wire un13_lock_cry_3_0_S0 ; +wire un13_lock_cry_3_0_S1 ; +wire un13_lock_cry_6 ; +wire un13_lock_cry_5_0_S0 ; +wire un13_lock_cry_5_0_S1 ; +wire un13_lock_cry_8 ; +wire un13_lock_cry_7_0_S0 ; +wire un13_lock_cry_7_0_S1 ; +wire un13_lock_cry_10 ; +wire un13_lock_cry_9_0_S0 ; +wire un13_lock_cry_9_0_S1 ; +wire un13_lock_cry_12 ; +wire un13_lock_cry_11_0_S0 ; +wire un13_lock_cry_11_0_S1 ; +wire un13_lock_cry_14 ; +wire un13_lock_cry_13_0_S0 ; +wire un13_lock_cry_13_0_S1 ; +wire un13_lock_cry_16 ; +wire un13_lock_cry_15_0_S0 ; +wire un13_lock_cry_15_0_S1 ; +wire un13_lock_cry_18 ; +wire un13_lock_cry_17_0_S0 ; +wire un13_lock_cry_17_0_S1 ; +wire un13_lock_cry_20 ; +wire un13_lock_cry_19_0_S0 ; +wire un13_lock_cry_19_0_S1 ; +wire un13_lock_cry_21_0_COUT ; +wire un13_lock_cry_21_0_S0 ; +wire un13_unlock_cry_0 ; +wire un13_unlock_cry_0_0_S0 ; +wire un13_unlock_cry_0_0_S1 ; +wire un13_unlock_cry_2 ; +wire un13_unlock_cry_1_0_S0 ; +wire un13_unlock_cry_1_0_S1 ; +wire un13_unlock_cry_4 ; +wire un13_unlock_cry_3_0_S0 ; +wire un13_unlock_cry_3_0_S1 ; +wire un13_unlock_cry_6 ; +wire un13_unlock_cry_5_0_S0 ; +wire un13_unlock_cry_5_0_S1 ; +wire un13_unlock_cry_8 ; +wire un13_unlock_cry_7_0_S0 ; +wire un13_unlock_cry_7_0_S1 ; +wire un13_unlock_cry_10 ; +wire un13_unlock_cry_9_0_S0 ; +wire un13_unlock_cry_9_0_S1 ; +wire un13_unlock_cry_12 ; +wire un13_unlock_cry_11_0_S0 ; +wire un13_unlock_cry_11_0_S1 ; +wire un13_unlock_cry_14 ; +wire un13_unlock_cry_13_0_S0 ; +wire un13_unlock_cry_13_0_S1 ; +wire un13_unlock_cry_16 ; +wire un13_unlock_cry_15_0_S0 ; +wire un13_unlock_cry_15_0_S1 ; +wire un13_unlock_cry_18 ; +wire un13_unlock_cry_17_0_S0 ; +wire un13_unlock_cry_17_0_S1 ; +wire un13_unlock_cry_20 ; +wire un13_unlock_cry_19_0_S0 ; +wire un13_unlock_cry_19_0_S1 ; +wire un13_unlock_cry_21_0_COUT ; +wire un13_unlock_cry_21_0_S0 ; +wire N_21 ; +wire N_20 ; +wire N_19 ; +wire N_18 ; +wire N_14 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_9 ; + INV phb_RNO ( + .A(phb_cnt[2]), + .Z(phb_cnt_i[2]) +); + INV \phb_cnt_RNO[0] ( + .A(phb_cnt[0]), + .Z(phb_cnt_i[0]) +); + INV pll_lock_RNI6JK9 ( + .A(pll_lock), + .Z(pll_lock_i) +); + LUT4 rtc_ctrl4_0_a3_RNO ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(rtc_ctrl4_0_a3_1) +); +defparam rtc_ctrl4_0_a3_RNO.init=16'h2000; + LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 ( + .A(un13_lock_20), + .B(pcount[20]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_20) +); +defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_19_0_RNO ( + .A(un13_lock_19), + .B(pcount[19]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_19) +); +defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 ( + .A(un13_lock_18), + .B(pcount[18]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_18) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO ( + .A(un13_lock_17), + .B(pcount[17]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_17) +); +defparam un1_pcount_diff_1_cry_17_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO_0_cZ ( + .A(un13_lock_16), + .B(pcount[16]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_cry_15_0_RNO_0) +); +defparam un1_pcount_diff_1_cry_15_0_RNO_0_cZ.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO ( + .A(un13_lock_15), + .B(pcount[15]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_15) +); +defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 ( + .A(un13_lock_14), + .B(pcount[14]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_14) +); +defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO ( + .A(un13_lock_13), + .B(pcount[13]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_13) +); +defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 ( + .A(un13_lock_12), + .B(pcount[12]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_12) +); +defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO ( + .A(un13_lock_11), + .B(pcount[11]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_11) +); +defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 ( + .A(un13_lock_10), + .B(pcount[10]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_10) +); +defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO ( + .A(un13_lock_9), + .B(pcount[9]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_9) +); +defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 ( + .A(un13_lock_8), + .B(pcount[8]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_8) +); +defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO ( + .A(un13_lock_7), + .B(pcount[7]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_7) +); +defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 ( + .A(un13_lock_6), + .B(pcount[6]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_6) +); +defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO ( + .A(un13_lock_5), + .B(pcount[5]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_5) +); +defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 ( + .A(un13_lock_4), + .B(pcount[4]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_4) +); +defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO ( + .A(un13_lock_3), + .B(pcount[3]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_3) +); +defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 ( + .A(un13_lock_2), + .B(pcount[2]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_2) +); +defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO ( + .A(un13_lock_1), + .B(pcount[1]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_1) +); +defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355; + LUT4 ppul_sync_p3_RNIU65C ( + .A(un13_lock_21), + .B(ppul_sync_p3), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(N_7) +); +defparam ppul_sync_p3_RNIU65C.init=16'h2F20; + LUT4 \pcount_diff_RNO[0] ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(pcount[0]), + .D(un13_lock_0), + .Z(un1_pcount_diff_i[0]) +); +defparam \pcount_diff_RNO[0] .init=16'hFD20; +// @16:1304 + LUT4 rtc_ctrl_0 ( + .A(rtc_ctrl4), + .B(rtc_ctrl), + .C(VCC), + .D(VCC), + .Z(N_2121_0) +); +defparam rtc_ctrl_0.init=16'hEEEE; +// @16:1278 + FD1P3DX unlock_reg ( + .D(unlock_5), + .SP(unlock_1_sqmuxa_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(unlock) +); +// @16:1801 + FD1S3DX \sll_state_reg[0] ( + .D(N_95_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[0]) +); +// @16:1801 + FD1S3DX \sll_state_reg[1] ( + .D(N_97_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[1]) +); +// @16:1304 + FD1S3DX rtc_pul_p1_reg ( + .D(rtc_pul), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul_p1) +); +// @16:1304 + FD1P3DX rtc_pul_reg ( + .D(rtc_pul5), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul) +); +// @16:1304 + FD1S3DX rtc_ctrl_reg ( + .D(N_2121_0), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_ctrl) +); +// @16:1350 + FD1P3DX rstat_pclk_reg ( + .D(rstat_pclk_2), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rstat_pclk) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[0] ( + .D(rhb_wait_cnt_s[0]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[0]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[1] ( + .D(rhb_wait_cnt_s[1]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[1]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[2] ( + .D(rhb_wait_cnt_s[2]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[2]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[3] ( + .D(rhb_wait_cnt_s[3]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[3]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[4] ( + .D(rhb_wait_cnt_s[4]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[4]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[5] ( + .D(rhb_wait_cnt_s[5]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[5]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[6] ( + .D(rhb_wait_cnt_s[6]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[6]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[7] ( + .D(rhb_wait_cnt_s[7]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[7]) +); +// @16:1350 + FD1S3DX rhb_sync_p2_reg ( + .D(rhb_sync_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p2) +); +// @16:1350 + FD1S3DX rhb_sync_p1_reg ( + .D(rhb_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p1) +); +// @16:1304 + FD1S3DX \rcount_reg[0] ( + .D(rcount_s[0]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[0]) +); +// @16:1304 + FD1S3DX \rcount_reg[1] ( + .D(rcount_s[1]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[1]) +); +// @16:1304 + FD1S3DX \rcount_reg[2] ( + .D(rcount_s[2]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[2]) +); +// @16:1304 + FD1S3DX \rcount_reg[3] ( + .D(rcount_s[3]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[3]) +); +// @16:1304 + FD1S3DX \rcount_reg[4] ( + .D(rcount_s[4]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[4]) +); +// @16:1304 + FD1S3DX \rcount_reg[5] ( + .D(rcount_s[5]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[5]) +); +// @16:1304 + FD1S3DX \rcount_reg[6] ( + .D(rcount_s[6]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[6]) +); +// @16:1304 + FD1S3DX \rcount_reg[7] ( + .D(rcount_s[7]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[7]) +); +// @16:1304 + FD1S3DX \rcount_reg[8] ( + .D(rcount_s[8]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[8]) +); +// @16:1304 + FD1S3DX \rcount_reg[9] ( + .D(rcount_s[9]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[9]) +); +// @16:1304 + FD1S3DX \rcount_reg[10] ( + .D(rcount_s[10]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[10]) +); +// @16:1304 + FD1S3DX \rcount_reg[11] ( + .D(rcount_s[11]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[11]) +); +// @16:1304 + FD1S3DX \rcount_reg[12] ( + .D(rcount_s[12]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[12]) +); +// @16:1304 + FD1S3DX \rcount_reg[13] ( + .D(rcount_s[13]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[13]) +); +// @16:1304 + FD1S3DX \rcount_reg[14] ( + .D(rcount_s[14]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[14]) +); +// @16:1304 + FD1S3DX \rcount_reg[15] ( + .D(rcount_s[15]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[15]) +); +// @16:1408 + FD1S3DX ppul_sync_p3_reg ( + .D(ppul_sync_p2), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p3) +); +// @16:1408 + FD1S3DX ppul_sync_p2_reg ( + .D(ppul_sync_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p2) +); +// @16:1408 + FD1S3DX ppul_sync_p1_reg ( + .D(ppul_sync), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p1) +); +// @16:1879 + FD1S3DX pll_lock_reg ( + .D(N_53_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pll_lock) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[0] ( + .D(phb_cnt_i[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[0]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[1] ( + .D(phb_cnt_RNO[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[1]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[2] ( + .D(phb_cnt_RNO[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[2]) +); +// @16:1759 + FD1S3DX phb_reg ( + .D(phb_cnt_i[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb) +); +// @16:1278 + FD1S3DX pdiff_sync_p1_reg ( + .D(pdiff_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync_p1) +); +// @16:1759 + FD1S3DX \pcount_reg[0] ( + .D(pcount_s[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[0]) +); +// @16:1759 + FD1P3BX \pcount_diff[0] ( + .D(un1_pcount_diff_i[0]), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_0) +); +// @16:1759 + FD1S3DX \pcount_reg[1] ( + .D(pcount_s[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[1]) +); +// @16:1759 + FD1P3BX \pcount_diff[1] ( + .D(un1_pcount_diff_1_cry_1_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_1) +); +// @16:1759 + FD1P3BX \pcount_diff[2] ( + .D(un1_pcount_diff_1_cry_1_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_2) +); +// @16:1759 + FD1S3DX \pcount_reg[2] ( + .D(pcount_s[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[2]) +); +// @16:1759 + FD1P3BX \pcount_diff[3] ( + .D(un1_pcount_diff_1_cry_3_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_3) +); +// @16:1759 + FD1S3DX \pcount_reg[3] ( + .D(pcount_s[3]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[3]) +); +// @16:1759 + FD1P3BX \pcount_diff[4] ( + .D(un1_pcount_diff_1_cry_3_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_4) +); +// @16:1759 + FD1S3DX \pcount_reg[4] ( + .D(pcount_s[4]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[4]) +); +// @16:1759 + FD1P3BX \pcount_diff[5] ( + .D(un1_pcount_diff_1_cry_5_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_5) +); +// @16:1759 + FD1S3DX \pcount_reg[5] ( + .D(pcount_s[5]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[5]) +); +// @16:1759 + FD1S3DX \pcount_reg[6] ( + .D(pcount_s[6]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[6]) +); +// @16:1759 + FD1P3BX \pcount_diff[6] ( + .D(un1_pcount_diff_1_cry_5_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_6) +); +// @16:1759 + FD1S3DX \pcount_reg[7] ( + .D(pcount_s[7]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[7]) +); +// @16:1759 + FD1P3BX \pcount_diff[7] ( + .D(un1_pcount_diff_1_cry_7_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_7) +); +// @16:1759 + FD1S3DX \pcount_reg[8] ( + .D(pcount_s[8]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[8]) +); +// @16:1759 + FD1P3BX \pcount_diff[8] ( + .D(un1_pcount_diff_1_cry_7_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_8) +); +// @16:1759 + FD1P3BX \pcount_diff[9] ( + .D(un1_pcount_diff_1_cry_9_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_9) +); +// @16:1759 + FD1S3DX \pcount_reg[9] ( + .D(pcount_s[9]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[9]) +); +// @16:1759 + FD1S3DX \pcount_reg[10] ( + .D(pcount_s[10]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[10]) +); +// @16:1759 + FD1P3BX \pcount_diff[10] ( + .D(un1_pcount_diff_1_cry_9_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_10) +); +// @16:1759 + FD1P3BX \pcount_diff[11] ( + .D(un1_pcount_diff_1_cry_11_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_11) +); +// @16:1759 + FD1S3DX \pcount_reg[11] ( + .D(pcount_s[11]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[11]) +); +// @16:1759 + FD1S3DX \pcount_reg[12] ( + .D(pcount_s[12]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[12]) +); +// @16:1759 + FD1P3BX \pcount_diff[12] ( + .D(un1_pcount_diff_1_cry_11_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_12) +); +// @16:1759 + FD1P3BX \pcount_diff[13] ( + .D(un1_pcount_diff_1_cry_13_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_13) +); +// @16:1759 + FD1S3DX \pcount_reg[13] ( + .D(pcount_s[13]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[13]) +); +// @16:1759 + FD1P3BX \pcount_diff[14] ( + .D(un1_pcount_diff_1_cry_13_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_14) +); +// @16:1759 + FD1S3DX \pcount_reg[14] ( + .D(pcount_s[14]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[14]) +); +// @16:1759 + FD1S3DX \pcount_reg[15] ( + .D(pcount_s[15]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[15]) +); +// @16:1759 + FD1P3BX \pcount_diff[15] ( + .D(un1_pcount_diff_1_cry_15_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_15) +); +// @16:1759 + FD1S3DX \pcount_reg[16] ( + .D(pcount_s[16]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[16]) +); +// @16:1759 + FD1P3DX \pcount_diff[16] ( + .D(un1_pcount_diff_1_cry_15_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_16) +); +// @16:1759 + FD1P3DX \pcount_diff[17] ( + .D(un1_pcount_diff_1_cry_17_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_17) +); +// @16:1759 + FD1S3DX \pcount_reg[17] ( + .D(pcount_s[17]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[17]) +); +// @16:1759 + FD1P3DX \pcount_diff[18] ( + .D(un1_pcount_diff_1_cry_17_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_18) +); +// @16:1759 + FD1S3DX \pcount_reg[18] ( + .D(pcount_s[18]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[18]) +); +// @16:1759 + FD1S3DX \pcount_reg[19] ( + .D(pcount_s[19]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[19]) +); +// @16:1759 + FD1P3DX \pcount_diff[19] ( + .D(un1_pcount_diff_1_cry_19_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_19) +); +// @16:1759 + FD1S3DX \pcount_reg[20] ( + .D(pcount_s[20]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[20]) +); +// @16:1759 + FD1P3DX \pcount_diff[20] ( + .D(un1_pcount_diff_1_cry_19_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_20) +); +// @16:1759 + FD1P3DX \pcount_diff[21] ( + .D(un1_pcount_diff_1_s_21_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_21) +); +// @16:1759 + FD1S3DX \pcount_reg[21] ( + .D(pcount_s[21]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[21]) +); +// @16:1278 + FD1P3DX lock_reg ( + .D(lock_5), + .SP(lock_1_sqmuxa_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(lock) +); +// @16:1739 + FD1S3DX \genblk5.rdiff_comp_lock[2] ( + .D(VCC), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rdiff_comp_lock[2]) +); +// @16:1801 + LUT4 \sll_state_RNO[0] ( + .A(N_98), + .B(lock), + .C(rstat_pclk), + .D(sll_state[0]), + .Z(N_95_i) +); +defparam \sll_state_RNO[0] .init=16'hE050; +// @16:1334 + LUT4 rtc_pul5_0_0 ( + .A(rtc_pul5_0_o3), + .B(rtc_pul5_0_a3_6), + .C(rtc_pul5_0_a3_7), + .D(un1_rcount_1_0_a3), + .Z(rtc_pul5) +); +defparam rtc_pul5_0_0.init=16'hFF80; +// @16:1389 + LUT4 rstat_pclk_2_iv ( + .A(rhb_wait_cnt12), + .B(rstat_pclk), + .C(un1_rhb_wait_cnt_4), + .D(un1_rhb_wait_cnt_5), + .Z(rstat_pclk_2) +); +defparam rstat_pclk_2_iv.init=16'hAEEE; +// @16:1801 + LUT4 \sll_state_RNO[1] ( + .A(N_99), + .B(rstat_pclk), + .C(sll_state[1]), + .D(unlock), + .Z(N_97_i) +); +defparam \sll_state_RNO[1] .init=16'h8088; +// @16:1328 + LUT4 rtc_ctrl4_0_a3 ( + .A(rtc_ctrl4_0_a3_1), + .B(rtc_ctrl4_0_a3_12_4), + .C(rtc_ctrl4_0_a3_12_5), + .D(rtc_ctrl4_10), + .Z(rtc_ctrl4) +); +defparam rtc_ctrl4_0_a3.init=16'h8000; +// @16:1319 + LUT4 un1_rcount_1_0_a3_cZ ( + .A(rtc_ctrl4_0_a3_12_4), + .B(rtc_ctrl4_0_a3_12_5), + .C(rtc_ctrl4_10), + .D(un1_rcount_1_0_a3_1), + .Z(un1_rcount_1_0_a3) +); +defparam un1_rcount_1_0_a3_cZ.init=16'h8000; +// @16:1278 + LUT4 lock_1_sqmuxa_i_cZ ( + .A(lock), + .B(pdiff_sync), + .C(pdiff_sync_p1), + .D(VCC), + .Z(lock_1_sqmuxa_i) +); +defparam lock_1_sqmuxa_i_cZ.init=16'h7575; +// @16:1278 + LUT4 unlock_1_sqmuxa_i_cZ ( + .A(pdiff_sync), + .B(pdiff_sync_p1), + .C(unlock), + .D(VCC), + .Z(unlock_1_sqmuxa_i) +); +defparam unlock_1_sqmuxa_i_cZ.init=16'h4F4F; +// @16:1334 + LUT4 rtc_pul5_0_o3_cZ ( + .A(N_6), + .B(rcount[1]), + .C(rcount[2]), + .D(rcount[3]), + .Z(rtc_pul5_0_o3) +); +defparam rtc_pul5_0_o3_cZ.init=16'hAAAB; +// @16:1334 + LUT4 rtc_pul5_0_a3_7_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rtc_pul5_0_a3_5), + .D(VCC), + .Z(rtc_pul5_0_a3_7) +); +defparam rtc_pul5_0_a3_7_cZ.init=16'h1010; +// @16:1801 + LUT4 \sll_state_ns_i_m4[1] ( + .A(lock), + .B(rtc_pul), + .C(rtc_pul_p1), + .D(sll_state[1]), + .Z(N_99) +); +defparam \sll_state_ns_i_m4[1] .init=16'hEF20; +// @16:1879 + LUT4 pll_lock_RNO ( + .A(sll_state[0]), + .B(sll_state[1]), + .C(VCC), + .D(VCC), + .Z(N_53_i) +); +defparam pll_lock_RNO.init=16'h8888; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[2] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(phb_cnt[2]), + .D(VCC), + .Z(phb_cnt_RNO[2]) +); +defparam \phb_cnt_RNO_cZ[2] .init=16'h7878; +// @16:1801 + LUT4 \sll_state_ns_i_o4[0] ( + .A(rtc_pul), + .B(rtc_pul_p1), + .C(sll_state[1]), + .D(VCC), + .Z(N_98) +); +defparam \sll_state_ns_i_o4[0] .init=16'hBFBF; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_10 ( + .A(rcount[1]), + .B(rcount[3]), + .C(rcount[6]), + .D(rcount[15]), + .Z(rtc_ctrl4_10) +); +defparam rtc_ctrl4_0_a3_10.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_4_cZ ( + .A(rhb_wait_cnt[4]), + .B(rhb_wait_cnt[5]), + .C(rhb_wait_cnt[6]), + .D(rhb_wait_cnt[7]), + .Z(un1_rhb_wait_cnt_4) +); +defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_5_cZ ( + .A(rhb_wait_cnt[0]), + .B(rhb_wait_cnt[1]), + .C(rhb_wait_cnt[2]), + .D(rhb_wait_cnt[3]), + .Z(un1_rhb_wait_cnt_5) +); +defparam un1_rhb_wait_cnt_5_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_4_cZ ( + .A(rcount[11]), + .B(rcount[12]), + .C(rcount[13]), + .D(rcount[14]), + .Z(rtc_ctrl4_0_a3_12_4) +); +defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_5_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rcount[9]), + .D(rcount[10]), + .Z(rtc_ctrl4_0_a3_12_5) +); +defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000; +// @16:1334 + LUT4 rtc_pul5_0_a3_5_cZ ( + .A(rcount[6]), + .B(rcount[13]), + .C(rcount[14]), + .D(rcount[15]), + .Z(rtc_pul5_0_a3_5) +); +defparam rtc_pul5_0_a3_5_cZ.init=16'h0001; +// @16:1334 + LUT4 rtc_pul5_0_a3_6_cZ ( + .A(rcount[9]), + .B(rcount[10]), + .C(rcount[11]), + .D(rcount[12]), + .Z(rtc_pul5_0_a3_6) +); +defparam rtc_pul5_0_a3_6_cZ.init=16'h0001; +// @16:1768 + LUT4 pcount10_0_o3 ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(VCC), + .D(VCC), + .Z(N_8) +); +defparam pcount10_0_o3.init=16'hDDDD; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[1] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(VCC), + .D(VCC), + .Z(phb_cnt_RNO[1]) +); +defparam \phb_cnt_RNO_cZ[1] .init=16'h6666; +// @16:1328 + LUT4 rtc_ctrl4_0_o3 ( + .A(rcount[4]), + .B(rcount[5]), + .C(VCC), + .D(VCC), + .Z(N_6) +); +defparam rtc_ctrl4_0_o3.init=16'h7777; +// @16:1286 + LUT4 unlock_5_cZ ( + .A(pdiff_sync), + .B(un13_unlock_cry_21), + .C(VCC), + .D(VCC), + .Z(unlock_5) +); +defparam unlock_5_cZ.init=16'h8888; +// @16:1292 + LUT4 lock_5_cZ ( + .A(pdiff_sync), + .B(un13_lock_cry_21_i), + .C(VCC), + .D(VCC), + .Z(lock_5) +); +defparam lock_5_cZ.init=16'h8888; +// @16:1389 + LUT4 rhb_wait_cnt12_cZ ( + .A(rhb_sync_p1), + .B(rhb_sync_p2), + .C(VCC), + .D(VCC), + .Z(rhb_wait_cnt12) +); +defparam rhb_wait_cnt12_cZ.init=16'h2222; +// @16:1786 + LUT4 \un1_pcount_diff_cZ[0] ( + .A(un13_lock_0), + .B(pcount[0]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff[0]) +); +defparam \un1_pcount_diff_cZ[0] .init=16'h5355; +// @16:1319 + LUT4 un1_rcount_1_0_a3_1_cZ ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(un1_rcount_1_0_a3_1) +); +defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000; +// @16:1350 + LUT4 rhb_sync_p2_RNIU9TG1 ( + .A(un1_rhb_wait_cnt_5), + .B(un1_rhb_wait_cnt_4), + .C(rhb_sync_p2), + .D(rhb_sync_p1), + .Z(rhb_wait_cnt_scalar) +); +defparam rhb_sync_p2_RNIU9TG1.init=16'h7077; + CCU2C \pcount_cry_0[0] ( + .A0(VCC), + .B0(N_8), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_9), + .COUT(pcount_cry[0]), + .S0(pcount_cry_0_S0[0]), + .S1(pcount_s[0]) +); +defparam \pcount_cry_0[0] .INIT0=16'h500c; +defparam \pcount_cry_0[0] .INIT1=16'h8000; +defparam \pcount_cry_0[0] .INJECT1_0="NO"; +defparam \pcount_cry_0[0] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[1] ( + .A0(N_8), + .B0(pcount[1]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[0]), + .COUT(pcount_cry[2]), + .S0(pcount_s[1]), + .S1(pcount_s[2]) +); +defparam \pcount_cry_0[1] .INIT0=16'h8000; +defparam \pcount_cry_0[1] .INIT1=16'h8000; +defparam \pcount_cry_0[1] .INJECT1_0="NO"; +defparam \pcount_cry_0[1] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[3] ( + .A0(N_8), + .B0(pcount[3]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[2]), + .COUT(pcount_cry[4]), + .S0(pcount_s[3]), + .S1(pcount_s[4]) +); +defparam \pcount_cry_0[3] .INIT0=16'h8000; +defparam \pcount_cry_0[3] .INIT1=16'h8000; +defparam \pcount_cry_0[3] .INJECT1_0="NO"; +defparam \pcount_cry_0[3] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[5] ( + .A0(N_8), + .B0(pcount[5]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[4]), + .COUT(pcount_cry[6]), + .S0(pcount_s[5]), + .S1(pcount_s[6]) +); +defparam \pcount_cry_0[5] .INIT0=16'h8000; +defparam \pcount_cry_0[5] .INIT1=16'h8000; +defparam \pcount_cry_0[5] .INJECT1_0="NO"; +defparam \pcount_cry_0[5] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[7] ( + .A0(N_8), + .B0(pcount[7]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[6]), + .COUT(pcount_cry[8]), + .S0(pcount_s[7]), + .S1(pcount_s[8]) +); +defparam \pcount_cry_0[7] .INIT0=16'h8000; +defparam \pcount_cry_0[7] .INIT1=16'h8000; +defparam \pcount_cry_0[7] .INJECT1_0="NO"; +defparam \pcount_cry_0[7] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[9] ( + .A0(N_8), + .B0(pcount[9]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[8]), + .COUT(pcount_cry[10]), + .S0(pcount_s[9]), + .S1(pcount_s[10]) +); +defparam \pcount_cry_0[9] .INIT0=16'h8000; +defparam \pcount_cry_0[9] .INIT1=16'h8000; +defparam \pcount_cry_0[9] .INJECT1_0="NO"; +defparam \pcount_cry_0[9] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[11] ( + .A0(N_8), + .B0(pcount[11]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[10]), + .COUT(pcount_cry[12]), + .S0(pcount_s[11]), + .S1(pcount_s[12]) +); +defparam \pcount_cry_0[11] .INIT0=16'h8000; +defparam \pcount_cry_0[11] .INIT1=16'h8000; +defparam \pcount_cry_0[11] .INJECT1_0="NO"; +defparam \pcount_cry_0[11] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[13] ( + .A0(N_8), + .B0(pcount[13]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[12]), + .COUT(pcount_cry[14]), + .S0(pcount_s[13]), + .S1(pcount_s[14]) +); +defparam \pcount_cry_0[13] .INIT0=16'h8000; +defparam \pcount_cry_0[13] .INIT1=16'h8000; +defparam \pcount_cry_0[13] .INJECT1_0="NO"; +defparam \pcount_cry_0[13] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[15] ( + .A0(N_8), + .B0(pcount[15]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[16]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[14]), + .COUT(pcount_cry[16]), + .S0(pcount_s[15]), + .S1(pcount_s[16]) +); +defparam \pcount_cry_0[15] .INIT0=16'h8000; +defparam \pcount_cry_0[15] .INIT1=16'h8000; +defparam \pcount_cry_0[15] .INJECT1_0="NO"; +defparam \pcount_cry_0[15] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[17] ( + .A0(N_8), + .B0(pcount[17]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[18]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[16]), + .COUT(pcount_cry[18]), + .S0(pcount_s[17]), + .S1(pcount_s[18]) +); +defparam \pcount_cry_0[17] .INIT0=16'h8000; +defparam \pcount_cry_0[17] .INIT1=16'h8000; +defparam \pcount_cry_0[17] .INJECT1_0="NO"; +defparam \pcount_cry_0[17] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[19] ( + .A0(N_8), + .B0(pcount[19]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[20]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[18]), + .COUT(pcount_cry[20]), + .S0(pcount_s[19]), + .S1(pcount_s[20]) +); +defparam \pcount_cry_0[19] .INIT0=16'h8000; +defparam \pcount_cry_0[19] .INIT1=16'h8000; +defparam \pcount_cry_0[19] .INJECT1_0="NO"; +defparam \pcount_cry_0[19] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_s_0[21] ( + .A0(N_8), + .B0(pcount[21]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[20]), + .COUT(pcount_s_0_COUT[21]), + .S0(pcount_s[21]), + .S1(pcount_s_0_S1[21]) +); +defparam \pcount_s_0[21] .INIT0=16'h800a; +defparam \pcount_s_0[21] .INIT1=16'h5003; +defparam \pcount_s_0[21] .INJECT1_0="NO"; +defparam \pcount_s_0[21] .INJECT1_1="NO"; + CCU2C \rcount_cry_0[0] ( + .A0(VCC), + .B0(un1_rcount_1_0_a3), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(rcount_cry[0]), + .S0(rcount_cry_0_S0[0]), + .S1(rcount_s[0]) +); +defparam \rcount_cry_0[0] .INIT0=16'h5003; +defparam \rcount_cry_0[0] .INIT1=16'h4000; +defparam \rcount_cry_0[0] .INJECT1_0="NO"; +defparam \rcount_cry_0[0] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[1] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[1]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[0]), + .COUT(rcount_cry[2]), + .S0(rcount_s[1]), + .S1(rcount_s[2]) +); +defparam \rcount_cry_0[1] .INIT0=16'h4000; +defparam \rcount_cry_0[1] .INIT1=16'h4000; +defparam \rcount_cry_0[1] .INJECT1_0="NO"; +defparam \rcount_cry_0[1] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[3] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[3]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[2]), + .COUT(rcount_cry[4]), + .S0(rcount_s[3]), + .S1(rcount_s[4]) +); +defparam \rcount_cry_0[3] .INIT0=16'h4000; +defparam \rcount_cry_0[3] .INIT1=16'h4000; +defparam \rcount_cry_0[3] .INJECT1_0="NO"; +defparam \rcount_cry_0[3] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[5] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[5]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[4]), + .COUT(rcount_cry[6]), + .S0(rcount_s[5]), + .S1(rcount_s[6]) +); +defparam \rcount_cry_0[5] .INIT0=16'h4000; +defparam \rcount_cry_0[5] .INIT1=16'h4000; +defparam \rcount_cry_0[5] .INJECT1_0="NO"; +defparam \rcount_cry_0[5] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[7] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[7]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[6]), + .COUT(rcount_cry[8]), + .S0(rcount_s[7]), + .S1(rcount_s[8]) +); +defparam \rcount_cry_0[7] .INIT0=16'h4000; +defparam \rcount_cry_0[7] .INIT1=16'h4000; +defparam \rcount_cry_0[7] .INJECT1_0="NO"; +defparam \rcount_cry_0[7] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[9] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[9]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[8]), + .COUT(rcount_cry[10]), + .S0(rcount_s[9]), + .S1(rcount_s[10]) +); +defparam \rcount_cry_0[9] .INIT0=16'h4000; +defparam \rcount_cry_0[9] .INIT1=16'h4000; +defparam \rcount_cry_0[9] .INJECT1_0="NO"; +defparam \rcount_cry_0[9] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[11] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[11]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[10]), + .COUT(rcount_cry[12]), + .S0(rcount_s[11]), + .S1(rcount_s[12]) +); +defparam \rcount_cry_0[11] .INIT0=16'h4000; +defparam \rcount_cry_0[11] .INIT1=16'h4000; +defparam \rcount_cry_0[11] .INJECT1_0="NO"; +defparam \rcount_cry_0[11] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[13] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[13]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[12]), + .COUT(rcount_cry[14]), + .S0(rcount_s[13]), + .S1(rcount_s[14]) +); +defparam \rcount_cry_0[13] .INIT0=16'h4000; +defparam \rcount_cry_0[13] .INIT1=16'h4000; +defparam \rcount_cry_0[13] .INJECT1_0="NO"; +defparam \rcount_cry_0[13] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_s_0[15] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[15]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[14]), + .COUT(rcount_s_0_COUT[15]), + .S0(rcount_s[15]), + .S1(rcount_s_0_S1[15]) +); +defparam \rcount_s_0[15] .INIT0=16'h4005; +defparam \rcount_s_0[15] .INIT1=16'h5003; +defparam \rcount_s_0[15] .INJECT1_0="NO"; +defparam \rcount_s_0[15] .INJECT1_1="NO"; + CCU2C \rhb_wait_cnt_cry_0[0] ( + .A0(VCC), + .B0(rhb_wait_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rhb_wait_cnt_cry[0]), + .S0(rhb_wait_cnt_cry_0_S0[0]), + .S1(rhb_wait_cnt_s[0]) +); +defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c; +defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[1] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[0]), + .COUT(rhb_wait_cnt_cry[2]), + .S0(rhb_wait_cnt_s[1]), + .S1(rhb_wait_cnt_s[2]) +); +defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[3] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[2]), + .COUT(rhb_wait_cnt_cry[4]), + .S0(rhb_wait_cnt_s[3]), + .S1(rhb_wait_cnt_s[4]) +); +defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[5] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rhb_wait_cnt_scalar), + .B1(rhb_wait_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[4]), + .COUT(rhb_wait_cnt_cry[6]), + .S0(rhb_wait_cnt_s[5]), + .S1(rhb_wait_cnt_s[6]) +); +defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_s_0[7] ( + .A0(rhb_wait_cnt_scalar), + .B0(rhb_wait_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[6]), + .COUT(rhb_wait_cnt_s_0_COUT[7]), + .S0(rhb_wait_cnt_s[7]), + .S1(rhb_wait_cnt_s_0_S1[7]) +); +defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a; +defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO"; + CCU2C un1_pcount_diff_1_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff[0]), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(un1_pcount_diff_1_cry_0), + .S0(un1_pcount_diff_1_cry_0_0_S0), + .S1(un1_pcount_diff_1_cry_0_0_S1) +); +defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003; +defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_1_0 ( + .A0(un1_pcount_diff_1_axb_1), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_2), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_0), + .COUT(un1_pcount_diff_1_cry_2), + .S0(un1_pcount_diff_1_cry_1_0_S0), + .S1(un1_pcount_diff_1_cry_1_0_S1) +); +defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_3_0 ( + .A0(un1_pcount_diff_1_axb_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_2), + .COUT(un1_pcount_diff_1_cry_4), + .S0(un1_pcount_diff_1_cry_3_0_S0), + .S1(un1_pcount_diff_1_cry_3_0_S1) +); +defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_5_0 ( + .A0(un1_pcount_diff_1_axb_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_4), + .COUT(un1_pcount_diff_1_cry_6), + .S0(un1_pcount_diff_1_cry_5_0_S0), + .S1(un1_pcount_diff_1_cry_5_0_S1) +); +defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_7_0 ( + .A0(un1_pcount_diff_1_axb_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_6), + .COUT(un1_pcount_diff_1_cry_8), + .S0(un1_pcount_diff_1_cry_7_0_S0), + .S1(un1_pcount_diff_1_cry_7_0_S1) +); +defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_9_0 ( + .A0(un1_pcount_diff_1_axb_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_8), + .COUT(un1_pcount_diff_1_cry_10), + .S0(un1_pcount_diff_1_cry_9_0_S0), + .S1(un1_pcount_diff_1_cry_9_0_S1) +); +defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_11_0 ( + .A0(un1_pcount_diff_1_axb_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_10), + .COUT(un1_pcount_diff_1_cry_12), + .S0(un1_pcount_diff_1_cry_11_0_S0), + .S1(un1_pcount_diff_1_cry_11_0_S1) +); +defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_13_0 ( + .A0(un1_pcount_diff_1_axb_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_12), + .COUT(un1_pcount_diff_1_cry_14), + .S0(un1_pcount_diff_1_cry_13_0_S0), + .S1(un1_pcount_diff_1_cry_13_0_S1) +); +defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_15_0 ( + .A0(un1_pcount_diff_1_axb_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(rdiff_comp_lock[2]), + .C1(un1_pcount_diff_1_cry_15_0_RNO_0), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_14), + .COUT(un1_pcount_diff_1_cry_16), + .S0(un1_pcount_diff_1_cry_15_0_S0), + .S1(un1_pcount_diff_1_cry_15_0_S1) +); +defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INIT1=16'hb404; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_17_0 ( + .A0(un1_pcount_diff_1_axb_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_16), + .COUT(un1_pcount_diff_1_cry_18), + .S0(un1_pcount_diff_1_cry_17_0_S0), + .S1(un1_pcount_diff_1_cry_17_0_S1) +); +defparam un1_pcount_diff_1_cry_17_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_19_0 ( + .A0(un1_pcount_diff_1_axb_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_18), + .COUT(un1_pcount_diff_1_cry_20), + .S0(un1_pcount_diff_1_cry_19_0_S0), + .S1(un1_pcount_diff_1_cry_19_0_S1) +); +defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_s_21_0 ( + .A0(pcount[21]), + .B0(un13_lock_21), + .C0(N_8), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_20), + .COUT(un1_pcount_diff_1_s_21_0_COUT), + .S0(un1_pcount_diff_1_s_21_0_S0), + .S1(un1_pcount_diff_1_s_21_0_S1) +); +defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a; +defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003; +defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO"; + CCU2C un13_lock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(un13_lock_cry_0), + .S0(un13_lock_cry_0_0_S0), + .S1(un13_lock_cry_0_0_S1) +); +defparam un13_lock_cry_0_0.INIT0=16'h5003; +defparam un13_lock_cry_0_0.INIT1=16'h900a; +defparam un13_lock_cry_0_0.INJECT1_0="NO"; +defparam un13_lock_cry_0_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_0), + .COUT(un13_lock_cry_2), + .S0(un13_lock_cry_1_0_S0), + .S1(un13_lock_cry_1_0_S1) +); +defparam un13_lock_cry_1_0.INIT0=16'h900a; +defparam un13_lock_cry_1_0.INIT1=16'h500a; +defparam un13_lock_cry_1_0.INJECT1_0="NO"; +defparam un13_lock_cry_1_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_3_0 ( + .A0(un13_lock_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_2), + .COUT(un13_lock_cry_4), + .S0(un13_lock_cry_3_0_S0), + .S1(un13_lock_cry_3_0_S1) +); +defparam un13_lock_cry_3_0.INIT0=16'h500a; +defparam un13_lock_cry_3_0.INIT1=16'h900a; +defparam un13_lock_cry_3_0.INJECT1_0="NO"; +defparam un13_lock_cry_3_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_5_0 ( + .A0(un13_lock_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_4), + .COUT(un13_lock_cry_6), + .S0(un13_lock_cry_5_0_S0), + .S1(un13_lock_cry_5_0_S1) +); +defparam un13_lock_cry_5_0.INIT0=16'h500a; +defparam un13_lock_cry_5_0.INIT1=16'h500a; +defparam un13_lock_cry_5_0.INJECT1_0="NO"; +defparam un13_lock_cry_5_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_6), + .COUT(un13_lock_cry_8), + .S0(un13_lock_cry_7_0_S0), + .S1(un13_lock_cry_7_0_S1) +); +defparam un13_lock_cry_7_0.INIT0=16'h500a; +defparam un13_lock_cry_7_0.INIT1=16'h500a; +defparam un13_lock_cry_7_0.INJECT1_0="NO"; +defparam un13_lock_cry_7_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_8), + .COUT(un13_lock_cry_10), + .S0(un13_lock_cry_9_0_S0), + .S1(un13_lock_cry_9_0_S1) +); +defparam un13_lock_cry_9_0.INIT0=16'h500a; +defparam un13_lock_cry_9_0.INIT1=16'h500a; +defparam un13_lock_cry_9_0.INJECT1_0="NO"; +defparam un13_lock_cry_9_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_10), + .COUT(un13_lock_cry_12), + .S0(un13_lock_cry_11_0_S0), + .S1(un13_lock_cry_11_0_S1) +); +defparam un13_lock_cry_11_0.INIT0=16'h500a; +defparam un13_lock_cry_11_0.INIT1=16'h500a; +defparam un13_lock_cry_11_0.INJECT1_0="NO"; +defparam un13_lock_cry_11_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_12), + .COUT(un13_lock_cry_14), + .S0(un13_lock_cry_13_0_S0), + .S1(un13_lock_cry_13_0_S1) +); +defparam un13_lock_cry_13_0.INIT0=16'h500a; +defparam un13_lock_cry_13_0.INIT1=16'h500a; +defparam un13_lock_cry_13_0.INJECT1_0="NO"; +defparam un13_lock_cry_13_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_14), + .COUT(un13_lock_cry_16), + .S0(un13_lock_cry_15_0_S0), + .S1(un13_lock_cry_15_0_S1) +); +defparam un13_lock_cry_15_0.INIT0=16'h500a; +defparam un13_lock_cry_15_0.INIT1=16'h500a; +defparam un13_lock_cry_15_0.INJECT1_0="NO"; +defparam un13_lock_cry_15_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_16), + .COUT(un13_lock_cry_18), + .S0(un13_lock_cry_17_0_S0), + .S1(un13_lock_cry_17_0_S1) +); +defparam un13_lock_cry_17_0.INIT0=16'h500a; +defparam un13_lock_cry_17_0.INIT1=16'h500a; +defparam un13_lock_cry_17_0.INJECT1_0="NO"; +defparam un13_lock_cry_17_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_18), + .COUT(un13_lock_cry_20), + .S0(un13_lock_cry_19_0_S0), + .S1(un13_lock_cry_19_0_S1) +); +defparam un13_lock_cry_19_0.INIT0=16'h500a; +defparam un13_lock_cry_19_0.INIT1=16'h500a; +defparam un13_lock_cry_19_0.INJECT1_0="NO"; +defparam un13_lock_cry_19_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_20), + .COUT(un13_lock_cry_21_0_COUT), + .S0(un13_lock_cry_21_0_S0), + .S1(un13_lock_cry_21_i) +); +defparam un13_lock_cry_21_0.INIT0=16'h500f; +defparam un13_lock_cry_21_0.INIT1=16'ha003; +defparam un13_lock_cry_21_0.INJECT1_0="NO"; +defparam un13_lock_cry_21_0.INJECT1_1="NO"; + CCU2C un13_unlock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(un13_unlock_cry_0), + .S0(un13_unlock_cry_0_0_S0), + .S1(un13_unlock_cry_0_0_S1) +); +defparam un13_unlock_cry_0_0.INIT0=16'h5003; +defparam un13_unlock_cry_0_0.INIT1=16'h900a; +defparam un13_unlock_cry_0_0.INJECT1_0="NO"; +defparam un13_unlock_cry_0_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_0), + .COUT(un13_unlock_cry_2), + .S0(un13_unlock_cry_1_0_S0), + .S1(un13_unlock_cry_1_0_S1) +); +defparam un13_unlock_cry_1_0.INIT0=16'h900a; +defparam un13_unlock_cry_1_0.INIT1=16'h900a; +defparam un13_unlock_cry_1_0.INJECT1_0="NO"; +defparam un13_unlock_cry_1_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_3_0 ( + .A0(un13_lock_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_2), + .COUT(un13_unlock_cry_4), + .S0(un13_unlock_cry_3_0_S0), + .S1(un13_unlock_cry_3_0_S1) +); +defparam un13_unlock_cry_3_0.INIT0=16'h500a; +defparam un13_unlock_cry_3_0.INIT1=16'h500a; +defparam un13_unlock_cry_3_0.INJECT1_0="NO"; +defparam un13_unlock_cry_3_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_5_0 ( + .A0(un13_lock_5), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_4), + .COUT(un13_unlock_cry_6), + .S0(un13_unlock_cry_5_0_S0), + .S1(un13_unlock_cry_5_0_S1) +); +defparam un13_unlock_cry_5_0.INIT0=16'h900a; +defparam un13_unlock_cry_5_0.INIT1=16'h500a; +defparam un13_unlock_cry_5_0.INJECT1_0="NO"; +defparam un13_unlock_cry_5_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_6), + .COUT(un13_unlock_cry_8), + .S0(un13_unlock_cry_7_0_S0), + .S1(un13_unlock_cry_7_0_S1) +); +defparam un13_unlock_cry_7_0.INIT0=16'h500a; +defparam un13_unlock_cry_7_0.INIT1=16'h500a; +defparam un13_unlock_cry_7_0.INJECT1_0="NO"; +defparam un13_unlock_cry_7_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_8), + .COUT(un13_unlock_cry_10), + .S0(un13_unlock_cry_9_0_S0), + .S1(un13_unlock_cry_9_0_S1) +); +defparam un13_unlock_cry_9_0.INIT0=16'h500a; +defparam un13_unlock_cry_9_0.INIT1=16'h500a; +defparam un13_unlock_cry_9_0.INJECT1_0="NO"; +defparam un13_unlock_cry_9_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_10), + .COUT(un13_unlock_cry_12), + .S0(un13_unlock_cry_11_0_S0), + .S1(un13_unlock_cry_11_0_S1) +); +defparam un13_unlock_cry_11_0.INIT0=16'h500a; +defparam un13_unlock_cry_11_0.INIT1=16'h500a; +defparam un13_unlock_cry_11_0.INJECT1_0="NO"; +defparam un13_unlock_cry_11_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_12), + .COUT(un13_unlock_cry_14), + .S0(un13_unlock_cry_13_0_S0), + .S1(un13_unlock_cry_13_0_S1) +); +defparam un13_unlock_cry_13_0.INIT0=16'h500a; +defparam un13_unlock_cry_13_0.INIT1=16'h500a; +defparam un13_unlock_cry_13_0.INJECT1_0="NO"; +defparam un13_unlock_cry_13_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_14), + .COUT(un13_unlock_cry_16), + .S0(un13_unlock_cry_15_0_S0), + .S1(un13_unlock_cry_15_0_S1) +); +defparam un13_unlock_cry_15_0.INIT0=16'h500a; +defparam un13_unlock_cry_15_0.INIT1=16'h500a; +defparam un13_unlock_cry_15_0.INJECT1_0="NO"; +defparam un13_unlock_cry_15_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_16), + .COUT(un13_unlock_cry_18), + .S0(un13_unlock_cry_17_0_S0), + .S1(un13_unlock_cry_17_0_S1) +); +defparam un13_unlock_cry_17_0.INIT0=16'h500a; +defparam un13_unlock_cry_17_0.INIT1=16'h500a; +defparam un13_unlock_cry_17_0.INJECT1_0="NO"; +defparam un13_unlock_cry_17_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_18), + .COUT(un13_unlock_cry_20), + .S0(un13_unlock_cry_19_0_S0), + .S1(un13_unlock_cry_19_0_S1) +); +defparam un13_unlock_cry_19_0.INIT0=16'h500a; +defparam un13_unlock_cry_19_0.INIT1=16'h500a; +defparam un13_unlock_cry_19_0.INJECT1_0="NO"; +defparam un13_unlock_cry_19_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_20), + .COUT(un13_unlock_cry_21_0_COUT), + .S0(un13_unlock_cry_21_0_S0), + .S1(un13_unlock_cry_21) +); +defparam un13_unlock_cry_21_0.INIT0=16'h500f; +defparam un13_unlock_cry_21_0.INIT1=16'h5003; +defparam un13_unlock_cry_21_0.INJECT1_0="NO"; +defparam un13_unlock_cry_21_0.INJECT1_1="NO"; +//@16:1801 +//@8:424 +// @16:1211 + sync_0s phb_sync_inst ( + .phb(phb), + .rhb_sync(rhb_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); +// @16:1220 + sync_0s_6 rtc_sync_inst ( + .rtc_pul(rtc_pul), + .ppul_sync(ppul_sync), + .sli_rst(sli_rst), + .tx_pclk(tx_pclk) +); +// @16:1228 + sync_0s_0 pdiff_sync_inst ( + .ppul_sync(ppul_sync), + .pdiff_sync(pdiff_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sgmii_ecp5sll_core_Z1_layer1 */ + +module sgmii_ecp5rsl_core_Z2_layer1 ( + rx_pcs_rst_c, + tx_pcs_rst_c, + serdes_rst_dual_c, + tx_serdes_rst_c, + rsl_rx_pcs_rst_c, + rsl_tx_pcs_rst_c, + rsl_tx_serdes_rst_c, + rsl_tx_rdy, + pll_lock_i, + pll_refclki, + rsl_rx_rdy, + rsl_rst, + rxrefclk, + rsl_disable, + rx_serdes_rst_c, + rst_dual_c, + rx_cdr_lol_s, + rx_los_low_s, + rsl_rx_serdes_rst_c, + rsl_serdes_rst_dual_c +) +; +input rx_pcs_rst_c ; +input tx_pcs_rst_c ; +input serdes_rst_dual_c ; +input tx_serdes_rst_c ; +output rsl_rx_pcs_rst_c ; +output rsl_tx_pcs_rst_c ; +output rsl_tx_serdes_rst_c ; +output rsl_tx_rdy ; +input pll_lock_i ; +input pll_refclki ; +output rsl_rx_rdy ; +input rsl_rst ; +input rxrefclk ; +input rsl_disable ; +input rx_serdes_rst_c ; +input rst_dual_c ; +input rx_cdr_lol_s ; +input rx_los_low_s ; +output rsl_rx_serdes_rst_c ; +output rsl_serdes_rst_dual_c ; +wire rx_pcs_rst_c ; +wire tx_pcs_rst_c ; +wire serdes_rst_dual_c ; +wire tx_serdes_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_tx_pcs_rst_c ; +wire rsl_tx_serdes_rst_c ; +wire rsl_tx_rdy ; +wire pll_lock_i ; +wire pll_refclki ; +wire rsl_rx_rdy ; +wire rsl_rst ; +wire rxrefclk ; +wire rsl_disable ; +wire rx_serdes_rst_c ; +wire rst_dual_c ; +wire rx_cdr_lol_s ; +wire rx_los_low_s ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire [1:0] rxs_cnt; +wire [1:0] rxs_cnt_3; +wire [0:0] rxpr_appd_RNO; +wire [2:0] plol0_cnt; +wire [2:0] plol0_cnt_3; +wire [0:0] rxsr_appd; +wire [1:0] rxs_cnt_QN; +wire [3:0] rlos_db_cnt; +wire [3:0] rlos_db_cnt_QN; +wire [17:0] rlols0_cnt_s; +wire [17:0] rlols0_cnt; +wire [17:0] rlols0_cnt_QN; +wire [3:0] rlol_db_cnt; +wire [3:0] rlol_db_cnt_QN; +wire [18:0] rlol1_cnt_s; +wire [18:0] rlol1_cnt; +wire [18:0] rlol1_cnt_QN; +wire [11:0] rxr_wt_cnt_s; +wire [11:0] rxr_wt_cnt; +wire [11:0] rxr_wt_cnt_QN; +wire [0:0] rxsr_appd_QN; +wire [0:0] rxpr_appd; +wire [0:0] rxpr_appd_QN; +wire [1:0] txs_cnt; +wire [1:0] txs_cnt_QN; +wire [1:1] txs_cnt_RNO; +wire [1:0] txp_cnt; +wire [1:0] txp_cnt_QN; +wire [1:1] txp_cnt_RNO; +wire [19:0] plol_cnt_s; +wire [19:0] plol_cnt; +wire [19:0] plol_cnt_QN; +wire [2:0] plol0_cnt_QN; +wire [11:0] txr_wt_cnt_s; +wire [11:0] txr_wt_cnt; +wire [11:0] txr_wt_cnt_QN; +wire [0:0] txpr_appd; +wire [0:0] txpr_appd_QN; +wire [0:0] un1_rlol_db_cnt_zero; +wire [0:0] un1_rlos_db_cnt_zero; +wire [0:0] un1_rlol_db_cnt_zero_bm; +wire [0:0] un1_rlol_db_cnt_zero_am; +wire [0:0] un1_rlos_db_cnt_zero_bm; +wire [0:0] un1_rlos_db_cnt_zero_am; +wire [16:0] rlol1_cnt_cry; +wire [0:0] rlol1_cnt_cry_0_S0; +wire [17:17] rlol1_cnt_cry_0_COUT; +wire [16:0] rlols0_cnt_cry; +wire [0:0] rlols0_cnt_cry_0_S0; +wire [17:17] rlols0_cnt_s_0_COUT; +wire [17:17] rlols0_cnt_s_0_S1; +wire [10:0] txr_wt_cnt_cry; +wire [0:0] txr_wt_cnt_cry_0_S0; +wire [11:11] txr_wt_cnt_s_0_COUT; +wire [11:11] txr_wt_cnt_s_0_S1; +wire [10:0] rxr_wt_cnt_cry; +wire [0:0] rxr_wt_cnt_cry_0_S0; +wire [11:11] rxr_wt_cnt_s_0_COUT; +wire [11:11] rxr_wt_cnt_s_0_S1; +wire [18:0] plol_cnt_cry; +wire [0:0] plol_cnt_cry_0_S0; +wire [19:19] plol_cnt_s_0_COUT; +wire [19:19] plol_cnt_s_0_S1; +wire rxs_rst ; +wire VCC ; +wire rlos_db_p1 ; +wire rlos_db ; +wire rxp_rst25 ; +wire rlol_db ; +wire un1_rui_rst_dual_c_1_1 ; +wire plol0_cnt9 ; +wire waita_plol0 ; +wire rx_any_rst ; +wire un3_rx_all_well_2 ; +wire un17_rxr_wt_tc ; +wire rx_all_well ; +wire un3_rx_all_well_1 ; +wire rxr_wt_cnt9 ; +wire un1_rui_rst_dual_c_1_i ; +wire rlol1_cnt_tc_1 ; +wire rlol1_cnt_scalar ; +wire rxr_wt_en ; +wire rxr_wt_cnte ; +wire un18_txr_wt_tc ; +wire tx_any_rst ; +wire pll_lol_p2 ; +wire un2_plol_fedge_5_i ; +wire N_2160_0 ; +wire waita_rlols06 ; +wire un1_rlols0_cnt_tc ; +wire waita_rlols0 ; +wire waita_rlols0_QN ; +wire wait_calib_RNO ; +wire un1_rlos_fedge_1 ; +wire wait_calib ; +wire wait_calib_QN ; +wire rxs_rst6 ; +wire un1_rxs_cnt_tc ; +wire rxs_rst_QN ; +wire un2_rlos_redge_1_i ; +wire rxp_rst2 ; +wire rxp_rst2_QN ; +wire rlos_p1 ; +wire rlos_p2 ; +wire rlos_p2_QN ; +wire rlos_p1_QN ; +wire rlos_db_p1_QN ; +wire rlos_db_cnt_axb_0 ; +wire rlos_db_cnt_cry_1_0_S0 ; +wire rlos_db_cnt_cry_1_0_S1 ; +wire rlos_db_cnt_s_3_0_S0 ; +wire un1_rlos_db_cnt_max ; +wire rlos_db_QN ; +wire rlols0_cnte ; +wire rlol_p1 ; +wire rlol_p2 ; +wire rlol_p2_QN ; +wire rlol_p1_QN ; +wire rlol_db_p1 ; +wire rlol_db_p1_QN ; +wire rlol_db_cnt_axb_0 ; +wire rlol_db_cnt_cry_1_0_S0 ; +wire rlol_db_cnt_cry_1_0_S1 ; +wire rlol_db_cnt_s_3_0_S0 ; +wire un1_rlol_db_cnt_max ; +wire rlol_db_QN ; +wire rlol1_cnte ; +wire rxsdr_appd_2 ; +wire rxsdr_appd_4 ; +wire rxsdr_appd_QN ; +wire un1_dual_or_rserd_rst_2_i ; +wire rxr_wt_en_QN ; +wire rxdpr_appd ; +wire rxdpr_appd_QN ; +wire ruo_rx_rdyr_QN ; +wire un2_rdo_serdes_rst_dual_c_2_i ; +wire plol_fedge ; +wire un1_plol0_cnt_tc_1_i ; +wire waita_plol0_QN ; +wire un1_plol_cnt_tc ; +wire un2_plol_cnt_tc ; +wire txs_rst ; +wire txs_rst_QN ; +wire N_10_i ; +wire un9_plol0_cnt_tc ; +wire un1_plol0_cnt_tc_1 ; +wire txp_rst ; +wire txp_rst_QN ; +wire N_11_i ; +wire pll_lol_p3 ; +wire pll_lol_p3_QN ; +wire pll_lol_p1 ; +wire pll_lol_p2_QN ; +wire pll_lol_p1_QN ; +wire txsr_appd_2 ; +wire txsr_appd_4 ; +wire txsr_appd_QN ; +wire un1_dual_or_serd_rst_1_1 ; +wire un1_dual_or_serd_rst_1_i ; +wire txr_wt_en ; +wire txr_wt_en_QN ; +wire txr_wt_cnte ; +wire un2_plol_fedge_2 ; +wire un2_plol_fedge_3_i ; +wire txdpr_appd ; +wire txdpr_appd_QN ; +wire un2_plol_fedge_5_1 ; +wire ruo_tx_rdyr_QN ; +wire un2_plol_fedge_8_i ; +wire rlols0_cnt_tc_1 ; +wire rlos_redge ; +wire rlols0_cnt11_0 ; +wire plol_cnt_scalar ; +wire rlols0_cnt_scalar ; +wire un8_rxs_cnt_tc ; +wire un1_txsr_appd ; +wire un1_dual_or_rserd_rst_2_0 ; +wire un1_rxsdr_or_sr_appd ; +wire un2_rdo_serdes_rst_dual_c_1_1 ; +wire rlols0_cnt_tc_1_10 ; +wire rlols0_cnt_tc_1_11 ; +wire rlols0_cnt_tc_1_12 ; +wire rlols0_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_11 ; +wire rlol1_cnt_tc_1_12 ; +wire rlol1_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_14 ; +wire un1_plol_cnt_tc_11 ; +wire un1_plol_cnt_tc_12 ; +wire un1_plol_cnt_tc_13 ; +wire un1_plol_cnt_tc_14 ; +wire CO0_2 ; +wire un17_rxr_wt_tc_6 ; +wire un17_rxr_wt_tc_7 ; +wire un17_rxr_wt_tc_8 ; +wire un18_txr_wt_tc_6 ; +wire un18_txr_wt_tc_7 ; +wire un18_txr_wt_tc_8 ; +wire rlols0_cnt_tc_1_9 ; +wire un1_plol_cnt_tc_10 ; +wire rlol1_cnt_tc_1_10 ; +wire txr_wt_cnt_scalar ; +wire rlos_db_cnt_cry_0 ; +wire rlos_db_cnt_cry_0_0_S0 ; +wire rlos_db_cnt_cry_0_0_S1 ; +wire rlos_db_cnt_cry_2 ; +wire rlos_db_cnt_s_3_0_COUT ; +wire rlos_db_cnt_s_3_0_S1 ; +wire rlol_db_cnt_cry_0 ; +wire rlol_db_cnt_cry_0_0_S0 ; +wire rlol_db_cnt_cry_0_0_S1 ; +wire rlol_db_cnt_cry_2 ; +wire rlol_db_cnt_s_3_0_COUT ; +wire rlol_db_cnt_s_3_0_S1 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_6 ; +wire N_7 ; + LUT4 \genblk2.rxs_cnt_RNO[0] ( + .A(rxs_rst), + .B(rxs_cnt[0]), + .C(rxs_cnt[1]), + .D(VCC), + .Z(rxs_cnt_3[0]) +); +defparam \genblk2.rxs_cnt_RNO[0] .init=16'h2626; + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_rx_serdes_rst_c), + .C(rx_los_low_s), + .D(rx_cdr_lol_s), + .Z(rxpr_appd_RNO[0]) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'h0001; + LUT4 \genblk2.rxp_rst2_RNO ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_rx_serdes_rst_c), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rxp_rst25) +); +defparam \genblk2.rxp_rst2_RNO .init=16'hEFEE; + LUT4 \genblk2.genblk3.rxdpr_appd_RNO ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_rx_serdes_rst_c), + .C(rlos_db), + .D(rlol_db), + .Z(un1_rui_rst_dual_c_1_1) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'h0001; + LUT4 \genblk1.plol0_cnt_RNO[1] ( + .A(plol0_cnt[1]), + .B(plol0_cnt9), + .C(waita_plol0), + .D(plol0_cnt[0]), + .Z(plol0_cnt_3[1]) +); +defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222; + LUT4 \genblk2.genblk3.ruo_rx_rdyr_RNO ( + .A(rx_any_rst), + .B(rlos_db), + .C(rlol_db), + .D(VCC), + .Z(un3_rx_all_well_2) +); +defparam \genblk2.genblk3.ruo_rx_rdyr_RNO .init=16'h0101; + LUT4 \genblk2.genblk3.rxr_wt_en_RNO ( + .A(un17_rxr_wt_tc), + .B(rsl_serdes_rst_dual_c), + .C(rsl_rx_serdes_rst_c), + .D(rx_all_well), + .Z(un3_rx_all_well_1) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h0100; + LUT4 rx_any_rst_RNIFD021 ( + .A(rx_any_rst), + .B(un17_rxr_wt_tc), + .C(rlos_db), + .D(rlol_db), + .Z(rxr_wt_cnt9) +); +defparam rx_any_rst_RNIFD021.init=16'hFFFE; + LUT4 \genblk2.genblk3.rxdpr_appd_RNO_0 ( + .A(rst_dual_c), + .B(rsl_serdes_rst_dual_c), + .C(rsl_rx_serdes_rst_c), + .D(rx_all_well), + .Z(un1_rui_rst_dual_c_1_i) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO_0 .init=16'hFEFF; + LUT4 \genblk2.rlos_db_p1_RNIS0OP ( + .A(rlol1_cnt_tc_1), + .B(rxs_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlol1_cnt_scalar) +); +defparam \genblk2.rlos_db_p1_RNIS0OP .init=16'h1011; + LUT4 \genblk2.genblk3.rxr_wt_en_RNIQF0H1 ( + .A(rxr_wt_en), + .B(rx_any_rst), + .C(rx_all_well), + .D(un17_rxr_wt_tc), + .Z(rxr_wt_cnte) +); +defparam \genblk2.genblk3.rxr_wt_en_RNIQF0H1 .init=16'hFFEF; + LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO ( + .A(un18_txr_wt_tc), + .B(tx_any_rst), + .C(pll_lol_p2), + .D(VCC), + .Z(un2_plol_fedge_5_i) +); +defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hFEFE; + LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] ( + .A(rxsr_appd[0]), + .B(rx_serdes_rst_c), + .C(rxs_rst), + .D(rsl_disable), + .Z(N_2160_0) +); +defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE; +// @16:759 + FD1P3DX \genblk2.waita_rlols0 ( + .D(waita_rlols06), + .SP(un1_rlols0_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(waita_rlols0) +); +// @16:656 + FD1P3BX \genblk2.wait_calib ( + .D(wait_calib_RNO), + .SP(un1_rlos_fedge_1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(wait_calib) +); +// @16:694 + FD1P3DX \genblk2.rxs_rst ( + .D(rxs_rst6), + .SP(un1_rxs_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_rst) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[0] ( + .D(rxs_cnt_3[0]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[0]) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[1] ( + .D(rxs_cnt_3[1]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[1]) +); +// @16:806 + FD1P3BX \genblk2.rxp_rst2 ( + .D(rxp_rst25), + .SP(un2_rlos_redge_1_i), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxp_rst2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p2 ( + .D(rlos_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p1 ( + .D(rx_los_low_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p1) +); +// @16:567 + FD1S3BX \genblk2.rlos_db_p1 ( + .D(rlos_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_p1) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[0] ( + .D(rlos_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[0]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[1] ( + .D(rlos_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[1]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[2] ( + .D(rlos_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[2]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[3] ( + .D(rlos_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[3]) +); +// @16:649 + FD1P3BX \genblk2.rlos_db ( + .D(rlos_db_cnt[1]), + .SP(un1_rlos_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[0] ( + .D(rlols0_cnt_s[0]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[0]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[1] ( + .D(rlols0_cnt_s[1]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[1]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[2] ( + .D(rlols0_cnt_s[2]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[2]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[3] ( + .D(rlols0_cnt_s[3]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[3]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[4] ( + .D(rlols0_cnt_s[4]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[4]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[5] ( + .D(rlols0_cnt_s[5]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[5]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[6] ( + .D(rlols0_cnt_s[6]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[6]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[7] ( + .D(rlols0_cnt_s[7]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[7]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[8] ( + .D(rlols0_cnt_s[8]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[8]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[9] ( + .D(rlols0_cnt_s[9]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[9]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[10] ( + .D(rlols0_cnt_s[10]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[10]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[11] ( + .D(rlols0_cnt_s[11]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[11]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[12] ( + .D(rlols0_cnt_s[12]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[12]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[13] ( + .D(rlols0_cnt_s[13]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[13]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[14] ( + .D(rlols0_cnt_s[14]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[14]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[15] ( + .D(rlols0_cnt_s[15]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[15]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[16] ( + .D(rlols0_cnt_s[16]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[16]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[17] ( + .D(rlols0_cnt_s[17]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[17]) +); +// @16:567 + FD1S3DX \genblk2.rlol_p2 ( + .D(rlol_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p2) +); +// @16:567 + FD1S3DX \genblk2.rlol_p1 ( + .D(rx_cdr_lol_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p1) +); +// @16:567 + FD1S3BX \genblk2.rlol_db_p1 ( + .D(rlol_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_p1) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[0] ( + .D(rlol_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[0]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[1] ( + .D(rlol_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[1]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[2] ( + .D(rlol_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[2]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[3] ( + .D(rlol_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[3]) +); +// @16:633 + FD1P3BX \genblk2.rlol_db ( + .D(rlol_db_cnt[1]), + .SP(un1_rlol_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[0] ( + .D(rlol1_cnt_s[0]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[0]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[1] ( + .D(rlol1_cnt_s[1]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[1]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[2] ( + .D(rlol1_cnt_s[2]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[2]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[3] ( + .D(rlol1_cnt_s[3]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[3]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[4] ( + .D(rlol1_cnt_s[4]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[4]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[5] ( + .D(rlol1_cnt_s[5]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[5]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[6] ( + .D(rlol1_cnt_s[6]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[6]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[7] ( + .D(rlol1_cnt_s[7]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[7]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[8] ( + .D(rlol1_cnt_s[8]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[8]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[9] ( + .D(rlol1_cnt_s[9]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[9]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[10] ( + .D(rlol1_cnt_s[10]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[10]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[11] ( + .D(rlol1_cnt_s[11]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[11]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[12] ( + .D(rlol1_cnt_s[12]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[12]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[13] ( + .D(rlol1_cnt_s[13]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[13]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[14] ( + .D(rlol1_cnt_s[14]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[14]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[15] ( + .D(rlol1_cnt_s[15]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[15]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[16] ( + .D(rlol1_cnt_s[16]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[16]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[17] ( + .D(rlol1_cnt_s[17]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[17]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[18] ( + .D(rlol1_cnt_s[18]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[18]) +); +// @16:865 + FD1S3BX \genblk2.genblk3.rxsdr_appd ( + .D(rxsdr_appd_2), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxsdr_appd_4) +); +// @16:900 + FD1P3DX \genblk2.genblk3.rxr_wt_en ( + .D(un3_rx_all_well_1), + .SP(un1_dual_or_rserd_rst_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_en) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0] ( + .D(rxr_wt_cnt_s[0]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[0]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1] ( + .D(rxr_wt_cnt_s[1]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[1]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2] ( + .D(rxr_wt_cnt_s[2]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[2]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3] ( + .D(rxr_wt_cnt_s[3]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[3]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4] ( + .D(rxr_wt_cnt_s[4]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[4]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5] ( + .D(rxr_wt_cnt_s[5]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[5]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6] ( + .D(rxr_wt_cnt_s[6]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[6]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7] ( + .D(rxr_wt_cnt_s[7]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[7]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8] ( + .D(rxr_wt_cnt_s[8]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[8]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9] ( + .D(rxr_wt_cnt_s[9]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[9]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10] ( + .D(rxr_wt_cnt_s[10]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[10]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11] ( + .D(rxr_wt_cnt_s[11]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[11]) +); +// @16:871 + FD1P3DX \genblk2.genblk3.rxdpr_appd ( + .D(un1_rui_rst_dual_c_1_1), + .SP(un1_rui_rst_dual_c_1_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxdpr_appd) +); +// @16:920 + FD1P3DX \genblk2.genblk3.ruo_rx_rdyr ( + .D(un3_rx_all_well_2), + .SP(rxr_wt_cnt9), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rsl_rx_rdy) +); +// @16:882 + FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0] ( + .D(N_2160_0), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxsr_appd[0]) +); +// @16:888 + FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0] ( + .D(rxpr_appd_RNO[0]), + .SP(un2_rdo_serdes_rst_dual_c_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxpr_appd[0]) +); +// @16:443 + FD1P3DX \genblk1.waita_plol0 ( + .D(plol_fedge), + .SP(un1_plol0_cnt_tc_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(waita_plol0) +); +// @16:422 + FD1P3DX \genblk1.txs_rst ( + .D(un1_plol_cnt_tc), + .SP(un2_plol_cnt_tc), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_rst) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[0] ( + .D(N_10_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[0]) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[1] ( + .D(txs_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[1]) +); +// @16:461 + FD1P3DX \genblk1.txp_rst ( + .D(un9_plol0_cnt_tc), + .SP(un1_plol0_cnt_tc_1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_rst) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[0] ( + .D(N_11_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[0]) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[1] ( + .D(txp_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[0] ( + .D(plol_cnt_s[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[0]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[1] ( + .D(plol_cnt_s[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[2] ( + .D(plol_cnt_s[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[2]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[3] ( + .D(plol_cnt_s[3]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[3]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[4] ( + .D(plol_cnt_s[4]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[4]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[5] ( + .D(plol_cnt_s[5]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[5]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[6] ( + .D(plol_cnt_s[6]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[6]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[7] ( + .D(plol_cnt_s[7]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[7]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[8] ( + .D(plol_cnt_s[8]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[8]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[9] ( + .D(plol_cnt_s[9]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[9]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[10] ( + .D(plol_cnt_s[10]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[10]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[11] ( + .D(plol_cnt_s[11]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[11]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[12] ( + .D(plol_cnt_s[12]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[12]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[13] ( + .D(plol_cnt_s[13]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[13]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[14] ( + .D(plol_cnt_s[14]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[14]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[15] ( + .D(plol_cnt_s[15]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[15]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[16] ( + .D(plol_cnt_s[16]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[16]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[17] ( + .D(plol_cnt_s[17]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[17]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[18] ( + .D(plol_cnt_s[18]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[18]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[19] ( + .D(plol_cnt_s[19]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[19]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[0] ( + .D(plol0_cnt_3[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[0]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[1] ( + .D(plol0_cnt_3[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[1]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[2] ( + .D(plol0_cnt_3[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[2]) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p3 ( + .D(pll_lol_p2), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p3) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p2 ( + .D(pll_lol_p1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p2) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p1 ( + .D(pll_lock_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p1) +); +// @16:492 + FD1S3BX \genblk1.genblk2.txsr_appd ( + .D(txsr_appd_2), + .CK(pll_refclki), + .PD(rsl_rst), + .Q(txsr_appd_4) +); +// @16:519 + FD1P3DX \genblk1.genblk2.txr_wt_en ( + .D(un1_dual_or_serd_rst_1_1), + .SP(un1_dual_or_serd_rst_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_en) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[0] ( + .D(txr_wt_cnt_s[0]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[0]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[1] ( + .D(txr_wt_cnt_s[1]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[1]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[2] ( + .D(txr_wt_cnt_s[2]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[2]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[3] ( + .D(txr_wt_cnt_s[3]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[3]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[4] ( + .D(txr_wt_cnt_s[4]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[4]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[5] ( + .D(txr_wt_cnt_s[5]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[5]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[6] ( + .D(txr_wt_cnt_s[6]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[6]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[7] ( + .D(txr_wt_cnt_s[7]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[7]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[8] ( + .D(txr_wt_cnt_s[8]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[8]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[9] ( + .D(txr_wt_cnt_s[9]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[9]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[10] ( + .D(txr_wt_cnt_s[10]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[10]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[11] ( + .D(txr_wt_cnt_s[11]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[11]) +); +// @16:498 + FD1P3DX \genblk1.genblk2.txdpr_appd ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_3_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txdpr_appd) +); +// @16:537 + FD1P3DX \genblk1.genblk2.ruo_tx_rdyr ( + .D(un2_plol_fedge_5_1), + .SP(un2_plol_fedge_5_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(rsl_tx_rdy) +); +// @16:509 + FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0] ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_8_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txpr_appd[0]) +); +// @16:422 + LUT4 \genblk1.txs_cnt_RNO[0] ( + .A(txs_cnt[0]), + .B(txs_rst), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(N_10_i) +); +defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6; +// @16:434 + LUT4 \genblk1.txs_cnt_RNO[1] ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(txs_rst), + .D(un1_plol_cnt_tc), + .Z(txs_cnt_RNO[1]) +); +defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C; +// @16:806 + LUT4 \genblk2.rxp_rst2_RNO_0 ( + .A(rlols0_cnt_tc_1), + .B(rlos_redge), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un2_rlos_redge_1_i) +); +defparam \genblk2.rxp_rst2_RNO_0 .init=16'hFFFE; +// @16:519 + LUT4 \genblk1.genblk2.txr_wt_en_RNO ( + .A(txpr_appd[0]), + .B(pll_lol_p2), + .C(un1_dual_or_serd_rst_1_1), + .D(rsl_tx_rdy), + .Z(un1_dual_or_serd_rst_1_i) +); +defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F; +// @16:317 + LUT4 \genblk2.rxs_rst6 ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(rxs_rst6) +); +defparam \genblk2.rxs_rst6 .init=16'h2020; +// @8:394 + LUT4 \genblk2.wait_calib_RNIKRP81 ( + .A(rxs_rst), + .B(wait_calib), + .C(rlol1_cnt_tc_1), + .D(rlos_redge), + .Z(rlol1_cnte) +); +defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE; +// @8:394 + LUT4 \genblk2.waita_rlols0_RNI266C ( + .A(rlols0_cnt11_0), + .B(waita_rlols0), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(rlols0_cnte) +); +defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE; +// @16:412 + LUT4 \genblk1.plol_cnt11_i ( + .A(pll_lol_p2), + .B(un1_plol_cnt_tc), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(plol_cnt_scalar) +); +defparam \genblk1.plol_cnt11_i .init=16'h0202; +// @16:778 + LUT4 \genblk2.rlols0_cnt11_i ( + .A(rlols0_cnt11_0), + .B(rlols0_cnt_tc_1), + .C(VCC), + .D(VCC), + .Z(rlols0_cnt_scalar) +); +defparam \genblk2.rlols0_cnt11_i .init=16'h1111; +// @16:317 + LUT4 \genblk2.un1_rxs_cnt_tc ( + .A(rlol_db), + .B(rlos_db), + .C(un8_rxs_cnt_tc), + .D(rlol1_cnt_tc_1), + .Z(un1_rxs_cnt_tc) +); +defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC; +// @8:394 + LUT4 \genblk2.wait_calib_RNO ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(wait_calib_RNO) +); +defparam \genblk2.wait_calib_RNO .init=16'hA3A3; +// @16:509 + LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] ( + .A(un1_txsr_appd), + .B(pll_lol_p2), + .C(rsl_serdes_rst_dual_c), + .D(rsl_tx_serdes_rst_c), + .Z(un2_plol_fedge_8_i) +); +defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFFFE; +// @16:900 + LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0 ( + .A(un17_rxr_wt_tc), + .B(un1_dual_or_rserd_rst_2_0), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un1_dual_or_rserd_rst_2_i) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFFFB; +// @16:888 + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] ( + .A(un1_rxsdr_or_sr_appd), + .B(un2_rdo_serdes_rst_dual_c_1_1), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un2_rdo_serdes_rst_dual_c_2_i) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] .init=16'hFFFB; +// @8:394 + LUT4 \genblk1.genblk2.txr_wt_en_RNICEBT ( + .A(txr_wt_en), + .B(un18_txr_wt_tc), + .C(tx_any_rst), + .D(VCC), + .Z(txr_wt_cnte) +); +defparam \genblk1.genblk2.txr_wt_en_RNICEBT .init=16'hFEFE; +// @16:259 + LUT4 \genblk1.un2_plol_cnt_tc ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(un2_plol_cnt_tc) +); +defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8; +// @16:322 + LUT4 \genblk2.un1_rlos_fedge_1 ( + .A(rlos_db), + .B(rlos_db_p1), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(un1_rlos_fedge_1) +); +defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6; +// @16:340 + LUT4 \genblk2.un1_rlols0_cnt_tc ( + .A(rlols0_cnt11_0), + .B(waita_rlols06), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(un1_rlols0_cnt_tc) +); +defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE; +// @16:498 + LUT4 \genblk1.genblk2.txdpr_appd_RNO ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(rst_dual_c), + .Z(un2_plol_fedge_3_i) +); +defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFFFE; +// @16:461 + LUT4 \genblk1.txp_cnt_RNO[0] ( + .A(txp_cnt[0]), + .B(txp_rst), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(N_11_i) +); +defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6; +// @16:473 + LUT4 \genblk1.txp_cnt_RNO[1] ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(txp_rst), + .D(un9_plol0_cnt_tc), + .Z(txp_cnt_RNO[1]) +); +defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C; +// @16:522 + LUT4 un1_dual_or_serd_rst_1_1_cZ ( + .A(un18_txr_wt_tc), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un1_dual_or_serd_rst_1_1) +); +defparam un1_dual_or_serd_rst_1_1_cZ.init=16'h0101; +// @16:282 + LUT4 un2_plol_fedge_5_1_cZ ( + .A(pll_lol_p2), + .B(tx_any_rst), + .C(VCC), + .D(VCC), + .Z(un2_plol_fedge_5_1) +); +defparam un2_plol_fedge_5_1_cZ.init=16'h1111; +// @16:388 + LUT4 rlols0_cnt_tc_1_cZ ( + .A(rlols0_cnt_tc_1_10), + .B(rlols0_cnt_tc_1_11), + .C(rlols0_cnt_tc_1_12), + .D(rlols0_cnt_tc_1_13), + .Z(rlols0_cnt_tc_1) +); +defparam rlols0_cnt_tc_1_cZ.init=16'h8000; +// @16:387 + LUT4 rlol1_cnt_tc_1_cZ ( + .A(rlol1_cnt_tc_1_11), + .B(rlol1_cnt_tc_1_12), + .C(rlol1_cnt_tc_1_13), + .D(rlol1_cnt_tc_1_14), + .Z(rlol1_cnt_tc_1) +); +defparam rlol1_cnt_tc_1_cZ.init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc ( + .A(un1_plol_cnt_tc_11), + .B(un1_plol_cnt_tc_12), + .C(un1_plol_cnt_tc_13), + .D(un1_plol_cnt_tc_14), + .Z(un1_plol_cnt_tc) +); +defparam \genblk1.un1_plol_cnt_tc .init=16'h8000; +// @16:625 + LUT4 \un1_genblk2.rlol_db_cnt_axb_0 ( + .A(rlol_db_cnt[0]), + .B(un1_rlol_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlol_db_cnt_axb_0) +); +defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999; +// @16:641 + LUT4 \un1_genblk2.rlos_db_cnt_axb_0 ( + .A(rlos_db_cnt[0]), + .B(un1_rlos_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlos_db_cnt_axb_0) +); +defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999; +// @16:443 + LUT4 \genblk1.waita_plol0_RNO ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1_i) +); +defparam \genblk1.waita_plol0_RNO .init=16'hF6F6; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[2] ( + .A(CO0_2), + .B(plol0_cnt9), + .C(plol0_cnt[1]), + .D(plol0_cnt[2]), + .Z(plol0_cnt_3[2]) +); +defparam \genblk1.plol0_cnt_3[2] .init=16'h1320; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[0] ( + .A(plol0_cnt9), + .B(plol0_cnt[0]), + .C(waita_plol0), + .D(VCC), + .Z(plol0_cnt_3[0]) +); +defparam \genblk1.plol0_cnt_3[0] .init=16'h1414; +// @16:493 + LUT4 \genblk1.genblk2.txsr_appd_2 ( + .A(txsr_appd_4), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(txsr_appd_2) +); +defparam \genblk1.genblk2.txsr_appd_2 .init=16'hFEFE; +// @16:514 + LUT4 \genblk1.genblk2.mfor[0].un1_txsr_appd ( + .A(txdpr_appd), + .B(txsr_appd_4), + .C(rsl_tx_pcs_rst_c), + .D(VCC), + .Z(un1_txsr_appd) +); +defparam \genblk1.genblk2.mfor[0].un1_txsr_appd .init=16'hC8C8; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc ( + .A(un17_rxr_wt_tc_6), + .B(un17_rxr_wt_tc_7), + .C(un17_rxr_wt_tc_8), + .D(VCC), + .Z(un17_rxr_wt_tc) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080; +// @16:863 + LUT4 rx_any_rst_cZ ( + .A(rsl_rx_pcs_rst_c), + .B(rsl_rx_serdes_rst_c), + .C(rsl_serdes_rst_dual_c), + .D(rst_dual_c), + .Z(rx_any_rst) +); +defparam rx_any_rst_cZ.init=16'hFFFE; +// @16:490 + LUT4 tx_any_rst_cZ ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_tx_pcs_rst_c), + .C(rsl_tx_serdes_rst_c), + .D(rst_dual_c), + .Z(tx_any_rst) +); +defparam tx_any_rst_cZ.init=16'hFFFE; +// @16:211 + LUT4 un2_plol_fedge_2_cZ ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un2_plol_fedge_2) +); +defparam un2_plol_fedge_2_cZ.init=16'h0101; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc ( + .A(un18_txr_wt_tc_6), + .B(un18_txr_wt_tc_7), + .C(un18_txr_wt_tc_8), + .D(VCC), + .Z(un18_txr_wt_tc) +); +defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_bm[0]) +); +defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlol_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlol_db_cnt_zero_bm[0]), + .BLUT(un1_rlol_db_cnt_zero_am[0]), + .C0(rlol_p2), + .Z(un1_rlol_db_cnt_zero[0]) +); +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_bm[0]) +); +defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlos_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlos_db_cnt_zero_bm[0]), + .BLUT(un1_rlos_db_cnt_zero_am[0]), + .C0(rlos_p2), + .Z(un1_rlos_db_cnt_zero[0]) +); +// @16:309 + LUT4 \genblk2.un1_rlol_db_cnt_max ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_max) +); +defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001; +// @16:315 + LUT4 \genblk2.un1_rlos_db_cnt_max ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_max) +); +defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001; +// @16:269 + LUT4 \genblk1.un1_plol0_cnt_tc_1 ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1) +); +defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8; +// @16:764 + LUT4 \genblk2.waita_rlols06 ( + .A(rlol_db), + .B(rlol_db_p1), + .C(rlos_db), + .D(rlos_db_p1), + .Z(waita_rlols06) +); +defparam \genblk2.waita_rlols06 .init=16'h0504; +// @16:708 + LUT4 \rxs_cnt_3_cZ[1] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[1]) +); +defparam \rxs_cnt_3_cZ[1] .init=16'h6464; +// @16:893 + LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd ( + .A(rxsr_appd[0]), + .B(rx_all_well), + .C(rxsdr_appd_4), + .D(rsl_rx_pcs_rst_c), + .Z(un1_rxsdr_or_sr_appd) +); +defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd .init=16'h3200; +// @16:388 + LUT4 rlols0_cnt_tc_1_13_cZ ( + .A(rlols0_cnt[16]), + .B(rlols0_cnt[17]), + .C(rlols0_cnt_tc_1_9), + .D(VCC), + .Z(rlols0_cnt_tc_1_13) +); +defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_14 ( + .A(plol_cnt[4]), + .B(plol_cnt[5]), + .C(plol_cnt[18]), + .D(un1_plol_cnt_tc_10), + .Z(un1_plol_cnt_tc_14) +); +defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_14_cZ ( + .A(rlol1_cnt[11]), + .B(rlol1_cnt[12]), + .C(rlol1_cnt[18]), + .D(rlol1_cnt_tc_1_10), + .Z(rlol1_cnt_tc_1_14) +); +defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100; +// @16:904 + LUT4 un1_dual_or_rserd_rst_2_0_cZ ( + .A(rxpr_appd[0]), + .B(rxdpr_appd), + .C(rx_all_well), + .D(rsl_rx_rdy), + .Z(un1_dual_or_rserd_rst_2_0) +); +defparam un1_dual_or_rserd_rst_2_0_cZ.init=16'hF010; +// @16:438 + LUT4 rdo_tx_serdes_rst_c ( + .A(rsl_disable), + .B(txs_rst), + .C(tx_serdes_rst_c), + .D(VCC), + .Z(rsl_tx_serdes_rst_c) +); +defparam rdo_tx_serdes_rst_c.init=16'hF4F4; +// @16:375 + LUT4 rdo_serdes_rst_dual_c ( + .A(rsl_disable), + .B(rsl_rst), + .C(serdes_rst_dual_c), + .D(VCC), + .Z(rsl_serdes_rst_dual_c) +); +defparam rdo_serdes_rst_dual_c.init=16'hF4F4; +// @16:479 + LUT4 \rdo_tx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(txp_rst), + .C(tx_pcs_rst_c), + .D(VCC), + .Z(rsl_tx_pcs_rst_c) +); +defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:743 + LUT4 \rdo_rx_serdes_rst_c_1[0] ( + .A(rsl_disable), + .B(rxs_rst), + .C(rx_serdes_rst_c), + .D(VCC), + .Z(rsl_rx_serdes_rst_c) +); +defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4; +// @16:852 + LUT4 \rdo_rx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(rxp_rst2), + .C(rx_pcs_rst_c), + .D(VCC), + .Z(rsl_rx_pcs_rst_c) +); +defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:459 + LUT4 \genblk1.un9_plol0_cnt_tc ( + .A(plol0_cnt[0]), + .B(plol0_cnt[1]), + .C(plol0_cnt[2]), + .D(VCC), + .Z(un9_plol0_cnt_tc) +); +defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_6 ( + .A(txr_wt_cnt[0]), + .B(txr_wt_cnt[8]), + .C(txr_wt_cnt[9]), + .D(txr_wt_cnt[11]), + .Z(un18_txr_wt_tc_6) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_7 ( + .A(txr_wt_cnt[3]), + .B(txr_wt_cnt[4]), + .C(txr_wt_cnt[5]), + .D(txr_wt_cnt[7]), + .Z(un18_txr_wt_tc_7) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_8 ( + .A(txr_wt_cnt[1]), + .B(txr_wt_cnt[2]), + .C(txr_wt_cnt[6]), + .D(txr_wt_cnt[10]), + .Z(un18_txr_wt_tc_8) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6 ( + .A(rxr_wt_cnt[0]), + .B(rxr_wt_cnt[8]), + .C(rxr_wt_cnt[9]), + .D(rxr_wt_cnt[11]), + .Z(un17_rxr_wt_tc_6) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7 ( + .A(rxr_wt_cnt[3]), + .B(rxr_wt_cnt[4]), + .C(rxr_wt_cnt[5]), + .D(rxr_wt_cnt[7]), + .Z(un17_rxr_wt_tc_7) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8 ( + .A(rxr_wt_cnt[1]), + .B(rxr_wt_cnt[2]), + .C(rxr_wt_cnt[6]), + .D(rxr_wt_cnt[10]), + .Z(un17_rxr_wt_tc_8) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_9_cZ ( + .A(rlols0_cnt[1]), + .B(rlols0_cnt[2]), + .C(rlols0_cnt[3]), + .D(rlols0_cnt[4]), + .Z(rlols0_cnt_tc_1_9) +); +defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_10_cZ ( + .A(rlols0_cnt[0]), + .B(rlols0_cnt[10]), + .C(rlols0_cnt[14]), + .D(rlols0_cnt[15]), + .Z(rlols0_cnt_tc_1_10) +); +defparam rlols0_cnt_tc_1_10_cZ.init=16'h4000; +// @16:388 + LUT4 rlols0_cnt_tc_1_11_cZ ( + .A(rlols0_cnt[9]), + .B(rlols0_cnt[11]), + .C(rlols0_cnt[12]), + .D(rlols0_cnt[13]), + .Z(rlols0_cnt_tc_1_11) +); +defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_12_cZ ( + .A(rlols0_cnt[5]), + .B(rlols0_cnt[6]), + .C(rlols0_cnt[7]), + .D(rlols0_cnt[8]), + .Z(rlols0_cnt_tc_1_12) +); +defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_10 ( + .A(plol_cnt[2]), + .B(plol_cnt[3]), + .C(plol_cnt[17]), + .D(plol_cnt[19]), + .Z(un1_plol_cnt_tc_10) +); +defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h1000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_11 ( + .A(plol_cnt[13]), + .B(plol_cnt[14]), + .C(plol_cnt[15]), + .D(plol_cnt[16]), + .Z(un1_plol_cnt_tc_11) +); +defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_12 ( + .A(plol_cnt[7]), + .B(plol_cnt[8]), + .C(plol_cnt[9]), + .D(plol_cnt[11]), + .Z(un1_plol_cnt_tc_12) +); +defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_13 ( + .A(plol_cnt[1]), + .B(plol_cnt[6]), + .C(plol_cnt[10]), + .D(plol_cnt[12]), + .Z(un1_plol_cnt_tc_13) +); +defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0008; +// @16:387 + LUT4 rlol1_cnt_tc_1_10_cZ ( + .A(rlol1_cnt[7]), + .B(rlol1_cnt[8]), + .C(rlol1_cnt[9]), + .D(rlol1_cnt[10]), + .Z(rlol1_cnt_tc_1_10) +); +defparam rlol1_cnt_tc_1_10_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_11_cZ ( + .A(rlol1_cnt[3]), + .B(rlol1_cnt[4]), + .C(rlol1_cnt[5]), + .D(rlol1_cnt[6]), + .Z(rlol1_cnt_tc_1_11) +); +defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_12_cZ ( + .A(rlol1_cnt[0]), + .B(rlol1_cnt[1]), + .C(rlol1_cnt[2]), + .D(rlol1_cnt[17]), + .Z(rlol1_cnt_tc_1_12) +); +defparam rlol1_cnt_tc_1_12_cZ.init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_13_cZ ( + .A(rlol1_cnt[13]), + .B(rlol1_cnt[14]), + .C(rlol1_cnt[15]), + .D(rlol1_cnt[16]), + .Z(rlol1_cnt_tc_1_13) +); +defparam rlol1_cnt_tc_1_13_cZ.init=16'h0040; +// @16:457 + LUT4 \genblk1.plol0_cnt_3_RNO[2] ( + .A(plol0_cnt[0]), + .B(waita_plol0), + .C(VCC), + .D(VCC), + .Z(CO0_2) +); +defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888; +// @16:441 + LUT4 plol_fedge_cZ ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(VCC), + .D(VCC), + .Z(plol_fedge) +); +defparam plol_fedge_cZ.init=16'h4444; +// @16:601 + LUT4 rx_all_well_cZ ( + .A(rlol_db), + .B(rlos_db), + .C(VCC), + .D(VCC), + .Z(rx_all_well) +); +defparam rx_all_well_cZ.init=16'h1111; +// @16:866 + LUT4 \genblk2.genblk3.rxsdr_appd_2 ( + .A(rxsdr_appd_4), + .B(serdes_rst_dual_c), + .C(VCC), + .D(VCC), + .Z(rxsdr_appd_2) +); +defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE; +// @16:436 + LUT4 \genblk2.un8_rxs_cnt_tc ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(VCC), + .D(VCC), + .Z(un8_rxs_cnt_tc) +); +defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888; +// @16:757 + LUT4 rlos_redge_cZ ( + .A(rlos_db), + .B(rlos_db_p1), + .C(VCC), + .D(VCC), + .Z(rlos_redge) +); +defparam rlos_redge_cZ.init=16'h2222; +// @16:891 + LUT4 un2_rdo_serdes_rst_dual_c_1_1_cZ ( + .A(rx_cdr_lol_s), + .B(rx_los_low_s), + .C(VCC), + .D(VCC), + .Z(un2_rdo_serdes_rst_dual_c_1_1) +); +defparam un2_rdo_serdes_rst_dual_c_1_1_cZ.init=16'h1111; +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_am_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_am[0]) +); +defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_am_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_am[0]) +); +defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:454 + LUT4 \genblk1.plol0_cnt9 ( + .A(pll_lol_p2), + .B(plol0_cnt[2]), + .C(plol0_cnt[1]), + .D(plol0_cnt[0]), + .Z(plol0_cnt9) +); +defparam \genblk1.plol0_cnt9 .init=16'hAAAE; +// @16:783 + LUT4 \genblk2.rlols0_cnt11_0 ( + .A(rlol_db_p1), + .B(rlol_db), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlols0_cnt11_0) +); +defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44; +// @16:527 + LUT4 \genblk1.genblk2.txr_wt_cnt9_i ( + .A(tx_any_rst), + .B(un18_txr_wt_tc_8), + .C(un18_txr_wt_tc_7), + .D(un18_txr_wt_tc_6), + .Z(txr_wt_cnt_scalar) +); +defparam \genblk1.genblk2.txr_wt_cnt9_i .init=16'h1555; + CCU2C \genblk2.rlol1_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlol1_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_7), + .COUT(rlol1_cnt_cry[0]), + .S0(rlol1_cnt_cry_0_S0[0]), + .S1(rlol1_cnt_s[0]) +); +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[1] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[0]), + .COUT(rlol1_cnt_cry[2]), + .S0(rlol1_cnt_s[1]), + .S1(rlol1_cnt_s[2]) +); +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[3] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[2]), + .COUT(rlol1_cnt_cry[4]), + .S0(rlol1_cnt_s[3]), + .S1(rlol1_cnt_s[4]) +); +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[5] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[4]), + .COUT(rlol1_cnt_cry[6]), + .S0(rlol1_cnt_s[5]), + .S1(rlol1_cnt_s[6]) +); +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[7] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[6]), + .COUT(rlol1_cnt_cry[8]), + .S0(rlol1_cnt_s[7]), + .S1(rlol1_cnt_s[8]) +); +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[9] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[8]), + .COUT(rlol1_cnt_cry[10]), + .S0(rlol1_cnt_s[9]), + .S1(rlol1_cnt_s[10]) +); +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[11] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[10]), + .COUT(rlol1_cnt_cry[12]), + .S0(rlol1_cnt_s[11]), + .S1(rlol1_cnt_s[12]) +); +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[13] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[12]), + .COUT(rlol1_cnt_cry[14]), + .S0(rlol1_cnt_s[13]), + .S1(rlol1_cnt_s[14]) +); +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[15] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[14]), + .COUT(rlol1_cnt_cry[16]), + .S0(rlol1_cnt_s[15]), + .S1(rlol1_cnt_s[16]) +); +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[17] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[16]), + .COUT(rlol1_cnt_cry_0_COUT[17]), + .S0(rlol1_cnt_s[17]), + .S1(rlol1_cnt_s[18]) +); +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO"; + CCU2C \genblk2.rlols0_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlols0_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_6), + .COUT(rlols0_cnt_cry[0]), + .S0(rlols0_cnt_cry_0_S0[0]), + .S1(rlols0_cnt_s[0]) +); +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[1] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[0]), + .COUT(rlols0_cnt_cry[2]), + .S0(rlols0_cnt_s[1]), + .S1(rlols0_cnt_s[2]) +); +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[3] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[2]), + .COUT(rlols0_cnt_cry[4]), + .S0(rlols0_cnt_s[3]), + .S1(rlols0_cnt_s[4]) +); +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[5] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[4]), + .COUT(rlols0_cnt_cry[6]), + .S0(rlols0_cnt_s[5]), + .S1(rlols0_cnt_s[6]) +); +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[7] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[6]), + .COUT(rlols0_cnt_cry[8]), + .S0(rlols0_cnt_s[7]), + .S1(rlols0_cnt_s[8]) +); +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[9] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[8]), + .COUT(rlols0_cnt_cry[10]), + .S0(rlols0_cnt_s[9]), + .S1(rlols0_cnt_s[10]) +); +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[11] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[10]), + .COUT(rlols0_cnt_cry[12]), + .S0(rlols0_cnt_s[11]), + .S1(rlols0_cnt_s[12]) +); +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[13] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[12]), + .COUT(rlols0_cnt_cry[14]), + .S0(rlols0_cnt_s[13]), + .S1(rlols0_cnt_s[14]) +); +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[15] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[14]), + .COUT(rlols0_cnt_cry[16]), + .S0(rlols0_cnt_s[15]), + .S1(rlols0_cnt_s[16]) +); +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_s_0[17] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[16]), + .COUT(rlols0_cnt_s_0_COUT[17]), + .S0(rlols0_cnt_s[17]), + .S1(rlols0_cnt_s_0_S1[17]) +); +defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a; +defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO"; + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(txr_wt_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(txr_wt_cnt_cry[0]), + .S0(txr_wt_cnt_cry_0_S0[0]), + .S1(txr_wt_cnt_s[0]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[0]), + .COUT(txr_wt_cnt_cry[2]), + .S0(txr_wt_cnt_s[1]), + .S1(txr_wt_cnt_s[2]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[2]), + .COUT(txr_wt_cnt_cry[4]), + .S0(txr_wt_cnt_s[3]), + .S1(txr_wt_cnt_s[4]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[4]), + .COUT(txr_wt_cnt_cry[6]), + .S0(txr_wt_cnt_s[5]), + .S1(txr_wt_cnt_s[6]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[6]), + .COUT(txr_wt_cnt_cry[8]), + .S0(txr_wt_cnt_s[7]), + .S1(txr_wt_cnt_s[8]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt_scalar), + .B1(txr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[8]), + .COUT(txr_wt_cnt_cry[10]), + .S0(txr_wt_cnt_s[9]), + .S1(txr_wt_cnt_s[10]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11] ( + .A0(txr_wt_cnt_scalar), + .B0(txr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[10]), + .COUT(txr_wt_cnt_s_0_COUT[11]), + .S0(txr_wt_cnt_s[11]), + .S1(txr_wt_cnt_s_0_S1[11]) +); +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h800a; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(rxr_wt_cnt9), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rxr_wt_cnt_cry[0]), + .S0(rxr_wt_cnt_cry_0_S0[0]), + .S1(rxr_wt_cnt_s[0]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[0]), + .COUT(rxr_wt_cnt_cry[2]), + .S0(rxr_wt_cnt_s[1]), + .S1(rxr_wt_cnt_s[2]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[2]), + .COUT(rxr_wt_cnt_cry[4]), + .S0(rxr_wt_cnt_s[3]), + .S1(rxr_wt_cnt_s[4]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[4]), + .COUT(rxr_wt_cnt_cry[6]), + .S0(rxr_wt_cnt_s[5]), + .S1(rxr_wt_cnt_s[6]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[6]), + .COUT(rxr_wt_cnt_cry[8]), + .S0(rxr_wt_cnt_s[7]), + .S1(rxr_wt_cnt_s[8]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[8]), + .COUT(rxr_wt_cnt_cry[10]), + .S0(rxr_wt_cnt_s[9]), + .S1(rxr_wt_cnt_s[10]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[10]), + .COUT(rxr_wt_cnt_s_0_COUT[11]), + .S0(rxr_wt_cnt_s[11]), + .S1(rxr_wt_cnt_s_0_S1[11]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk1.plol_cnt_cry_0[0] ( + .A0(VCC), + .B0(plol_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(plol_cnt_cry[0]), + .S0(plol_cnt_cry_0_S0[0]), + .S1(plol_cnt_s[0]) +); +defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[1] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[0]), + .COUT(plol_cnt_cry[2]), + .S0(plol_cnt_s[1]), + .S1(plol_cnt_s[2]) +); +defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[3] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[2]), + .COUT(plol_cnt_cry[4]), + .S0(plol_cnt_s[3]), + .S1(plol_cnt_s[4]) +); +defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[5] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[4]), + .COUT(plol_cnt_cry[6]), + .S0(plol_cnt_s[5]), + .S1(plol_cnt_s[6]) +); +defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[7] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[6]), + .COUT(plol_cnt_cry[8]), + .S0(plol_cnt_s[7]), + .S1(plol_cnt_s[8]) +); +defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[9] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[8]), + .COUT(plol_cnt_cry[10]), + .S0(plol_cnt_s[9]), + .S1(plol_cnt_s[10]) +); +defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[11] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[10]), + .COUT(plol_cnt_cry[12]), + .S0(plol_cnt_s[11]), + .S1(plol_cnt_s[12]) +); +defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[13] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[12]), + .COUT(plol_cnt_cry[14]), + .S0(plol_cnt_s[13]), + .S1(plol_cnt_s[14]) +); +defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[15] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[14]), + .COUT(plol_cnt_cry[16]), + .S0(plol_cnt_s[15]), + .S1(plol_cnt_s[16]) +); +defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[17] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[16]), + .COUT(plol_cnt_cry[18]), + .S0(plol_cnt_s[17]), + .S1(plol_cnt_s[18]) +); +defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_s_0[19] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[19]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[18]), + .COUT(plol_cnt_s_0_COUT[19]), + .S0(plol_cnt_s[19]), + .S1(plol_cnt_s_0_S1[19]) +); +defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a; +defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlos_db_cnt[0]), + .B1(un1_rlos_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(rlos_db_cnt_cry_0), + .S0(rlos_db_cnt_cry_0_0_S0), + .S1(rlos_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0 ( + .A0(un1_rlos_db_cnt_zero[0]), + .B0(rlos_p2), + .C0(rlos_db_cnt[1]), + .D0(VCC), + .A1(un1_rlos_db_cnt_zero[0]), + .B1(rlos_p2), + .C1(rlos_db_cnt[2]), + .D1(VCC), + .CIN(rlos_db_cnt_cry_0), + .COUT(rlos_db_cnt_cry_2), + .S0(rlos_db_cnt_cry_1_0_S0), + .S1(rlos_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_s_3_0 ( + .A0(rlos_db_cnt[3]), + .B0(rlos_p2), + .C0(un1_rlos_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlos_db_cnt_cry_2), + .COUT(rlos_db_cnt_s_3_0_COUT), + .S0(rlos_db_cnt_s_3_0_S0), + .S1(rlos_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlol_db_cnt[0]), + .B1(un1_rlol_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(rlol_db_cnt_cry_0), + .S0(rlol_db_cnt_cry_0_0_S0), + .S1(rlol_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0 ( + .A0(un1_rlol_db_cnt_zero[0]), + .B0(rlol_p2), + .C0(rlol_db_cnt[1]), + .D0(VCC), + .A1(un1_rlol_db_cnt_zero[0]), + .B1(rlol_p2), + .C1(rlol_db_cnt[2]), + .D1(VCC), + .CIN(rlol_db_cnt_cry_0), + .COUT(rlol_db_cnt_cry_2), + .S0(rlol_db_cnt_cry_1_0_S0), + .S1(rlol_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_s_3_0 ( + .A0(rlol_db_cnt[3]), + .B0(rlol_p2), + .C0(un1_rlol_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlol_db_cnt_cry_2), + .COUT(rlol_db_cnt_s_3_0_COUT), + .S0(rlol_db_cnt_s_3_0_S0), + .S1(rlol_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO"; +//@16:865 +//@16:492 + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sgmii_ecp5rsl_core_Z2_layer1 */ + +module sgmii_ecp5 ( + hdoutp, + hdoutn, + hdinp, + hdinn, + rxrefclk, + tx_pclk, + txi_clk, + txdata, + tx_k, + xmit, + tx_disp_correct, + rxdata, + rx_k, + rx_disp_err, + rx_cv_err, + signal_detect_c, + rx_los_low_s, + lsm_status_s, + ctc_urun_s, + ctc_orun_s, + rx_cdr_lol_s, + ctc_ins_s, + ctc_del_s, + sli_rst, + tx_pwrup_c, + rx_pwrup_c, + sci_wrdata, + sci_addr, + sci_rddata, + sci_en_dual, + sci_sel_dual, + sci_en, + sci_sel, + sci_rd, + sci_wrn, + sci_int, + cyawstn, + serdes_pdb, + pll_refclki, + rsl_disable, + rsl_rst, + serdes_rst_dual_c, + rst_dual_c, + tx_serdes_rst_c, + tx_pcs_rst_c, + pll_lol, + rsl_tx_rdy, + rx_serdes_rst_c, + rx_pcs_rst_c, + rsl_rx_rdy +) +; +output hdoutp ; +output hdoutn ; +input hdinp ; +input hdinn ; +input rxrefclk ; +output tx_pclk ; +input txi_clk ; +input [7:0] txdata ; +input [0:0] tx_k ; +input [0:0] xmit ; +input [0:0] tx_disp_correct ; +output [7:0] rxdata ; +output [0:0] rx_k ; +output [0:0] rx_disp_err ; +output [0:0] rx_cv_err ; +input signal_detect_c ; +output rx_los_low_s ; +output lsm_status_s ; +output ctc_urun_s ; +output ctc_orun_s ; +output rx_cdr_lol_s ; +output ctc_ins_s ; +output ctc_del_s ; +input sli_rst ; +input tx_pwrup_c ; +input rx_pwrup_c ; +input [7:0] sci_wrdata ; +input [5:0] sci_addr ; +output [7:0] sci_rddata ; +input sci_en_dual ; +input sci_sel_dual ; +input sci_en ; +input sci_sel ; +input sci_rd ; +input sci_wrn ; +output sci_int ; +input cyawstn ; +input serdes_pdb ; +input pll_refclki ; +input rsl_disable ; +input rsl_rst ; +input serdes_rst_dual_c ; +input rst_dual_c ; +input tx_serdes_rst_c ; +input tx_pcs_rst_c ; +output pll_lol ; +output rsl_tx_rdy ; +input rx_serdes_rst_c ; +input rx_pcs_rst_c ; +output rsl_rx_rdy ; +wire hdoutp ; +wire hdoutn ; +wire hdinp ; +wire hdinn ; +wire rxrefclk ; +wire tx_pclk ; +wire txi_clk ; +wire signal_detect_c ; +wire rx_los_low_s ; +wire lsm_status_s ; +wire ctc_urun_s ; +wire ctc_orun_s ; +wire rx_cdr_lol_s ; +wire ctc_ins_s ; +wire ctc_del_s ; +wire sli_rst ; +wire tx_pwrup_c ; +wire rx_pwrup_c ; +wire sci_en_dual ; +wire sci_sel_dual ; +wire sci_en ; +wire sci_sel ; +wire sci_rd ; +wire sci_wrn ; +wire sci_int ; +wire cyawstn ; +wire serdes_pdb ; +wire pll_refclki ; +wire rsl_disable ; +wire rsl_rst ; +wire serdes_rst_dual_c ; +wire rst_dual_c ; +wire tx_serdes_rst_c ; +wire tx_pcs_rst_c ; +wire pll_lol ; +wire rsl_tx_rdy ; +wire rx_serdes_rst_c ; +wire rx_pcs_rst_c ; +wire rsl_rx_rdy ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire n47_1 ; +wire n48_1 ; +wire n1_1 ; +wire n2_1 ; +wire n3_1 ; +wire n4_1 ; +wire n5_1 ; +wire n49_1 ; +wire n6_1 ; +wire n50_1 ; +wire n7_1 ; +wire n51_1 ; +wire n8_1 ; +wire n52_1 ; +wire n9_1 ; +wire n53_1 ; +wire n54_1 ; +wire n55_1 ; +wire n56_1 ; +wire n57_1 ; +wire n58_1 ; +wire n59_1 ; +wire n60_1 ; +wire n61_1 ; +wire n62_1 ; +wire n63_1 ; +wire n64_1 ; +wire n65_1 ; +wire n10_1 ; +wire n66_1 ; +wire n67_1 ; +wire n68_1 ; +wire n69_1 ; +wire n70_1 ; +wire n71_1 ; +wire n72_1 ; +wire n73_1 ; +wire n74_1 ; +wire n75_1 ; +wire n76_1 ; +wire n77_1 ; +wire n78_1 ; +wire n79_1 ; +wire n80_1 ; +wire n81_1 ; +wire n82_1 ; +wire n83_1 ; +wire n84_1 ; +wire n85_1 ; +wire n86_1 ; +wire n87_1 ; +wire n88_1 ; +wire n11_1 ; +wire n89_1 ; +wire n12_1 ; +wire n90_1 ; +wire n13_1 ; +wire n91_1 ; +wire n92_1 ; +wire n93_1 ; +wire n94_1 ; +wire n95_1 ; +wire n14_1 ; +wire n96_1 ; +wire n15_1 ; +wire n97_1 ; +wire n98_1 ; +wire n99_1 ; +wire n100_1 ; +wire n101_1 ; +wire n112_1 ; +wire n16_1 ; +wire n17_1 ; +wire n18_1 ; +wire n19_1 ; +wire n20_1 ; +wire n21_1 ; +wire n22_1 ; +wire n23_1 ; +wire n24_1 ; +wire n25_1 ; +wire n26_1 ; +wire n27_1 ; +wire n28_1 ; +wire n29_1 ; +wire n30_1 ; +wire n31_1 ; +wire n32_1 ; +wire n33_1 ; +wire n34_1 ; +wire n35_1 ; +wire n36_1 ; +wire n37_1 ; +wire n38_1 ; +wire n39_1 ; +wire n40_1 ; +wire n41_1 ; +wire n42_1 ; +wire n43_1 ; +wire n46_1 ; +wire GND ; +wire VCC ; + VHI VCC_0 ( + .Z(VCC) +); + VLO GND_0 ( + .Z(GND) +); +// @16:865 + PUR PUR_INST ( + .PUR(VCC) +); +// @16:865 + GSR GSR_INST ( + .GSR(VCC) +); +// @8:162 +(* CHAN="CH0" *) DCUA DCU0_inst ( + .CH0_HDINP(hdinp), + .CH1_HDINP(GND), + .CH0_HDINN(hdinn), + .CH1_HDINN(GND), + .D_TXBIT_CLKP_FROM_ND(GND), + .D_TXBIT_CLKN_FROM_ND(GND), + .D_SYNC_ND(GND), + .D_TXPLL_LOL_FROM_ND(GND), + .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(GND), + .CH0_FF_RXI_CLK(tx_pclk), + .CH1_FF_RXI_CLK(VCC), + .CH0_FF_TXI_CLK(txi_clk), + .CH1_FF_TXI_CLK(VCC), + .CH0_FF_EBRD_CLK(tx_pclk), + .CH1_FF_EBRD_CLK(VCC), + .CH0_FF_TX_D_0(txdata[0]), + .CH1_FF_TX_D_0(GND), + .CH0_FF_TX_D_1(txdata[1]), + .CH1_FF_TX_D_1(GND), + .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(GND), + .CH0_FF_TX_D_3(txdata[3]), + .CH1_FF_TX_D_3(GND), + .CH0_FF_TX_D_4(txdata[4]), + .CH1_FF_TX_D_4(GND), + .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(GND), + .CH0_FF_TX_D_6(txdata[6]), + .CH1_FF_TX_D_6(GND), + .CH0_FF_TX_D_7(txdata[7]), + .CH1_FF_TX_D_7(GND), + .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(GND), + .CH0_FF_TX_D_9(GND), + .CH1_FF_TX_D_9(GND), + .CH0_FF_TX_D_10(xmit[0]), + .CH1_FF_TX_D_10(GND), + .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(GND), + .CH0_FF_TX_D_12(GND), + .CH1_FF_TX_D_12(GND), + .CH0_FF_TX_D_13(GND), + .CH1_FF_TX_D_13(GND), + .CH0_FF_TX_D_14(GND), + .CH1_FF_TX_D_14(GND), + .CH0_FF_TX_D_15(GND), + .CH1_FF_TX_D_15(GND), + .CH0_FF_TX_D_16(GND), + .CH1_FF_TX_D_16(GND), + .CH0_FF_TX_D_17(GND), + .CH1_FF_TX_D_17(GND), + .CH0_FF_TX_D_18(GND), + .CH1_FF_TX_D_18(GND), + .CH0_FF_TX_D_19(GND), + .CH1_FF_TX_D_19(GND), + .CH0_FF_TX_D_20(GND), + .CH1_FF_TX_D_20(GND), + .CH0_FF_TX_D_21(GND), + .CH1_FF_TX_D_21(GND), + .CH0_FF_TX_D_22(GND), + .CH1_FF_TX_D_22(GND), + .CH0_FF_TX_D_23(GND), + .CH1_FF_TX_D_23(GND), + .CH0_FFC_EI_EN(GND), + .CH1_FFC_EI_EN(GND), + .CH0_FFC_PCIE_DET_EN(GND), + .CH1_FFC_PCIE_DET_EN(GND), + .CH0_FFC_PCIE_CT(GND), + .CH1_FFC_PCIE_CT(GND), + .CH0_FFC_SB_INV_RX(GND), + .CH1_FFC_SB_INV_RX(GND), + .CH0_FFC_ENABLE_CGALIGN(GND), + .CH1_FFC_ENABLE_CGALIGN(GND), + .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(GND), + .CH0_FFC_FB_LOOPBACK(GND), + .CH1_FFC_FB_LOOPBACK(GND), + .CH0_FFC_SB_PFIFO_LP(GND), + .CH1_FFC_SB_PFIFO_LP(GND), + .CH0_FFC_PFIFO_CLR(GND), + .CH1_FFC_PFIFO_CLR(GND), + .CH0_FFC_RATE_MODE_RX(GND), + .CH1_FFC_RATE_MODE_RX(GND), + .CH0_FFC_RATE_MODE_TX(GND), + .CH1_FFC_RATE_MODE_TX(GND), + .CH0_FFC_DIV11_MODE_RX(GND), + .CH1_FFC_DIV11_MODE_RX(GND), + .CH0_FFC_RX_GEAR_MODE(GND), + .CH1_FFC_RX_GEAR_MODE(GND), + .CH0_FFC_TX_GEAR_MODE(GND), + .CH1_FFC_TX_GEAR_MODE(GND), + .CH0_FFC_DIV11_MODE_TX(GND), + .CH1_FFC_DIV11_MODE_TX(GND), + .CH0_FFC_LDR_CORE2TX_EN(GND), + .CH1_FFC_LDR_CORE2TX_EN(GND), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), + .CH1_FFC_LANE_TX_RST(GND), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), + .CH1_FFC_LANE_RX_RST(GND), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), + .CH1_FFC_RRST(GND), + .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(GND), + .CH0_FFC_RXPWDNB(rx_pwrup_c), + .CH1_FFC_RXPWDNB(GND), + .CH0_LDR_CORE2TX(GND), + .CH1_LDR_CORE2TX(GND), + .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), + .D_SCIWDATA2(sci_wrdata[2]), + .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), + .D_SCIWDATA5(sci_wrdata[5]), + .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), + .D_SCIADDR0(sci_addr[0]), + .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), + .D_SCIADDR3(sci_addr[3]), + .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), + .D_SCIENAUX(sci_en_dual), + .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), + .CH1_SCIEN(GND), + .CH0_SCISEL(sci_sel), + .CH1_SCISEL(GND), + .D_SCIRD(sci_rd), + .D_SCIWSTN(sci_wrn), + .D_CYAWSTN(cyawstn), + .D_FFC_SYNC_TOGGLE(GND), + .D_FFC_DUAL_RST(rst_dual_c), + .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), + .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(GND), + .CH1_FFC_CDR_EN_BITSLIP(GND), + .D_SCAN_ENABLE(GND), + .D_SCAN_IN_0(GND), + .D_SCAN_IN_1(GND), + .D_SCAN_IN_2(GND), + .D_SCAN_IN_3(GND), + .D_SCAN_IN_4(GND), + .D_SCAN_IN_5(GND), + .D_SCAN_IN_6(GND), + .D_SCAN_IN_7(GND), + .D_SCAN_MODE(GND), + .D_SCAN_RESET(GND), + .D_CIN0(GND), + .D_CIN1(GND), + .D_CIN2(GND), + .D_CIN3(GND), + .D_CIN4(GND), + .D_CIN5(GND), + .D_CIN6(GND), + .D_CIN7(GND), + .D_CIN8(GND), + .D_CIN9(GND), + .D_CIN10(GND), + .D_CIN11(GND), + .CH0_HDOUTP(hdoutp), + .CH1_HDOUTP(n47_1), + .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n48_1), + .D_TXBIT_CLKP_TO_ND(n1_1), + .D_TXBIT_CLKN_TO_ND(n2_1), + .D_SYNC_PULSE2ND(n3_1), + .D_TXPLL_LOL_TO_ND(n4_1), + .CH0_FF_RX_F_CLK(n5_1), + .CH1_FF_RX_F_CLK(n49_1), + .CH0_FF_RX_H_CLK(n6_1), + .CH1_FF_RX_H_CLK(n50_1), + .CH0_FF_TX_F_CLK(n7_1), + .CH1_FF_TX_F_CLK(n51_1), + .CH0_FF_TX_H_CLK(n8_1), + .CH1_FF_TX_H_CLK(n52_1), + .CH0_FF_RX_PCLK(n9_1), + .CH1_FF_RX_PCLK(n53_1), + .CH0_FF_TX_PCLK(tx_pclk), + .CH1_FF_TX_PCLK(n54_1), + .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n55_1), + .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n56_1), + .CH0_FF_RX_D_2(rxdata[2]), + .CH1_FF_RX_D_2(n57_1), + .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n58_1), + .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n59_1), + .CH0_FF_RX_D_5(rxdata[5]), + .CH1_FF_RX_D_5(n60_1), + .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n61_1), + .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n62_1), + .CH0_FF_RX_D_8(rx_k[0]), + .CH1_FF_RX_D_8(n63_1), + .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n64_1), + .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n65_1), + .CH0_FF_RX_D_11(n10_1), + .CH1_FF_RX_D_11(n66_1), + .CH0_FF_RX_D_12(n67_1), + .CH1_FF_RX_D_12(n68_1), + .CH0_FF_RX_D_13(n69_1), + .CH1_FF_RX_D_13(n70_1), + .CH0_FF_RX_D_14(n71_1), + .CH1_FF_RX_D_14(n72_1), + .CH0_FF_RX_D_15(n73_1), + .CH1_FF_RX_D_15(n74_1), + .CH0_FF_RX_D_16(n75_1), + .CH1_FF_RX_D_16(n76_1), + .CH0_FF_RX_D_17(n77_1), + .CH1_FF_RX_D_17(n78_1), + .CH0_FF_RX_D_18(n79_1), + .CH1_FF_RX_D_18(n80_1), + .CH0_FF_RX_D_19(n81_1), + .CH1_FF_RX_D_19(n82_1), + .CH0_FF_RX_D_20(n83_1), + .CH1_FF_RX_D_20(n84_1), + .CH0_FF_RX_D_21(n85_1), + .CH1_FF_RX_D_21(n86_1), + .CH0_FF_RX_D_22(n87_1), + .CH1_FF_RX_D_22(n88_1), + .CH0_FF_RX_D_23(n11_1), + .CH1_FF_RX_D_23(n89_1), + .CH0_FFS_PCIE_DONE(n12_1), + .CH1_FFS_PCIE_DONE(n90_1), + .CH0_FFS_PCIE_CON(n13_1), + .CH1_FFS_PCIE_CON(n91_1), + .CH0_FFS_RLOS(rx_los_low_s), + .CH1_FFS_RLOS(n92_1), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n93_1), + .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n94_1), + .CH0_FFS_CC_OVERRUN(ctc_orun_s), + .CH1_FFS_CC_OVERRUN(n95_1), + .CH0_FFS_RXFBFIFO_ERROR(n14_1), + .CH1_FFS_RXFBFIFO_ERROR(n96_1), + .CH0_FFS_TXFBFIFO_ERROR(n15_1), + .CH1_FFS_TXFBFIFO_ERROR(n97_1), + .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n98_1), + .CH0_FFS_SKP_ADDED(ctc_ins_s), + .CH1_FFS_SKP_ADDED(n99_1), + .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n100_1), + .CH0_LDR_RX2CORE(n101_1), + .CH1_LDR_RX2CORE(n112_1), + .D_SCIRDATA0(sci_rddata[0]), + .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), + .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), + .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n16_1), + .D_SCAN_OUT_1(n17_1), + .D_SCAN_OUT_2(n18_1), + .D_SCAN_OUT_3(n19_1), + .D_SCAN_OUT_4(n20_1), + .D_SCAN_OUT_5(n21_1), + .D_SCAN_OUT_6(n22_1), + .D_SCAN_OUT_7(n23_1), + .D_COUT0(n24_1), + .D_COUT1(n25_1), + .D_COUT2(n26_1), + .D_COUT3(n27_1), + .D_COUT4(n28_1), + .D_COUT5(n29_1), + .D_COUT6(n30_1), + .D_COUT7(n31_1), + .D_COUT8(n32_1), + .D_COUT9(n33_1), + .D_COUT10(n34_1), + .D_COUT11(n35_1), + .D_COUT12(n36_1), + .D_COUT13(n37_1), + .D_COUT14(n38_1), + .D_COUT15(n39_1), + .D_COUT16(n40_1), + .D_COUT17(n41_1), + .D_COUT18(n42_1), + .D_COUT19(n43_1), + .D_REFCLKI(pll_refclki), + .D_FFS_PLOL(n46_1) +); +defparam DCU0_inst.D_MACROPDB = "0b1"; +defparam DCU0_inst.D_IB_PWDNB = "0b1"; +defparam DCU0_inst.D_XGE_MODE = "0b0"; +defparam DCU0_inst.D_LOW_MARK = "0d4"; +defparam DCU0_inst.D_HIGH_MARK = "0d12"; +defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; +defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; +defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; +defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; +defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; +defparam DCU0_inst.CH0_UC_MODE = "0b0"; +defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; +defparam DCU0_inst.CH0_RIO_MODE = "0b0"; +defparam DCU0_inst.CH0_WA_MODE = "0b0"; +defparam DCU0_inst.CH0_INVERT_RX = "0b0"; +defparam DCU0_inst.CH0_INVERT_TX = "0b0"; +defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; +defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0"; +defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; +defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; +defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; +defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; +defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; +defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_CTC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; +defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1"; +defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; +defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; +defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; +defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC"; +defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050"; +defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; +defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; +defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; +defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b000"; +defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; +defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00"; +defparam DCU0_inst.CH0_REQ_EN = "0b1"; +defparam DCU0_inst.CH0_RTERM_RX = "0d22"; +defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; +defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; +defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; +defparam DCU0_inst.CH0_TPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0"; +defparam DCU0_inst.CH0_RTERM_TX = "0d19"; +defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; +defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101"; +defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; +defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; +defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; +defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_RPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0"; +defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; +defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010"; +defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; +defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; +defparam DCU0_inst.CH0_RX_LOS_EN = "0b1"; +defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0"; +defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; +defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; +defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; +defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; +defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; +defparam DCU0_inst.CH0_RXIN_CM = "0b11"; +defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; +defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; +defparam DCU0_inst.D_TX_MAX_RATE = "2"; +defparam DCU0_inst.CH0_CDR_MAX_RATE = "2"; +defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100"; +defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; +defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; +defparam DCU0_inst.CH0_PROTOCOL = "GBE"; +defparam DCU0_inst.D_ISETLOS = "0d0"; +defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; +defparam DCU0_inst.D_SETICONST_AUX = "0b00"; +defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; +defparam DCU0_inst.D_SETICONST_CH = "0b00"; +defparam DCU0_inst.D_REQ_ISET = "0b000"; +defparam DCU0_inst.D_PD_ISET = "0b00"; +defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; +defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; +defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; +defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; +defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; +defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; +defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; +defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; +defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; +defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; +defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; +defparam DCU0_inst.CH0_DCOSTEP = "0b00"; +defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; +defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; +defparam DCU0_inst.CH0_DCOITUNE = "0b00"; +defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; +defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; +defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; +defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; +defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; +defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; +defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; +defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; +defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; +defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; +defparam DCU0_inst.D_SETPLLRC = "0d1"; +defparam DCU0_inst.D_REFCK_MODE = "0b001"; +defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000"; +defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; +defparam DCU0_inst.D_RG_EN = "0b0"; +defparam DCU0_inst.D_RG_SET = "0b00"; +defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; +defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; +defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; +defparam DCU0_inst.D_CMUSETZGM = "0b000"; +defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; +defparam DCU0_inst.D_CMUSETP1GM = "0b000"; +defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; +defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; +defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; +defparam DCU0_inst.D_CMUSETICP4P = "0b01"; +defparam DCU0_inst.D_CMUSETBIASI = "0b00"; +// @8:424 + sgmii_ecp5sll_core_Z1_layer1 sll_inst ( + .tx_pclk(tx_pclk), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki), + .pll_lock_i(pll_lol) +); +// @8:394 + sgmii_ecp5rsl_core_Z2_layer1 rsl_inst ( + .rx_pcs_rst_c(rx_pcs_rst_c), + .tx_pcs_rst_c(tx_pcs_rst_c), + .serdes_rst_dual_c(serdes_rst_dual_c), + .tx_serdes_rst_c(tx_serdes_rst_c), + .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c), + .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c), + .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rsl_tx_rdy(rsl_tx_rdy), + .pll_lock_i(pll_lol), + .pll_refclki(pll_refclki), + .rsl_rx_rdy(rsl_rx_rdy), + .rsl_rst(rsl_rst), + .rxrefclk(rxrefclk), + .rsl_disable(rsl_disable), + .rx_serdes_rst_c(rx_serdes_rst_c), + .rst_dual_c(rst_dual_c), + .rx_cdr_lol_s(rx_cdr_lol_s), + .rx_los_low_s(rx_los_low_s), + .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c), + .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c) +); +endmodule /* sgmii_ecp5 */ + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf new file mode 100644 index 0000000..9cbac38 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf @@ -0,0 +1,29 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints +#FREQUENCY PORT "pll_refclki" 100.0 MHz; +#FREQUENCY PORT "rxrefclk" 100.0 MHz; +#FREQUENCY NET "tx_pclk" 100.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk"; +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap new file mode 100644 index 0000000..3910cac --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap new file mode 100644 index 0000000..af92e0b --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap new file mode 100644 index 0000000..3793ead --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap @@ -0,0 +1 @@ +./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/metrics.db new file mode 100644 index 0000000000000000000000000000000000000000..4a54f9aa56330721e7268276626c67bb6ab973b2 GIT binary patch literal 20480 zcmeI3Piq@T7{+&P*;-LXTT_BDMs$LbDlU~H$#N`HL*u3`0JH!9Jy5q}SZ?6#}K__6zh&^iulnYW2^kCZPwD@C;sS{=DzAkACdsogF>?@zB$P zcS037nr|5&8>VU8<=ilgYjiEqHEJ2^#Mh{qqs}Ft*NpPtFBt`7*j>Xu%Kys#q7E7e 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b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt @@ -0,0 +1,16 @@ +@N|Running in 64-bit mode +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +@N|Running in 64-bit mode +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +@N|Running in 64-bit mode + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml new file mode 100644 index 0000000..ca7d50b --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml @@ -0,0 +1,41 @@ + + + + + + /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr + Synopsys HDL Compiler + + + Completed + + + + 15 + /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt + + + 77 + /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt + + + 0 + /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt + + + - + + + 00h:00m:02s + + + - + + + 1557482336 + + + \ No newline at end of file diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt new file mode 100644 index 0000000..0eac89c --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt @@ -0,0 +1,78 @@ +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml new file mode 100644 index 0000000..58aa421 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt +Resource Usage + + +221 + + +0 + + +0 + + +0 + + +153 + + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt new file mode 100644 index 0000000..89ed59a --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt @@ -0,0 +1,22 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..37c27e7 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +3 / 0 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..aa1f7f0 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +22 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt + + + +4 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt + + + +0h:00m:03s + + +0h:00m:03s + + +153MB + + +1557482342 + + + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..354cbb6 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml @@ -0,0 +1,41 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +sgmii_ecp5|pll_refclki +100.0 MHz +168.9 MHz +4.079 + + +sgmii_ecp5|rxrefclk +100.0 MHz +170.5 MHz +4.136 + + +sgmii_ecp5|tx_pclk_inferred_clock +100.0 MHz +237.5 MHz +5.789 + + +System +100.0 MHz +840.7 MHz +8.810 + + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt new file mode 100644 index 0000000..d44b509 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt @@ -0,0 +1,4 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt new file mode 100644 index 0000000..a540d08 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt @@ -0,0 +1,9 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml new file mode 100644 index 0000000..127251d --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +9 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt + + + +3 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +144MB + + +1557482338 + + + diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt new file mode 100644 index 0000000..47b05ba --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt @@ -0,0 +1,3 @@ +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr new file mode 100644 index 0000000..77a0cae --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr @@ -0,0 +1,352 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. +Post processing for work.sgmii_ecp5.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 11:58:55 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. + + PPROTOCOL=24'b010001110100001001000101 + PLOL_SETTING=32'b00000000000000000000000000000000 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000010011 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111 + PPCLK_TC=32'b00000000000000010000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = sgmii_ecp5sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=24'b010001110100001001000101 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = sgmii_ecp5rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 4 reachable states with original encodings of: + 00 + 01 + 10 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 11:58:56 2019 + +###########################################################] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..d028ab57b460c029f040b39c37ad880998e9090a GIT binary patch literal 32768 zcmeHQON<*y8MepcdCxe{4Vw@sl3n(}#O`i)du%6xon$9rc4x?L9%Q8}IQ!gNtN~N;!HwJ(0BMnc6+y6jG z{(sPsO`Un~8`E%AI`_>KJdz_}AYmY3AYmY3AYmY3AYmY3AYmY3AYmY3;QyR~AU%5Q z70)z*|*(y%1o_HMIa2T+jIu z*5P&R2Wov4ySiWS>y}}tSa+4Kr>gI)1*TIs^!( z_=GI5gY3*u$PQ=SSA`+sX)Y0$86uwI67d{E#FJbiE-^$r!6jmbR){msC1Qp~h&DzM zUn70BSgNoyHH(TsOifZKyRUc+V)&tk-SELK>==r=>lv!$)Kq<4^@BWG);2Km8y-f% zI!wz2>lmJD@Mk;i4}0CvBe(g@_1dXwQ2^oKB$lG0QK~v@<~PNV zxS#&(jUf=|naf0=IjJoW@fQo=V+Mwf3(&?a$F3EMc~MZeOLD>AvE5b8#|2PC0e-gN z2et6$MX6X7ffy(xarYXAF92nN??>9G@0bnZ020U2^=V6hp9i;}{m+BrK6(RABbVTm zmEkme8cvzRWN!X2IQF?_ZfM4x{_XUUsjbPk6aPQ)|Cxn6691ojcW7@>9&|DTU(h{XSou~sMke|)oPiU0qo^N@-EpZNcS@&9{;AAUsq{{!hvDmOiI za{A2F`N`#pTjSQ)8>8PI`EK^D;h$uFGxW#w-{FD}@6oKEromv9vx&Q?ccwcHJ5U3C zMG_xlrPN)j9K3AmTp+CSir^9i`utX2PjKgK8E zUJGaX2YixGz|oGmvmUH}z#rukaI}Ap5wLZF0^Z=Pm+rM>rf&sX$GODYD`3_?-Y2=l z+iST@|9C&bCEi|(W%|c^j7z-Cj4bO3F7YxmIjo~x;$>!WxJM{n?pC1ps?hzfKqvnH z!IYKCJux#oePQagNqgd}<8O}raP(IrZ)g9J9Ugu%lOMX6ehn_^|7fnulwXar@m`D$ z_^~*k>qS1HM#uViph|o~jSlniKo$9f8towBfhzC`H5yQe2Wo*&sL^pf9;kUfp+<-F zc%Yu)6KXVk5D(N@KA}bf2eCk{e~LooEm+UMf~Y^wB~k_kMEyA~kutC!>d$hCG#Vg? zr=32-B~k{4QvH)$B4uDF)t}}PDFZX9{uGx;d;UMhEV=K1NJsW&J8Jn{Yn z8ox01_0jK-{B>kDduh0q`QFga(|>}CK1@eby#y-0*<`*2Oew*Jlqxxwdu{*=lM6_B z&vbm%EylC~OkLm-p&1`S{31n2jX{>%_{u^FbV$zo(BZbL>UJQlNU%;LCQY8ZNV}tP zh?~KVwDu;Y_%mY^m14CB4=ChPXS3Xv0sGEsTA-<>iH1+MC3X^L zknK%I(7h8;y+FmkLc|w~#TXZTMH71zVH+Y9U#iN*-7BjkIY_tM2t=)6-GrT#kd>nm zfZXlPiMWXSI%47bJN^FDez4^;^25gnT#WvJ?Ht9s3Y_=&0dD@D442VyE=BB(r? zr&&i4%}`42#ey_QO4|7PqTDCE>+k{}?qALJyeX*yd> zkzW}Ua)lW3lAt^Qd4uX4GSU+FOx4-x{PyQ)uaIS5+vO0sTvf#T)%Fm%kG&dZ4t{HS zP->?UDM^5c)P0*efDg7+_G-U-WC@VpynCLionc70Q~|YD$+;8y?jA5v*PIkgU~K!u z)oaDRA8Cl}F+yr~I7p)VkC8`S9tpygwv<)s19B0+EpB5Tq< zX?eW0rFmzO(sGbABC*15UWE|SrsYbQ3Ovk^*vb@6(u{`=1*t17Qf?6gLPNS^`vJ+K zDCE&~2W?>Nw(LprvW{UU#&yk|@H$Te8x%o)I@N`IbJ*L&=fMPljC0fg4L{IrFx>g< zfC%VnE)OPvPN1zw10mq@Ug&Ml?jksJvF2?GfO2?GfO2?GfO z2?GfO2?GfO2?GfO2?P6JpecSHmUOI;B^_}8I+5ADlUNoY2OQjI019RIy0=5`G2kG) j9e5h7c!e+z+!MrtTiO{mrqfA#0b6nx3Ho;Xwh{jWXc+k{ literal 0 HcmV?d00001 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap new file mode 100644 index 0000000..14937c8 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap @@ -0,0 +1 @@ +./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr new file mode 100644 index 0000000..bc02d12 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr @@ -0,0 +1,682 @@ +# Fri May 10 11:58:58 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.36ns 154 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 11:59:02 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.184 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.700 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +======================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[7] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[7] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[7] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 153 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 11:59:02 2019 + +###########################################################] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..1e1a850b20308c7deb626fa6593c682b7dc66616 GIT binary patch literal 16384 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc +@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 + +0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +====================================================================================================================== + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! 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    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 11:58:54 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : sgmii_ecp5.vhd(30) | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : sgmii_ecp5.vhd(30) | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N:CD630 : sgmii_ecp5.vhd(30) | Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : sgmii_ecp5_softlogic.v(1968) | Synthesizing module sync in library work.
+
+	PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:CG364 : sgmii_ecp5_softlogic.v(1051) | Synthesizing module sgmii_ecp5sll_core in library work.
+
+	PPROTOCOL=24'b010001110100001001000101
+	PLOL_SETTING=32'b00000000000000000000000000000000
+	PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+	PPCIE_MAX_RATE=24'b001100100010111000110101
+	PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+	PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
+	PPCLK_TC=32'b00000000000000010000000000000000
+	PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+	PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+	PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+	LPLL_LOSS_ST=2'b00
+	LPLL_PRELOSS_ST=2'b01
+	LPLL_PRELOCK_ST=2'b10
+	LPLL_LOCK_ST=2'b11
+	LRCLK_TC=16'b1111111111111111
+	LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+	LHB_WAIT_CNT=8'b11111111
+	LPCLK_TC_0=32'b00000000000000001000000000000000
+	LPCLK_TC_1=32'b00000000000000010000000000000000
+	LPCLK_TC_2=32'b00000000000000100000000000000000
+	LPCLK_TC_3=32'b00000000000000101000000000000000
+	LPCLK_TC_4=32'b00000000000000010000000000000000
+	LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+	LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+	LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+	LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+	LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+	LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+	LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+	LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+	LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+	LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+	LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+	LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+	LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+	LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+	LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+	LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+	LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+	LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+	LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N:CG179 : sgmii_ecp5_softlogic.v(1287) | Removing redundant assignment.
+@N:CG179 : sgmii_ecp5_softlogic.v(1293) | Removing redundant assignment.
+@W:CL169 : sgmii_ecp5_softlogic.v(1350) | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : sgmii_ecp5_softlogic.v(92) | Synthesizing module sgmii_ecp5rsl_core in library work.
+
+	pnum_channels=32'b00000000000000000000000000000001
+	pprotocol=24'b010001110100001001000101
+	pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+	pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_tx_rdy=32'b00000000000000000000101110111000
+	pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_rx_rdy=32'b00000000000000000000101110111000
+	wa_num_cycles=32'b00000000000000000000010000000000
+	dac_num_cycles=32'b00000000000000000000000000000011
+	lreset_pwidth=32'b00000000000000000000000000000011
+	lwait_b4_trst=32'b00000000000010111110101111000010
+	lwait_b4_trst_s=32'b00000000000000000000001100001101
+	lplol_cnt_width=32'b00000000000000000000000000010100
+	lwait_after_plol0=32'b00000000000000000000000000000100
+	lwait_b4_rrst=32'b00000000000000101100000000000000
+	lrrst_wait_width=32'b00000000000000000000000000010100
+	lwait_after_rrst=32'b00000000000011000011010100000000
+	lwait_b4_rrst_s=32'b00000000000000000000000111001100
+	lrlol_cnt_width=32'b00000000000000000000000000010011
+	lwait_after_lols=32'b00000000000000001100010000000000
+	lwait_after_lols_s=32'b00000000000000000000000010010110
+	llols_cnt_width=32'b00000000000000000000000000010010
+	lrdb_max=32'b00000000000000000000000000001111
+	ltxr_wait_width=32'b00000000000000000000000000001100
+	lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W:CG133 : sgmii_ecp5_softlogic.v(326) | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(327) | Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(328) | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(341) | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(342) | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(343) | Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(346) | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(347) | Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W:CG360 : sgmii_ecp5_softlogic.v(350) | Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(351) | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(352) | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(353) | Removing wire data_loop_b_tc, as there is no assignment to it.
+@W:CL169 : sgmii_ecp5_softlogic.v(806) | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(567) | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(567) | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W:CL190 : sgmii_ecp5_softlogic.v(694) | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : sgmii_ecp5_softlogic.v(461) | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : sgmii_ecp5_softlogic.v(422) | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL260 : sgmii_ecp5_softlogic.v(422) | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : sgmii_ecp5_softlogic.v(461) | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : sgmii_ecp5_softlogic.v(694) | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL246 : sgmii_ecp5_softlogic.v(200) | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(204) | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(205) | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(206) | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(207) | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL279 : sgmii_ecp5_softlogic.v(1739) | Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL279 : sgmii_ecp5_softlogic.v(1739) | Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL169 : sgmii_ecp5_softlogic.v(1739) | Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(1739) | Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+@N:CL201 : sgmii_ecp5_softlogic.v(1801) | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+
+
    +
    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:57 2019
+
+###########################################################]
+
+
     +
    +
+Pre-mapping Report
+
+
+
     +
    +
+# Fri May 10 11:58:57 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+Linked File: sgmii_ecp5_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N:BN362 : sgmii_ecp5_softlogic.v(1408) | Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1244) | Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1252) | Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1236) | Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1268) | Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:BN115 : sgmii_ecp5_softlogic.v(1260) | Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W:MT529 : sgmii_ecp5_softlogic.v(1988) | Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : sgmii_ecp5_softlogic.v(567) | Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : sgmii_ecp5_softlogic.v(1988) | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:MO225 : sgmii_ecp5_softlogic.v(1801) | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 11:58:58 2019
+
+###########################################################]
+
+
     +
    +
+Map & Optimize Report
+
+
+
     +
    +
+# Fri May 10 11:58:58 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:MO225 : sgmii_ecp5_softlogic.v(1801) | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N:MO231 : sgmii_ecp5_softlogic.v(1350) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(1304) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(1759) | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(412) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(909) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(527) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(778) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:MO231 : sgmii_ecp5_softlogic.v(680) | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     5.36ns		 154 /       221
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:FX1019 : sgmii_ecp5_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+ClockId0001        pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+ClockId0002        rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+ClockId0003        DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W:MT246 : sgmii_ecp5.vhd(162) | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" 
+@W:MT420 :  | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 11:59:02 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.184  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.700
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                         Required          
+Instance                             Reference               Type        Pin     Net                  Time         Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+========================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[7] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]            FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[7]                              Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       153
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 11:59:02 2019
+
+###########################################################]
+
+
     diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm new file mode 100644 index 0000000..50ff329 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/statusReport.html b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..e6db2e2 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/statusReport.html @@ -0,0 +1,115 @@ + + + Project Status Summary Page + + + + + + +
    + + + + + + + + + + +
    Project Settings
    Project Name sgmii_ecp5 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module sgmii_ecp5
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete15770-00m:02s-5/10/19
    11:58 AM
    (premap)Complete9300m:00s0m:00s144MB5/10/19
    11:58 AM
    (fpga_mapper)Complete22400m:03s0m:03s153MB5/10/19
    11:59 AM
    Multi-srs GeneratorComplete5/10/19
    11:58 AM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 221I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 153

    + + + + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    sgmii_ecp5|pll_refclki100.0 MHz168.9 MHz4.079
    sgmii_ecp5|rxrefclk100.0 MHz170.5 MHz4.136
    sgmii_ecp5|tx_pclk_inferred_clock100.0 MHz237.5 MHz5.789
    System100.0 MHz840.7 MHz8.810
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 3 / 0

    +
    +
    + \ No newline at end of file diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/.cckTransfer b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/.cckTransfer new file mode 100644 index 0000000000000000000000000000000000000000..2c37cc7991f84a576cf96c46dcbfb802cf15c04e GIT binary patch literal 457 zcmV;)0XF_0iwFP!0000015#C0RVXORFG)=YSq#94t{2rX;w(zUx3vy=G6l!|=VwxA$i- z=J85+^gjf4xnk_{ON%9uzL7-M7vx|v@wKO8*YdD20b*q&9DzbzRg@> zQit3H z(u0^mjyYslDtJ>NH3`@Qc}uRvj&-bqA#moC^J_k~wC)kdvRTJ~;ntcCPu(k$eX0YO zlyZ?YTzGR`)FxFLvesgNcp?ox>5fWbdG855|L4FVVCoTakUU(vq%_Ge6I;G;0~8)e zyMdx(lwGe{JT>R4g5Ehn7PKe_uA{Z_geQ}YwbgEALY#9UkJ)-YHIZK&8*V$EIyr?3{Z=B zzDym=EZBcMIGD6k96xvXPj4QL-5t7t-Y~YRf!)-CEFL>O0RCFYQvk3$&t;3|x{~)1oK3M42fQBX=uyF?mOk zN!Y8&ZqO|W-!~|@oh9@})EeA6@8D~~)vRe}Y@t6xl_ zH+jpmpu9F+woXbFd#p)m5PF>Jyqj_PZG?iLFBSM<$y_dOh&soXI)W_|+5v+P ziUu3Mv?s3h(}>zkb5^ForpaYcH+@y|tA}?gZukm`$C;wa=Z{?gE7bovzMp-O#WKPJHtp{8BAvb#rqF*bu5;c7`$twF+G~HNCURHNAUaGnGyo_V$ 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a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdep b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdep new file mode 100644 index 0000000..18f4970 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdep @@ -0,0 +1,22 @@ +#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761 +#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557482335 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630 +#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557482333 +#numinternalfiles:6 +#defaultlanguage:verilog +0 "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog +#Dependency Lists(Uses List) +0 -1 +#Dependency Lists(Users Of) +0 -1 +#Design Unit to File Association +module work sgmii_ecp5rsl_core 0 +module work sync 0 +module work sgmii_ecp5sll_core 0 +#Unbound instances to file Association. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr new file mode 100644 index 0000000..37d628b --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr @@ -0,0 +1 @@ +#XMR Information diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info new file mode 100644 index 0000000..defe9c7 --- /dev/null +++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info @@ -0,0 +1,2 @@ +|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;| 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z7Ih*~U!yuu02*^6V`(h2I?)4aW#iGgS+q3VWmX@10N)n>?nV&N_gNt@SmeTTN$`#1 z*+F#0jHSC2{mC{W7SWkvUSqwE43BC8frSjY9nsw}O|i6t>oFchPM|qX$7VSHTzr>x z^c2TWqgAYr^ndVpq_{TFS1*Jeh<_WV_&18E;1*a82l$t2TmChF(3yo3=Ws-#el11& zr#MG|9*R5AyN4e6mJL|GvaZ`8Jv)AItdS_w<(n=aYiG47dDk z&3Ac~aEO=FFvpGGIYAv6xDd7bf2`<1OR*lfwmBOv3+3!c2hv-(XJp%0j>_wdVlfd9qHFPHz0KsLtwyD@UE zS8Mo1#s75tul{cmyyrviJCP5rCca4%T{HUDuKeCun0ssI2|NjF3$W&8U@5%!JhAbxD literal 0 HcmV?d00001 diff --git a/gbe/cores/test_gbepcs/test_gbepcs.sbx b/gbe/cores/test_gbepcs/test_gbepcs.sbx new file mode 100644 index 0000000..63e4629 --- /dev/null +++ b/gbe/cores/test_gbepcs/test_gbepcs.sbx @@ -0,0 +1,2171 @@ + + + + LATTICE + LOCAL + test_gbepcs + 1.0 + + + Diamond_Synthesis + synthesis + + ./test_gbepcs.vhd + vhdlSource + + + + Diamond_Simulation + simulation + + ./test_gbepcs.vhd + vhdlSource + + + + + + + + + sgmii_ecp5_ctc_del_s + sgmii_ecp5_ctc_del_s + + out + + + + sgmii_ecp5.ctc_del_s + + + + + sgmii_ecp5_ctc_ins_s + sgmii_ecp5_ctc_ins_s + + out + + + + sgmii_ecp5.ctc_ins_s + + + + + sgmii_ecp5_ctc_orun_s + sgmii_ecp5_ctc_orun_s + + out + + + + sgmii_ecp5.ctc_orun_s + + + + + sgmii_ecp5_ctc_urun_s + sgmii_ecp5_ctc_urun_s + + out + + + + sgmii_ecp5.ctc_urun_s + + + + + sgmii_ecp5_cyawstn + sgmii_ecp5_cyawstn + + in + + + + sgmii_ecp5.cyawstn + + + + + sgmii_ecp5_hdinn + sgmii_ecp5_hdinn + + in + + + + sgmii_ecp5.hdinn + + + + + sgmii_ecp5_hdinp + sgmii_ecp5_hdinp + + in + + + + sgmii_ecp5.hdinp + + + + + sgmii_ecp5_hdoutn + sgmii_ecp5_hdoutn + + out + + + + sgmii_ecp5.hdoutn + + + + + sgmii_ecp5_hdoutp + sgmii_ecp5_hdoutp + + out + + + + sgmii_ecp5.hdoutp + + + + + sgmii_ecp5_lsm_status_s + sgmii_ecp5_lsm_status_s + + out + + + + sgmii_ecp5.lsm_status_s + + + + + sgmii_ecp5_pll_lol + sgmii_ecp5_pll_lol + + out + + + + sgmii_ecp5.pll_lol + + + + + sgmii_ecp5_pll_refclki + sgmii_ecp5_pll_refclki + + in + + + + sgmii_ecp5.pll_refclki + + + + + sgmii_ecp5_rsl_disable + sgmii_ecp5_rsl_disable + + in + + + + sgmii_ecp5.rsl_disable + + + + + sgmii_ecp5_rsl_rst + sgmii_ecp5_rsl_rst + + in + + + + sgmii_ecp5.rsl_rst + + + + + sgmii_ecp5_rsl_rx_rdy + sgmii_ecp5_rsl_rx_rdy + + out + + + + sgmii_ecp5.rsl_rx_rdy + + + + + sgmii_ecp5_rsl_tx_rdy + sgmii_ecp5_rsl_tx_rdy + + out + + + + sgmii_ecp5.rsl_tx_rdy + + + + + sgmii_ecp5_rst_dual_c + sgmii_ecp5_rst_dual_c + + in + + + + sgmii_ecp5.rst_dual_c + + + + + sgmii_ecp5_rx_cdr_lol_s + sgmii_ecp5_rx_cdr_lol_s + + out + + + + sgmii_ecp5.rx_cdr_lol_s + + + + + sgmii_ecp5_rx_los_low_s + sgmii_ecp5_rx_los_low_s + + out + + + + sgmii_ecp5.rx_los_low_s + + + + + sgmii_ecp5_rx_pcs_rst_c + sgmii_ecp5_rx_pcs_rst_c + + in + + + + sgmii_ecp5.rx_pcs_rst_c + + + + + sgmii_ecp5_rx_pwrup_c + sgmii_ecp5_rx_pwrup_c + + in + + + + sgmii_ecp5.rx_pwrup_c + + + + + sgmii_ecp5_rx_serdes_rst_c + sgmii_ecp5_rx_serdes_rst_c + + in + + + + sgmii_ecp5.rx_serdes_rst_c + + + + + sgmii_ecp5_rxrefclk + sgmii_ecp5_rxrefclk + + in + + + + sgmii_ecp5.rxrefclk + + + + + sgmii_ecp5_sci_en + sgmii_ecp5_sci_en + + in + + + + sgmii_ecp5.sci_en + + + + + sgmii_ecp5_sci_en_dual + sgmii_ecp5_sci_en_dual + + in + + + + sgmii_ecp5.sci_en_dual + + + + + sgmii_ecp5_sci_int + sgmii_ecp5_sci_int + + out + + + + sgmii_ecp5.sci_int + + + + + sgmii_ecp5_sci_rd + sgmii_ecp5_sci_rd + + in + + + + sgmii_ecp5.sci_rd + + + + + sgmii_ecp5_sci_sel + sgmii_ecp5_sci_sel + + in + + + + sgmii_ecp5.sci_sel + + + + + sgmii_ecp5_sci_sel_dual + sgmii_ecp5_sci_sel_dual + + in + + + + sgmii_ecp5.sci_sel_dual + + + + + sgmii_ecp5_sci_wrn + sgmii_ecp5_sci_wrn + + in + + + + sgmii_ecp5.sci_wrn + + + + + sgmii_ecp5_serdes_pdb + sgmii_ecp5_serdes_pdb + + in + + + + sgmii_ecp5.serdes_pdb + + + + + sgmii_ecp5_serdes_rst_dual_c + sgmii_ecp5_serdes_rst_dual_c + + in + + + + sgmii_ecp5.serdes_rst_dual_c + + + + + sgmii_ecp5_signal_detect_c + sgmii_ecp5_signal_detect_c + + in + + + + sgmii_ecp5.signal_detect_c + + + + + sgmii_ecp5_tx_pclk + sgmii_ecp5_tx_pclk + + out + + + + sgmii_ecp5.tx_pclk + + + + + sgmii_ecp5_tx_pcs_rst_c + sgmii_ecp5_tx_pcs_rst_c + + in + + + + sgmii_ecp5.tx_pcs_rst_c + + + + + sgmii_ecp5_tx_pwrup_c + sgmii_ecp5_tx_pwrup_c + + in + + + + sgmii_ecp5.tx_pwrup_c + + + + + sgmii_ecp5_tx_serdes_rst_c + sgmii_ecp5_tx_serdes_rst_c + + in + + + + sgmii_ecp5.tx_serdes_rst_c + + + + + sgmii_ecp5_txi_clk + sgmii_ecp5_txi_clk + + in + + + + sgmii_ecp5.txi_clk + + + + + sgmii_ecp5_rx_cv_err + sgmii_ecp5_rx_cv_err + + out + + 0 + 0 + + + + + sgmii_ecp5.rx_cv_err + + + + + sgmii_ecp5_rx_disp_err + sgmii_ecp5_rx_disp_err + + out + + 0 + 0 + + + + + sgmii_ecp5.rx_disp_err + + + + + sgmii_ecp5_rx_k + sgmii_ecp5_rx_k + + out + + 0 + 0 + + + + + sgmii_ecp5.rx_k + + + + + sgmii_ecp5_rxdata + sgmii_ecp5_rxdata + + out + + 7 + 0 + + + + + sgmii_ecp5.rxdata + + + + + sgmii_ecp5_sci_addr + sgmii_ecp5_sci_addr + + in + + 5 + 0 + + + + + sgmii_ecp5.sci_addr + + + + + sgmii_ecp5_sci_rddata + sgmii_ecp5_sci_rddata + + out + + 7 + 0 + + + + + sgmii_ecp5.sci_rddata + + + + + sgmii_ecp5_sci_wrdata + sgmii_ecp5_sci_wrdata + + in + + 7 + 0 + + + + + sgmii_ecp5.sci_wrdata + + + + + sgmii_ecp5_tx_disp_correct + sgmii_ecp5_tx_disp_correct + + in + + 0 + 0 + + + + + sgmii_ecp5.tx_disp_correct + + + + + sgmii_ecp5_tx_k + sgmii_ecp5_tx_k + + in + + 0 + 0 + + + + + sgmii_ecp5.tx_k + + + + + sgmii_ecp5_txdata + sgmii_ecp5_txdata + + in + + 7 + 0 + + + + + sgmii_ecp5.txdata + + + + + sgmii_ecp5_xmit + sgmii_ecp5_xmit + + in + + 0 + 0 + + + + + sgmii_ecp5.xmit + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-05-10.11:53:39 AM + 2019-05-10.11:59:27 AM + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + test_gbepcs + 1.0 + + + sgmii_ecp5 + + Lattice Semiconductor Corporation + LEGACY + PCS + 8.2 + + + Diamond_Simulation + simulation + + ./sgmii_ecp5/sgmii_ecp5_softlogic.v + verilogSource + + + ./sgmii_ecp5/sgmii_ecp5.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./sgmii_ecp5/sgmii_ecp5_softlogic.v + verilogSource + + + ./sgmii_ecp5/sgmii_ecp5.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + ctc_del_s + ctc_del_s + + out + + + + ctc_ins_s + ctc_ins_s + + out + + + + ctc_orun_s + ctc_orun_s + + out + + + + ctc_urun_s + ctc_urun_s + + out + + + + cyawstn + cyawstn + + in + + + + hdinn + hdinn + + in + + + + true + + + + + hdinp + hdinp + + in + + + + true + + + + + hdoutn + hdoutn + + out + + + + true + + + + + hdoutp + hdoutp + + out + + + + true + + + + + lsm_status_s + lsm_status_s + + out + + + + pll_lol + pll_lol + + out + + + + pll_refclki + pll_refclki + + in + + + + rsl_disable + rsl_disable + + in + + + + rsl_rst + rsl_rst + + in + + + + rsl_rx_rdy + rsl_rx_rdy + + out + + + + rsl_tx_rdy + rsl_tx_rdy + + out + + + + rst_dual_c + rst_dual_c + + in + + + + rx_cdr_lol_s + rx_cdr_lol_s + + out + + + + rx_los_low_s + rx_los_low_s + + out + + + + rx_pcs_rst_c + rx_pcs_rst_c + + in + + + + rx_pwrup_c + rx_pwrup_c + + in + + + + rx_serdes_rst_c + rx_serdes_rst_c + + in + + + + rxrefclk + rxrefclk + + in + + + + sci_en + sci_en + + in + + + + sci_en_dual + sci_en_dual + + in + + + + sci_int + sci_int + + out + + + + sci_rd + sci_rd + + in + + + + sci_sel + sci_sel + + in + + + + sci_sel_dual + sci_sel_dual + + in + + + + sci_wrn + sci_wrn + + in + + + + serdes_pdb + serdes_pdb + + in + + + + serdes_rst_dual_c + serdes_rst_dual_c + + in + + + + signal_detect_c + signal_detect_c + + in + + + + sli_rst + sli_rst + + in + + + + true + + + + + tx_pclk + tx_pclk + + out + + + + tx_pcs_rst_c + tx_pcs_rst_c + + in + + + + tx_pwrup_c + tx_pwrup_c + + in + + + + tx_serdes_rst_c + tx_serdes_rst_c + + in + + + + txi_clk + txi_clk + + in + + + + rx_cv_err + rx_cv_err + + out + + 0 + 0 + + + + + rx_disp_err + rx_disp_err + + out + + 0 + 0 + + + + + rx_k + rx_k + + out + + 0 + 0 + + + + + rxdata + rxdata + + out + + 7 + 0 + + + + + sci_addr + sci_addr + + in + + 5 + 0 + + + + + sci_rddata + sci_rddata + + out + + 7 + 0 + + + + + sci_wrdata + sci_wrdata + + in + + 7 + 0 + + + + + tx_disp_correct + tx_disp_correct + + in + + 0 + 0 + + + + + tx_k + tx_k + + in + + 0 + 0 + + + + + txdata + txdata + + in + + 7 + 0 + + + + + xmit + xmit + + in + + 0 + 0 + + + + + + + synplify + 2019-05-10.11:59:27 AM + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + Lane0 + DCUCHANNEL + + true + false + DCUCHANNEL + 9 + + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PCS + + + CoreRevision + 8.2 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/10/2019 + + + ModuleName + sgmii_ecp5 + + + ParameterFileVersion + 1.0 + + + SourceFormat + VHDL + + + Time + 11:58:52 + + + VendorName + Lattice Semiconductor Corporation + + + + ;ACHARA + 0 00H + + + ;ACHARB + 0 00H + + + ;ACHARM + 0 00H + + + ;RXMCAENABLE + Disabled + + + CDRLOLACTION + Full Recalibration + + + CDRLOLRANGE + 0 + + + CDR_MAX_RATE + 2 + + + CDR_MULT + 10X + + + CDR_REF_RATE + 200.0000 + + + CH_MODE + Rx and Tx + + + Destination + Synplicity + + + EDIF + 1 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + IO_TYPE + GbE + + + LEQ + 0 + + + LOOPBACK + Disabled + + + LOSPORT + Enabled + + + NUM_CHS + 1 + + + Order + Big Endian [MSB:LSB] + + + PPORT_RX_RDY + Enabled + + + PPORT_TX_RDY + Enabled + + + PROTOCOL + GbE + + + PWAIT_RX_RDY + 3000 + + + PWAIT_TX_RDY + 3000 + + + RCSRC + Disabled + + + REFCLK_RATE + 200.0000 + + + RSTSEQSEL + Enabled + + + RX8B10B + Enabled + + + RXCOMMAA + 1010000011 + + + RXCOMMAB + 0101111100 + + + RXCOMMAM + 1111111111 + + + RXCOUPLING + AC + + + RXCTC + Enabled + + + RXCTCBYTEN + 0 00H + + + RXCTCBYTEN1 + 0 00H + + + RXCTCBYTEN2 + 1 BCH + + + RXCTCBYTEN3 + 0 50H + + + RXCTCMATCHPATTERN + M2-S2 + + + RXDIFFTERM + 50 ohms + + + RXFIFO_ENABLE + Enabled + + + RXINVPOL + Non-invert + + + RXLDR + Off + + + RXLOSTHRESHOLD + 2 + + + RXLSM + Enabled + + + RXSC + K28P5 + + + RXWA + Barrel Shift + + + RX_DATA_WIDTH + 8/10-Bit + + + RX_FICLK_RATE + 200.0000 + + + RX_LINE_RATE + 2.0000 + + + RX_RATE_DIV + Full Rate + + + SCIPORT + Enabled + + + SOFTLOL + Enabled + + + TX8B10B + Enabled + + + TXAMPLITUDE + 1100 + + + TXDEPOST + Disabled + + + TXDEPRE + Disabled + + + TXDIFFTERM + 50 ohms + + + TXFIFO_ENABLE + Enabled + + + TXINVPOL + Non-invert + + + TXLDR + Off + + + TXPLLLOLTHRESHOLD + 0 + + + TXPLLMULT + 10X + + + TX_DATA_WIDTH + 8/10-Bit + + + TX_FICLK_RATE + 200.0000 + + + TX_LINE_RATE + 2.0000 + + + TX_MAX_RATE + 2 + + + TX_RATE_DIV + Full Rate + + + VHDL + 1 + + + Verilog + 0 + + + + sgmii_ecp5.pp + pp + + + sgmii_ecp5.sym + sym + + + sgmii_ecp5.tft + tft + + + sgmii_ecp5.txt + pcs_module + + + + + DCUCHANNEL + 1 + + true + false + DCUCHANNEL + + Lane0 + + + + + + + + + sgmii_ecp5_ctc_del_s + sgmii_ecp5_ctc_del_s + + + + + sgmii_ecp5_ctc_ins_s + sgmii_ecp5_ctc_ins_s + + + + + sgmii_ecp5_ctc_orun_s + sgmii_ecp5_ctc_orun_s + + + + + sgmii_ecp5_ctc_urun_s + sgmii_ecp5_ctc_urun_s + + + + + sgmii_ecp5_cyawstn + sgmii_ecp5_cyawstn + + + + + sgmii_ecp5_hdinn + sgmii_ecp5_hdinn + + + sys_yes + + + + + + + sgmii_ecp5_hdinp + sgmii_ecp5_hdinp + + + sys_yes + + + + + + + sgmii_ecp5_hdoutn + sgmii_ecp5_hdoutn + + + sys_yes + + + + + + + sgmii_ecp5_hdoutp + sgmii_ecp5_hdoutp + + + sys_yes + + + + + + + sgmii_ecp5_lsm_status_s + sgmii_ecp5_lsm_status_s + + + + + sgmii_ecp5_pll_lol + sgmii_ecp5_pll_lol + + + + + sgmii_ecp5_pll_refclki + sgmii_ecp5_pll_refclki + + + + + sgmii_ecp5_rsl_disable + sgmii_ecp5_rsl_disable + + + + + sgmii_ecp5_rsl_rst + sgmii_ecp5_rsl_rst + + + + + sgmii_ecp5_rsl_rx_rdy + sgmii_ecp5_rsl_rx_rdy + + + + + sgmii_ecp5_rsl_tx_rdy + sgmii_ecp5_rsl_tx_rdy + + + + + sgmii_ecp5_rst_dual_c + sgmii_ecp5_rst_dual_c + + + + + sgmii_ecp5_rx_cdr_lol_s + sgmii_ecp5_rx_cdr_lol_s + + + + + sgmii_ecp5_rx_los_low_s + sgmii_ecp5_rx_los_low_s + + + + + sgmii_ecp5_rx_pcs_rst_c + sgmii_ecp5_rx_pcs_rst_c + + + + + sgmii_ecp5_rx_pwrup_c + sgmii_ecp5_rx_pwrup_c + + + + + sgmii_ecp5_rx_serdes_rst_c + sgmii_ecp5_rx_serdes_rst_c + + + + + sgmii_ecp5_rxrefclk + sgmii_ecp5_rxrefclk + + + + + sgmii_ecp5_sci_en + sgmii_ecp5_sci_en + + + + + sgmii_ecp5_sci_en_dual + sgmii_ecp5_sci_en_dual + + + + + sgmii_ecp5_sci_int + sgmii_ecp5_sci_int + + + + + sgmii_ecp5_sci_rd + sgmii_ecp5_sci_rd + + + + + sgmii_ecp5_sci_sel + sgmii_ecp5_sci_sel + + + + + sgmii_ecp5_sci_sel_dual + sgmii_ecp5_sci_sel_dual + + + + + sgmii_ecp5_sci_wrn + sgmii_ecp5_sci_wrn + + + + + sgmii_ecp5_serdes_pdb + sgmii_ecp5_serdes_pdb + + + + + sgmii_ecp5_serdes_rst_dual_c + sgmii_ecp5_serdes_rst_dual_c + + + + + sgmii_ecp5_signal_detect_c + sgmii_ecp5_signal_detect_c + + + + + sgmii_ecp5_tx_pclk + sgmii_ecp5_tx_pclk + + + + + sgmii_ecp5_tx_pcs_rst_c + sgmii_ecp5_tx_pcs_rst_c + + + + + sgmii_ecp5_tx_pwrup_c + sgmii_ecp5_tx_pwrup_c + + + + + sgmii_ecp5_tx_serdes_rst_c + sgmii_ecp5_tx_serdes_rst_c + + + + + sgmii_ecp5_txi_clk + sgmii_ecp5_txi_clk + + + + + sgmii_ecp5_rx_cv_err + sgmii_ecp5_rx_cv_err + + + + + sgmii_ecp5_rx_cv_err[0] + sgmii_ecp5_rx_cv_err[0] + + + + + sgmii_ecp5_rx_disp_err + sgmii_ecp5_rx_disp_err + + + + + sgmii_ecp5_rx_disp_err[0] + sgmii_ecp5_rx_disp_err[0] + + + + + sgmii_ecp5_rx_k + sgmii_ecp5_rx_k + + + + + sgmii_ecp5_rx_k[0] + sgmii_ecp5_rx_k[0] + + + + + sgmii_ecp5_rxdata + sgmii_ecp5_rxdata + + + + + sgmii_ecp5_rxdata[0] + sgmii_ecp5_rxdata[0] + + + + + sgmii_ecp5_rxdata[1] + sgmii_ecp5_rxdata[1] + + + + + sgmii_ecp5_rxdata[2] + sgmii_ecp5_rxdata[2] + + + + + sgmii_ecp5_rxdata[3] + sgmii_ecp5_rxdata[3] + + + + + sgmii_ecp5_rxdata[4] + sgmii_ecp5_rxdata[4] + + + + + sgmii_ecp5_rxdata[5] + sgmii_ecp5_rxdata[5] + + + + + sgmii_ecp5_rxdata[6] + sgmii_ecp5_rxdata[6] + + + + + sgmii_ecp5_rxdata[7] + sgmii_ecp5_rxdata[7] + + + + + sgmii_ecp5_sci_addr + sgmii_ecp5_sci_addr + + + + + sgmii_ecp5_sci_addr[0] + sgmii_ecp5_sci_addr[0] + + + + + sgmii_ecp5_sci_addr[1] + sgmii_ecp5_sci_addr[1] + + + + + sgmii_ecp5_sci_addr[2] + sgmii_ecp5_sci_addr[2] + + + + + sgmii_ecp5_sci_addr[3] + sgmii_ecp5_sci_addr[3] + + + + + sgmii_ecp5_sci_addr[4] + sgmii_ecp5_sci_addr[4] + + + + + sgmii_ecp5_sci_addr[5] + sgmii_ecp5_sci_addr[5] + + + + + sgmii_ecp5_sci_rddata + sgmii_ecp5_sci_rddata + + + + + sgmii_ecp5_sci_rddata[0] + sgmii_ecp5_sci_rddata[0] + + + + + sgmii_ecp5_sci_rddata[1] + sgmii_ecp5_sci_rddata[1] + + + + + sgmii_ecp5_sci_rddata[2] + sgmii_ecp5_sci_rddata[2] + + + + + sgmii_ecp5_sci_rddata[3] + sgmii_ecp5_sci_rddata[3] + + + + + sgmii_ecp5_sci_rddata[4] + sgmii_ecp5_sci_rddata[4] + + + + + sgmii_ecp5_sci_rddata[5] + sgmii_ecp5_sci_rddata[5] + + + + + sgmii_ecp5_sci_rddata[6] + sgmii_ecp5_sci_rddata[6] + + + + + sgmii_ecp5_sci_rddata[7] + sgmii_ecp5_sci_rddata[7] + + + + + sgmii_ecp5_sci_wrdata + sgmii_ecp5_sci_wrdata + + + + + sgmii_ecp5_sci_wrdata[0] + sgmii_ecp5_sci_wrdata[0] + + + + + sgmii_ecp5_sci_wrdata[1] + sgmii_ecp5_sci_wrdata[1] + + + + + sgmii_ecp5_sci_wrdata[2] + sgmii_ecp5_sci_wrdata[2] + + + + + sgmii_ecp5_sci_wrdata[3] + sgmii_ecp5_sci_wrdata[3] + + + + + sgmii_ecp5_sci_wrdata[4] + sgmii_ecp5_sci_wrdata[4] + + + + + sgmii_ecp5_sci_wrdata[5] + sgmii_ecp5_sci_wrdata[5] + + + + + sgmii_ecp5_sci_wrdata[6] + sgmii_ecp5_sci_wrdata[6] + + + + + sgmii_ecp5_sci_wrdata[7] + sgmii_ecp5_sci_wrdata[7] + + + + + sgmii_ecp5_tx_disp_correct + sgmii_ecp5_tx_disp_correct + + + + + sgmii_ecp5_tx_disp_correct[0] + sgmii_ecp5_tx_disp_correct[0] + + + + + sgmii_ecp5_tx_k + sgmii_ecp5_tx_k + + + + + sgmii_ecp5_tx_k[0] + sgmii_ecp5_tx_k[0] + + + + + sgmii_ecp5_txdata + sgmii_ecp5_txdata + + + + + sgmii_ecp5_txdata[0] + sgmii_ecp5_txdata[0] + + + + + sgmii_ecp5_txdata[1] + sgmii_ecp5_txdata[1] + + + + + sgmii_ecp5_txdata[2] + sgmii_ecp5_txdata[2] + + + + + sgmii_ecp5_txdata[3] + sgmii_ecp5_txdata[3] + + + + + sgmii_ecp5_txdata[4] + sgmii_ecp5_txdata[4] + + + + + sgmii_ecp5_txdata[5] + sgmii_ecp5_txdata[5] + + + + + sgmii_ecp5_txdata[6] + sgmii_ecp5_txdata[6] + + + + + sgmii_ecp5_txdata[7] + sgmii_ecp5_txdata[7] + + + + + sgmii_ecp5_xmit + sgmii_ecp5_xmit + + + + + sgmii_ecp5_xmit[0] + sgmii_ecp5_xmit[0] + + + + + + diff --git a/gbe/cores/test_gbepcs/test_gbepcs.vhd b/gbe/cores/test_gbepcs/test_gbepcs.vhd new file mode 100644 index 0000000..6f75c97 --- /dev/null +++ b/gbe/cores/test_gbepcs/test_gbepcs.vhd @@ -0,0 +1,167 @@ + + +-- +-- Verific VHDL Description of module test_gbepcs +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity test_gbepcs is + port (sgmii_ecp5_rx_cv_err: out std_logic_vector(0 downto 0); + sgmii_ecp5_rx_disp_err: out std_logic_vector(0 downto 0); + sgmii_ecp5_rx_k: out std_logic_vector(0 downto 0); + sgmii_ecp5_rxdata: out std_logic_vector(7 downto 0); + sgmii_ecp5_sci_addr: in std_logic_vector(5 downto 0); + sgmii_ecp5_sci_rddata: out std_logic_vector(7 downto 0); + sgmii_ecp5_sci_wrdata: in std_logic_vector(7 downto 0); + sgmii_ecp5_tx_disp_correct: in std_logic_vector(0 downto 0); + sgmii_ecp5_tx_k: in std_logic_vector(0 downto 0); + sgmii_ecp5_txdata: in std_logic_vector(7 downto 0); + sgmii_ecp5_xmit: in std_logic_vector(0 downto 0); + sgmii_ecp5_ctc_del_s: out std_logic; + sgmii_ecp5_ctc_ins_s: out std_logic; + sgmii_ecp5_ctc_orun_s: out std_logic; + sgmii_ecp5_ctc_urun_s: out std_logic; + sgmii_ecp5_cyawstn: in std_logic; + sgmii_ecp5_hdinn: in std_logic; + sgmii_ecp5_hdinp: in std_logic; + sgmii_ecp5_hdoutn: out std_logic; + sgmii_ecp5_hdoutp: out std_logic; + sgmii_ecp5_lsm_status_s: out std_logic; + sgmii_ecp5_pll_lol: out std_logic; + sgmii_ecp5_pll_refclki: in std_logic; + sgmii_ecp5_rsl_disable: in std_logic; + sgmii_ecp5_rsl_rst: in std_logic; + sgmii_ecp5_rsl_rx_rdy: out std_logic; + sgmii_ecp5_rsl_tx_rdy: out std_logic; + sgmii_ecp5_rst_dual_c: in std_logic; + sgmii_ecp5_rx_cdr_lol_s: out std_logic; + sgmii_ecp5_rx_los_low_s: out std_logic; + sgmii_ecp5_rx_pcs_rst_c: in std_logic; + sgmii_ecp5_rx_pwrup_c: in std_logic; + sgmii_ecp5_rx_serdes_rst_c: in std_logic; + sgmii_ecp5_rxrefclk: in std_logic; + sgmii_ecp5_sci_en: in std_logic; + sgmii_ecp5_sci_en_dual: in std_logic; + sgmii_ecp5_sci_int: out std_logic; + sgmii_ecp5_sci_rd: in std_logic; + sgmii_ecp5_sci_sel: in std_logic; + sgmii_ecp5_sci_sel_dual: in std_logic; + sgmii_ecp5_sci_wrn: in std_logic; + sgmii_ecp5_serdes_pdb: in std_logic; + sgmii_ecp5_serdes_rst_dual_c: in std_logic; + sgmii_ecp5_signal_detect_c: in std_logic; + sgmii_ecp5_tx_pclk: out std_logic; + sgmii_ecp5_tx_pcs_rst_c: in std_logic; + sgmii_ecp5_tx_pwrup_c: in std_logic; + sgmii_ecp5_tx_serdes_rst_c: in std_logic; + sgmii_ecp5_txi_clk: in std_logic + ); + +end entity test_gbepcs; -- sbp_module=true + +architecture test_gbepcs of test_gbepcs is + component sgmii_ecp5 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + xmit: in std_logic_vector(0 downto 0); + ctc_del_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_orun_s: out std_logic; + ctc_urun_s: out std_logic; + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + sli_rst: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic; + txi_clk: in std_logic + ); + + end component sgmii_ecp5; -- not_need_bbox=true + + + signal sli_rst_wire0,gnd : std_logic; +begin + sli_rst_wire0 <= sgmii_ecp5_serdes_rst_dual_c OR sgmii_ecp5_tx_serdes_rst_c OR (NOT sgmii_ecp5_serdes_pdb) OR (NOT sgmii_ecp5_tx_pwrup_c); + sgmii_ecp5_inst: component sgmii_ecp5 port map (rx_cv_err(0)=>sgmii_ecp5_rx_cv_err(0), + rx_disp_err(0)=>sgmii_ecp5_rx_disp_err(0),rx_k(0)=>sgmii_ecp5_rx_k(0), + rxdata(7)=>sgmii_ecp5_rxdata(7),rxdata(6)=>sgmii_ecp5_rxdata(6), + rxdata(5)=>sgmii_ecp5_rxdata(5),rxdata(4)=>sgmii_ecp5_rxdata(4), + rxdata(3)=>sgmii_ecp5_rxdata(3),rxdata(2)=>sgmii_ecp5_rxdata(2), + rxdata(1)=>sgmii_ecp5_rxdata(1),rxdata(0)=>sgmii_ecp5_rxdata(0), + sci_addr(5)=>sgmii_ecp5_sci_addr(5),sci_addr(4)=>sgmii_ecp5_sci_addr(4), + sci_addr(3)=>sgmii_ecp5_sci_addr(3),sci_addr(2)=>sgmii_ecp5_sci_addr(2), + sci_addr(1)=>sgmii_ecp5_sci_addr(1),sci_addr(0)=>sgmii_ecp5_sci_addr(0), + sci_rddata(7)=>sgmii_ecp5_sci_rddata(7),sci_rddata(6)=>sgmii_ecp5_sci_rddata(6), + sci_rddata(5)=>sgmii_ecp5_sci_rddata(5),sci_rddata(4)=>sgmii_ecp5_sci_rddata(4), + sci_rddata(3)=>sgmii_ecp5_sci_rddata(3),sci_rddata(2)=>sgmii_ecp5_sci_rddata(2), + sci_rddata(1)=>sgmii_ecp5_sci_rddata(1),sci_rddata(0)=>sgmii_ecp5_sci_rddata(0), + sci_wrdata(7)=>sgmii_ecp5_sci_wrdata(7),sci_wrdata(6)=>sgmii_ecp5_sci_wrdata(6), + sci_wrdata(5)=>sgmii_ecp5_sci_wrdata(5),sci_wrdata(4)=>sgmii_ecp5_sci_wrdata(4), + sci_wrdata(3)=>sgmii_ecp5_sci_wrdata(3),sci_wrdata(2)=>sgmii_ecp5_sci_wrdata(2), + sci_wrdata(1)=>sgmii_ecp5_sci_wrdata(1),sci_wrdata(0)=>sgmii_ecp5_sci_wrdata(0), + tx_disp_correct(0)=>sgmii_ecp5_tx_disp_correct(0),tx_k(0)=>sgmii_ecp5_tx_k(0), + txdata(7)=>sgmii_ecp5_txdata(7),txdata(6)=>sgmii_ecp5_txdata(6), + txdata(5)=>sgmii_ecp5_txdata(5),txdata(4)=>sgmii_ecp5_txdata(4), + txdata(3)=>sgmii_ecp5_txdata(3),txdata(2)=>sgmii_ecp5_txdata(2), + txdata(1)=>sgmii_ecp5_txdata(1),txdata(0)=>sgmii_ecp5_txdata(0), + xmit(0)=>sgmii_ecp5_xmit(0),ctc_del_s=>sgmii_ecp5_ctc_del_s,ctc_ins_s=>sgmii_ecp5_ctc_ins_s, + ctc_orun_s=>sgmii_ecp5_ctc_orun_s,ctc_urun_s=>sgmii_ecp5_ctc_urun_s, + cyawstn=>sgmii_ecp5_cyawstn,hdinn=>sgmii_ecp5_hdinn,hdinp=>sgmii_ecp5_hdinp, + hdoutn=>sgmii_ecp5_hdoutn,hdoutp=>sgmii_ecp5_hdoutp,lsm_status_s=>sgmii_ecp5_lsm_status_s, + pll_lol=>sgmii_ecp5_pll_lol,pll_refclki=>sgmii_ecp5_pll_refclki, + rsl_disable=>sgmii_ecp5_rsl_disable,rsl_rst=>sgmii_ecp5_rsl_rst, + rsl_rx_rdy=>sgmii_ecp5_rsl_rx_rdy,rsl_tx_rdy=>sgmii_ecp5_rsl_tx_rdy, + rst_dual_c=>sgmii_ecp5_rst_dual_c,rx_cdr_lol_s=>sgmii_ecp5_rx_cdr_lol_s, + rx_los_low_s=>sgmii_ecp5_rx_los_low_s,rx_pcs_rst_c=>sgmii_ecp5_rx_pcs_rst_c, + rx_pwrup_c=>sgmii_ecp5_rx_pwrup_c,rx_serdes_rst_c=>sgmii_ecp5_rx_serdes_rst_c, + rxrefclk=>sgmii_ecp5_rxrefclk,sci_en=>sgmii_ecp5_sci_en,sci_en_dual=>sgmii_ecp5_sci_en_dual, + sci_int=>sgmii_ecp5_sci_int,sci_rd=>sgmii_ecp5_sci_rd,sci_sel=>sgmii_ecp5_sci_sel, + sci_sel_dual=>sgmii_ecp5_sci_sel_dual,sci_wrn=>sgmii_ecp5_sci_wrn, + serdes_pdb=>sgmii_ecp5_serdes_pdb,serdes_rst_dual_c=>sgmii_ecp5_serdes_rst_dual_c, + signal_detect_c=>sgmii_ecp5_signal_detect_c,sli_rst=>sli_rst_wire0, + tx_pclk=>sgmii_ecp5_tx_pclk,tx_pcs_rst_c=>sgmii_ecp5_tx_pcs_rst_c, + tx_pwrup_c=>sgmii_ecp5_tx_pwrup_c,tx_serdes_rst_c=>sgmii_ecp5_tx_serdes_rst_c, + txi_clk=>sgmii_ecp5_txi_clk); + gnd <= '0' ; + +end architecture test_gbepcs; -- sbp_module=true + diff --git a/gbe/cores/test_gbepcs/test_gbepcs_tmpl.v b/gbe/cores/test_gbepcs/test_gbepcs_tmpl.v new file mode 100644 index 0000000..89088e9 --- /dev/null +++ b/gbe/cores/test_gbepcs/test_gbepcs_tmpl.v @@ -0,0 +1,19 @@ +//Verilog instantiation template + +test_gbepcs _inst (.sgmii_ecp5_rx_cv_err(), .sgmii_ecp5_rx_disp_err(), .sgmii_ecp5_rx_k(), + .sgmii_ecp5_rxdata(), .sgmii_ecp5_sci_addr(), .sgmii_ecp5_sci_rddata(), + .sgmii_ecp5_sci_wrdata(), .sgmii_ecp5_tx_disp_correct(), .sgmii_ecp5_tx_k(), + .sgmii_ecp5_txdata(), .sgmii_ecp5_xmit(), .sgmii_ecp5_ctc_del_s(), + .sgmii_ecp5_ctc_ins_s(), .sgmii_ecp5_ctc_orun_s(), .sgmii_ecp5_ctc_urun_s(), + .sgmii_ecp5_cyawstn(), .sgmii_ecp5_hdinn(), .sgmii_ecp5_hdinp(), + .sgmii_ecp5_hdoutn(), .sgmii_ecp5_hdoutp(), .sgmii_ecp5_lsm_status_s(), + .sgmii_ecp5_pll_lol(), .sgmii_ecp5_pll_refclki(), .sgmii_ecp5_rsl_disable(), + .sgmii_ecp5_rsl_rst(), .sgmii_ecp5_rsl_rx_rdy(), .sgmii_ecp5_rsl_tx_rdy(), + .sgmii_ecp5_rst_dual_c(), .sgmii_ecp5_rx_cdr_lol_s(), .sgmii_ecp5_rx_los_low_s(), + .sgmii_ecp5_rx_pcs_rst_c(), .sgmii_ecp5_rx_pwrup_c(), .sgmii_ecp5_rx_serdes_rst_c(), + .sgmii_ecp5_rxrefclk(), .sgmii_ecp5_sci_en(), .sgmii_ecp5_sci_en_dual(), + .sgmii_ecp5_sci_int(), .sgmii_ecp5_sci_rd(), .sgmii_ecp5_sci_sel(), + .sgmii_ecp5_sci_sel_dual(), .sgmii_ecp5_sci_wrn(), .sgmii_ecp5_serdes_pdb(), + .sgmii_ecp5_serdes_rst_dual_c(), .sgmii_ecp5_signal_detect_c(), + .sgmii_ecp5_tx_pclk(), .sgmii_ecp5_tx_pcs_rst_c(), .sgmii_ecp5_tx_pwrup_c(), + .sgmii_ecp5_tx_serdes_rst_c(), .sgmii_ecp5_txi_clk()); \ No newline at end of file diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.sbx b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.sbx new file mode 100644 index 0000000..8a2304e --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.sbx @@ -0,0 +1,2096 @@ + + + + LATTICE + LOCAL + serdes_sync_0 + 1.0 + + + Diamond_Synthesis + synthesis + + ./serdes_sync_0.vhd + vhdlSource + + + + Diamond_Simulation + simulation + + ./serdes_sync_0.vhd + vhdlSource + + + + + + + + + serdes_sync_1_cyawstn + serdes_sync_1_cyawstn + + in + + + + serdes_sync_1.cyawstn + + + + + serdes_sync_1_hdinn + serdes_sync_1_hdinn + + in + + + + serdes_sync_1.hdinn + + + + + serdes_sync_1_hdinp + serdes_sync_1_hdinp + + in + + + + serdes_sync_1.hdinp + + + + + serdes_sync_1_hdoutn + serdes_sync_1_hdoutn + + out + + + + serdes_sync_1.hdoutn + + + + + serdes_sync_1_hdoutp + serdes_sync_1_hdoutp + + out + + + + serdes_sync_1.hdoutp + + + + + serdes_sync_1_lsm_status_s + serdes_sync_1_lsm_status_s + + out + + + + serdes_sync_1.lsm_status_s + + + + + serdes_sync_1_pll_lol + serdes_sync_1_pll_lol + + out + + + + serdes_sync_1.pll_lol + + + + + serdes_sync_1_pll_refclki + serdes_sync_1_pll_refclki + + in + + + + serdes_sync_1.pll_refclki + + + + + serdes_sync_1_rsl_disable + serdes_sync_1_rsl_disable + + in + + + + serdes_sync_1.rsl_disable + + + + + serdes_sync_1_rsl_rst + serdes_sync_1_rsl_rst + + in + + + + serdes_sync_1.rsl_rst + + + + + serdes_sync_1_rsl_rx_rdy + serdes_sync_1_rsl_rx_rdy + + out + + + + serdes_sync_1.rsl_rx_rdy + + + + + serdes_sync_1_rsl_tx_rdy + serdes_sync_1_rsl_tx_rdy + + out + + + + serdes_sync_1.rsl_tx_rdy + + + + + serdes_sync_1_rst_dual_c + serdes_sync_1_rst_dual_c + + in + + + + serdes_sync_1.rst_dual_c + + + + + serdes_sync_1_rx_cdr_lol_s + serdes_sync_1_rx_cdr_lol_s + + out + + + + serdes_sync_1.rx_cdr_lol_s + + + + + serdes_sync_1_rx_los_low_s + serdes_sync_1_rx_los_low_s + + out + + + + serdes_sync_1.rx_los_low_s + + + + + serdes_sync_1_rx_pclk + serdes_sync_1_rx_pclk + + out + + + + serdes_sync_1.rx_pclk + + + + + serdes_sync_1_rx_pcs_rst_c + serdes_sync_1_rx_pcs_rst_c + + in + + + + serdes_sync_1.rx_pcs_rst_c + + + + + serdes_sync_1_rx_pwrup_c + serdes_sync_1_rx_pwrup_c + + in + + + + serdes_sync_1.rx_pwrup_c + + + + + serdes_sync_1_rx_serdes_rst_c + serdes_sync_1_rx_serdes_rst_c + + in + + + + serdes_sync_1.rx_serdes_rst_c + + + + + serdes_sync_1_rxrefclk + serdes_sync_1_rxrefclk + + in + + + + serdes_sync_1.rxrefclk + + + + + serdes_sync_1_sci_en + serdes_sync_1_sci_en + + in + + + + serdes_sync_1.sci_en + + + + + serdes_sync_1_sci_en_dual + serdes_sync_1_sci_en_dual + + in + + + + serdes_sync_1.sci_en_dual + + + + + serdes_sync_1_sci_int + serdes_sync_1_sci_int + + out + + + + serdes_sync_1.sci_int + + + + + serdes_sync_1_sci_rd + serdes_sync_1_sci_rd + + in + + + + serdes_sync_1.sci_rd + + + + + serdes_sync_1_sci_sel + serdes_sync_1_sci_sel + + in + + + + serdes_sync_1.sci_sel + + + + + serdes_sync_1_sci_sel_dual + serdes_sync_1_sci_sel_dual + + in + + + + serdes_sync_1.sci_sel_dual + + + + + serdes_sync_1_sci_wrn + serdes_sync_1_sci_wrn + + in + + + + serdes_sync_1.sci_wrn + + + + + serdes_sync_1_serdes_pdb + serdes_sync_1_serdes_pdb + + in + + + + serdes_sync_1.serdes_pdb + + + + + serdes_sync_1_serdes_rst_dual_c + serdes_sync_1_serdes_rst_dual_c + + in + + + + serdes_sync_1.serdes_rst_dual_c + + + + + serdes_sync_1_signal_detect_c + serdes_sync_1_signal_detect_c + + in + + + + serdes_sync_1.signal_detect_c + + + + + serdes_sync_1_tx_idle_c + serdes_sync_1_tx_idle_c + + in + + + + serdes_sync_1.tx_idle_c + + + + + serdes_sync_1_tx_pclk + serdes_sync_1_tx_pclk + + out + + + + serdes_sync_1.tx_pclk + + + + + serdes_sync_1_tx_pcs_rst_c + serdes_sync_1_tx_pcs_rst_c + + in + + + + serdes_sync_1.tx_pcs_rst_c + + + + + serdes_sync_1_tx_pwrup_c + serdes_sync_1_tx_pwrup_c + + in + + + + serdes_sync_1.tx_pwrup_c + + + + + serdes_sync_1_tx_serdes_rst_c + serdes_sync_1_tx_serdes_rst_c + + in + + + + serdes_sync_1.tx_serdes_rst_c + + + + + serdes_sync_1_rx_cv_err + serdes_sync_1_rx_cv_err + + out + + 0 + 0 + + + + + serdes_sync_1.rx_cv_err + + + + + serdes_sync_1_rx_disp_err + serdes_sync_1_rx_disp_err + + out + + 0 + 0 + + + + + serdes_sync_1.rx_disp_err + + + + + serdes_sync_1_rx_k + serdes_sync_1_rx_k + + out + + 0 + 0 + + + + + serdes_sync_1.rx_k + + + + + serdes_sync_1_rxdata + serdes_sync_1_rxdata + + out + + 7 + 0 + + + + + serdes_sync_1.rxdata + + + + + serdes_sync_1_sci_addr + serdes_sync_1_sci_addr + + in + + 5 + 0 + + + + + serdes_sync_1.sci_addr + + + + + serdes_sync_1_sci_rddata + serdes_sync_1_sci_rddata + + out + + 7 + 0 + + + + + serdes_sync_1.sci_rddata + + + + + serdes_sync_1_sci_wrdata + serdes_sync_1_sci_wrdata + + in + + 7 + 0 + + + + + serdes_sync_1.sci_wrdata + + + + + serdes_sync_1_tx_disp_sel + serdes_sync_1_tx_disp_sel + + in + + 0 + 0 + + + + + serdes_sync_1.tx_disp_sel + + + + + serdes_sync_1_tx_force_disp + serdes_sync_1_tx_force_disp + + in + + 0 + 0 + + + + + serdes_sync_1.tx_force_disp + + + + + serdes_sync_1_tx_k + serdes_sync_1_tx_k + + in + + 0 + 0 + + + + + serdes_sync_1.tx_k + + + + + serdes_sync_1_txdata + serdes_sync_1_txdata + + in + + 7 + 0 + + + + + serdes_sync_1.txdata + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-05-10.09:27:16 AM + 2019-05-10.11:03:41 AM + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + serdes_sync_0 + 1.0 + + + serdes_sync_1 + + Lattice Semiconductor Corporation + LEGACY + PCS + 8.2 + + + Diamond_Simulation + simulation + + ./serdes_sync_1/serdes_sync_1_softlogic.v + verilogSource + + + ./serdes_sync_1/serdes_sync_1.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./serdes_sync_1/serdes_sync_1_softlogic.v + verilogSource + + + ./serdes_sync_1/serdes_sync_1.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + cyawstn + cyawstn + + in + + + + hdinn + hdinn + + in + + + + true + + + + + hdinp + hdinp + + in + + + + true + + + + + hdoutn + hdoutn + + out + + + + true + + + + + hdoutp + hdoutp + + out + + + + true + + + + + lsm_status_s + lsm_status_s + + out + + + + pll_lol + pll_lol + + out + + + + pll_refclki + pll_refclki + + in + + + + rsl_disable + rsl_disable + + in + + + + rsl_rst + rsl_rst + + in + + + + rsl_rx_rdy + rsl_rx_rdy + + out + + + + rsl_tx_rdy + rsl_tx_rdy + + out + + + + rst_dual_c + rst_dual_c + + in + + + + rx_cdr_lol_s + rx_cdr_lol_s + + out + + + + rx_los_low_s + rx_los_low_s + + out + + + + rx_pclk + rx_pclk + + out + + + + rx_pcs_rst_c + rx_pcs_rst_c + + in + + + + rx_pwrup_c + rx_pwrup_c + + in + + + + rx_serdes_rst_c + rx_serdes_rst_c + + in + + + + rxrefclk + rxrefclk + + in + + + + sci_en + sci_en + + in + + + + sci_en_dual + sci_en_dual + + in + + + + sci_int + sci_int + + out + + + + sci_rd + sci_rd + + in + + + + sci_sel + sci_sel + + in + + + + sci_sel_dual + sci_sel_dual + + in + + + + sci_wrn + sci_wrn + + in + + + + serdes_pdb + serdes_pdb + + in + + + + serdes_rst_dual_c + serdes_rst_dual_c + + in + + + + signal_detect_c + signal_detect_c + + in + + + + sli_rst + sli_rst + + in + + + + true + + + + + tx_idle_c + tx_idle_c + + in + + + + tx_pclk + tx_pclk + + out + + + + tx_pcs_rst_c + tx_pcs_rst_c + + in + + + + tx_pwrup_c + tx_pwrup_c + + in + + + + tx_serdes_rst_c + tx_serdes_rst_c + + in + + + + rx_cv_err + rx_cv_err + + out + + 0 + 0 + + + + + rx_disp_err + rx_disp_err + + out + + 0 + 0 + + + + + rx_k + rx_k + + out + + 0 + 0 + + + + + rxdata + rxdata + + out + + 7 + 0 + + + + + sci_addr + sci_addr + + in + + 5 + 0 + + + + + sci_rddata + sci_rddata + + out + + 7 + 0 + + + + + sci_wrdata + sci_wrdata + + in + + 7 + 0 + + + + + tx_disp_sel + tx_disp_sel + + in + + 0 + 0 + + + + + tx_force_disp + tx_force_disp + + in + + 0 + 0 + + + + + tx_k + tx_k + + in + + 0 + 0 + + + + + txdata + txdata + + in + + 7 + 0 + + + + + + + synplify + 2019-05-10.11:03:41 AM + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + Lane0 + DCUCHANNEL + + true + false + DCUCHANNEL + 9 + + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PCS + + + CoreRevision + 8.2 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/10/2019 + + + ModuleName + serdes_sync_1 + + + ParameterFileVersion + 1.0 + + + SourceFormat + VHDL + + + Time + 10:23:27 + + + VendorName + Lattice Semiconductor Corporation + + + + ;ACHARA + 0 00H + + + ;ACHARB + 0 00H + + + ;ACHARM + 0 00H + + + ;RXMCAENABLE + Disabled + + + CDRLOLACTION + Full Recalibration + + + CDRLOLRANGE + 3 + + + CDR_MAX_RATE + 1.25 + + + CDR_MULT + 10X + + + CDR_REF_RATE + 125.0000 + + + CH_MODE + Rx and Tx + + + Destination + Synplicity + + + EDIF + 1 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + IO_TYPE + G8B10B + + + LEQ + 0 + + + LOOPBACK + Disabled + + + LOSPORT + Enabled + + + NUM_CHS + 1 + + + Order + Big Endian [MSB:LSB] + + + PPORT_RX_RDY + Enabled + + + PPORT_TX_RDY + Enabled + + + PROTOCOL + G8B10B + + + PWAIT_RX_RDY + 3000 + + + PWAIT_TX_RDY + 3000 + + + RCSRC + Disabled + + + REFCLK_RATE + 125.0000 + + + RSTSEQSEL + Enabled + + + RX8B10B + Enabled + + + RXCOMMAA + 1100000100 + + + RXCOMMAB + 0011111000 + + + RXCOMMAM + 1111111100 + + + RXCOUPLING + AC + + + RXCTC + Disabled + + + RXCTCBYTEN + 0 00H + + + RXCTCBYTEN1 + 0 00H + + + RXCTCBYTEN2 + 0 00H + + + RXCTCBYTEN3 + 0 00H + + + RXCTCMATCHPATTERN + M4-S4 + + + RXDIFFTERM + 50 ohms + + + RXFIFO_ENABLE + Enabled + + + RXINVPOL + Non-invert + + + RXLDR + Off + + + RXLOSTHRESHOLD + 4 + + + RXLSM + Enabled + + + RXSC + K28P157 + + + RXWA + Barrel Shift + + + RX_DATA_WIDTH + 8/10-Bit + + + RX_FICLK_RATE + 125.0000 + + + RX_LINE_RATE + 1.2500 + + + RX_RATE_DIV + Full Rate + + + SCIPORT + Enabled + + + SOFTLOL + Enabled + + + TX8B10B + Enabled + + + TXAMPLITUDE + 800 + + + TXDEPOST + Disabled + + + TXDEPRE + Disabled + + + TXDIFFTERM + 50 ohms + + + TXFIFO_ENABLE + Enabled + + + TXINVPOL + Non-invert + + + TXLDR + Off + + + TXPLLLOLTHRESHOLD + 1 + + + TXPLLMULT + 10X + + + TX_DATA_WIDTH + 8/10-Bit + + + TX_FICLK_RATE + 125.0000 + + + TX_LINE_RATE + 1.2500 + + + TX_MAX_RATE + 1.25 + + + TX_RATE_DIV + Full Rate + + + VHDL + 1 + + + Verilog + 0 + + + + serdes_sync_1.pp + pp + + + serdes_sync_1.sym + sym + + + serdes_sync_1.tft + tft + + + serdes_sync_1.txt + pcs_module + + + + + DCUCHANNEL + 1 + + true + false + DCUCHANNEL + + Lane0 + + + + + + + + + serdes_sync_1_cyawstn + serdes_sync_1_cyawstn + + + + + serdes_sync_1_hdinn + serdes_sync_1_hdinn + + + sys_yes + + + + + + + serdes_sync_1_hdinp + serdes_sync_1_hdinp + + + sys_yes + + + + + + + serdes_sync_1_hdoutn + serdes_sync_1_hdoutn + + + sys_yes + + + + + + + serdes_sync_1_hdoutp + serdes_sync_1_hdoutp + + + sys_yes + + + + + + + serdes_sync_1_lsm_status_s + serdes_sync_1_lsm_status_s + + + + + serdes_sync_1_pll_lol + serdes_sync_1_pll_lol + + + + + serdes_sync_1_pll_refclki + serdes_sync_1_pll_refclki + + + + + serdes_sync_1_rsl_disable + serdes_sync_1_rsl_disable + + + + + serdes_sync_1_rsl_rst + serdes_sync_1_rsl_rst + + + + + serdes_sync_1_rsl_rx_rdy + serdes_sync_1_rsl_rx_rdy + + + + + serdes_sync_1_rsl_tx_rdy + serdes_sync_1_rsl_tx_rdy + + + + + serdes_sync_1_rst_dual_c + serdes_sync_1_rst_dual_c + + + + + serdes_sync_1_rx_cdr_lol_s + serdes_sync_1_rx_cdr_lol_s + + + + + serdes_sync_1_rx_los_low_s + serdes_sync_1_rx_los_low_s + + + + + serdes_sync_1_rx_pclk + serdes_sync_1_rx_pclk + + + + + serdes_sync_1_rx_pcs_rst_c + serdes_sync_1_rx_pcs_rst_c + + + + + serdes_sync_1_rx_pwrup_c + serdes_sync_1_rx_pwrup_c + + + + + serdes_sync_1_rx_serdes_rst_c + serdes_sync_1_rx_serdes_rst_c + + + + + serdes_sync_1_rxrefclk + serdes_sync_1_rxrefclk + + + + + serdes_sync_1_sci_en + serdes_sync_1_sci_en + + + + + serdes_sync_1_sci_en_dual + serdes_sync_1_sci_en_dual + + + + + serdes_sync_1_sci_int + serdes_sync_1_sci_int + + + + + serdes_sync_1_sci_rd + serdes_sync_1_sci_rd + + + + + serdes_sync_1_sci_sel + serdes_sync_1_sci_sel + + + + + serdes_sync_1_sci_sel_dual + serdes_sync_1_sci_sel_dual + + + + + serdes_sync_1_sci_wrn + serdes_sync_1_sci_wrn + + + + + serdes_sync_1_serdes_pdb + serdes_sync_1_serdes_pdb + + + + + serdes_sync_1_serdes_rst_dual_c + serdes_sync_1_serdes_rst_dual_c + + + + + serdes_sync_1_signal_detect_c + serdes_sync_1_signal_detect_c + + + + + serdes_sync_1_tx_idle_c + serdes_sync_1_tx_idle_c + + + + + serdes_sync_1_tx_pclk + serdes_sync_1_tx_pclk + + + + + serdes_sync_1_tx_pcs_rst_c + serdes_sync_1_tx_pcs_rst_c + + + + + serdes_sync_1_tx_pwrup_c + serdes_sync_1_tx_pwrup_c + + + + + serdes_sync_1_tx_serdes_rst_c + serdes_sync_1_tx_serdes_rst_c + + + + + serdes_sync_1_rx_cv_err + serdes_sync_1_rx_cv_err + + + + + serdes_sync_1_rx_cv_err[0] + serdes_sync_1_rx_cv_err[0] + + + + + serdes_sync_1_rx_disp_err + serdes_sync_1_rx_disp_err + + + + + serdes_sync_1_rx_disp_err[0] + serdes_sync_1_rx_disp_err[0] + + + + + serdes_sync_1_rx_k + serdes_sync_1_rx_k + + + + + serdes_sync_1_rx_k[0] + serdes_sync_1_rx_k[0] + + + + + serdes_sync_1_rxdata + serdes_sync_1_rxdata + + + + + serdes_sync_1_rxdata[0] + serdes_sync_1_rxdata[0] + + + + + serdes_sync_1_rxdata[1] + serdes_sync_1_rxdata[1] + + + + + serdes_sync_1_rxdata[2] + serdes_sync_1_rxdata[2] + + + + + serdes_sync_1_rxdata[3] + serdes_sync_1_rxdata[3] + + + + + serdes_sync_1_rxdata[4] + serdes_sync_1_rxdata[4] + + + + + serdes_sync_1_rxdata[5] + serdes_sync_1_rxdata[5] + + + + + serdes_sync_1_rxdata[6] + serdes_sync_1_rxdata[6] + + + + + serdes_sync_1_rxdata[7] + serdes_sync_1_rxdata[7] + + + + + serdes_sync_1_sci_addr + serdes_sync_1_sci_addr + + + + + serdes_sync_1_sci_addr[0] + serdes_sync_1_sci_addr[0] + + + + + serdes_sync_1_sci_addr[1] + serdes_sync_1_sci_addr[1] + + + + + serdes_sync_1_sci_addr[2] + serdes_sync_1_sci_addr[2] + + + + + serdes_sync_1_sci_addr[3] + serdes_sync_1_sci_addr[3] + + + + + serdes_sync_1_sci_addr[4] + serdes_sync_1_sci_addr[4] + + + + + serdes_sync_1_sci_addr[5] + serdes_sync_1_sci_addr[5] + + + + + serdes_sync_1_sci_rddata + serdes_sync_1_sci_rddata + + + + + serdes_sync_1_sci_rddata[0] + serdes_sync_1_sci_rddata[0] + + + + + serdes_sync_1_sci_rddata[1] + serdes_sync_1_sci_rddata[1] + + + + + serdes_sync_1_sci_rddata[2] + serdes_sync_1_sci_rddata[2] + + + + + serdes_sync_1_sci_rddata[3] + serdes_sync_1_sci_rddata[3] + + + + + serdes_sync_1_sci_rddata[4] + serdes_sync_1_sci_rddata[4] + + + + + serdes_sync_1_sci_rddata[5] + serdes_sync_1_sci_rddata[5] + + + + + serdes_sync_1_sci_rddata[6] + serdes_sync_1_sci_rddata[6] + + + + + serdes_sync_1_sci_rddata[7] + serdes_sync_1_sci_rddata[7] + + + + + serdes_sync_1_sci_wrdata + serdes_sync_1_sci_wrdata + + + + + serdes_sync_1_sci_wrdata[0] + serdes_sync_1_sci_wrdata[0] + + + + + serdes_sync_1_sci_wrdata[1] + serdes_sync_1_sci_wrdata[1] + + + + + serdes_sync_1_sci_wrdata[2] + serdes_sync_1_sci_wrdata[2] + + + + + serdes_sync_1_sci_wrdata[3] + serdes_sync_1_sci_wrdata[3] + + + + + serdes_sync_1_sci_wrdata[4] + serdes_sync_1_sci_wrdata[4] + + + + + serdes_sync_1_sci_wrdata[5] + serdes_sync_1_sci_wrdata[5] + + + + + serdes_sync_1_sci_wrdata[6] + serdes_sync_1_sci_wrdata[6] + + + + + serdes_sync_1_sci_wrdata[7] + serdes_sync_1_sci_wrdata[7] + + + + + serdes_sync_1_tx_disp_sel + serdes_sync_1_tx_disp_sel + + + + + serdes_sync_1_tx_disp_sel[0] + serdes_sync_1_tx_disp_sel[0] + + + + + serdes_sync_1_tx_force_disp + serdes_sync_1_tx_force_disp + + + + + serdes_sync_1_tx_force_disp[0] + serdes_sync_1_tx_force_disp[0] + + + + + serdes_sync_1_tx_k + serdes_sync_1_tx_k + + + + + serdes_sync_1_tx_k[0] + serdes_sync_1_tx_k[0] + + + + + serdes_sync_1_txdata + serdes_sync_1_txdata + + + + + serdes_sync_1_txdata[0] + serdes_sync_1_txdata[0] + + + + + serdes_sync_1_txdata[1] + serdes_sync_1_txdata[1] + + + + + serdes_sync_1_txdata[2] + serdes_sync_1_txdata[2] + + + + + serdes_sync_1_txdata[3] + serdes_sync_1_txdata[3] + + + + + serdes_sync_1_txdata[4] + serdes_sync_1_txdata[4] + + + + + serdes_sync_1_txdata[5] + serdes_sync_1_txdata[5] + + + + + serdes_sync_1_txdata[6] + serdes_sync_1_txdata[6] + + + + + serdes_sync_1_txdata[7] + serdes_sync_1_txdata[7] + + + + + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.vhd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.vhd new file mode 100644 index 0000000..6228fec --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.vhd @@ -0,0 +1,161 @@ + + +-- +-- Verific VHDL Description of module serdes_sync_0 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity serdes_sync_0 is + port (serdes_sync_1_rx_cv_err: out std_logic_vector(0 downto 0); + serdes_sync_1_rx_disp_err: out std_logic_vector(0 downto 0); + serdes_sync_1_rx_k: out std_logic_vector(0 downto 0); + serdes_sync_1_rxdata: out std_logic_vector(7 downto 0); + serdes_sync_1_sci_addr: in std_logic_vector(5 downto 0); + serdes_sync_1_sci_rddata: out std_logic_vector(7 downto 0); + serdes_sync_1_sci_wrdata: in std_logic_vector(7 downto 0); + serdes_sync_1_tx_disp_sel: in std_logic_vector(0 downto 0); + serdes_sync_1_tx_force_disp: in std_logic_vector(0 downto 0); + serdes_sync_1_tx_k: in std_logic_vector(0 downto 0); + serdes_sync_1_txdata: in std_logic_vector(7 downto 0); + serdes_sync_1_cyawstn: in std_logic; + serdes_sync_1_hdinn: in std_logic; + serdes_sync_1_hdinp: in std_logic; + serdes_sync_1_hdoutn: out std_logic; + serdes_sync_1_hdoutp: out std_logic; + serdes_sync_1_lsm_status_s: out std_logic; + serdes_sync_1_pll_lol: out std_logic; + serdes_sync_1_pll_refclki: in std_logic; + serdes_sync_1_rsl_disable: in std_logic; + serdes_sync_1_rsl_rst: in std_logic; + serdes_sync_1_rsl_rx_rdy: out std_logic; + serdes_sync_1_rsl_tx_rdy: out std_logic; + serdes_sync_1_rst_dual_c: in std_logic; + serdes_sync_1_rx_cdr_lol_s: out std_logic; + serdes_sync_1_rx_los_low_s: out std_logic; + serdes_sync_1_rx_pclk: out std_logic; + serdes_sync_1_rx_pcs_rst_c: in std_logic; + serdes_sync_1_rx_pwrup_c: in std_logic; + serdes_sync_1_rx_serdes_rst_c: in std_logic; + serdes_sync_1_rxrefclk: in std_logic; + serdes_sync_1_sci_en: in std_logic; + serdes_sync_1_sci_en_dual: in std_logic; + serdes_sync_1_sci_int: out std_logic; + serdes_sync_1_sci_rd: in std_logic; + serdes_sync_1_sci_sel: in std_logic; + serdes_sync_1_sci_sel_dual: in std_logic; + serdes_sync_1_sci_wrn: in std_logic; + serdes_sync_1_serdes_pdb: in std_logic; + serdes_sync_1_serdes_rst_dual_c: in std_logic; + serdes_sync_1_signal_detect_c: in std_logic; + serdes_sync_1_tx_idle_c: in std_logic; + serdes_sync_1_tx_pclk: out std_logic; + serdes_sync_1_tx_pcs_rst_c: in std_logic; + serdes_sync_1_tx_pwrup_c: in std_logic; + serdes_sync_1_tx_serdes_rst_c: in std_logic + ); + +end entity serdes_sync_0; -- sbp_module=true + +architecture serdes_sync_0 of serdes_sync_0 is + component serdes_sync_1 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pclk: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + sli_rst: in std_logic; + tx_idle_c: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic + ); + + end component serdes_sync_1; -- not_need_bbox=true + + + signal sli_rst_wire0,gnd : std_logic; +begin + sli_rst_wire0 <= serdes_sync_1_serdes_rst_dual_c OR serdes_sync_1_tx_serdes_rst_c OR (NOT serdes_sync_1_serdes_pdb) OR (NOT serdes_sync_1_tx_pwrup_c); + serdes_sync_1_inst: component serdes_sync_1 port map (rx_cv_err(0)=>serdes_sync_1_rx_cv_err(0), + rx_disp_err(0)=>serdes_sync_1_rx_disp_err(0),rx_k(0)=>serdes_sync_1_rx_k(0), + rxdata(7)=>serdes_sync_1_rxdata(7),rxdata(6)=>serdes_sync_1_rxdata(6), + rxdata(5)=>serdes_sync_1_rxdata(5),rxdata(4)=>serdes_sync_1_rxdata(4), + rxdata(3)=>serdes_sync_1_rxdata(3),rxdata(2)=>serdes_sync_1_rxdata(2), + rxdata(1)=>serdes_sync_1_rxdata(1),rxdata(0)=>serdes_sync_1_rxdata(0), + sci_addr(5)=>serdes_sync_1_sci_addr(5),sci_addr(4)=>serdes_sync_1_sci_addr(4), + sci_addr(3)=>serdes_sync_1_sci_addr(3),sci_addr(2)=>serdes_sync_1_sci_addr(2), + sci_addr(1)=>serdes_sync_1_sci_addr(1),sci_addr(0)=>serdes_sync_1_sci_addr(0), + sci_rddata(7)=>serdes_sync_1_sci_rddata(7),sci_rddata(6)=>serdes_sync_1_sci_rddata(6), + sci_rddata(5)=>serdes_sync_1_sci_rddata(5),sci_rddata(4)=>serdes_sync_1_sci_rddata(4), + sci_rddata(3)=>serdes_sync_1_sci_rddata(3),sci_rddata(2)=>serdes_sync_1_sci_rddata(2), + sci_rddata(1)=>serdes_sync_1_sci_rddata(1),sci_rddata(0)=>serdes_sync_1_sci_rddata(0), + sci_wrdata(7)=>serdes_sync_1_sci_wrdata(7),sci_wrdata(6)=>serdes_sync_1_sci_wrdata(6), + sci_wrdata(5)=>serdes_sync_1_sci_wrdata(5),sci_wrdata(4)=>serdes_sync_1_sci_wrdata(4), + sci_wrdata(3)=>serdes_sync_1_sci_wrdata(3),sci_wrdata(2)=>serdes_sync_1_sci_wrdata(2), + sci_wrdata(1)=>serdes_sync_1_sci_wrdata(1),sci_wrdata(0)=>serdes_sync_1_sci_wrdata(0), + tx_disp_sel(0)=>serdes_sync_1_tx_disp_sel(0),tx_force_disp(0)=>serdes_sync_1_tx_force_disp(0), + tx_k(0)=>serdes_sync_1_tx_k(0),txdata(7)=>serdes_sync_1_txdata(7), + txdata(6)=>serdes_sync_1_txdata(6),txdata(5)=>serdes_sync_1_txdata(5), + txdata(4)=>serdes_sync_1_txdata(4),txdata(3)=>serdes_sync_1_txdata(3), + txdata(2)=>serdes_sync_1_txdata(2),txdata(1)=>serdes_sync_1_txdata(1), + txdata(0)=>serdes_sync_1_txdata(0),cyawstn=>serdes_sync_1_cyawstn, + hdinn=>serdes_sync_1_hdinn,hdinp=>serdes_sync_1_hdinp,hdoutn=>serdes_sync_1_hdoutn, + hdoutp=>serdes_sync_1_hdoutp,lsm_status_s=>serdes_sync_1_lsm_status_s, + pll_lol=>serdes_sync_1_pll_lol,pll_refclki=>serdes_sync_1_pll_refclki, + rsl_disable=>serdes_sync_1_rsl_disable,rsl_rst=>serdes_sync_1_rsl_rst, + rsl_rx_rdy=>serdes_sync_1_rsl_rx_rdy,rsl_tx_rdy=>serdes_sync_1_rsl_tx_rdy, + rst_dual_c=>serdes_sync_1_rst_dual_c,rx_cdr_lol_s=>serdes_sync_1_rx_cdr_lol_s, + rx_los_low_s=>serdes_sync_1_rx_los_low_s,rx_pclk=>serdes_sync_1_rx_pclk, + rx_pcs_rst_c=>serdes_sync_1_rx_pcs_rst_c,rx_pwrup_c=>serdes_sync_1_rx_pwrup_c, + rx_serdes_rst_c=>serdes_sync_1_rx_serdes_rst_c,rxrefclk=>serdes_sync_1_rxrefclk, + sci_en=>serdes_sync_1_sci_en,sci_en_dual=>serdes_sync_1_sci_en_dual, + sci_int=>serdes_sync_1_sci_int,sci_rd=>serdes_sync_1_sci_rd,sci_sel=>serdes_sync_1_sci_sel, + sci_sel_dual=>serdes_sync_1_sci_sel_dual,sci_wrn=>serdes_sync_1_sci_wrn, + serdes_pdb=>serdes_sync_1_serdes_pdb,serdes_rst_dual_c=>serdes_sync_1_serdes_rst_dual_c, + signal_detect_c=>serdes_sync_1_signal_detect_c,sli_rst=>sli_rst_wire0, + tx_idle_c=>serdes_sync_1_tx_idle_c,tx_pclk=>serdes_sync_1_tx_pclk, + tx_pcs_rst_c=>serdes_sync_1_tx_pcs_rst_c,tx_pwrup_c=>serdes_sync_1_tx_pwrup_c, + tx_serdes_rst_c=>serdes_sync_1_tx_serdes_rst_c); + gnd <= '0' ; + +end architecture serdes_sync_0; -- sbp_module=true + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0_tmpl.v b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0_tmpl.v new file mode 100644 index 0000000..a6828ba --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0_tmpl.v @@ -0,0 +1,19 @@ +//Verilog instantiation template + +serdes_sync_0 _inst (.serdes_sync_1_rx_cv_err(), .serdes_sync_1_rx_disp_err(), + .serdes_sync_1_rx_k(), .serdes_sync_1_rxdata(), .serdes_sync_1_sci_addr(), + .serdes_sync_1_sci_rddata(), .serdes_sync_1_sci_wrdata(), .serdes_sync_1_tx_disp_sel(), + .serdes_sync_1_tx_force_disp(), .serdes_sync_1_tx_k(), .serdes_sync_1_txdata(), + .serdes_sync_1_cyawstn(), .serdes_sync_1_hdinn(), .serdes_sync_1_hdinp(), + .serdes_sync_1_hdoutn(), .serdes_sync_1_hdoutp(), .serdes_sync_1_lsm_status_s(), + .serdes_sync_1_pll_lol(), .serdes_sync_1_pll_refclki(), .serdes_sync_1_rsl_disable(), + .serdes_sync_1_rsl_rst(), .serdes_sync_1_rsl_rx_rdy(), .serdes_sync_1_rsl_tx_rdy(), + .serdes_sync_1_rst_dual_c(), .serdes_sync_1_rx_cdr_lol_s(), + .serdes_sync_1_rx_los_low_s(), .serdes_sync_1_rx_pclk(), .serdes_sync_1_rx_pcs_rst_c(), + .serdes_sync_1_rx_pwrup_c(), .serdes_sync_1_rx_serdes_rst_c(), + .serdes_sync_1_rxrefclk(), .serdes_sync_1_sci_en(), .serdes_sync_1_sci_en_dual(), + .serdes_sync_1_sci_int(), .serdes_sync_1_sci_rd(), .serdes_sync_1_sci_sel(), + .serdes_sync_1_sci_sel_dual(), .serdes_sync_1_sci_wrn(), .serdes_sync_1_serdes_pdb(), + .serdes_sync_1_serdes_rst_dual_c(), .serdes_sync_1_signal_detect_c(), + .serdes_sync_1_tx_idle_c(), .serdes_sync_1_tx_pclk(), .serdes_sync_1_tx_pcs_rst_c(), + .serdes_sync_1_tx_pwrup_c(), .serdes_sync_1_tx_serdes_rst_c()); \ No newline at end of file diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_0.lpc b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_0.lpc new file mode 100644 index 0000000..b79efbe --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_0.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=04/24/2019 +ModuleName=serdes_sync_0 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=16:52:37 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=3 +CDR_MAX_RATE=2 +CDR_MULT=10X +CDR_REF_RATE=200.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=G8B10B +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=G8B10B +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=200.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1100000100 +RXCOMMAB=0011111000 +RXCOMMAM=1111111100 +RXCOUPLING=AC +RXCTC=Disabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=0 00H +RXCTCBYTEN3=0 00H +RXCTCMATCHPATTERN=M4-S4 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P157 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=200.0000 +RX_LINE_RATE=2.0000 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=800 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=1 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=200.0000 +TX_LINE_RATE=2.0000 +TX_MAX_RATE=2 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +serdes_sync_0.pp=pp +serdes_sync_0.sym=sym +serdes_sync_0.tft=tft +serdes_sync_0.txt=pcs_module +[SYSTEMPNR] +LN0=DCU0_CH0 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cmd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cmd new file mode 100644 index 0000000..a65388e --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cmd @@ -0,0 +1,18 @@ +PROJECT: serdes_sync_1 + working_path: "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results" + module: serdes_sync_1 + verilog_file_list: "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" + vlog_std_v2001: true + constraint_file_name: "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc" + suffix_name: edn + output_file_name: serdes_sync_1 + write_prf: true + disable_io_insertion: true + force_gsr: false + frequency: 100 + fanout_limit: 50 + retiming: false + pipe: false + part: LFE5UM-85F + speed_grade: 8 + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cst b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cst new file mode 100644 index 0000000..0a83d53 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cst @@ -0,0 +1,3 @@ +Date=05/10/2019 +Time=10:23:27 + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc new file mode 100644 index 0000000..5424a21 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU1_CH1} diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.lpc b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.lpc new file mode 100644 index 0000000..6149a02 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=05/10/2019 +ModuleName=serdes_sync_1 +ParameterFileVersion=1.0 +SourceFormat=VHDL +Time=10:23:27 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=3 +CDR_MAX_RATE=1.25 +CDR_MULT=10X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=G8B10B +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=G8B10B +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1100000100 +RXCOMMAB=0011111000 +RXCOMMAM=1111111100 +RXCOUPLING=AC +RXCTC=Disabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=0 00H +RXCTCBYTEN3=0 00H +RXCTCMATCHPATTERN=M4-S4 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P157 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=800 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=1 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +serdes_sync_1.pp=pp +serdes_sync_1.sym=sym +serdes_sync_1.tft=tft +serdes_sync_1.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH1 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngd new file mode 100644 index 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Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes_sync_1rsl_core +-- + +-- serdes_sync_1rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes_sync_1sll_core +-- + +-- serdes_sync_1sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes_sync_1 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity serdes_sync_1 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + rx_pclk: out std_logic; + tx_pclk: out std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + tx_idle_c: in std_logic; + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + rx_cdr_lol_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity serdes_sync_1; + +architecture v1 of serdes_sync_1 is + component serdes_sync_1rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "G8B10B"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component serdes_sync_1rsl_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component serdes_sync_1sll_core is + generic (PPROTOCOL: string := "G8B10B"; + PLOL_SETTING: integer := 1; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 39; + PDIFF_VAL_UNLOCK: integer := 262; + PPCLK_TC: integer := 131072; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component serdes_sync_1sll_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, + n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, + n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, + rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23, + n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37, + n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51, + n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65, + n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79, + n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93, + n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114, + n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122, + n123,\_Z\,n127,n126,gnd,pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU1_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU1_inst : label is "CH1"; +begin + rx_pclk <= rx_pclk_c; + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b1", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b0", + CH1_MATCH_4_ENABLE=>"0b1",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x1BC", + CH1_CC_MATCH_2=>"0x11C",CH1_CC_MATCH_3=>"0x11C",CH1_CC_MATCH_4=>"0x11C", + CH1_UDF_COMMA_MASK=>"0x0ff",CH1_UDF_COMMA_A=>"0x083",CH1_UDF_COMMA_B=>"0x07C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b00",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b00",CH1_TDRV_SLICE0_CUR=>"0b000",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b01", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b1",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b100",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d800",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d0",D_CMUSETI4CPP=>"0d0",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b11",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d10", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b01", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n106,CH1_HDINP=>hdinp,CH0_HDINN=>n106,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, + CH0_RX_REFCLK=>n106,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n105,CH1_FF_RXI_CLK=>rx_pclk_c, + CH0_FF_TXI_CLK=>n105,CH1_FF_TXI_CLK=>tx_pclk_c,CH0_FF_EBRD_CLK=>n105, + CH1_FF_EBRD_CLK=>n48,CH0_FF_TX_D_0=>n106,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n106, + CH1_FF_TX_D_1=>txdata(1),CH0_FF_TX_D_2=>n106,CH1_FF_TX_D_2=>txdata(2), + CH0_FF_TX_D_3=>n106,CH1_FF_TX_D_3=>txdata(3),CH0_FF_TX_D_4=>n106,CH1_FF_TX_D_4=>txdata(4), + CH0_FF_TX_D_5=>n106,CH1_FF_TX_D_5=>txdata(5),CH0_FF_TX_D_6=>n106,CH1_FF_TX_D_6=>txdata(6), + CH0_FF_TX_D_7=>n106,CH1_FF_TX_D_7=>txdata(7),CH0_FF_TX_D_8=>n106,CH1_FF_TX_D_8=>tx_k(0), + CH0_FF_TX_D_9=>n106,CH1_FF_TX_D_9=>tx_force_disp(0),CH0_FF_TX_D_10=>n106, + CH1_FF_TX_D_10=>tx_disp_sel(0),CH0_FF_TX_D_11=>n106,CH1_FF_TX_D_11=>n47, + CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106, + CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106, + CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106, + CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106, + CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106, + CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,CH0_FF_TX_D_23=>n106,CH1_FF_TX_D_23=>n47, + CH0_FFC_EI_EN=>n106,CH1_FFC_EI_EN=>tx_idle_c,CH0_FFC_PCIE_DET_EN=>n106, + CH1_FFC_PCIE_DET_EN=>n47,CH0_FFC_PCIE_CT=>n106,CH1_FFC_PCIE_CT=>n47,CH0_FFC_SB_INV_RX=>n106, + CH1_FFC_SB_INV_RX=>n106,CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106, + CH0_FFC_SIGNAL_DETECT=>n106,CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n106, + CH1_FFC_FB_LOOPBACK=>n47,CH0_FFC_SB_PFIFO_LP=>n106,CH1_FFC_SB_PFIFO_LP=>n47, + CH0_FFC_PFIFO_CLR=>n106,CH1_FFC_PFIFO_CLR=>n47,CH0_FFC_RATE_MODE_RX=>n106, + CH1_FFC_RATE_MODE_RX=>n106,CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106, + CH0_FFC_DIV11_MODE_RX=>n106,CH1_FFC_DIV11_MODE_RX=>n47,CH0_FFC_DIV11_MODE_TX=>n106, + CH1_FFC_DIV11_MODE_TX=>n47,CH0_FFC_RX_GEAR_MODE=>n106,CH1_FFC_RX_GEAR_MODE=>n47, + CH0_FFC_TX_GEAR_MODE=>n106,CH1_FFC_TX_GEAR_MODE=>n47,CH0_FFC_LDR_CORE2TX_EN=>n106, + CH1_FFC_LDR_CORE2TX_EN=>n106,CH0_FFC_LANE_TX_RST=>n106,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c, + CH0_FFC_LANE_RX_RST=>n106,CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n106, + CH1_FFC_RRST=>rsl_rx_serdes_rst_c,CH0_FFC_TXPWDNB=>n106,CH1_FFC_TXPWDNB=>tx_pwrup_c, + CH0_FFC_RXPWDNB=>n106,CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n106, + CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1), + D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4), + D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7), + D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2), + D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5), + D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n106,CH1_SCIEN=>sci_en, + CH0_SCISEL=>n106,CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn, + D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,D_FFC_DUAL_RST=>rsl_rst_dual_c, + D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c, + CH0_FFC_CDR_EN_BITSLIP=>n106,CH1_FFC_CDR_EN_BITSLIP=>n47,D_SCAN_ENABLE=>n47, + D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47, + D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47, + D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47, + D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47, + D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>n50,CH1_HDOUTP=>hdoutp, + CH0_HDOUTN=>n51,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2, + D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n52,CH1_FF_RX_F_CLK=>n5, + CH0_FF_RX_H_CLK=>n53,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n54,CH1_FF_TX_F_CLK=>n7, + CH0_FF_TX_H_CLK=>n55,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n56,CH1_FF_RX_PCLK=>rx_pclk_c, + CH0_FF_TX_PCLK=>n57,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n58,CH1_FF_RX_D_0=>rxdata(0), + CH0_FF_RX_D_1=>n59,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n60,CH1_FF_RX_D_2=>rxdata(2), + CH0_FF_RX_D_3=>n61,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n62,CH1_FF_RX_D_4=>rxdata(4), + CH0_FF_RX_D_5=>n63,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n64,CH1_FF_RX_D_6=>rxdata(6), + CH0_FF_RX_D_7=>n65,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n66,CH1_FF_RX_D_8=>rx_k(0), + CH0_FF_RX_D_9=>n67,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n68, + CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n69,CH1_FF_RX_D_11=>n9,CH0_FF_RX_D_12=>n70, + CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74, + CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78, + CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82, + CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86, + CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90, + CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n92,CH1_FF_RX_D_23=>n10,CH0_FFS_PCIE_DONE=>n93, + CH1_FFS_PCIE_DONE=>n11,CH0_FFS_PCIE_CON=>n94,CH1_FFS_PCIE_CON=>n12,CH0_FFS_RLOS=>n95, + CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n96,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s, + CH0_FFS_CC_UNDERRUN=>n97,CH1_FFS_CC_UNDERRUN=>n13,CH0_FFS_CC_OVERRUN=>n98, + CH1_FFS_CC_OVERRUN=>n14,CH0_FFS_RXFBFIFO_ERROR=>n99,CH1_FFS_RXFBFIFO_ERROR=>n15, + CH0_FFS_TXFBFIFO_ERROR=>n100,CH1_FFS_TXFBFIFO_ERROR=>n16,CH0_FFS_RLOL=>n101, + CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n102,CH1_FFS_SKP_ADDED=>n17, + CH0_FFS_SKP_DELETED=>n103,CH1_FFS_SKP_DELETED=>n18,CH0_LDR_RX2CORE=>n104, + CH1_LDR_RX2CORE=>n115,D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1), + D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4), + D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7), + D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21, + D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25, + D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30, + D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36, + D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41, + D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46, + D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49); + n48 <= '1' ; + n47 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n44 <= 'Z' ; + n45 <= 'Z' ; + n46 <= 'Z' ; + n49 <= 'Z' ; + n106 <= '0' ; + n105 <= '1' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n102 <= 'Z' ; + n103 <= 'Z' ; + n104 <= 'Z' ; + n115 <= 'Z' ; + rsl_inst: component serdes_sync_1rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125, + rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125, + rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125, + rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119, + rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n114 <= '1' ; + n113 <= '0' ; + n125 <= '0' ; + n124 <= '1' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + n121 <= 'Z' ; + n122 <= 'Z' ; + n123 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component serdes_sync_1sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n127 <= '1' ; + n126 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_ngd.asd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v new file mode 100644 index 0000000..ec34b40 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module serdes_sync_1rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module serdes_sync_1sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/.recordref b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_CMD_.CML b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_CMD_.CML new file mode 100644 index 0000000..4fa0e06 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs -top serdes_sync_1 -hdllog /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/ -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib -v2001 -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -lib work /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_cmd._cml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_cmd._cml new file mode 100644 index 0000000..20bb359 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top serdes_sync_1 -osyn /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs \ No newline at end of file diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/backup/serdes_sync_1.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/backup/serdes_sync_1.srr new file mode 100644 index 0000000..5a66bb2 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/backup/serdes_sync_1.srr @@ -0,0 +1,1145 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 09:32:32 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +VHDL syntax check successful! + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:32:33 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 09:32:33 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +VHDL syntax check successful! +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1. +Post processing for work.serdes_sync_1.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 09:32:33 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work. + + PPROTOCOL=48'b010001110011100001000010001100010011000001000010 + PLOL_SETTING=32'b00000000000000000000000000000001 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000010011 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000010000011 + PPCLK_TC=32'b00000000000000010000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = serdes_sync_1sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL177 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Sharing sequential element genblk5.rdiff_comp_lock. Add a syn_preserve attribute to the element to prevent sharing. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=48'b010001110011100001000010001100010011000001000010 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = serdes_sync_1rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 7 to 6 of genblk5.rdiff_comp_unlock[7:5]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[5]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 3 reachable states with original encodings of: + 00 + 01 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 09:32:34 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:32:34 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:32:34 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 09:32:35 2019 + +###########################################################] +Pre-mapping Report + +# Fri May 10 09:32:35 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist serdes_sync_1 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - serdes_sync_1|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 92 + +0 - serdes_sync_1|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +========================================================================================================================= + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 09:32:36 2019 + +###########################################################] +Map & Optimize Report + +# Fri May 10 09:32:36 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.35ns 151 / 220 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 90 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount_diff[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 09:32:39 2019 +# + + +Top view: serdes_sync_1 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------------- +serdes_sync_1|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +serdes_sync_1|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +=========================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System serdes_sync_1|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki System | 10.000 8.307 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk System | 10.000 8.193 | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk serdes_sync_1|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +=================================================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: serdes_sync_1|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +======================================================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + The end point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[9] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[11] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[12] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[12] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[13] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +=========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +=========================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] serdes_sync_1|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +============================================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +DCU0_inst System DCUA CH0_FF_RX_PCLK rx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D un2_rdo_serdes_rst_dual_c_1 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_RXI_CLK rx_pclk 10.000 10.000 +========================================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 B In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_2_0 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +================================================================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 220 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 96 +GSR: 1 +INV: 3 +ORCALUT4: 150 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 09:32:40 2019 + +###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm/layer0.xdm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..9cf4948 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm/layer0.xdm @@ -0,0 +1,542 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +SS1SS1SS1S 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+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/run_options.txt @@ -0,0 +1,76 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/run_options.txt +#-- Written on Fri May 10 10:23:30 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "serdes_sync_1" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./serdes_sync_1.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf" +impl -active "syn_results" diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scemi_cfg.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs new file mode 100644 index 0000000..27162ad --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs @@ -0,0 +1,74 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "serdes_sync_1" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf" +impl -active "syn_results" diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.areasrr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.areasrr new file mode 100644 index 0000000..0e55e08 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.areasrr @@ -0,0 +1,97 @@ +---------------------------------------------------------------------- +Report for cell serdes_sync_1.v1 + +Register bits: 220 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + CCU2C 113 100.0 + DCUA 1 100.0 + FD1P3BX 20 100.0 + FD1P3DX 92 100.0 + FD1S3BX 12 100.0 + FD1S3DX 96 100.0 + GSR 1 100.0 + INV 3 100.0 + ORCALUT4 150 100.0 + PFUMX 2 100.0 + PUR 1 100.0 + VHI 6 100.0 + VLO 6 100.0 +SUB MODULES + serdes_sync_1rsl_core_Z2_layer1 1 100.0 + serdes_sync_1sll_core_Z1_layer1 1 100.0 + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 508 +---------------------------------------------------------------------- +Report for cell serdes_sync_1rsl_core_Z2_layer1.netlist + Instance path: rsl_inst + Cell usage: + cell count Res Usage(%) + CCU2C 51 45.1 + FD1P3BX 4 20.0 + FD1P3DX 74 80.4 + FD1S3BX 12 100.0 + FD1S3DX 37 38.5 + ORCALUT4 99 66.0 + PFUMX 2 100.0 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 281 +---------------------------------------------------------------------- +Report for cell serdes_sync_1sll_core_Z1_layer1.netlist + Instance path: sll_inst + Cell usage: + cell count Res Usage(%) + CCU2C 62 54.9 + FD1P3BX 16 80.0 + FD1P3DX 18 19.6 + FD1S3DX 59 61.5 + INV 3 100.0 + ORCALUT4 51 34.0 + VHI 4 66.7 + VLO 4 66.7 +SUB MODULES + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 220 +---------------------------------------------------------------------- +Report for cell sync_0s_0.netlist + Original Cell name sync_0s + Instance path: sll_inst.pdiff_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s_6.netlist + Original Cell name sync_0s + Instance path: sll_inst.rtc_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s.netlist + Original Cell name sync_0s + Instance path: sll_inst.phb_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.fse b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.fse new file mode 100644 index 0000000..f4aa273 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.fse @@ -0,0 +1,10 @@ + +fsm_encoding {61801018011} sequential + +fsm_state_encoding {61801018011} LPLL_LOSS_ST {00} + +fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01} + +fsm_state_encoding {61801018011} LPLL_LOCK_ST {10} + +fsm_registers {61801018011} {sll_state[1]} {sll_state[0]} diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.htm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.htm new file mode 100644 index 0000000..757e0e6 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.htm @@ -0,0 +1,9 @@ + + + syntmp/serdes_sync_1_srr.htm log file + + + + + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj new file mode 100644 index 0000000..e8c4120 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj @@ -0,0 +1,47 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj +#-- Written on Fri May 10 10:23:30 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" +add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" +add_file -constraint {"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc"} + +#-- top module name +set_option -top_module serdes_sync_1 + +#-- set result format/file last +project -result_file "serdes_sync_1.edn" + +#-- error message log file +project -log_file serdes_sync_1.srf + +#-- run Synplify with 'arrange VHDL file' +project -run diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srd new file mode 100644 index 0000000000000000000000000000000000000000..6e49b641d14b951c6cf0e66fd4eb3e64942319cf GIT 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zKw9$NDp`KXO<`NOUI$}oY=gZC+rQ3XKeat6TS1QtdXtCpy_Dnp-bp(K z6yN4#oIgL1mR7NwQvd#J+}(8|pSha2Vn0ssI2|NjF3x=TBHSc3%s D*vuTL literal 0 HcmV?d00001 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf new file mode 100644 index 0000000..6dd20a1 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf @@ -0,0 +1,1147 @@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 10:23:30 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 10:23:30 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 10:23:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1. +Post processing for work.serdes_sync_1.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 10:23:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work. + + PPROTOCOL=48'b010001110011100001000010001100010011000001000010 + PLOL_SETTING=32'b00000000000000000000000000000001 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = serdes_sync_1sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=48'b010001110011100001000010001100010011000001000010 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = serdes_sync_1rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 3 reachable states with original encodings of: + 00 + 01 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:33 2019 + +###########################################################] +# Fri May 10 10:23:33 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist serdes_sync_1 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - serdes_sync_1|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 92 + +0 - serdes_sync_1|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +========================================================================================================================= + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 10:23:34 2019 + +###########################################################] +# Fri May 10 10:23:34 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.35ns 151 / 220 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 90 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount_diff[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 10:23:38 2019 +# + + +Top view: serdes_sync_1 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------------- +serdes_sync_1|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +serdes_sync_1|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +=========================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System serdes_sync_1|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki System | 10.000 8.307 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk System | 10.000 8.193 | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk serdes_sync_1|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +=================================================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: serdes_sync_1|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +======================================================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + The end point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[9] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[11] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[12] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[12] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[13] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +=========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +=========================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] serdes_sync_1|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +============================================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +DCU0_inst System DCUA CH0_FF_RX_PCLK rx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D un2_rdo_serdes_rst_dual_c_1 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_RXI_CLK rx_pclk 10.000 10.000 +========================================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 B In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_2_0 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +================================================================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 220 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 96 +GSR: 1 +INV: 3 +ORCALUT4: 150 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 10:23:38 2019 + +###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srm new file mode 100644 index 0000000000000000000000000000000000000000..75dd84ec5b8f027aba1d82b1a72a73c57adc6f10 GIT binary patch literal 31292 zcmY(q2Uru&^FOYlAkqY+H$@SocL*h@h^RCL>AiPChX4T)rASkHkBW#0gx(>chaP%| zP!k|PfB>Nc`1yH%pXdKP|9kGa+uhll+u51D*UWP}Jh8X0{dbV*>g($Z2=s})))EaL zDSEQ+oCzp0qlNvCcy+Z6u})l(AKk-lTGF?@QuVC^N6+#?zJE(=6^|Q#YU>^pWH43v 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@@ +#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 +#install: /home/soft/lattice/diamond/3.10_x64/synpbase +#OS: Linux +#Hostname: lxhadeb07 + +# Fri May 10 10:23:30 2019 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 10:23:30 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 10:23:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1. +Post processing for work.serdes_sync_1.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 10:23:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work. + + PPROTOCOL=48'b010001110011100001000010001100010011000001000010 + PLOL_SETTING=32'b00000000000000000000000000000001 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = serdes_sync_1sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=48'b010001110011100001000010001100010011000001000010 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = serdes_sync_1rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 3 reachable states with original encodings of: + 00 + 01 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:33 2019 + +###########################################################] +# Fri May 10 10:23:33 2019 + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist serdes_sync_1 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - serdes_sync_1|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 92 + +0 - serdes_sync_1|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +========================================================================================================================= + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 10:23:34 2019 + +###########################################################] +# Fri May 10 10:23:34 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.35ns 151 / 220 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 90 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount_diff[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 10:23:38 2019 +# + + +Top view: serdes_sync_1 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------------- +serdes_sync_1|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +serdes_sync_1|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +=========================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System serdes_sync_1|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki System | 10.000 8.307 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk System | 10.000 8.193 | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk serdes_sync_1|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +=================================================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: serdes_sync_1|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +======================================================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + The end point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[9] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[11] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[12] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[12] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[13] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +=========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +=========================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] serdes_sync_1|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +============================================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +DCU0_inst System DCUA CH0_FF_RX_PCLK rx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D un2_rdo_serdes_rst_dual_c_1 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_RXI_CLK rx_pclk 10.000 10.000 +========================================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 B In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_2_0 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +================================================================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 220 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 96 +GSR: 1 +INV: 3 +ORCALUT4: 150 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 10:23:38 2019 + +###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..ba0ed54fa8e1d8251937bc443b82c33069d29f68 GIT binary patch literal 40960 zcmeHQ+jHC4d8eogb*I;j*V$~Ho>jJuv}=(7c<1i6k!4G9EU&$`TxYG_q7ZQ?Ap!v` z0E(0?uS@P`+NSO7qz~;hkL^n{oxb%g|3F{*()KmenNDZ=(7vQ;;%PIT>GvIgH(Ru2 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zz7E)L$L~N?a8eik@p}ow>U#;2U;16!-zS{(eF7X~;_Gknn+tV)O53%4`MtK|J7zEW zV(>K_HsASYIHvwq&@JDCJAS`|zTLH=yW}Z~X)Pi(<=q=23P?xv9gCE{>2>6nN9j#K z_s(e_Df&2yManR}EWRVMR^|Qfv^@I}@^lri;W~^$7Xxm$bJgkm9{>OV|Nr80P~ZXp R009600|2xTG0UH90RS4(1mgez literal 0 HcmV?d00001 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vhm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vhm new file mode 100644 index 0000000..cc3fb94 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vhm @@ -0,0 +1,6398 @@ +-- +-- Written by Synplicity +-- Product Version "M-2017.03L-SP1-1" +-- Program "Synplify Pro", Mapper "maplat, Build 1796R" +-- Fri May 10 10:23:37 2019 +-- + +-- +-- Written by Synplify Pro version Build 1796R +-- Fri May 10 10:23:37 2019 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_0 is +port( + ppul_sync : in std_logic; + pdiff_sync : out std_logic; + sli_rst : in std_logic; + pll_refclki : in std_logic); +end sync_0s_0; + +architecture beh of sync_0s_0 is + signal DATA_P1 : std_logic ; + signal DATA_P2_QN_1 : std_logic ; + signal VCC : std_logic ; + signal DATA_P1_QN_1 : std_logic ; + signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => pll_refclki, + CD => sli_rst, + Q => pdiff_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => ppul_sync, + CK => pll_refclki, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s_6 is +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic); +end sync_0s_6; + +architecture beh of sync_0s_6 is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( + D => DATA_P1, + CK => tx_pclk, + CD => sli_rst, + Q => ppul_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( + D => rtc_pul, + CK => tx_pclk, + CD => sli_rst, + Q => DATA_P1); +VCC_0: VHI port map ( + Z => VCC); +II_GND: VLO port map ( + Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity sync_0s is +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic); +end sync_0s; + +architecture beh of sync_0s is +signal DATA_P1 : std_logic ; +signal DATA_P2_QN_0 : std_logic ; +signal VCC : std_logic ; +signal DATA_P1_QN_0 : std_logic ; +signal GND : std_logic ; +begin +DATA_P2_REG_Z10: FD1S3DX port map ( +D => DATA_P1, +CK => pll_refclki, +CD => sli_rst, +Q => rhb_sync); +DATA_P1_REG_Z12: FD1S3DX port map ( +D => phb, +CK => pll_refclki, +CD => sli_rst, +Q => DATA_P1); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity serdes_sync_1rsl_core_Z2_layer1 is +port( +rx_pcs_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rst_dual_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rx_serdes_rst_c : in std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic; +rsl_disable : in std_logic; +tx_pcs_rst_c : in std_logic); +end serdes_sync_1rsl_core_Z2_layer1; + +architecture beh of serdes_sync_1rsl_core_Z2_layer1 is +signal PLOL0_CNT : std_logic_vector(2 downto 0); +signal PLOL0_CNT_3 : std_logic_vector(2 downto 0); +signal RXSR_APPD : std_logic_vector(0 to 0); +signal RXS_CNT_3 : std_logic_vector(1 downto 0); +signal RXS_CNT : std_logic_vector(1 downto 0); +signal RXS_CNT_QN : std_logic_vector(1 downto 0); +signal RLOS_DB_CNT : std_logic_vector(3 downto 0); +signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOLS0_CNT_S : std_logic_vector(17 downto 0); +signal RLOLS0_CNT : std_logic_vector(17 downto 0); +signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0); +signal RLOL_DB_CNT : std_logic_vector(3 downto 0); +signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0); +signal RLOL1_CNT_S : std_logic_vector(18 downto 0); +signal RLOL1_CNT : std_logic_vector(18 downto 0); +signal RLOL1_CNT_QN : std_logic_vector(18 downto 0); +signal RXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal RXR_WT_CNT : std_logic_vector(11 downto 0); +signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal RXSR_APPD_QN : std_logic_vector(0 to 0); +signal RXPR_APPD : std_logic_vector(0 to 0); +signal RXPR_APPD_QN : std_logic_vector(0 to 0); +signal TXS_CNT : std_logic_vector(1 downto 0); +signal TXS_CNT_QN : std_logic_vector(1 downto 0); +signal TXS_CNT_RNO : std_logic_vector(1 to 1); +signal TXP_CNT : std_logic_vector(1 downto 0); +signal TXP_CNT_QN : std_logic_vector(1 downto 0); +signal TXP_CNT_RNO : std_logic_vector(1 to 1); +signal PLOL_CNT_S : std_logic_vector(19 downto 0); +signal PLOL_CNT : std_logic_vector(19 downto 0); +signal PLOL_CNT_QN : std_logic_vector(19 downto 0); +signal PLOL0_CNT_QN : std_logic_vector(2 downto 0); +signal TXR_WT_CNT_S : std_logic_vector(11 downto 0); +signal TXR_WT_CNT : std_logic_vector(11 downto 0); +signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0); +signal TXPR_APPD : std_logic_vector(0 to 0); +signal TXPR_APPD_QN : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0); +signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0); +signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17); +signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17); +signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0); +signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11); +signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11); +signal PLOL_CNT_CRY : std_logic_vector(18 downto 0); +signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19); +signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19); +signal TXDPR_APPD : std_logic ; +signal TXP_RST : std_logic ; +signal UN2_RDO_TX_PCS_RST_C : std_logic ; +signal RSL_SERDES_RST_DUAL_C_10 : std_logic ; +signal RSL_RX_SERDES_RST_C_9 : std_logic ; +signal RLOS_DB_P1 : std_logic ; +signal RLOS_DB : std_logic ; +signal RXP_RST25 : std_logic ; +signal PLOL0_CNT9 : std_logic ; +signal WAITA_PLOL0 : std_logic ; +signal DUAL_OR_SERD_RST : std_logic ; +signal UN18_TXR_WT_TC_8 : std_logic ; +signal UN18_TXR_WT_TC_7 : std_logic ; +signal UN18_TXR_WT_TC_6 : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ; +signal UN17_RXR_WT_TC_8 : std_logic ; +signal UN17_RXR_WT_TC_7 : std_logic ; +signal UN17_RXR_WT_TC_6 : std_logic ; +signal UN3_RX_ALL_WELL_1 : std_logic ; +signal RLOL1_CNT_TC_1 : std_logic ; +signal RXS_RST : std_logic ; +signal \RLOL1_CNT_\ : std_logic ; +signal UN2_PLOL_FEDGE_5_1 : std_logic ; +signal UN2_PLOL_FEDGE_5_I : std_logic ; +signal N_2175_0 : std_logic ; +signal WAITA_RLOLS06 : std_logic ; +signal UN1_RLOLS0_CNT_TC : std_logic ; +signal WAITA_RLOLS0 : std_logic ; +signal WAITA_RLOLS0_QN : std_logic ; +signal VCC : std_logic ; +signal WAIT_CALIB_RNO : std_logic ; +signal UN1_RLOS_FEDGE_1 : std_logic ; +signal WAIT_CALIB : std_logic ; +signal WAIT_CALIB_QN : std_logic ; +signal RXS_RST6 : std_logic ; +signal UN1_RXS_CNT_TC : std_logic ; +signal RXS_RST_QN : std_logic ; +signal UN2_RLOS_REDGE_1_I : std_logic ; +signal RXP_RST2 : std_logic ; +signal RXP_RST2_QN : std_logic ; +signal RLOS_P1 : std_logic ; +signal RLOS_P2 : std_logic ; +signal RLOS_P2_QN : std_logic ; +signal RLOS_P1_QN : std_logic ; +signal RLOS_DB_P1_QN : std_logic ; +signal RLOS_DB_CNT_AXB_0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOS_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOS_DB_CNT_MAX : std_logic ; +signal RLOS_DB_QN : std_logic ; +signal RLOLS0_CNTE : std_logic ; +signal RLOL_P1 : std_logic ; +signal RLOL_P2 : std_logic ; +signal RLOL_P2_QN : std_logic ; +signal RLOL_P1_QN : std_logic ; +signal RLOL_DB : std_logic ; +signal RLOL_DB_P1 : std_logic ; +signal RLOL_DB_P1_QN : std_logic ; +signal RLOL_DB_CNT_AXB_0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ; +signal RLOL_DB_CNT_S_3_0_S0 : std_logic ; +signal UN1_RLOL_DB_CNT_MAX : std_logic ; +signal RLOL_DB_QN : std_logic ; +signal RLOL1_CNTE : std_logic ; +signal RXSDR_APPD_2 : std_logic ; +signal RXSDR_APPD : std_logic ; +signal RXSDR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ; +signal RXR_WT_EN : std_logic ; +signal RXR_WT_EN_QN : std_logic ; +signal RXR_WT_CNTE : std_logic ; +signal UN1_RUI_RST_DUAL_C_1_I : std_logic ; +signal RXDPR_APPD : std_logic ; +signal RXDPR_APPD_QN : std_logic ; +signal UN3_RX_ALL_WELL_2 : std_logic ; +signal RXR_WT_CNT9 : std_logic ; +signal RSL_RX_RDY_8 : std_logic ; +signal RUO_RX_RDYR_QN : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_1 : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ; +signal PLOL_FEDGE : std_logic ; +signal UN1_PLOL0_CNT_TC_1_I : std_logic ; +signal WAITA_PLOL0_QN : std_logic ; +signal UN1_PLOL_CNT_TC : std_logic ; +signal UN2_PLOL_CNT_TC : std_logic ; +signal TXS_RST : std_logic ; +signal TXS_RST_QN : std_logic ; +signal N_10_I : std_logic ; +signal UN9_PLOL0_CNT_TC : std_logic ; +signal UN1_PLOL0_CNT_TC_1 : std_logic ; +signal TXP_RST_QN : std_logic ; +signal N_11_I : std_logic ; +signal PLL_LOL_P2 : std_logic ; +signal PLL_LOL_P3 : std_logic ; +signal PLL_LOL_P3_QN : std_logic ; +signal PLL_LOL_P1 : std_logic ; +signal PLL_LOL_P2_QN : std_logic ; +signal PLL_LOL_P1_QN : std_logic ; +signal TXSR_APPD_2 : std_logic ; +signal TXSR_APPD : std_logic ; +signal TXSR_APPD_QN : std_logic ; +signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ; +signal TXR_WT_EN : std_logic ; +signal TXR_WT_EN_QN : std_logic ; +signal TXR_WT_CNTE : std_logic ; +signal UN2_PLOL_FEDGE_2 : std_logic ; +signal UN2_PLOL_FEDGE_3_I : std_logic ; +signal TXDPR_APPD_QN : std_logic ; +signal RSL_TX_RDY_7 : std_logic ; +signal RUO_TX_RDYR_QN : std_logic ; +signal UN2_PLOL_FEDGE_8_I : std_logic ; +signal RLOLS0_CNT_TC_1 : std_logic ; +signal RLOS_REDGE : std_logic ; +signal RLOLS0_CNT11_0 : std_logic ; +signal RSL_TX_SERDES_RST_C_6 : std_logic ; +signal \PLOL_CNT_\ : std_logic ; +signal \RLOLS0_CNT_\ : std_logic ; +signal UN8_RXS_CNT_TC : std_logic ; +signal TXSR_APPD_4 : std_logic ; +signal UN17_RXR_WT_TC : std_logic ; +signal UN1_DUAL_OR_RSERD_RST_2_0 : std_logic ; +signal UN1_RXSDR_OR_SR_APPD_0 : std_logic ; +signal UN2_RDO_SERDES_RST_DUAL_C_2_0 : std_logic ; +signal RSL_RX_PCS_RST_C_5 : std_logic ; +signal TXR_WT_CNT9 : std_logic ; +signal RX_ANY_RST : std_logic ; +signal UN18_TXR_WT_TC : std_logic ; +signal RSL_TX_PCS_RST_C_4 : std_logic ; +signal RLOLS0_CNT_TC_1_10 : std_logic ; +signal RLOLS0_CNT_TC_1_11 : std_logic ; +signal RLOLS0_CNT_TC_1_12 : std_logic ; +signal RLOLS0_CNT_TC_1_13 : std_logic ; +signal RLOL1_CNT_TC_1_11 : std_logic ; +signal RLOL1_CNT_TC_1_12 : std_logic ; +signal RLOL1_CNT_TC_1_13 : std_logic ; +signal RLOL1_CNT_TC_1_14 : std_logic ; +signal UN1_PLOL_CNT_TC_11 : std_logic ; +signal UN1_PLOL_CNT_TC_12 : std_logic ; +signal UN1_PLOL_CNT_TC_13 : std_logic ; +signal UN1_PLOL_CNT_TC_14 : std_logic ; +signal CO0_2 : std_logic ; +signal RLOLS0_CNT_TC_1_9 : std_logic ; +signal UN1_PLOL_CNT_TC_10 : std_logic ; +signal RLOL1_CNT_TC_1_10 : std_logic ; +signal UN3_RX_ALL_WELL_2_1 : std_logic ; +signal RXSDR_APPD_4 : std_logic ; +signal RLOS_DB_CNT_CRY_0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOS_DB_CNT_CRY_2 : std_logic ; +signal RLOS_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOS_DB_CNT_S_3_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ; +signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ; +signal RLOL_DB_CNT_CRY_2 : std_logic ; +signal RLOL_DB_CNT_S_3_0_COUT : std_logic ; +signal RLOL_DB_CNT_S_3_0_S1 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_6 : std_logic ; +signal N_7 : std_logic ; +begin +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO_0[0]\: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => TXDPR_APPD, +B => tx_pcs_rst_c, +C => TXP_RST, +D => rsl_disable, +Z => UN2_RDO_TX_PCS_RST_C); +\GENBLK2.RXP_RST2_RNO\: LUT4 +generic map( + init => X"EFEE" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => RSL_RX_SERDES_RST_C_9, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => RXP_RST25); +\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 +generic map( + init => X"1222" +) +port map ( +A => PLOL0_CNT(1), +B => PLOL0_CNT9, +C => WAITA_PLOL0, +D => PLOL0_CNT(0), +Z => PLOL0_CNT_3(1)); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6_RNI7IS21\: LUT4 +generic map( + init => X"1555" +) +port map ( +A => DUAL_OR_SERD_RST, +B => UN18_TXR_WT_TC_8, +C => UN18_TXR_WT_TC_7, +D => UN18_TXR_WT_TC_6, +Z => UN1_DUAL_OR_SERD_RST_1_1); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 +generic map( + init => X"2AAA" +) +port map ( +A => UN1_RUI_RST_DUAL_C_1_1, +B => UN17_RXR_WT_TC_8, +C => UN17_RXR_WT_TC_7, +D => UN17_RXR_WT_TC_6, +Z => UN3_RX_ALL_WELL_1); +\GENBLK2.RLOS_DB_P1_RNIS0OP\: LUT4 +generic map( + init => X"1011" +) +port map ( +A => RLOL1_CNT_TC_1, +B => RXS_RST, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => \RLOL1_CNT_\); +\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 +generic map( + init => X"D555" +) +port map ( +A => UN2_PLOL_FEDGE_5_1, +B => UN18_TXR_WT_TC_8, +C => UN18_TXR_WT_TC_7, +D => UN18_TXR_WT_TC_6, +Z => UN2_PLOL_FEDGE_5_I); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RXSR_APPD(0), +B => rx_serdes_rst_c, +C => RXS_RST, +D => rsl_disable, +Z => N_2175_0); +\GENBLK2.WAITA_RLOLS0_REG_Z610\: FD1P3DX port map ( +D => WAITA_RLOLS06, +SP => UN1_RLOLS0_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => WAITA_RLOLS0); +\GENBLK2.WAIT_CALIB_REG_Z612\: FD1P3BX port map ( +D => WAIT_CALIB_RNO, +SP => UN1_RLOS_FEDGE_1, +CK => rxrefclk, +PD => rsl_rst, +Q => WAIT_CALIB); +\GENBLK2.RXS_RST_REG_Z614\: FD1P3DX port map ( +D => RXS_RST6, +SP => UN1_RXS_CNT_TC, +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_RST); +\GENBLK2.RXS_CNT[0]_REG_Z616\: FD1S3DX port map ( +D => RXS_CNT_3(0), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(0)); +\GENBLK2.RXS_CNT[1]_REG_Z618\: FD1S3DX port map ( +D => RXS_CNT_3(1), +CK => rxrefclk, +CD => rsl_rst, +Q => RXS_CNT(1)); +\GENBLK2.RXP_RST2_REG_Z620\: FD1P3BX port map ( +D => RXP_RST25, +SP => UN2_RLOS_REDGE_1_I, +CK => rxrefclk, +PD => rsl_rst, +Q => RXP_RST2); +\GENBLK2.RLOS_P2_REG_Z622\: FD1S3DX port map ( +D => RLOS_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P2); +\GENBLK2.RLOS_P1_REG_Z624\: FD1S3DX port map ( +D => rx_los_low_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOS_P1); +\GENBLK2.RLOS_DB_P1_REG_Z626\: FD1S3BX port map ( +D => RLOS_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_P1); +\GENBLK2.RLOS_DB_CNT[0]_REG_Z628\: FD1S3BX port map ( +D => RLOS_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(0)); +\GENBLK2.RLOS_DB_CNT[1]_REG_Z630\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(1)); +\GENBLK2.RLOS_DB_CNT[2]_REG_Z632\: FD1S3BX port map ( +D => RLOS_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(2)); +\GENBLK2.RLOS_DB_CNT[3]_REG_Z634\: FD1S3BX port map ( +D => RLOS_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB_CNT(3)); +\GENBLK2.RLOS_DB_REG_Z636\: FD1P3BX port map ( +D => RLOS_DB_CNT(1), +SP => UN1_RLOS_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOS_DB); +\GENBLK2.RLOLS0_CNT[0]_REG_Z638\: FD1P3DX port map ( +D => RLOLS0_CNT_S(0), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(0)); +\GENBLK2.RLOLS0_CNT[1]_REG_Z640\: FD1P3DX port map ( +D => RLOLS0_CNT_S(1), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(1)); +\GENBLK2.RLOLS0_CNT[2]_REG_Z642\: FD1P3DX port map ( +D => RLOLS0_CNT_S(2), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(2)); +\GENBLK2.RLOLS0_CNT[3]_REG_Z644\: FD1P3DX port map ( +D => RLOLS0_CNT_S(3), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(3)); +\GENBLK2.RLOLS0_CNT[4]_REG_Z646\: FD1P3DX port map ( +D => RLOLS0_CNT_S(4), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(4)); +\GENBLK2.RLOLS0_CNT[5]_REG_Z648\: FD1P3DX port map ( +D => RLOLS0_CNT_S(5), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(5)); +\GENBLK2.RLOLS0_CNT[6]_REG_Z650\: FD1P3DX port map ( +D => RLOLS0_CNT_S(6), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(6)); +\GENBLK2.RLOLS0_CNT[7]_REG_Z652\: FD1P3DX port map ( +D => RLOLS0_CNT_S(7), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(7)); +\GENBLK2.RLOLS0_CNT[8]_REG_Z654\: FD1P3DX port map ( +D => RLOLS0_CNT_S(8), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(8)); +\GENBLK2.RLOLS0_CNT[9]_REG_Z656\: FD1P3DX port map ( +D => RLOLS0_CNT_S(9), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(9)); +\GENBLK2.RLOLS0_CNT[10]_REG_Z658\: FD1P3DX port map ( +D => RLOLS0_CNT_S(10), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(10)); +\GENBLK2.RLOLS0_CNT[11]_REG_Z660\: FD1P3DX port map ( +D => RLOLS0_CNT_S(11), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(11)); +\GENBLK2.RLOLS0_CNT[12]_REG_Z662\: FD1P3DX port map ( +D => RLOLS0_CNT_S(12), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(12)); +\GENBLK2.RLOLS0_CNT[13]_REG_Z664\: FD1P3DX port map ( +D => RLOLS0_CNT_S(13), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(13)); +\GENBLK2.RLOLS0_CNT[14]_REG_Z666\: FD1P3DX port map ( +D => RLOLS0_CNT_S(14), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(14)); +\GENBLK2.RLOLS0_CNT[15]_REG_Z668\: FD1P3DX port map ( +D => RLOLS0_CNT_S(15), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(15)); +\GENBLK2.RLOLS0_CNT[16]_REG_Z670\: FD1P3DX port map ( +D => RLOLS0_CNT_S(16), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(16)); +\GENBLK2.RLOLS0_CNT[17]_REG_Z672\: FD1P3DX port map ( +D => RLOLS0_CNT_S(17), +SP => RLOLS0_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOLS0_CNT(17)); +\GENBLK2.RLOL_P2_REG_Z674\: FD1S3DX port map ( +D => RLOL_P1, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P2); +\GENBLK2.RLOL_P1_REG_Z676\: FD1S3DX port map ( +D => rx_cdr_lol_s, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL_P1); +\GENBLK2.RLOL_DB_P1_REG_Z678\: FD1S3BX port map ( +D => RLOL_DB, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_P1); +\GENBLK2.RLOL_DB_CNT[0]_REG_Z680\: FD1S3BX port map ( +D => RLOL_DB_CNT_AXB_0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(0)); +\GENBLK2.RLOL_DB_CNT[1]_REG_Z682\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(1)); +\GENBLK2.RLOL_DB_CNT[2]_REG_Z684\: FD1S3BX port map ( +D => RLOL_DB_CNT_CRY_1_0_S1, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(2)); +\GENBLK2.RLOL_DB_CNT[3]_REG_Z686\: FD1S3BX port map ( +D => RLOL_DB_CNT_S_3_0_S0, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB_CNT(3)); +\GENBLK2.RLOL_DB_REG_Z688\: FD1P3BX port map ( +D => RLOL_DB_CNT(1), +SP => UN1_RLOL_DB_CNT_MAX, +CK => rxrefclk, +PD => rsl_rst, +Q => RLOL_DB); +\GENBLK2.RLOL1_CNT[0]_REG_Z690\: FD1P3DX port map ( +D => RLOL1_CNT_S(0), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(0)); +\GENBLK2.RLOL1_CNT[1]_REG_Z692\: FD1P3DX port map ( +D => RLOL1_CNT_S(1), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(1)); +\GENBLK2.RLOL1_CNT[2]_REG_Z694\: FD1P3DX port map ( +D => RLOL1_CNT_S(2), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(2)); +\GENBLK2.RLOL1_CNT[3]_REG_Z696\: FD1P3DX port map ( +D => RLOL1_CNT_S(3), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(3)); +\GENBLK2.RLOL1_CNT[4]_REG_Z698\: FD1P3DX port map ( +D => RLOL1_CNT_S(4), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(4)); +\GENBLK2.RLOL1_CNT[5]_REG_Z700\: FD1P3DX port map ( +D => RLOL1_CNT_S(5), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(5)); +\GENBLK2.RLOL1_CNT[6]_REG_Z702\: FD1P3DX port map ( +D => RLOL1_CNT_S(6), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(6)); +\GENBLK2.RLOL1_CNT[7]_REG_Z704\: FD1P3DX port map ( +D => RLOL1_CNT_S(7), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(7)); +\GENBLK2.RLOL1_CNT[8]_REG_Z706\: FD1P3DX port map ( +D => RLOL1_CNT_S(8), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(8)); +\GENBLK2.RLOL1_CNT[9]_REG_Z708\: FD1P3DX port map ( +D => RLOL1_CNT_S(9), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(9)); +\GENBLK2.RLOL1_CNT[10]_REG_Z710\: FD1P3DX port map ( +D => RLOL1_CNT_S(10), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(10)); +\GENBLK2.RLOL1_CNT[11]_REG_Z712\: FD1P3DX port map ( +D => RLOL1_CNT_S(11), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(11)); +\GENBLK2.RLOL1_CNT[12]_REG_Z714\: FD1P3DX port map ( +D => RLOL1_CNT_S(12), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(12)); +\GENBLK2.RLOL1_CNT[13]_REG_Z716\: FD1P3DX port map ( +D => RLOL1_CNT_S(13), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(13)); +\GENBLK2.RLOL1_CNT[14]_REG_Z718\: FD1P3DX port map ( +D => RLOL1_CNT_S(14), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(14)); +\GENBLK2.RLOL1_CNT[15]_REG_Z720\: FD1P3DX port map ( +D => RLOL1_CNT_S(15), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(15)); +\GENBLK2.RLOL1_CNT[16]_REG_Z722\: FD1P3DX port map ( +D => RLOL1_CNT_S(16), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(16)); +\GENBLK2.RLOL1_CNT[17]_REG_Z724\: FD1P3DX port map ( +D => RLOL1_CNT_S(17), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(17)); +\GENBLK2.RLOL1_CNT[18]_REG_Z726\: FD1P3DX port map ( +D => RLOL1_CNT_S(18), +SP => RLOL1_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RLOL1_CNT(18)); +\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z728\: FD1S3BX port map ( +D => RXSDR_APPD_2, +CK => rxrefclk, +PD => rsl_rst, +Q => RXSDR_APPD); +\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z730\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_1, +SP => UN1_DUAL_OR_RSERD_RST_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_EN); +\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z732\: FD1P3DX port map ( +D => RXR_WT_CNT_S(0), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z734\: FD1P3DX port map ( +D => RXR_WT_CNT_S(1), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(1)); +\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z736\: FD1P3DX port map ( +D => RXR_WT_CNT_S(2), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z738\: FD1P3DX port map ( +D => RXR_WT_CNT_S(3), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(3)); +\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z740\: FD1P3DX port map ( +D => RXR_WT_CNT_S(4), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z742\: FD1P3DX port map ( +D => RXR_WT_CNT_S(5), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(5)); +\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z744\: FD1P3DX port map ( +D => RXR_WT_CNT_S(6), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z746\: FD1P3DX port map ( +D => RXR_WT_CNT_S(7), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(7)); +\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z748\: FD1P3DX port map ( +D => RXR_WT_CNT_S(8), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z750\: FD1P3DX port map ( +D => RXR_WT_CNT_S(9), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(9)); +\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z752\: FD1P3DX port map ( +D => RXR_WT_CNT_S(10), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z754\: FD1P3DX port map ( +D => RXR_WT_CNT_S(11), +SP => RXR_WT_CNTE, +CK => rxrefclk, +CD => rsl_rst, +Q => RXR_WT_CNT(11)); +\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z756\: FD1P3DX port map ( +D => UN1_RUI_RST_DUAL_C_1_1, +SP => UN1_RUI_RST_DUAL_C_1_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXDPR_APPD); +\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z758\: FD1P3DX port map ( +D => UN3_RX_ALL_WELL_2, +SP => RXR_WT_CNT9, +CK => rxrefclk, +CD => rsl_rst, +Q => RSL_RX_RDY_8); +\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z760\: FD1S3DX port map ( +D => N_2175_0, +CK => rxrefclk, +CD => rsl_rst, +Q => RXSR_APPD(0)); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z762\: FD1P3DX port map ( +D => UN2_RDO_SERDES_RST_DUAL_C_1, +SP => UN2_RDO_SERDES_RST_DUAL_C_2_I, +CK => rxrefclk, +CD => rsl_rst, +Q => RXPR_APPD(0)); +\GENBLK1.WAITA_PLOL0_REG_Z764\: FD1P3DX port map ( +D => PLOL_FEDGE, +SP => UN1_PLOL0_CNT_TC_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => WAITA_PLOL0); +\GENBLK1.TXS_RST_REG_Z766\: FD1P3DX port map ( +D => UN1_PLOL_CNT_TC, +SP => UN2_PLOL_CNT_TC, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_RST); +\GENBLK1.TXS_CNT[0]_REG_Z768\: FD1S3DX port map ( +D => N_10_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(0)); +\GENBLK1.TXS_CNT[1]_REG_Z770\: FD1S3DX port map ( +D => TXS_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXS_CNT(1)); +\GENBLK1.TXP_RST_REG_Z772\: FD1P3DX port map ( +D => UN9_PLOL0_CNT_TC, +SP => UN1_PLOL0_CNT_TC_1, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_RST); +\GENBLK1.TXP_CNT[0]_REG_Z774\: FD1S3DX port map ( +D => N_11_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(0)); +\GENBLK1.TXP_CNT[1]_REG_Z776\: FD1S3DX port map ( +D => TXP_CNT_RNO(1), +CK => pll_refclki, +CD => rsl_rst, +Q => TXP_CNT(1)); +\GENBLK1.PLOL_CNT[0]_REG_Z778\: FD1S3DX port map ( +D => PLOL_CNT_S(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(0)); +\GENBLK1.PLOL_CNT[1]_REG_Z780\: FD1S3DX port map ( +D => PLOL_CNT_S(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(1)); +\GENBLK1.PLOL_CNT[2]_REG_Z782\: FD1S3DX port map ( +D => PLOL_CNT_S(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(2)); +\GENBLK1.PLOL_CNT[3]_REG_Z784\: FD1S3DX port map ( +D => PLOL_CNT_S(3), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(3)); +\GENBLK1.PLOL_CNT[4]_REG_Z786\: FD1S3DX port map ( +D => PLOL_CNT_S(4), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(4)); +\GENBLK1.PLOL_CNT[5]_REG_Z788\: FD1S3DX port map ( +D => PLOL_CNT_S(5), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(5)); +\GENBLK1.PLOL_CNT[6]_REG_Z790\: FD1S3DX port map ( +D => PLOL_CNT_S(6), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(6)); +\GENBLK1.PLOL_CNT[7]_REG_Z792\: FD1S3DX port map ( +D => PLOL_CNT_S(7), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(7)); +\GENBLK1.PLOL_CNT[8]_REG_Z794\: FD1S3DX port map ( +D => PLOL_CNT_S(8), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(8)); +\GENBLK1.PLOL_CNT[9]_REG_Z796\: FD1S3DX port map ( +D => PLOL_CNT_S(9), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(9)); +\GENBLK1.PLOL_CNT[10]_REG_Z798\: FD1S3DX port map ( +D => PLOL_CNT_S(10), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(10)); +\GENBLK1.PLOL_CNT[11]_REG_Z800\: FD1S3DX port map ( +D => PLOL_CNT_S(11), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(11)); +\GENBLK1.PLOL_CNT[12]_REG_Z802\: FD1S3DX port map ( +D => PLOL_CNT_S(12), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(12)); +\GENBLK1.PLOL_CNT[13]_REG_Z804\: FD1S3DX port map ( +D => PLOL_CNT_S(13), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(13)); +\GENBLK1.PLOL_CNT[14]_REG_Z806\: FD1S3DX port map ( +D => PLOL_CNT_S(14), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(14)); +\GENBLK1.PLOL_CNT[15]_REG_Z808\: FD1S3DX port map ( +D => PLOL_CNT_S(15), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(15)); +\GENBLK1.PLOL_CNT[16]_REG_Z810\: FD1S3DX port map ( +D => PLOL_CNT_S(16), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(16)); +\GENBLK1.PLOL_CNT[17]_REG_Z812\: FD1S3DX port map ( +D => PLOL_CNT_S(17), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(17)); +\GENBLK1.PLOL_CNT[18]_REG_Z814\: FD1S3DX port map ( +D => PLOL_CNT_S(18), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(18)); +\GENBLK1.PLOL_CNT[19]_REG_Z816\: FD1S3DX port map ( +D => PLOL_CNT_S(19), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL_CNT(19)); +\GENBLK1.PLOL0_CNT[0]_REG_Z818\: FD1S3DX port map ( +D => PLOL0_CNT_3(0), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(0)); +\GENBLK1.PLOL0_CNT[1]_REG_Z820\: FD1S3DX port map ( +D => PLOL0_CNT_3(1), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(1)); +\GENBLK1.PLOL0_CNT[2]_REG_Z822\: FD1S3DX port map ( +D => PLOL0_CNT_3(2), +CK => pll_refclki, +CD => rsl_rst, +Q => PLOL0_CNT(2)); +\GENBLK1.PLL_LOL_P3_REG_Z824\: FD1S3DX port map ( +D => PLL_LOL_P2, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P3); +\GENBLK1.PLL_LOL_P2_REG_Z826\: FD1S3DX port map ( +D => PLL_LOL_P1, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P2); +\GENBLK1.PLL_LOL_P1_REG_Z828\: FD1S3DX port map ( +D => pll_lock_i, +CK => pll_refclki, +CD => rsl_rst, +Q => PLL_LOL_P1); +\GENBLK1.GENBLK2.TXSR_APPD_REG_Z830\: FD1S3BX port map ( +D => TXSR_APPD_2, +CK => pll_refclki, +PD => rsl_rst, +Q => TXSR_APPD); +\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z832\: FD1P3DX port map ( +D => UN1_DUAL_OR_SERD_RST_1_1, +SP => UN1_DUAL_OR_SERD_RST_1_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_EN); +\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z834\: FD1P3DX port map ( +D => TXR_WT_CNT_S(0), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z836\: FD1P3DX port map ( +D => TXR_WT_CNT_S(1), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(1)); +\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z838\: FD1P3DX port map ( +D => TXR_WT_CNT_S(2), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z840\: FD1P3DX port map ( +D => TXR_WT_CNT_S(3), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(3)); +\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z842\: FD1P3DX port map ( +D => TXR_WT_CNT_S(4), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z844\: FD1P3DX port map ( +D => TXR_WT_CNT_S(5), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(5)); +\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z846\: FD1P3DX port map ( +D => TXR_WT_CNT_S(6), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z848\: FD1P3DX port map ( +D => TXR_WT_CNT_S(7), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(7)); +\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z850\: FD1P3DX port map ( +D => TXR_WT_CNT_S(8), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z852\: FD1P3DX port map ( +D => TXR_WT_CNT_S(9), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(9)); +\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z854\: FD1P3DX port map ( +D => TXR_WT_CNT_S(10), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z856\: FD1P3DX port map ( +D => TXR_WT_CNT_S(11), +SP => TXR_WT_CNTE, +CK => pll_refclki, +CD => rsl_rst, +Q => TXR_WT_CNT(11)); +\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z858\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_3_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXDPR_APPD); +\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z860\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_5_1, +SP => UN2_PLOL_FEDGE_5_I, +CK => pll_refclki, +CD => rsl_rst, +Q => RSL_TX_RDY_7); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z862\: FD1P3DX port map ( +D => UN2_PLOL_FEDGE_2, +SP => UN2_PLOL_FEDGE_8_I, +CK => pll_refclki, +CD => rsl_rst, +Q => TXPR_APPD(0)); +\GENBLK1.TXS_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXS_CNT(0), +B => TXS_RST, +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => N_10_I); +\GENBLK1.TXS_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => TXS_RST, +D => UN1_PLOL_CNT_TC, +Z => TXS_CNT_RNO(1)); +\GENBLK2.RXP_RST2_RNO_0\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RLOLS0_CNT_TC_1, +B => RLOS_REDGE, +C => RSL_RX_SERDES_RST_C_9, +D => RSL_SERDES_RST_DUAL_C_10, +Z => UN2_RLOS_REDGE_1_I); +\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 +generic map( + init => X"0F2F" +) +port map ( +A => TXPR_APPD(0), +B => PLL_LOL_P2, +C => UN1_DUAL_OR_SERD_RST_1_1, +D => RSL_TX_RDY_7, +Z => UN1_DUAL_OR_SERD_RST_1_I); +\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RXS_RST, +B => WAIT_CALIB, +C => RLOL1_CNT_TC_1, +D => RLOS_REDGE, +Z => RLOL1_CNTE); +\GENBLK2.RXS_RST6\: LUT4 +generic map( + init => X"2020" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => RXS_RST6); +\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS0, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => RLOLS0_CNTE); +\GENBLK2.GENBLK3.RXR_WT_EN_RNI1B6E\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RXR_WT_CNT9, +B => RXR_WT_EN, +C => VCC, +D => VCC, +Z => RXR_WT_CNTE); +\GENBLK1.PLOL_CNT11_I\: LUT4 +generic map( + init => X"0202" +) +port map ( +A => PLL_LOL_P2, +B => UN1_PLOL_CNT_TC, +C => RSL_TX_SERDES_RST_C_6, +D => VCC, +Z => \PLOL_CNT_\); +\GENBLK2.RLOLS0_CNT11_I\: LUT4 +generic map( + init => X"1111" +) +port map ( +A => RLOLS0_CNT11_0, +B => RLOLS0_CNT_TC_1, +C => VCC, +D => VCC, +Z => \RLOLS0_CNT_\); +\GENBLK2.UN1_RXS_CNT_TC\: LUT4 +generic map( + init => X"FEFC" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => UN8_RXS_CNT_TC, +D => RLOL1_CNT_TC_1, +Z => UN1_RXS_CNT_TC); +\GENBLK2.WAIT_CALIB_RNO\: LUT4 +generic map( + init => X"A3A3" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => WAIT_CALIB_RNO); +\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"FEFA" +) +port map ( +A => DUAL_OR_SERD_RST, +B => UN2_RDO_TX_PCS_RST_C, +C => PLL_LOL_P2, +D => TXSR_APPD_4, +Z => UN2_PLOL_FEDGE_8_I); +\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 +generic map( + init => X"FFFB" +) +port map ( +A => UN17_RXR_WT_TC, +B => UN1_DUAL_OR_RSERD_RST_2_0, +C => RSL_RX_SERDES_RST_C_9, +D => RSL_SERDES_RST_DUAL_C_10, +Z => UN1_DUAL_OR_RSERD_RST_2_I); +\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 +generic map( + init => X"FFB3" +) +port map ( +A => UN1_RXSDR_OR_SR_APPD_0, +B => UN2_RDO_SERDES_RST_DUAL_C_2_0, +C => RSL_RX_PCS_RST_C_5, +D => RSL_RX_SERDES_RST_C_9, +Z => UN2_RDO_SERDES_RST_DUAL_C_2_I); +\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 +generic map( + init => X"DDDD" +) +port map ( +A => UN1_RUI_RST_DUAL_C_1_1, +B => rst_dual_c, +C => VCC, +D => VCC, +Z => UN1_RUI_RST_DUAL_C_1_I); +\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXS_CNT(0), +B => TXS_CNT(1), +C => UN1_PLOL_CNT_TC, +D => VCC, +Z => UN2_PLOL_CNT_TC); +\GENBLK1.GENBLK2.TXR_WT_EN_RNI1JHS\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => TXR_WT_CNT9, +B => TXR_WT_EN, +C => VCC, +D => VCC, +Z => TXR_WT_CNTE); +\GENBLK2.GENBLK3.RXR_WT_CNT9\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => UN17_RXR_WT_TC, +B => RLOL_DB, +C => RLOS_DB, +D => RX_ANY_RST, +Z => RXR_WT_CNT9); +\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => RLOLS0_CNT11_0, +B => WAITA_RLOLS06, +C => RLOLS0_CNT_TC_1, +D => VCC, +Z => UN1_RLOLS0_CNT_TC); +\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => RLOL1_CNT_TC_1, +D => VCC, +Z => UN1_RLOS_FEDGE_1); +\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 +generic map( + init => X"FEFE" +) +port map ( +A => DUAL_OR_SERD_RST, +B => PLL_LOL_P2, +C => rst_dual_c, +D => VCC, +Z => UN2_PLOL_FEDGE_3_I); +\GENBLK1.TXP_CNT_RNO[0]\: LUT4 +generic map( + init => X"A6A6" +) +port map ( +A => TXP_CNT(0), +B => TXP_RST, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => N_11_I); +\GENBLK1.TXP_CNT_RNO[1]\: LUT4 +generic map( + init => X"CC6C" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => TXP_RST, +D => UN9_PLOL0_CNT_TC, +Z => TXP_CNT_RNO(1)); +UN3_RX_ALL_WELL_2_Z887: LUT4 +generic map( + init => X"0101" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RX_ANY_RST, +D => VCC, +Z => UN3_RX_ALL_WELL_2); +\GENBLK1.GENBLK2.TXR_WT_CNT9\: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => DUAL_OR_SERD_RST, +B => UN18_TXR_WT_TC, +C => RSL_TX_PCS_RST_C_4, +D => rst_dual_c, +Z => TXR_WT_CNT9); +UN2_PLOL_FEDGE_5_1_Z889: LUT4 +generic map( + init => X"0001" +) +port map ( +A => DUAL_OR_SERD_RST, +B => PLL_LOL_P2, +C => RSL_TX_PCS_RST_C_4, +D => rst_dual_c, +Z => UN2_PLOL_FEDGE_5_1); +RLOLS0_CNT_TC_1_Z890: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOLS0_CNT_TC_1_10, +B => RLOLS0_CNT_TC_1_11, +C => RLOLS0_CNT_TC_1_12, +D => RLOLS0_CNT_TC_1_13, +Z => RLOLS0_CNT_TC_1); +RLOL1_CNT_TC_1_Z891: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL1_CNT_TC_1_11, +B => RLOL1_CNT_TC_1_12, +C => RLOL1_CNT_TC_1_13, +D => RLOL1_CNT_TC_1_14, +Z => RLOL1_CNT_TC_1); +\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => UN1_PLOL_CNT_TC_11, +B => UN1_PLOL_CNT_TC_12, +C => UN1_PLOL_CNT_TC_13, +D => UN1_PLOL_CNT_TC_14, +Z => UN1_PLOL_CNT_TC); +\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOL_DB_CNT(0), +B => UN1_RLOL_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOL_DB_CNT_AXB_0); +\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 +generic map( + init => X"9999" +) +port map ( +A => RLOS_DB_CNT(0), +B => UN1_RLOS_DB_CNT_ZERO(0), +C => VCC, +D => VCC, +Z => RLOS_DB_CNT_AXB_0); +\GENBLK1.WAITA_PLOL0_RNO\: LUT4 +generic map( + init => X"F6F6" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1_I); +\GENBLK1.PLOL0_CNT_3[2]\: LUT4 +generic map( + init => X"1320" +) +port map ( +A => CO0_2, +B => PLOL0_CNT9, +C => PLOL0_CNT(1), +D => PLOL0_CNT(2), +Z => PLOL0_CNT_3(2)); +\GENBLK1.PLOL0_CNT_3[0]\: LUT4 +generic map( + init => X"1414" +) +port map ( +A => PLOL0_CNT9, +B => PLOL0_CNT(0), +C => WAITA_PLOL0, +D => VCC, +Z => PLOL0_CNT_3(0)); +UN1_RUI_RST_DUAL_C_1_1_Z898: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL_DB, +B => RLOS_DB, +C => RSL_RX_SERDES_RST_C_9, +D => RSL_SERDES_RST_DUAL_C_10, +Z => UN1_RUI_RST_DUAL_C_1_1); +UN2_RDO_SERDES_RST_DUAL_C_1_Z899: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RSL_RX_SERDES_RST_C_9, +B => RSL_SERDES_RST_DUAL_C_10, +C => rx_cdr_lol_s, +D => rx_los_low_s, +Z => UN2_RDO_SERDES_RST_DUAL_C_1); +\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => DUAL_OR_SERD_RST, +B => TXSR_APPD_4, +C => VCC, +D => VCC, +Z => TXSR_APPD_2); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN18_TXR_WT_TC_6, +B => UN18_TXR_WT_TC_7, +C => UN18_TXR_WT_TC_8, +D => VCC, +Z => UN18_TXR_WT_TC); +UN2_PLOL_FEDGE_2_Z902: LUT4 +generic map( + init => X"0101" +) +port map ( +A => PLL_LOL_P2, +B => RSL_SERDES_RST_DUAL_C_10, +C => RSL_TX_SERDES_RST_C_6, +D => VCC, +Z => UN2_PLOL_FEDGE_2); +RX_ANY_RST_Z903: LUT4 +generic map( + init => X"FFFE" +) +port map ( +A => RSL_RX_PCS_RST_C_5, +B => RSL_RX_SERDES_RST_C_9, +C => RSL_SERDES_RST_DUAL_C_10, +D => rst_dual_c, +Z => RX_ANY_RST); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 +generic map( + init => X"8080" +) +port map ( +A => UN17_RXR_WT_TC_6, +B => UN17_RXR_WT_TC_7, +C => UN17_RXR_WT_TC_8, +D => VCC, +Z => UN17_RXR_WT_TC); +\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z905\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_BM(0)); +\UN1_RLOL_DB_CNT_ZERO[0]_Z906\: PFUMX port map ( +ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0), +C0 => RLOL_P2, +Z => UN1_RLOL_DB_CNT_ZERO(0)); +\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z907\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_BM(0)); +\UN1_RLOS_DB_CNT_ZERO[0]_Z908\: PFUMX port map ( +ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0), +BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0), +C0 => RLOS_P2, +Z => UN1_RLOS_DB_CNT_ZERO(0)); +\RXS_CNT_3[1]_Z909\: LUT4 +generic map( + init => X"6464" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => RXS_RST, +D => VCC, +Z => RXS_CNT_3(1)); +\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 +generic map( + init => X"F8F8" +) +port map ( +A => TXP_CNT(0), +B => TXP_CNT(1), +C => UN9_PLOL0_CNT_TC, +D => VCC, +Z => UN1_PLOL0_CNT_TC_1); +\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_MAX); +\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 +generic map( + init => X"8001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_MAX); +\GENBLK2.WAITA_RLOLS06\: LUT4 +generic map( + init => X"0504" +) +port map ( +A => RLOL_DB, +B => RLOL_DB_P1, +C => RLOS_DB, +D => RLOS_DB_P1, +Z => WAITA_RLOLS06); +RLOLS0_CNT_TC_1_13_Z914: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RLOLS0_CNT(16), +B => RLOLS0_CNT(17), +C => RLOLS0_CNT_TC_1_9, +D => VCC, +Z => RLOLS0_CNT_TC_1_13); +\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 +generic map( + init => X"0100" +) +port map ( +A => PLOL_CNT(5), +B => PLOL_CNT(10), +C => PLOL_CNT(18), +D => UN1_PLOL_CNT_TC_10, +Z => UN1_PLOL_CNT_TC_14); +RLOL1_CNT_TC_1_14_Z916: LUT4 +generic map( + init => X"0100" +) +port map ( +A => RLOL1_CNT(12), +B => RLOL1_CNT(13), +C => RLOL1_CNT(18), +D => RLOL1_CNT_TC_1_10, +Z => RLOL1_CNT_TC_1_14); +UN2_RDO_SERDES_RST_DUAL_C_2_0_Z917: LUT4 +generic map( + init => X"0101" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => rx_cdr_lol_s, +C => rx_los_low_s, +D => VCC, +Z => UN2_RDO_SERDES_RST_DUAL_C_2_0); +UN1_DUAL_OR_RSERD_RST_2_0_Z918: LUT4 +generic map( + init => X"0101" +) +port map ( +A => UN3_RX_ALL_WELL_2_1, +B => RLOL_DB, +C => RLOS_DB, +D => VCC, +Z => UN1_DUAL_OR_RSERD_RST_2_0); +\RXS_CNT_3[0]_Z919\: LUT4 +generic map( + init => X"5252" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => RXS_RST, +D => VCC, +Z => RXS_CNT_3(0)); +\RDO_RX_SERDES_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXS_RST, +C => rx_serdes_rst_c, +D => VCC, +Z => RSL_RX_SERDES_RST_C_9); +\RDO_TX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXP_RST, +C => tx_pcs_rst_c, +D => VCC, +Z => RSL_TX_PCS_RST_C_4); +RDO_TX_SERDES_RST_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => TXS_RST, +C => tx_serdes_rst_c, +D => VCC, +Z => RSL_TX_SERDES_RST_C_6); +RDO_SERDES_RST_DUAL_C: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => rsl_rst, +C => serdes_rst_dual_c, +D => VCC, +Z => RSL_SERDES_RST_DUAL_C_10); +\GENBLK2.GENBLK3.UN3_RX_ALL_WELL_2_1\: LUT4 +generic map( + init => X"0E0E" +) +port map ( +A => RXPR_APPD(0), +B => RXDPR_APPD, +C => RSL_RX_RDY_8, +D => VCC, +Z => UN3_RX_ALL_WELL_2_1); +\RDO_RX_PCS_RST_C_1[0]\: LUT4 +generic map( + init => X"F4F4" +) +port map ( +A => rsl_disable, +B => RXP_RST2, +C => rx_pcs_rst_c, +D => VCC, +Z => RSL_RX_PCS_RST_C_5); +\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 +generic map( + init => X"1010" +) +port map ( +A => PLOL0_CNT(0), +B => PLOL0_CNT(1), +C => PLOL0_CNT(2), +D => VCC, +Z => UN9_PLOL0_CNT_TC); +\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD_0\: LUT4 +generic map( + init => X"FCA8" +) +port map ( +A => RXSR_APPD(0), +B => RLOL_DB, +C => RLOS_DB, +D => RXSDR_APPD_4, +Z => UN1_RXSDR_OR_SR_APPD_0); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => TXR_WT_CNT(0), +B => TXR_WT_CNT(8), +C => TXR_WT_CNT(9), +D => TXR_WT_CNT(11), +Z => UN18_TXR_WT_TC_6); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => TXR_WT_CNT(3), +B => TXR_WT_CNT(4), +C => TXR_WT_CNT(5), +D => TXR_WT_CNT(7), +Z => UN18_TXR_WT_TC_7); +\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => TXR_WT_CNT(1), +B => TXR_WT_CNT(2), +C => TXR_WT_CNT(6), +D => TXR_WT_CNT(10), +Z => UN18_TXR_WT_TC_8); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RXR_WT_CNT(3), +B => RXR_WT_CNT(4), +C => RXR_WT_CNT(5), +D => RXR_WT_CNT(7), +Z => UN17_RXR_WT_TC_6); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RXR_WT_CNT(0), +B => RXR_WT_CNT(8), +C => RXR_WT_CNT(9), +D => RXR_WT_CNT(11), +Z => UN17_RXR_WT_TC_7); +\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RXR_WT_CNT(1), +B => RXR_WT_CNT(2), +C => RXR_WT_CNT(6), +D => RXR_WT_CNT(10), +Z => UN17_RXR_WT_TC_8); +RLOLS0_CNT_TC_1_9_Z934: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(9), +B => RLOLS0_CNT(11), +C => RLOLS0_CNT(12), +D => RLOLS0_CNT(13), +Z => RLOLS0_CNT_TC_1_9); +RLOLS0_CNT_TC_1_10_Z935: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(5), +B => RLOLS0_CNT(6), +C => RLOLS0_CNT(7), +D => RLOLS0_CNT(8), +Z => RLOLS0_CNT_TC_1_10); +RLOLS0_CNT_TC_1_11_Z936: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOLS0_CNT(1), +B => RLOLS0_CNT(2), +C => RLOLS0_CNT(3), +D => RLOLS0_CNT(4), +Z => RLOLS0_CNT_TC_1_11); +RLOLS0_CNT_TC_1_12_Z937: LUT4 +generic map( + init => X"4000" +) +port map ( +A => RLOLS0_CNT(0), +B => RLOLS0_CNT(10), +C => RLOLS0_CNT(14), +D => RLOLS0_CNT(15), +Z => RLOLS0_CNT_TC_1_12); +\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 +generic map( + init => X"0080" +) +port map ( +A => PLOL_CNT(1), +B => PLOL_CNT(6), +C => PLOL_CNT(7), +D => PLOL_CNT(12), +Z => UN1_PLOL_CNT_TC_10); +\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(8), +B => PLOL_CNT(9), +C => PLOL_CNT(11), +D => PLOL_CNT(13), +Z => UN1_PLOL_CNT_TC_11); +\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 +generic map( + init => X"8000" +) +port map ( +A => PLOL_CNT(14), +B => PLOL_CNT(15), +C => PLOL_CNT(16), +D => PLOL_CNT(17), +Z => UN1_PLOL_CNT_TC_12); +\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 +generic map( + init => X"0100" +) +port map ( +A => PLOL_CNT(2), +B => PLOL_CNT(3), +C => PLOL_CNT(4), +D => PLOL_CNT(19), +Z => UN1_PLOL_CNT_TC_13); +RLOL1_CNT_TC_1_10_Z942: LUT4 +generic map( + init => X"0800" +) +port map ( +A => RLOL1_CNT(14), +B => RLOL1_CNT(15), +C => RLOL1_CNT(16), +D => RLOL1_CNT(17), +Z => RLOL1_CNT_TC_1_10); +RLOL1_CNT_TC_1_11_Z943: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(0), +B => RLOL1_CNT(1), +C => RLOL1_CNT(2), +D => RLOL1_CNT(3), +Z => RLOL1_CNT_TC_1_11); +RLOL1_CNT_TC_1_12_Z944: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(4), +B => RLOL1_CNT(5), +C => RLOL1_CNT(6), +D => RLOL1_CNT(7), +Z => RLOL1_CNT_TC_1_12); +RLOL1_CNT_TC_1_13_Z945: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL1_CNT(8), +B => RLOL1_CNT(9), +C => RLOL1_CNT(10), +D => RLOL1_CNT(11), +Z => RLOL1_CNT_TC_1_13); +\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PLOL0_CNT(0), +B => WAITA_PLOL0, +C => VCC, +D => VCC, +Z => CO0_2); +PLOL_FEDGE_Z947: LUT4 +generic map( + init => X"4444" +) +port map ( +A => PLL_LOL_P2, +B => PLL_LOL_P3, +C => VCC, +D => VCC, +Z => PLOL_FEDGE); +\GENBLK2.UN8_RXS_CNT_TC\: LUT4 +generic map( + init => X"8888" +) +port map ( +A => RXS_CNT(0), +B => RXS_CNT(1), +C => VCC, +D => VCC, +Z => UN8_RXS_CNT_TC); +RLOS_REDGE_Z949: LUT4 +generic map( + init => X"2222" +) +port map ( +A => RLOS_DB, +B => RLOS_DB_P1, +C => VCC, +D => VCC, +Z => RLOS_REDGE); +\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RXSDR_APPD_4, +B => serdes_rst_dual_c, +C => VCC, +D => VCC, +Z => RXSDR_APPD_2); +\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z951\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOS_DB_CNT(0), +B => RLOS_DB_CNT(1), +C => RLOS_DB_CNT(2), +D => RLOS_DB_CNT(3), +Z => UN1_RLOS_DB_CNT_ZERO_AM(0)); +\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z952\: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RLOL_DB_CNT(0), +B => RLOL_DB_CNT(1), +C => RLOL_DB_CNT(2), +D => RLOL_DB_CNT(3), +Z => UN1_RLOL_DB_CNT_ZERO_AM(0)); +DUAL_OR_SERD_RST_Z953: LUT4 +generic map( + init => X"EEFE" +) +port map ( +A => RSL_SERDES_RST_DUAL_C_10, +B => tx_serdes_rst_c, +C => TXS_RST, +D => rsl_disable, +Z => DUAL_OR_SERD_RST); +\GENBLK1.PLOL0_CNT9\: LUT4 +generic map( + init => X"AAAE" +) +port map ( +A => PLL_LOL_P2, +B => PLOL0_CNT(2), +C => PLOL0_CNT(1), +D => PLOL0_CNT(0), +Z => PLOL0_CNT9); +\GENBLK2.RLOLS0_CNT11_0\: LUT4 +generic map( + init => X"4F44" +) +port map ( +A => RLOL_DB_P1, +B => RLOL_DB, +C => RLOS_DB_P1, +D => RLOS_DB, +Z => RLOLS0_CNT11_0); +\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOL1_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_7, +COUT => RLOL1_CNT_CRY(0), +S0 => RLOL1_CNT_CRY_0_S0(0), +S1 => RLOL1_CNT_S(0)); +\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(0), +COUT => RLOL1_CNT_CRY(2), +S0 => RLOL1_CNT_S(1), +S1 => RLOL1_CNT_S(2)); +\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(2), +COUT => RLOL1_CNT_CRY(4), +S0 => RLOL1_CNT_S(3), +S1 => RLOL1_CNT_S(4)); +\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(4), +COUT => RLOL1_CNT_CRY(6), +S0 => RLOL1_CNT_S(5), +S1 => RLOL1_CNT_S(6)); +\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(6), +COUT => RLOL1_CNT_CRY(8), +S0 => RLOL1_CNT_S(7), +S1 => RLOL1_CNT_S(8)); +\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(8), +COUT => RLOL1_CNT_CRY(10), +S0 => RLOL1_CNT_S(9), +S1 => RLOL1_CNT_S(10)); +\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(10), +COUT => RLOL1_CNT_CRY(12), +S0 => RLOL1_CNT_S(11), +S1 => RLOL1_CNT_S(12)); +\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(12), +COUT => RLOL1_CNT_CRY(14), +S0 => RLOL1_CNT_S(13), +S1 => RLOL1_CNT_S(14)); +\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(14), +COUT => RLOL1_CNT_CRY(16), +S0 => RLOL1_CNT_S(15), +S1 => RLOL1_CNT_S(16)); +\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"800a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOL1_CNT_\, +B0 => RLOL1_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \RLOL1_CNT_\, +B1 => RLOL1_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => RLOL1_CNT_CRY(16), +COUT => RLOL1_CNT_CRY_0_COUT(17), +S0 => RLOL1_CNT_S(17), +S1 => RLOL1_CNT_S(18)); +\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \RLOLS0_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_6, +COUT => RLOLS0_CNT_CRY(0), +S0 => RLOLS0_CNT_CRY_0_S0(0), +S1 => RLOLS0_CNT_S(0)); +\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(0), +COUT => RLOLS0_CNT_CRY(2), +S0 => RLOLS0_CNT_S(1), +S1 => RLOLS0_CNT_S(2)); +\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(2), +COUT => RLOLS0_CNT_CRY(4), +S0 => RLOLS0_CNT_S(3), +S1 => RLOLS0_CNT_S(4)); +\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(4), +COUT => RLOLS0_CNT_CRY(6), +S0 => RLOLS0_CNT_S(5), +S1 => RLOLS0_CNT_S(6)); +\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(6), +COUT => RLOLS0_CNT_CRY(8), +S0 => RLOLS0_CNT_S(7), +S1 => RLOLS0_CNT_S(8)); +\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(8), +COUT => RLOLS0_CNT_CRY(10), +S0 => RLOLS0_CNT_S(9), +S1 => RLOLS0_CNT_S(10)); +\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(10), +COUT => RLOLS0_CNT_CRY(12), +S0 => RLOLS0_CNT_S(11), +S1 => RLOLS0_CNT_S(12)); +\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(12), +COUT => RLOLS0_CNT_CRY(14), +S0 => RLOLS0_CNT_S(13), +S1 => RLOLS0_CNT_S(14)); +\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \RLOLS0_CNT_\, +B1 => RLOLS0_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(14), +COUT => RLOLS0_CNT_CRY(16), +S0 => RLOLS0_CNT_S(15), +S1 => RLOLS0_CNT_S(16)); +\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \RLOLS0_CNT_\, +B0 => RLOLS0_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOLS0_CNT_CRY(16), +COUT => RLOLS0_CNT_S_0_COUT(17), +S0 => RLOLS0_CNT_S(17), +S1 => RLOLS0_CNT_S_0_S1(17)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => TXR_WT_CNT9, +C0 => VCC, +D0 => VCC, +A1 => TXR_WT_CNT9, +B1 => TXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => TXR_WT_CNT_CRY(0), +S0 => TXR_WT_CNT_CRY_0_S0(0), +S1 => TXR_WT_CNT_S(0)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => TXR_WT_CNT9, +B0 => TXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => TXR_WT_CNT9, +B1 => TXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(0), +COUT => TXR_WT_CNT_CRY(2), +S0 => TXR_WT_CNT_S(1), +S1 => TXR_WT_CNT_S(2)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => TXR_WT_CNT9, +B0 => TXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => TXR_WT_CNT9, +B1 => TXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(2), +COUT => TXR_WT_CNT_CRY(4), +S0 => TXR_WT_CNT_S(3), +S1 => TXR_WT_CNT_S(4)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => TXR_WT_CNT9, +B0 => TXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => TXR_WT_CNT9, +B1 => TXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(4), +COUT => TXR_WT_CNT_CRY(6), +S0 => TXR_WT_CNT_S(5), +S1 => TXR_WT_CNT_S(6)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => TXR_WT_CNT9, +B0 => TXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => TXR_WT_CNT9, +B1 => TXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(6), +COUT => TXR_WT_CNT_CRY(8), +S0 => TXR_WT_CNT_S(7), +S1 => TXR_WT_CNT_S(8)); +\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => TXR_WT_CNT9, +B0 => TXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => TXR_WT_CNT9, +B1 => TXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(8), +COUT => TXR_WT_CNT_CRY(10), +S0 => TXR_WT_CNT_S(9), +S1 => TXR_WT_CNT_S(10)); +\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => TXR_WT_CNT9, +B0 => TXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => TXR_WT_CNT_CRY(10), +COUT => TXR_WT_CNT_S_0_COUT(11), +S0 => TXR_WT_CNT_S(11), +S1 => TXR_WT_CNT_S_0_S1(11)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => RXR_WT_CNT9, +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RXR_WT_CNT_CRY(0), +S0 => RXR_WT_CNT_CRY_0_S0(0), +S1 => RXR_WT_CNT_S(0)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(0), +COUT => RXR_WT_CNT_CRY(2), +S0 => RXR_WT_CNT_S(1), +S1 => RXR_WT_CNT_S(2)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(2), +COUT => RXR_WT_CNT_CRY(4), +S0 => RXR_WT_CNT_S(3), +S1 => RXR_WT_CNT_S(4)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(4), +COUT => RXR_WT_CNT_CRY(6), +S0 => RXR_WT_CNT_S(5), +S1 => RXR_WT_CNT_S(6)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(6), +COUT => RXR_WT_CNT_CRY(8), +S0 => RXR_WT_CNT_S(7), +S1 => RXR_WT_CNT_S(8)); +\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => RXR_WT_CNT9, +B1 => RXR_WT_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(8), +COUT => RXR_WT_CNT_CRY(10), +S0 => RXR_WT_CNT_S(9), +S1 => RXR_WT_CNT_S(10)); +\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RXR_WT_CNT9, +B0 => RXR_WT_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RXR_WT_CNT_CRY(10), +COUT => RXR_WT_CNT_S_0_COUT(11), +S0 => RXR_WT_CNT_S(11), +S1 => RXR_WT_CNT_S_0_S1(11)); +\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => \PLOL_CNT_\, +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => PLOL_CNT_CRY(0), +S0 => PLOL_CNT_CRY_0_S0(0), +S1 => PLOL_CNT_S(0)); +\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(0), +COUT => PLOL_CNT_CRY(2), +S0 => PLOL_CNT_S(1), +S1 => PLOL_CNT_S(2)); +\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(2), +COUT => PLOL_CNT_CRY(4), +S0 => PLOL_CNT_S(3), +S1 => PLOL_CNT_S(4)); +\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(4), +COUT => PLOL_CNT_CRY(6), +S0 => PLOL_CNT_S(5), +S1 => PLOL_CNT_S(6)); +\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(8), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(6), +COUT => PLOL_CNT_CRY(8), +S0 => PLOL_CNT_S(7), +S1 => PLOL_CNT_S(8)); +\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(9), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(10), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(8), +COUT => PLOL_CNT_CRY(10), +S0 => PLOL_CNT_S(9), +S1 => PLOL_CNT_S(10)); +\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(11), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(12), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(10), +COUT => PLOL_CNT_CRY(12), +S0 => PLOL_CNT_S(11), +S1 => PLOL_CNT_S(12)); +\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(13), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(14), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(12), +COUT => PLOL_CNT_CRY(14), +S0 => PLOL_CNT_S(13), +S1 => PLOL_CNT_S(14)); +\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(15), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(16), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(14), +COUT => PLOL_CNT_CRY(16), +S0 => PLOL_CNT_S(15), +S1 => PLOL_CNT_S(16)); +\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(17), +C0 => VCC, +D0 => VCC, +A1 => \PLOL_CNT_\, +B1 => PLOL_CNT(18), +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(16), +COUT => PLOL_CNT_CRY(18), +S0 => PLOL_CNT_S(17), +S1 => PLOL_CNT_S(18)); +\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => \PLOL_CNT_\, +B0 => PLOL_CNT(19), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PLOL_CNT_CRY(18), +COUT => PLOL_CNT_S_0_COUT(19), +S0 => PLOL_CNT_S(19), +S1 => PLOL_CNT_S_0_S1(19)); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOS_DB_CNT(0), +B1 => UN1_RLOS_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => RLOS_DB_CNT_CRY_0, +S0 => RLOS_DB_CNT_CRY_0_0_S0, +S1 => RLOS_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOS_DB_CNT_ZERO(0), +B0 => RLOS_P2, +C0 => RLOS_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOS_DB_CNT_ZERO(0), +B1 => RLOS_P2, +C1 => RLOS_DB_CNT(2), +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_0, +COUT => RLOS_DB_CNT_CRY_2, +S0 => RLOS_DB_CNT_CRY_1_0_S0, +S1 => RLOS_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOS_DB_CNT(3), +B0 => RLOS_P2, +C0 => UN1_RLOS_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOS_DB_CNT_CRY_2, +COUT => RLOS_DB_CNT_S_3_0_COUT, +S0 => RLOS_DB_CNT_S_3_0_S0, +S1 => RLOS_DB_CNT_S_3_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => RLOL_DB_CNT(0), +B1 => UN1_RLOL_DB_CNT_ZERO(0), +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => RLOL_DB_CNT_CRY_0, +S0 => RLOL_DB_CNT_CRY_0_0_S0, +S1 => RLOL_DB_CNT_CRY_0_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C +generic map( + INIT0 => X"e101", + INIT1 => X"e101", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RLOL_DB_CNT_ZERO(0), +B0 => RLOL_P2, +C0 => RLOL_DB_CNT(1), +D0 => VCC, +A1 => UN1_RLOL_DB_CNT_ZERO(0), +B1 => RLOL_P2, +C1 => RLOL_DB_CNT(2), +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_0, +COUT => RLOL_DB_CNT_CRY_2, +S0 => RLOL_DB_CNT_CRY_1_0_S0, +S1 => RLOL_DB_CNT_CRY_1_0_S1); +\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C +generic map( + INIT0 => X"a90a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => RLOL_DB_CNT(3), +B0 => RLOL_P2, +C0 => UN1_RLOL_DB_CNT_ZERO(0), +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RLOL_DB_CNT_CRY_2, +COUT => RLOL_DB_CNT_S_3_0_COUT, +S0 => RLOL_DB_CNT_S_3_0_S0, +S1 => RLOL_DB_CNT_S_3_0_S1); +RXSDR_APPD_4 <= RXSDR_APPD; +TXSR_APPD_4 <= TXSR_APPD; +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_4; +rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_5; +rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_6; +rsl_tx_rdy <= RSL_TX_RDY_7; +rsl_rx_rdy <= RSL_RX_RDY_8; +rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_9; +rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_10; +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity serdes_sync_1sll_core_Z1_layer1 is +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic); +end serdes_sync_1sll_core_Z1_layer1; + +architecture beh of serdes_sync_1sll_core_Z1_layer1 is +signal PHB_CNT : std_logic_vector(2 downto 0); +signal PHB_CNT_I : std_logic_vector(2 downto 0); +signal RCOUNT : std_logic_vector(15 downto 0); +signal PCOUNT : std_logic_vector(21 downto 0); +signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0); +signal SLL_STATE : std_logic_vector(1 to 1); +signal SLL_STATE_QN : std_logic_vector(1 to 1); +signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT : std_logic_vector(7 downto 0); +signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0); +signal RCOUNT_S : std_logic_vector(15 downto 0); +signal RCOUNT_QN : std_logic_vector(15 downto 0); +signal PHB_CNT_QN : std_logic_vector(2 downto 0); +signal PHB_CNT_RNO : std_logic_vector(2 downto 1); +signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0); +signal PCOUNT_S : std_logic_vector(21 downto 0); +signal PCOUNT_QN : std_logic_vector(21 downto 0); +signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2); +signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2); +signal SLL_STATE_NS_I_0_M3 : std_logic_vector(1 to 1); +signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0); +signal PCOUNT_CRY : std_logic_vector(20 downto 0); +signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21); +signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21); +signal RCOUNT_CRY : std_logic_vector(14 downto 0); +signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15); +signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15); +signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0); +signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0); +signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7); +signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7); +signal PLL_LOCK : std_logic ; +signal RTC_CTRL4_0_A3_1 : std_logic ; +signal UN13_LOCK_20 : std_logic ; +signal PPUL_SYNC_P2 : std_logic ; +signal PPUL_SYNC_P1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ; +signal UN13_LOCK_19 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ; +signal UN13_LOCK_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ; +signal UN13_LOCK_17 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_RNO : std_logic ; +signal UN13_LOCK_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_16 : std_logic ; +signal UN13_LOCK_15 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ; +signal UN13_LOCK_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ; +signal UN13_LOCK_13 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ; +signal UN13_LOCK_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ; +signal UN13_LOCK_11 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ; +signal UN13_LOCK_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ; +signal UN13_LOCK_9 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ; +signal UN13_LOCK_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ; +signal UN13_LOCK_7 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ; +signal UN13_LOCK_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ; +signal UN13_LOCK_5 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ; +signal UN13_LOCK_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ; +signal UN13_LOCK_3 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ; +signal UN13_LOCK_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ; +signal UN13_LOCK_1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ; +signal UN13_LOCK_21 : std_logic ; +signal PPUL_SYNC_P3 : std_logic ; +signal N_7 : std_logic ; +signal UN13_LOCK_0 : std_logic ; +signal RTC_CTRL4 : std_logic ; +signal RTC_CTRL : std_logic ; +signal VCC : std_logic ; +signal N_2136_0 : std_logic ; +signal UNLOCK_5 : std_logic ; +signal UNLOCK_1_SQMUXA_I_0 : std_logic ; +signal UNLOCK : std_logic ; +signal UNLOCK_QN : std_logic ; +signal N_89_I : std_logic ; +signal RTC_PUL : std_logic ; +signal RTC_PUL_P1 : std_logic ; +signal RTC_PUL_P1_QN : std_logic ; +signal RTC_PUL5 : std_logic ; +signal RTC_PUL_QN : std_logic ; +signal RTC_CTRL_QN : std_logic ; +signal RSTAT_PCLK_2 : std_logic ; +signal RSTAT_PCLK : std_logic ; +signal RSTAT_PCLK_QN : std_logic ; +signal RHB_SYNC_P1 : std_logic ; +signal RHB_SYNC_P2 : std_logic ; +signal RHB_SYNC_P2_QN : std_logic ; +signal RHB_SYNC : std_logic ; +signal RHB_SYNC_P1_QN : std_logic ; +signal PPUL_SYNC_P3_QN : std_logic ; +signal PPUL_SYNC_P2_QN : std_logic ; +signal PPUL_SYNC : std_logic ; +signal PPUL_SYNC_P1_QN : std_logic ; +signal PLL_LOCK_QN : std_logic ; +signal PHB : std_logic ; +signal PHB_QN : std_logic ; +signal PDIFF_SYNC : std_logic ; +signal PDIFF_SYNC_P1 : std_logic ; +signal PDIFF_SYNC_P1_QN : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ; +signal LOCK_5 : std_logic ; +signal LOCK_1_SQMUXA_I_0 : std_logic ; +signal LOCK : std_logic ; +signal LOCK_QN : std_logic ; +signal RTC_PUL5_0_O3 : std_logic ; +signal RTC_PUL5_0_A3_6 : std_logic ; +signal RTC_PUL5_0_A3_7 : std_logic ; +signal UN1_RCOUNT_1_0_A3 : std_logic ; +signal UN1_RHB_WAIT_CNT : std_logic ; +signal N_12 : std_logic ; +signal RTC_CTRL4_0_A3_12_4 : std_logic ; +signal RTC_CTRL4_0_A3_12_5 : std_logic ; +signal RTC_CTRL4_10 : std_logic ; +signal UN1_RCOUNT_1_0_A3_1 : std_logic ; +signal N_6 : std_logic ; +signal UN1_RHB_WAIT_CNT_3 : std_logic ; +signal UN1_RHB_WAIT_CNT_4 : std_logic ; +signal RTC_PUL5_0_A3_5 : std_logic ; +signal UN13_LOCK_CRY_21_I : std_logic ; +signal UN13_UNLOCK_CRY_21 : std_logic ; +signal N_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ; +signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ; +signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ; +signal UN13_LOCK_CRY_0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S0 : std_logic ; +signal UN13_LOCK_CRY_0_0_S1 : std_logic ; +signal UN13_LOCK_CRY_2 : std_logic ; +signal UN13_LOCK_CRY_1_0_S0 : std_logic ; +signal UN13_LOCK_CRY_1_0_S1 : std_logic ; +signal UN13_LOCK_CRY_4 : std_logic ; +signal UN13_LOCK_CRY_3_0_S0 : std_logic ; +signal UN13_LOCK_CRY_3_0_S1 : std_logic ; +signal UN13_LOCK_CRY_6 : std_logic ; +signal UN13_LOCK_CRY_5_0_S0 : std_logic ; +signal UN13_LOCK_CRY_5_0_S1 : std_logic ; +signal UN13_LOCK_CRY_8 : std_logic ; +signal UN13_LOCK_CRY_7_0_S0 : std_logic ; +signal UN13_LOCK_CRY_7_0_S1 : std_logic ; +signal UN13_LOCK_CRY_10 : std_logic ; +signal UN13_LOCK_CRY_9_0_S0 : std_logic ; +signal UN13_LOCK_CRY_9_0_S1 : std_logic ; +signal UN13_LOCK_CRY_12 : std_logic ; +signal UN13_LOCK_CRY_11_0_S0 : std_logic ; +signal UN13_LOCK_CRY_11_0_S1 : std_logic ; +signal UN13_LOCK_CRY_14 : std_logic ; +signal UN13_LOCK_CRY_13_0_S0 : std_logic ; +signal UN13_LOCK_CRY_13_0_S1 : std_logic ; +signal UN13_LOCK_CRY_16 : std_logic ; +signal UN13_LOCK_CRY_15_0_S0 : std_logic ; +signal UN13_LOCK_CRY_15_0_S1 : std_logic ; +signal UN13_LOCK_CRY_18 : std_logic ; +signal UN13_LOCK_CRY_17_0_S0 : std_logic ; +signal UN13_LOCK_CRY_17_0_S1 : std_logic ; +signal UN13_LOCK_CRY_20 : std_logic ; +signal UN13_LOCK_CRY_19_0_S0 : std_logic ; +signal UN13_LOCK_CRY_19_0_S1 : std_logic ; +signal UN13_LOCK_CRY_21_0_COUT : std_logic ; +signal UN13_LOCK_CRY_21_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_2 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_4 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_6 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_8 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_10 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_12 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_14 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_16 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_18 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_20 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ; +signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ; +signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ; +signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ; +signal N_96 : std_logic ; +signal N_20 : std_logic ; +signal N_19 : std_logic ; +signal N_18 : std_logic ; +signal N_14 : std_logic ; +signal GND : std_logic ; +signal N_1 : std_logic ; +signal N_2 : std_logic ; +signal N_3 : std_logic ; +signal N_4 : std_logic ; +signal N_5 : std_logic ; +signal N_9 : std_logic ; +component sync_0s +port( +phb : in std_logic; +rhb_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +component sync_0s_6 +port( +rtc_pul : in std_logic; +ppul_sync : out std_logic; +sli_rst : in std_logic; +tx_pclk : in std_logic ); +end component; +component sync_0s_0 +port( +ppul_sync : in std_logic; +pdiff_sync : out std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic ); +end component; +begin +PHB_RNO: INV port map ( +A => PHB_CNT(2), +Z => PHB_CNT_I(2)); +\PHB_CNT_RNO[0]\: INV port map ( +A => PHB_CNT(0), +Z => PHB_CNT_I(0)); +PLL_LOCK_RNI6JK9: INV port map ( +A => PLL_LOCK, +Z => pll_lock_i); +RTC_CTRL4_0_A3_RNO: LUT4 +generic map( + init => X"2000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => RTC_CTRL4_0_A3_1); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_20, +B => PCOUNT(20), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_20); +UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_19, +B => PCOUNT(19), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_19); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_18, +B => PCOUNT(18), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_18); +UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_Z473: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_17, +B => PCOUNT(17), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_16, +B => PCOUNT(16), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_16); +UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_15, +B => PCOUNT(15), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_15); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_14, +B => PCOUNT(14), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_14); +UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_13, +B => PCOUNT(13), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_13); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_12, +B => PCOUNT(12), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_12); +UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_11, +B => PCOUNT(11), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_11); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_10, +B => PCOUNT(10), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_10); +UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_9, +B => PCOUNT(9), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_9); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_8, +B => PCOUNT(8), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_8); +UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_7, +B => PCOUNT(7), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_7); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_6, +B => PCOUNT(6), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_6); +UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_5, +B => PCOUNT(5), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_5); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_4, +B => PCOUNT(4), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_4); +UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_3, +B => PCOUNT(3), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_3); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_2, +B => PCOUNT(2), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_2); +UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_1, +B => PCOUNT(1), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF_1_AXB_1); +PPUL_SYNC_P3_RNIU65C: LUT4 +generic map( + init => X"2F20" +) +port map ( +A => UN13_LOCK_21, +B => PPUL_SYNC_P3, +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => N_7); +\PCOUNT_DIFF_RNO[0]\: LUT4 +generic map( + init => X"FD20" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => PCOUNT(0), +D => UN13_LOCK_0, +Z => UN1_PCOUNT_DIFF_I(0)); +RTC_CTRL_0: LUT4 +generic map( + init => X"EEEE" +) +port map ( +A => RTC_CTRL4, +B => RTC_CTRL, +C => VCC, +D => VCC, +Z => N_2136_0); +UNLOCK_REG_Z494: FD1P3DX port map ( +D => UNLOCK_5, +SP => UNLOCK_1_SQMUXA_I_0, +CK => pll_refclki, +CD => sli_rst, +Q => UNLOCK); +\SLL_STATE[1]_REG_Z496\: FD1S3DX port map ( +D => N_89_I, +CK => pll_refclki, +CD => sli_rst, +Q => SLL_STATE(1)); +RTC_PUL_P1_REG_Z498: FD1S3DX port map ( +D => RTC_PUL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL_P1); +RTC_PUL_REG_Z500: FD1P3DX port map ( +D => RTC_PUL5, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_PUL); +RTC_CTRL_REG_Z502: FD1S3DX port map ( +D => N_2136_0, +CK => pll_refclki, +CD => sli_rst, +Q => RTC_CTRL); +RSTAT_PCLK_REG_Z504: FD1P3DX port map ( +D => RSTAT_PCLK_2, +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RSTAT_PCLK); +\RHB_WAIT_CNT[0]_REG_Z506\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(0), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(0)); +\RHB_WAIT_CNT[1]_REG_Z508\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(1), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(1)); +\RHB_WAIT_CNT[2]_REG_Z510\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(2), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(2)); +\RHB_WAIT_CNT[3]_REG_Z512\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(3), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(3)); +\RHB_WAIT_CNT[4]_REG_Z514\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(4), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(4)); +\RHB_WAIT_CNT[5]_REG_Z516\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(5), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(5)); +\RHB_WAIT_CNT[6]_REG_Z518\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(6), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(6)); +\RHB_WAIT_CNT[7]_REG_Z520\: FD1P3DX port map ( +D => RHB_WAIT_CNT_S(7), +SP => RTC_CTRL, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_WAIT_CNT(7)); +RHB_SYNC_P2_REG_Z522: FD1S3DX port map ( +D => RHB_SYNC_P1, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P2); +RHB_SYNC_P1_REG_Z524: FD1S3DX port map ( +D => RHB_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => RHB_SYNC_P1); +\RCOUNT[0]_REG_Z526\: FD1S3DX port map ( +D => RCOUNT_S(0), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(0)); +\RCOUNT[1]_REG_Z528\: FD1S3DX port map ( +D => RCOUNT_S(1), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(1)); +\RCOUNT[2]_REG_Z530\: FD1S3DX port map ( +D => RCOUNT_S(2), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(2)); +\RCOUNT[3]_REG_Z532\: FD1S3DX port map ( +D => RCOUNT_S(3), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(3)); +\RCOUNT[4]_REG_Z534\: FD1S3DX port map ( +D => RCOUNT_S(4), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(4)); +\RCOUNT[5]_REG_Z536\: FD1S3DX port map ( +D => RCOUNT_S(5), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(5)); +\RCOUNT[6]_REG_Z538\: FD1S3DX port map ( +D => RCOUNT_S(6), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(6)); +\RCOUNT[7]_REG_Z540\: FD1S3DX port map ( +D => RCOUNT_S(7), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(7)); +\RCOUNT[8]_REG_Z542\: FD1S3DX port map ( +D => RCOUNT_S(8), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(8)); +\RCOUNT[9]_REG_Z544\: FD1S3DX port map ( +D => RCOUNT_S(9), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(9)); +\RCOUNT[10]_REG_Z546\: FD1S3DX port map ( +D => RCOUNT_S(10), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(10)); +\RCOUNT[11]_REG_Z548\: FD1S3DX port map ( +D => RCOUNT_S(11), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(11)); +\RCOUNT[12]_REG_Z550\: FD1S3DX port map ( +D => RCOUNT_S(12), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(12)); +\RCOUNT[13]_REG_Z552\: FD1S3DX port map ( +D => RCOUNT_S(13), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(13)); +\RCOUNT[14]_REG_Z554\: FD1S3DX port map ( +D => RCOUNT_S(14), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(14)); +\RCOUNT[15]_REG_Z556\: FD1S3DX port map ( +D => RCOUNT_S(15), +CK => pll_refclki, +CD => sli_rst, +Q => RCOUNT(15)); +PPUL_SYNC_P3_REG_Z558: FD1S3DX port map ( +D => PPUL_SYNC_P2, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P3); +PPUL_SYNC_P2_REG_Z560: FD1S3DX port map ( +D => PPUL_SYNC_P1, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P2); +PPUL_SYNC_P1_REG_Z562: FD1S3DX port map ( +D => PPUL_SYNC, +CK => tx_pclk, +CD => sli_rst, +Q => PPUL_SYNC_P1); +PLL_LOCK_REG_Z564: FD1S3DX port map ( +D => SLL_STATE(1), +CK => pll_refclki, +CD => sli_rst, +Q => PLL_LOCK); +\PHB_CNT[0]_REG_Z566\: FD1S3DX port map ( +D => PHB_CNT_I(0), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(0)); +\PHB_CNT[1]_REG_Z568\: FD1S3DX port map ( +D => PHB_CNT_RNO(1), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(1)); +\PHB_CNT[2]_REG_Z570\: FD1S3DX port map ( +D => PHB_CNT_RNO(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB_CNT(2)); +PHB_REG_Z572: FD1S3DX port map ( +D => PHB_CNT_I(2), +CK => tx_pclk, +CD => sli_rst, +Q => PHB); +PDIFF_SYNC_P1_REG_Z574: FD1S3DX port map ( +D => PDIFF_SYNC, +CK => pll_refclki, +CD => sli_rst, +Q => PDIFF_SYNC_P1); +\PCOUNT_DIFF[0]_REG_Z576\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_I(0), +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_0); +\PCOUNT[0]_REG_Z578\: FD1S3DX port map ( +D => PCOUNT_S(0), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(0)); +\PCOUNT[1]_REG_Z580\: FD1S3DX port map ( +D => PCOUNT_S(1), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(1)); +\PCOUNT_DIFF[1]_REG_Z582\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_1); +\PCOUNT_DIFF[2]_REG_Z584\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_2); +\PCOUNT[2]_REG_Z586\: FD1S3DX port map ( +D => PCOUNT_S(2), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(2)); +\PCOUNT[3]_REG_Z588\: FD1S3DX port map ( +D => PCOUNT_S(3), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(3)); +\PCOUNT_DIFF[3]_REG_Z590\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_3); +\PCOUNT_DIFF[4]_REG_Z592\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_4); +\PCOUNT[4]_REG_Z594\: FD1S3DX port map ( +D => PCOUNT_S(4), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(4)); +\PCOUNT[5]_REG_Z596\: FD1S3DX port map ( +D => PCOUNT_S(5), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(5)); +\PCOUNT_DIFF[5]_REG_Z598\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_5); +\PCOUNT_DIFF[6]_REG_Z600\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_6); +\PCOUNT[6]_REG_Z602\: FD1S3DX port map ( +D => PCOUNT_S(6), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(6)); +\PCOUNT_DIFF[7]_REG_Z604\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_7); +\PCOUNT[7]_REG_Z606\: FD1S3DX port map ( +D => PCOUNT_S(7), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(7)); +\PCOUNT[8]_REG_Z608\: FD1S3DX port map ( +D => PCOUNT_S(8), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(8)); +\PCOUNT_DIFF[8]_REG_Z610\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_8); +\PCOUNT_DIFF[9]_REG_Z612\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_9); +\PCOUNT[9]_REG_Z614\: FD1S3DX port map ( +D => PCOUNT_S(9), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(9)); +\PCOUNT[10]_REG_Z616\: FD1S3DX port map ( +D => PCOUNT_S(10), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(10)); +\PCOUNT_DIFF[10]_REG_Z618\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_10); +\PCOUNT_DIFF[11]_REG_Z620\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_11); +\PCOUNT[11]_REG_Z622\: FD1S3DX port map ( +D => PCOUNT_S(11), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(11)); +\PCOUNT[12]_REG_Z624\: FD1S3DX port map ( +D => PCOUNT_S(12), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(12)); +\PCOUNT_DIFF[12]_REG_Z626\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_12); +\PCOUNT[13]_REG_Z628\: FD1S3DX port map ( +D => PCOUNT_S(13), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(13)); +\PCOUNT_DIFF[13]_REG_Z630\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_13); +\PCOUNT_DIFF[14]_REG_Z632\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_14); +\PCOUNT[14]_REG_Z634\: FD1S3DX port map ( +D => PCOUNT_S(14), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(14)); +\PCOUNT_DIFF[15]_REG_Z636\: FD1P3BX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +SP => N_7, +CK => tx_pclk, +PD => sli_rst, +Q => UN13_LOCK_15); +\PCOUNT[15]_REG_Z638\: FD1S3DX port map ( +D => PCOUNT_S(15), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(15)); +\PCOUNT[16]_REG_Z640\: FD1S3DX port map ( +D => PCOUNT_S(16), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(16)); +\PCOUNT_DIFF[16]_REG_Z642\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_16); +\PCOUNT_DIFF[17]_REG_Z644\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_17); +\PCOUNT[17]_REG_Z646\: FD1S3DX port map ( +D => PCOUNT_S(17), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(17)); +\PCOUNT[18]_REG_Z648\: FD1S3DX port map ( +D => PCOUNT_S(18), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(18)); +\PCOUNT_DIFF[18]_REG_Z650\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_18); +\PCOUNT[19]_REG_Z652\: FD1S3DX port map ( +D => PCOUNT_S(19), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(19)); +\PCOUNT_DIFF[19]_REG_Z654\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_19); +\PCOUNT_DIFF[20]_REG_Z656\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_20); +\PCOUNT[20]_REG_Z658\: FD1S3DX port map ( +D => PCOUNT_S(20), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(20)); +\PCOUNT[21]_REG_Z660\: FD1S3DX port map ( +D => PCOUNT_S(21), +CK => tx_pclk, +CD => sli_rst, +Q => PCOUNT(21)); +\PCOUNT_DIFF[21]_REG_Z662\: FD1P3DX port map ( +D => UN1_PCOUNT_DIFF_1_S_21_0_S0, +SP => N_7, +CK => tx_pclk, +CD => sli_rst, +Q => UN13_LOCK_21); +LOCK_REG_Z664: FD1P3DX port map ( +D => LOCK_5, +SP => LOCK_1_SQMUXA_I_0, +CK => pll_refclki, +CD => sli_rst, +Q => LOCK); +\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z666\: FD1S3DX port map ( +D => VCC, +CK => pll_refclki, +CD => sli_rst, +Q => RDIFF_COMP_LOCK(2)); +RTC_PUL5_0_0: LUT4 +generic map( + init => X"FF80" +) +port map ( +A => RTC_PUL5_0_O3, +B => RTC_PUL5_0_A3_6, +C => RTC_PUL5_0_A3_7, +D => UN1_RCOUNT_1_0_A3, +Z => RTC_PUL5); +RSTAT_PCLK_2_IV_0_0: LUT4 +generic map( + init => X"5D0C" +) +port map ( +A => UN1_RHB_WAIT_CNT, +B => RHB_SYNC_P1, +C => RHB_SYNC_P2, +D => RSTAT_PCLK, +Z => RSTAT_PCLK_2); +\SLL_STATE_RNO[1]\: LUT4 +generic map( + init => X"4044" +) +port map ( +A => SLL_STATE_NS_I_0_M3(1), +B => RSTAT_PCLK, +C => SLL_STATE(1), +D => UNLOCK, +Z => N_89_I); +UN1_RHB_WAIT_CNT12_1_I_0_A3: LUT4 +generic map( + init => X"5151" +) +port map ( +A => UN1_RHB_WAIT_CNT, +B => RHB_SYNC_P1, +C => RHB_SYNC_P2, +D => VCC, +Z => N_12); +RTC_CTRL4_0_A3: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_1, +B => RTC_CTRL4_0_A3_12_4, +C => RTC_CTRL4_0_A3_12_5, +D => RTC_CTRL4_10, +Z => RTC_CTRL4); +UN1_RCOUNT_1_0_A3_Z672: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RTC_CTRL4_0_A3_12_4, +B => RTC_CTRL4_0_A3_12_5, +C => RTC_CTRL4_10, +D => UN1_RCOUNT_1_0_A3_1, +Z => UN1_RCOUNT_1_0_A3); +RTC_PUL5_0_O3_Z673: LUT4 +generic map( + init => X"AAAB" +) +port map ( +A => N_6, +B => RCOUNT(1), +C => RCOUNT(2), +D => RCOUNT(3), +Z => RTC_PUL5_0_O3); +UN1_RHB_WAIT_CNT_Z674: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(4), +B => RHB_WAIT_CNT(5), +C => UN1_RHB_WAIT_CNT_3, +D => UN1_RHB_WAIT_CNT_4, +Z => UN1_RHB_WAIT_CNT); +RTC_PUL5_0_A3_7_Z675: LUT4 +generic map( + init => X"1010" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RTC_PUL5_0_A3_5, +D => VCC, +Z => RTC_PUL5_0_A3_7); +\SLL_STATE_NS_I_0_M3[1]_Z676\: LUT4 +generic map( + init => X"10DF" +) +port map ( +A => LOCK, +B => RTC_PUL, +C => RTC_PUL_P1, +D => SLL_STATE(1), +Z => SLL_STATE_NS_I_0_M3(1)); +\PHB_CNT_RNO[2]_Z677\: LUT4 +generic map( + init => X"7878" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => PHB_CNT(2), +D => VCC, +Z => PHB_CNT_RNO(2)); +UNLOCK_1_SQMUXA_I_0_Z678: LUT4 +generic map( + init => X"4F4F" +) +port map ( +A => PDIFF_SYNC, +B => PDIFF_SYNC_P1, +C => UNLOCK, +D => VCC, +Z => UNLOCK_1_SQMUXA_I_0); +LOCK_1_SQMUXA_I_0_Z679: LUT4 +generic map( + init => X"7575" +) +port map ( +A => LOCK, +B => PDIFF_SYNC, +C => PDIFF_SYNC_P1, +D => VCC, +Z => LOCK_1_SQMUXA_I_0); +RTC_CTRL4_0_A3_10: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(1), +B => RCOUNT(3), +C => RCOUNT(6), +D => RCOUNT(15), +Z => RTC_CTRL4_10); +UN1_RHB_WAIT_CNT_4_Z681: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RHB_WAIT_CNT(0), +B => RHB_WAIT_CNT(1), +C => RHB_WAIT_CNT(2), +D => RHB_WAIT_CNT(3), +Z => UN1_RHB_WAIT_CNT_4); +RTC_CTRL4_0_A3_12_4_Z682: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(11), +B => RCOUNT(12), +C => RCOUNT(13), +D => RCOUNT(14), +Z => RTC_CTRL4_0_A3_12_4); +RTC_CTRL4_0_A3_12_5_Z683: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(7), +B => RCOUNT(8), +C => RCOUNT(9), +D => RCOUNT(10), +Z => RTC_CTRL4_0_A3_12_5); +RTC_PUL5_0_A3_5_Z684: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(6), +B => RCOUNT(13), +C => RCOUNT(14), +D => RCOUNT(15), +Z => RTC_PUL5_0_A3_5); +RTC_PUL5_0_A3_6_Z685: LUT4 +generic map( + init => X"0001" +) +port map ( +A => RCOUNT(9), +B => RCOUNT(10), +C => RCOUNT(11), +D => RCOUNT(12), +Z => RTC_PUL5_0_A3_6); +LOCK_5_Z686: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_LOCK_CRY_21_I, +C => VCC, +D => VCC, +Z => LOCK_5); +UNLOCK_5_Z687: LUT4 +generic map( + init => X"8888" +) +port map ( +A => PDIFF_SYNC, +B => UN13_UNLOCK_CRY_21, +C => VCC, +D => VCC, +Z => UNLOCK_5); +PCOUNT10_0_O3: LUT4 +generic map( + init => X"DDDD" +) +port map ( +A => PPUL_SYNC_P1, +B => PPUL_SYNC_P2, +C => VCC, +D => VCC, +Z => N_8); +\PHB_CNT_RNO[1]_Z689\: LUT4 +generic map( + init => X"6666" +) +port map ( +A => PHB_CNT(0), +B => PHB_CNT(1), +C => VCC, +D => VCC, +Z => PHB_CNT_RNO(1)); +RTC_CTRL4_0_O3: LUT4 +generic map( + init => X"7777" +) +port map ( +A => RCOUNT(4), +B => RCOUNT(5), +C => VCC, +D => VCC, +Z => N_6); +UN1_RHB_WAIT_CNT_3_Z691: LUT4 +generic map( + init => X"8888" +) +port map ( +A => RHB_WAIT_CNT(6), +B => RHB_WAIT_CNT(7), +C => VCC, +D => VCC, +Z => UN1_RHB_WAIT_CNT_3); +\UN1_PCOUNT_DIFF[0]_Z692\: LUT4 +generic map( + init => X"5355" +) +port map ( +A => UN13_LOCK_0, +B => PCOUNT(0), +C => PPUL_SYNC_P2, +D => PPUL_SYNC_P1, +Z => UN1_PCOUNT_DIFF(0)); +UN1_RCOUNT_1_0_A3_1_Z693: LUT4 +generic map( + init => X"8000" +) +port map ( +A => RCOUNT(2), +B => RCOUNT(0), +C => RCOUNT(5), +D => RCOUNT(4), +Z => UN1_RCOUNT_1_0_A3_1); +\PCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => N_8, +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_9, +COUT => PCOUNT_CRY(0), +S0 => PCOUNT_CRY_0_S0(0), +S1 => PCOUNT_S(0)); +\PCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(0), +COUT => PCOUNT_CRY(2), +S0 => PCOUNT_S(1), +S1 => PCOUNT_S(2)); +\PCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(2), +COUT => PCOUNT_CRY(4), +S0 => PCOUNT_S(3), +S1 => PCOUNT_S(4)); +\PCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(4), +COUT => PCOUNT_CRY(6), +S0 => PCOUNT_S(5), +S1 => PCOUNT_S(6)); +\PCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(6), +COUT => PCOUNT_CRY(8), +S0 => PCOUNT_S(7), +S1 => PCOUNT_S(8)); +\PCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(8), +COUT => PCOUNT_CRY(10), +S0 => PCOUNT_S(9), +S1 => PCOUNT_S(10)); +\PCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(10), +COUT => PCOUNT_CRY(12), +S0 => PCOUNT_S(11), +S1 => PCOUNT_S(12)); +\PCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(12), +COUT => PCOUNT_CRY(14), +S0 => PCOUNT_S(13), +S1 => PCOUNT_S(14)); +\PCOUNT_CRY_0[15]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(16), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(14), +COUT => PCOUNT_CRY(16), +S0 => PCOUNT_S(15), +S1 => PCOUNT_S(16)); +\PCOUNT_CRY_0[17]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(17), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(18), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(16), +COUT => PCOUNT_CRY(18), +S0 => PCOUNT_S(17), +S1 => PCOUNT_S(18)); +\PCOUNT_CRY_0[19]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(19), +C0 => VCC, +D0 => VCC, +A1 => N_8, +B1 => PCOUNT(20), +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(18), +COUT => PCOUNT_CRY(20), +S0 => PCOUNT_S(19), +S1 => PCOUNT_S(20)); +\PCOUNT_S_0[21]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => PCOUNT(21), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => PCOUNT_CRY(20), +COUT => PCOUNT_S_0_COUT(21), +S0 => PCOUNT_S(21), +S1 => PCOUNT_S_0_S1(21)); +\RCOUNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => UN1_RCOUNT_1_0_A3, +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_5, +COUT => RCOUNT_CRY(0), +S0 => RCOUNT_CRY_0_S0(0), +S1 => RCOUNT_S(0)); +\RCOUNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(1), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(2), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(0), +COUT => RCOUNT_CRY(2), +S0 => RCOUNT_S(1), +S1 => RCOUNT_S(2)); +\RCOUNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(3), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(4), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(2), +COUT => RCOUNT_CRY(4), +S0 => RCOUNT_S(3), +S1 => RCOUNT_S(4)); +\RCOUNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(5), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(6), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(4), +COUT => RCOUNT_CRY(6), +S0 => RCOUNT_S(5), +S1 => RCOUNT_S(6)); +\RCOUNT_CRY_0[7]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(7), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(8), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(6), +COUT => RCOUNT_CRY(8), +S0 => RCOUNT_S(7), +S1 => RCOUNT_S(8)); +\RCOUNT_CRY_0[9]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(9), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(10), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(8), +COUT => RCOUNT_CRY(10), +S0 => RCOUNT_S(9), +S1 => RCOUNT_S(10)); +\RCOUNT_CRY_0[11]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(11), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(12), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(10), +COUT => RCOUNT_CRY(12), +S0 => RCOUNT_S(11), +S1 => RCOUNT_S(12)); +\RCOUNT_CRY_0[13]\: CCU2C +generic map( + INIT0 => X"4000", + INIT1 => X"4000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(13), +C0 => VCC, +D0 => VCC, +A1 => UN1_RCOUNT_1_0_A3, +B1 => RCOUNT(14), +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(12), +COUT => RCOUNT_CRY(14), +S0 => RCOUNT_S(13), +S1 => RCOUNT_S(14)); +\RCOUNT_S_0[15]\: CCU2C +generic map( + INIT0 => X"4005", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_RCOUNT_1_0_A3, +B0 => RCOUNT(15), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RCOUNT_CRY(14), +COUT => RCOUNT_S_0_COUT(15), +S0 => RCOUNT_S(15), +S1 => RCOUNT_S_0_S1(15)); +\RHB_WAIT_CNT_CRY_0[0]\: CCU2C +generic map( + INIT0 => X"500c", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => N_12, +C0 => VCC, +D0 => VCC, +A1 => N_12, +B1 => RHB_WAIT_CNT(0), +C1 => VCC, +D1 => VCC, +CIN => N_4, +COUT => RHB_WAIT_CNT_CRY(0), +S0 => RHB_WAIT_CNT_CRY_0_S0(0), +S1 => RHB_WAIT_CNT_S(0)); +\RHB_WAIT_CNT_CRY_0[1]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_12, +B0 => RHB_WAIT_CNT(1), +C0 => VCC, +D0 => VCC, +A1 => N_12, +B1 => RHB_WAIT_CNT(2), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(0), +COUT => RHB_WAIT_CNT_CRY(2), +S0 => RHB_WAIT_CNT_S(1), +S1 => RHB_WAIT_CNT_S(2)); +\RHB_WAIT_CNT_CRY_0[3]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_12, +B0 => RHB_WAIT_CNT(3), +C0 => VCC, +D0 => VCC, +A1 => N_12, +B1 => RHB_WAIT_CNT(4), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(2), +COUT => RHB_WAIT_CNT_CRY(4), +S0 => RHB_WAIT_CNT_S(3), +S1 => RHB_WAIT_CNT_S(4)); +\RHB_WAIT_CNT_CRY_0[5]\: CCU2C +generic map( + INIT0 => X"8000", + INIT1 => X"8000", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_12, +B0 => RHB_WAIT_CNT(5), +C0 => VCC, +D0 => VCC, +A1 => N_12, +B1 => RHB_WAIT_CNT(6), +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(4), +COUT => RHB_WAIT_CNT_CRY(6), +S0 => RHB_WAIT_CNT_S(5), +S1 => RHB_WAIT_CNT_S(6)); +\RHB_WAIT_CNT_S_0[7]\: CCU2C +generic map( + INIT0 => X"800a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_12, +B0 => RHB_WAIT_CNT(7), +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => RHB_WAIT_CNT_CRY(6), +COUT => RHB_WAIT_CNT_S_0_COUT(7), +S0 => RHB_WAIT_CNT_S(7), +S1 => RHB_WAIT_CNT_S_0_S1(7)); +UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500f", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF(0), +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_3, +COUT => UN1_PCOUNT_DIFF_1_CRY_0, +S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1); +UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_1, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_2, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_0, +COUT => UN1_PCOUNT_DIFF_1_CRY_2, +S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1); +UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_2, +COUT => UN1_PCOUNT_DIFF_1_CRY_4, +S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1); +UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_4, +COUT => UN1_PCOUNT_DIFF_1_CRY_6, +S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1); +UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_6, +COUT => UN1_PCOUNT_DIFF_1_CRY_8, +S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1); +UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_8, +COUT => UN1_PCOUNT_DIFF_1_CRY_10, +S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1); +UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_10, +COUT => UN1_PCOUNT_DIFF_1_CRY_12, +S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1); +UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_12, +COUT => UN1_PCOUNT_DIFF_1_CRY_14, +S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1); +UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_14, +COUT => UN1_PCOUNT_DIFF_1_CRY_16, +S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1); +UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C +generic map( + INIT0 => X"b404", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => N_8, +B0 => RDIFF_COMP_LOCK(2), +C0 => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_16, +COUT => UN1_PCOUNT_DIFF_1_CRY_18, +S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1); +UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C +generic map( + INIT0 => X"a003", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN1_PCOUNT_DIFF_1_AXB_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN1_PCOUNT_DIFF_1_AXB_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_18, +COUT => UN1_PCOUNT_DIFF_1_CRY_20, +S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0, +S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1); +UN1_PCOUNT_DIFF_1_S_21_0: CCU2C +generic map( + INIT0 => X"350a", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => PCOUNT(21), +B0 => UN13_LOCK_21, +C0 => N_8, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN1_PCOUNT_DIFF_1_CRY_20, +COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT, +S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0, +S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1); +UN13_LOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => N_2, +COUT => UN13_LOCK_CRY_0, +S0 => UN13_LOCK_CRY_0_0_S0, +S1 => UN13_LOCK_CRY_0_0_S1); +UN13_LOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_0, +COUT => UN13_LOCK_CRY_2, +S0 => UN13_LOCK_CRY_1_0_S0, +S1 => UN13_LOCK_CRY_1_0_S1); +UN13_LOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_2, +COUT => UN13_LOCK_CRY_4, +S0 => UN13_LOCK_CRY_3_0_S0, +S1 => UN13_LOCK_CRY_3_0_S1); +UN13_LOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_4, +COUT => UN13_LOCK_CRY_6, +S0 => UN13_LOCK_CRY_5_0_S0, +S1 => UN13_LOCK_CRY_5_0_S1); +UN13_LOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_6, +COUT => UN13_LOCK_CRY_8, +S0 => UN13_LOCK_CRY_7_0_S0, +S1 => UN13_LOCK_CRY_7_0_S1); +UN13_LOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_8, +COUT => UN13_LOCK_CRY_10, +S0 => UN13_LOCK_CRY_9_0_S0, +S1 => UN13_LOCK_CRY_9_0_S1); +UN13_LOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_10, +COUT => UN13_LOCK_CRY_12, +S0 => UN13_LOCK_CRY_11_0_S0, +S1 => UN13_LOCK_CRY_11_0_S1); +UN13_LOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_12, +COUT => UN13_LOCK_CRY_14, +S0 => UN13_LOCK_CRY_13_0_S0, +S1 => UN13_LOCK_CRY_13_0_S1); +UN13_LOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_14, +COUT => UN13_LOCK_CRY_16, +S0 => UN13_LOCK_CRY_15_0_S0, +S1 => UN13_LOCK_CRY_15_0_S1); +UN13_LOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_16, +COUT => UN13_LOCK_CRY_18, +S0 => UN13_LOCK_CRY_17_0_S0, +S1 => UN13_LOCK_CRY_17_0_S1); +UN13_LOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_18, +COUT => UN13_LOCK_CRY_20, +S0 => UN13_LOCK_CRY_19_0_S0, +S1 => UN13_LOCK_CRY_19_0_S1); +UN13_LOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"a003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_LOCK_CRY_20, +COUT => UN13_LOCK_CRY_21_0_COUT, +S0 => UN13_LOCK_CRY_21_0_S0, +S1 => UN13_LOCK_CRY_21_I); +UN13_UNLOCK_CRY_0_0: CCU2C +generic map( + INIT0 => X"5003", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => VCC, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_0, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => N_1, +COUT => UN13_UNLOCK_CRY_0, +S0 => UN13_UNLOCK_CRY_0_0_S0, +S1 => UN13_UNLOCK_CRY_0_0_S1); +UN13_UNLOCK_CRY_1_0: CCU2C +generic map( + INIT0 => X"900a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_1, +B0 => RDIFF_COMP_LOCK(2), +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_2, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_0, +COUT => UN13_UNLOCK_CRY_2, +S0 => UN13_UNLOCK_CRY_1_0_S0, +S1 => UN13_UNLOCK_CRY_1_0_S1); +UN13_UNLOCK_CRY_3_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_3, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_4, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_2, +COUT => UN13_UNLOCK_CRY_4, +S0 => UN13_UNLOCK_CRY_3_0_S0, +S1 => UN13_UNLOCK_CRY_3_0_S1); +UN13_UNLOCK_CRY_5_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_5, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_6, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_4, +COUT => UN13_UNLOCK_CRY_6, +S0 => UN13_UNLOCK_CRY_5_0_S0, +S1 => UN13_UNLOCK_CRY_5_0_S1); +UN13_UNLOCK_CRY_7_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"900a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_7, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_8, +B1 => RDIFF_COMP_LOCK(2), +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_6, +COUT => UN13_UNLOCK_CRY_8, +S0 => UN13_UNLOCK_CRY_7_0_S0, +S1 => UN13_UNLOCK_CRY_7_0_S1); +UN13_UNLOCK_CRY_9_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_9, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_10, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_8, +COUT => UN13_UNLOCK_CRY_10, +S0 => UN13_UNLOCK_CRY_9_0_S0, +S1 => UN13_UNLOCK_CRY_9_0_S1); +UN13_UNLOCK_CRY_11_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_11, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_12, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_10, +COUT => UN13_UNLOCK_CRY_12, +S0 => UN13_UNLOCK_CRY_11_0_S0, +S1 => UN13_UNLOCK_CRY_11_0_S1); +UN13_UNLOCK_CRY_13_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_13, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_14, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_12, +COUT => UN13_UNLOCK_CRY_14, +S0 => UN13_UNLOCK_CRY_13_0_S0, +S1 => UN13_UNLOCK_CRY_13_0_S1); +UN13_UNLOCK_CRY_15_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_15, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_16, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_14, +COUT => UN13_UNLOCK_CRY_16, +S0 => UN13_UNLOCK_CRY_15_0_S0, +S1 => UN13_UNLOCK_CRY_15_0_S1); +UN13_UNLOCK_CRY_17_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_17, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_18, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_16, +COUT => UN13_UNLOCK_CRY_18, +S0 => UN13_UNLOCK_CRY_17_0_S0, +S1 => UN13_UNLOCK_CRY_17_0_S1); +UN13_UNLOCK_CRY_19_0: CCU2C +generic map( + INIT0 => X"500a", + INIT1 => X"500a", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_19, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => UN13_LOCK_20, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_18, +COUT => UN13_UNLOCK_CRY_20, +S0 => UN13_UNLOCK_CRY_19_0_S0, +S1 => UN13_UNLOCK_CRY_19_0_S1); +UN13_UNLOCK_CRY_21_0: CCU2C +generic map( + INIT0 => X"500f", + INIT1 => X"5003", + INJECT1_0 => "NO", + INJECT1_1 => "NO" +) +port map ( +A0 => UN13_LOCK_21, +B0 => VCC, +C0 => VCC, +D0 => VCC, +A1 => VCC, +B1 => VCC, +C1 => VCC, +D1 => VCC, +CIN => UN13_UNLOCK_CRY_20, +COUT => UN13_UNLOCK_CRY_21_0_COUT, +S0 => UN13_UNLOCK_CRY_21_0_S0, +S1 => UN13_UNLOCK_CRY_21); +PHB_SYNC_INST: sync_0s port map ( +phb => PHB, +rhb_sync => RHB_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +RTC_SYNC_INST: sync_0s_6 port map ( +rtc_pul => RTC_PUL, +ppul_sync => PPUL_SYNC, +sli_rst => sli_rst, +tx_pclk => tx_pclk); +PDIFF_SYNC_INST: sync_0s_0 port map ( +ppul_sync => PPUL_SYNC, +pdiff_sync => PDIFF_SYNC, +sli_rst => sli_rst, +pll_refclki => pll_refclki); +VCC_0: VHI port map ( +Z => VCC); +II_GND: VLO port map ( +Z => GND); +end beh; + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity serdes_sync_1 is +port( +hdoutp : out std_logic; +hdoutn : out std_logic; +hdinp : in std_logic; +hdinn : in std_logic; +rxrefclk : in std_logic; +rx_pclk : out std_logic; +tx_pclk : out std_logic; +txdata : in std_logic_vector(7 downto 0); +tx_k : in std_logic_vector(0 downto 0); +tx_force_disp : in std_logic_vector(0 downto 0); +tx_disp_sel : in std_logic_vector(0 downto 0); +rxdata : out std_logic_vector(7 downto 0); +rx_k : out std_logic_vector(0 downto 0); +rx_disp_err : out std_logic_vector(0 downto 0); +rx_cv_err : out std_logic_vector(0 downto 0); +tx_idle_c : in std_logic; +signal_detect_c : in std_logic; +rx_los_low_s : out std_logic; +lsm_status_s : out std_logic; +rx_cdr_lol_s : out std_logic; +sli_rst : in std_logic; +tx_pwrup_c : in std_logic; +rx_pwrup_c : in std_logic; +sci_wrdata : in std_logic_vector(7 downto 0); +sci_addr : in std_logic_vector(5 downto 0); +sci_rddata : out std_logic_vector(7 downto 0); +sci_en_dual : in std_logic; +sci_sel_dual : in std_logic; +sci_en : in std_logic; +sci_sel : in std_logic; +sci_rd : in std_logic; +sci_wrn : in std_logic; +sci_int : out std_logic; +cyawstn : in std_logic; +serdes_pdb : in std_logic; +pll_refclki : in std_logic; +rsl_disable : in std_logic; +rsl_rst : in std_logic; +serdes_rst_dual_c : in std_logic; +rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +tx_pcs_rst_c : in std_logic; +pll_lol : out std_logic; +rsl_tx_rdy : out std_logic; +rx_serdes_rst_c : in std_logic; +rx_pcs_rst_c : in std_logic; +rsl_rx_rdy : out std_logic); +end serdes_sync_1; + +architecture beh of serdes_sync_1 is +signal RX_PCLK_11 : std_logic ; +signal TX_PCLK_12 : std_logic ; +signal RX_LOS_LOW_S_13 : std_logic ; +signal RX_CDR_LOL_S_14 : std_logic ; +signal RSL_TX_PCS_RST_C : std_logic ; +signal RSL_RX_PCS_RST_C : std_logic ; +signal RSL_RX_SERDES_RST_C : std_logic ; +signal RSL_SERDES_RST_DUAL_C : std_logic ; +signal RSL_TX_SERDES_RST_C : std_logic ; +signal N50_1 : std_logic ; +signal N51_1 : std_logic ; +signal N1_1 : std_logic ; +signal N2_1 : std_logic ; +signal N3_1 : std_logic ; +signal N4_1 : std_logic ; +signal N5_1 : std_logic ; +signal N52_1 : std_logic ; +signal N6_1 : std_logic ; +signal N53_1 : std_logic ; +signal N7_1 : std_logic ; +signal N54_1 : std_logic ; +signal N8_1 : std_logic ; +signal N55_1 : std_logic ; +signal N56_1 : std_logic ; +signal N57_1 : std_logic ; +signal N58_1 : std_logic ; +signal N59_1 : std_logic ; +signal N60_1 : std_logic ; +signal N61_1 : std_logic ; +signal N62_1 : std_logic ; +signal N63_1 : std_logic ; +signal N64_1 : std_logic ; +signal N65_1 : std_logic ; +signal N66_1 : std_logic ; +signal N67_1 : std_logic ; +signal N68_1 : std_logic ; +signal N9_1 : std_logic ; +signal N69_1 : std_logic ; +signal N70_1 : std_logic ; +signal N71_1 : std_logic ; +signal N72_1 : std_logic ; +signal N73_1 : std_logic ; +signal N74_1 : std_logic ; +signal N75_1 : std_logic ; +signal N76_1 : std_logic ; +signal N77_1 : std_logic ; +signal N78_1 : std_logic ; +signal N79_1 : std_logic ; +signal N80_1 : std_logic ; +signal N81_1 : std_logic ; +signal N82_1 : std_logic ; +signal N83_1 : std_logic ; +signal N84_1 : std_logic ; +signal N85_1 : std_logic ; +signal N86_1 : std_logic ; +signal N87_1 : std_logic ; +signal N88_1 : std_logic ; +signal N89_1 : std_logic ; +signal N90_1 : std_logic ; +signal N91_1 : std_logic ; +signal N10_1 : std_logic ; +signal N92_1 : std_logic ; +signal N11_1 : std_logic ; +signal N93_1 : std_logic ; +signal N12_1 : std_logic ; +signal N94_1 : std_logic ; +signal N95_1 : std_logic ; +signal N96_1 : std_logic ; +signal N13_1 : std_logic ; +signal N97_1 : std_logic ; +signal N14_1 : std_logic ; +signal N98_1 : std_logic ; +signal N15_1 : std_logic ; +signal N99_1 : std_logic ; +signal N16_1 : std_logic ; +signal N100_1 : std_logic ; +signal N101_1 : std_logic ; +signal N17_1 : std_logic ; +signal N102_1 : std_logic ; +signal N18_1 : std_logic ; +signal N103_1 : std_logic ; +signal N104_1 : std_logic ; +signal N115_1 : std_logic ; +signal N19_1 : std_logic ; +signal N20_1 : std_logic ; +signal N21_1 : std_logic ; +signal N22_1 : std_logic ; +signal N23_1 : std_logic ; +signal N24_1 : std_logic ; +signal N25_1 : std_logic ; +signal N26_1 : std_logic ; +signal N27_1 : std_logic ; +signal N28_1 : std_logic ; +signal N29_1 : std_logic ; +signal N30_1 : std_logic ; +signal N31_1 : std_logic ; +signal N32_1 : std_logic ; +signal N33_1 : std_logic ; +signal N34_1 : std_logic ; +signal N35_1 : std_logic ; +signal N36_1 : std_logic ; +signal N37_1 : std_logic ; +signal N38_1 : std_logic ; +signal N39_1 : std_logic ; +signal N40_1 : std_logic ; +signal N41_1 : std_logic ; +signal N42_1 : std_logic ; +signal N43_1 : std_logic ; +signal N44_1 : std_logic ; +signal N45_1 : std_logic ; +signal N46_1 : std_logic ; +signal N49_1 : std_logic ; +signal TX_PCLK_I : std_logic ; +signal GND : std_logic ; +signal VCC : std_logic ; +signal \SLL_INST.PLL_LOCK_I_15\ : std_logic ; +component serdes_sync_1sll_core_Z1_layer1 +port( +tx_pclk : in std_logic; +sli_rst : in std_logic; +pll_refclki : in std_logic; +pll_lock_i : out std_logic ); +end component; +component serdes_sync_1rsl_core_Z2_layer1 +port( +rx_pcs_rst_c : in std_logic; +serdes_rst_dual_c : in std_logic; +tx_serdes_rst_c : in std_logic; +rsl_tx_pcs_rst_c : out std_logic; +rst_dual_c : in std_logic; +rsl_rx_pcs_rst_c : out std_logic; +rsl_tx_serdes_rst_c : out std_logic; +rsl_tx_rdy : out std_logic; +pll_lock_i : in std_logic; +pll_refclki : in std_logic; +rsl_rx_rdy : out std_logic; +rx_cdr_lol_s : in std_logic; +rx_los_low_s : in std_logic; +rsl_rst : in std_logic; +rxrefclk : in std_logic; +rx_serdes_rst_c : in std_logic; +rsl_rx_serdes_rst_c : out std_logic; +rsl_serdes_rst_dual_c : out std_logic; +rsl_disable : in std_logic; +tx_pcs_rst_c : in std_logic ); +end component; +begin +GND_0: VLO port map ( +Z => GND); +VCC_0: VHI port map ( +Z => VCC); +PUR_INST: PUR port map ( +PUR => VCC); +GSR_INST: GSR port map ( +GSR => VCC); +TX_PCLK_12 <= TX_PCLK_I; +DCU0_INST: DCUA +generic map( + D_MACROPDB => "0b1", + D_IB_PWDNB => "0b1", + D_XGE_MODE => "0b0", + D_LOW_MARK => "0d4", + D_HIGH_MARK => "0d12", + D_BUS8BIT_SEL => "0b0", + D_CDR_LOL_SET => "0b11", + D_BITCLK_LOCAL_EN => "0b1", + D_BITCLK_ND_EN => "0b0", + D_BITCLK_FROM_ND_EN => "0b0", + D_SYNC_LOCAL_EN => "0b1", + D_SYNC_ND_EN => "0b0", + CH0_UC_MODE => "0b1", + CH0_PCIE_MODE => "0b0", + CH0_RIO_MODE => "0b0", + CH0_WA_MODE => "0b0", + CH0_INVERT_RX => "0b0", + CH0_INVERT_TX => "0b0", + CH0_PRBS_SELECTION => "0b0", + CH0_GE_AN_ENABLE => "0b0", + CH0_PRBS_LOCK => "0b0", + CH0_PRBS_ENABLE => "0b0", + CH0_ENABLE_CG_ALIGN => "0b1", + CH0_TX_GEAR_MODE => "0b0", + CH0_RX_GEAR_MODE => "0b0", + CH0_PCS_DET_TIME_SEL => "0b00", + CH0_PCIE_EI_EN => "0b0", + CH0_TX_GEAR_BYPASS => "0b0", + CH0_ENC_BYPASS => "0b0", + CH0_SB_BYPASS => "0b0", + CH0_RX_SB_BYPASS => "0b0", + CH0_WA_BYPASS => "0b0", + CH0_DEC_BYPASS => "0b0", + CH0_CTC_BYPASS => "0b1", + CH0_RX_GEAR_BYPASS => "0b0", + CH0_LSM_DISABLE => "0b0", + CH0_MATCH_2_ENABLE => "0b0", + CH0_MATCH_4_ENABLE => "0b1", + CH0_MIN_IPG_CNT => "0b11", + CH0_CC_MATCH_1 => "0x1BC", + CH0_CC_MATCH_2 => "0x11C", + CH0_CC_MATCH_3 => "0x11C", + CH0_CC_MATCH_4 => "0x11C", + CH0_UDF_COMMA_MASK => "0x0ff", + CH0_UDF_COMMA_A => "0x083", + CH0_UDF_COMMA_B => "0x07C", + CH0_RX_DCO_CK_DIV => "0b010", + CH0_RCV_DCC_EN => "0b0", + CH0_REQ_LVL_SET => "0b00", + CH0_REQ_EN => "0b1", + CH0_RTERM_RX => "0d22", + CH0_PDEN_SEL => "0b1", + CH0_LDR_RX2CORE_SEL => "0b0", + CH0_LDR_CORE2TX_SEL => "0b0", + CH0_TPWDNB => "0b1", + CH0_RATE_MODE_TX => "0b0", + CH0_RTERM_TX => "0d19", + CH0_TX_CM_SEL => "0b00", + CH0_TDRV_PRE_EN => "0b0", + CH0_TDRV_SLICE0_SEL => "0b00", + CH0_TDRV_SLICE1_SEL => "0b00", + CH0_TDRV_SLICE2_SEL => "0b01", + CH0_TDRV_SLICE3_SEL => "0b01", + CH0_TDRV_SLICE4_SEL => "0b01", + CH0_TDRV_SLICE5_SEL => "0b00", + CH0_TDRV_SLICE0_CUR => "0b000", + CH0_TDRV_SLICE1_CUR => "0b000", + CH0_TDRV_SLICE2_CUR => "0b11", + CH0_TDRV_SLICE3_CUR => "0b11", + CH0_TDRV_SLICE4_CUR => "0b01", + CH0_TDRV_SLICE5_CUR => "0b00", + CH0_TDRV_DAT_SEL => "0b00", + CH0_TX_DIV11_SEL => "0b0", + CH0_RPWDNB => "0b1", + CH0_RATE_MODE_RX => "0b0", + CH0_RLOS_SEL => "0b1", + CH0_RX_LOS_LVL => "0b100", + CH0_RX_LOS_CEQ => "0b11", + CH0_RX_LOS_HYST_EN => "0b0", + CH0_RX_LOS_EN => "0b1", + CH0_RX_DIV11_SEL => "0b0", + CH0_SEL_SD_RX_CLK => "0b1", + CH0_FF_RX_H_CLK_EN => "0b0", + CH0_FF_RX_F_CLK_DIS => "0b0", + CH0_FF_TX_H_CLK_EN => "0b0", + CH0_FF_TX_F_CLK_DIS => "0b0", + CH0_RX_RATE_SEL => "0d10", + CH0_TDRV_POST_EN => "0b0", + CH0_TX_POST_SIGN => "0b0", + CH0_TX_PRE_SIGN => "0b0", + CH0_RXTERM_CM => "0b11", + CH0_RXIN_CM => "0b11", + CH0_LEQ_OFFSET_SEL => "0b0", + CH0_LEQ_OFFSET_TRIM => "0b000", + D_TX_MAX_RATE => "1.25", + CH0_CDR_MAX_RATE => "1.25", + CH0_TXAMPLITUDE => "0d800", + CH0_TXDEPRE => "DISABLED", + CH0_TXDEPOST => "DISABLED", + CH0_PROTOCOL => "G8B10B", + D_ISETLOS => "0d0", + D_SETIRPOLY_AUX => "0b00", + D_SETICONST_AUX => "0b00", + D_SETIRPOLY_CH => "0b00", + D_SETICONST_CH => "0b00", + D_REQ_ISET => "0b000", + D_PD_ISET => "0b00", + D_DCO_CALIB_TIME_SEL => "0b00", + CH0_DCOCTLGI => "0b010", + CH0_DCOATDDLY => "0b00", + CH0_DCOATDCFG => "0b00", + CH0_DCOBYPSATD => "0b1", + CH0_DCOSCALEI => "0b00", + CH0_DCOITUNE4LSB => "0b111", + CH0_DCOIOSTUNE => "0b000", + CH0_DCODISBDAVOID => "0b0", + CH0_DCOCALDIV => "0b001", + CH0_DCONUOFLSB => "0b101", + CH0_DCOIUPDNX2 => "0b1", + CH0_DCOSTEP => "0b00", + CH0_DCOSTARTVAL => "0b000", + CH0_DCOFLTDAC => "0b01", + CH0_DCOITUNE => "0b00", + CH0_DCOFTNRG => "0b110", + CH0_CDR_CNT4SEL => "0b00", + CH0_CDR_CNT8SEL => "0b00", + CH0_BAND_THRESHOLD => "0d0", + CH0_AUTO_FACQ_EN => "0b1", + CH0_AUTO_CALIB_EN => "0b1", + CH0_CALIB_CK_MODE => "0b0", + CH0_REG_BAND_OFFSET => "0d0", + CH0_REG_BAND_SEL => "0d0", + CH0_REG_IDAC_SEL => "0d0", + CH0_REG_IDAC_EN => "0b0", + D_TXPLL_PWDNB => "0b1", + D_SETPLLRC => "0d1", + D_REFCK_MODE => "0b001", + D_TX_VCO_CK_DIV => "0b010", + D_PLL_LOL_SET => "0b01", + D_RG_EN => "0b0", + D_RG_SET => "0b00", + D_CMUSETISCL4VCO => "0b000", + D_CMUSETI4VCO => "0b00", + D_CMUSETINITVCT => "0b00", + D_CMUSETZGM => "0b000", + D_CMUSETP2AGM => "0b000", + D_CMUSETP1GM => "0b000", + D_CMUSETI4CPZ => "0d0", + D_CMUSETI4CPP => "0d0", + D_CMUSETICP4Z => "0b101", + D_CMUSETICP4P => "0b11", + D_CMUSETBIASI => "0b00" +) +port map ( +CH0_HDINP => hdinp, +CH1_HDINP => GND, +CH0_HDINN => hdinn, +CH1_HDINN => GND, +D_TXBIT_CLKP_FROM_ND => GND, +D_TXBIT_CLKN_FROM_ND => GND, +D_SYNC_ND => GND, +D_TXPLL_LOL_FROM_ND => GND, +CH0_RX_REFCLK => rxrefclk, +CH1_RX_REFCLK => GND, +CH0_FF_RXI_CLK => RX_PCLK_11, +CH1_FF_RXI_CLK => VCC, +CH0_FF_TXI_CLK => TX_PCLK_12, +CH1_FF_TXI_CLK => VCC, +CH0_FF_EBRD_CLK => VCC, +CH1_FF_EBRD_CLK => VCC, +CH0_FF_TX_D_0 => txdata(0), +CH1_FF_TX_D_0 => GND, +CH0_FF_TX_D_1 => txdata(1), +CH1_FF_TX_D_1 => GND, +CH0_FF_TX_D_2 => txdata(2), +CH1_FF_TX_D_2 => GND, +CH0_FF_TX_D_3 => txdata(3), +CH1_FF_TX_D_3 => GND, +CH0_FF_TX_D_4 => txdata(4), +CH1_FF_TX_D_4 => GND, +CH0_FF_TX_D_5 => txdata(5), +CH1_FF_TX_D_5 => GND, +CH0_FF_TX_D_6 => txdata(6), +CH1_FF_TX_D_6 => GND, +CH0_FF_TX_D_7 => txdata(7), +CH1_FF_TX_D_7 => GND, +CH0_FF_TX_D_8 => tx_k(0), +CH1_FF_TX_D_8 => GND, +CH0_FF_TX_D_9 => tx_force_disp(0), +CH1_FF_TX_D_9 => GND, +CH0_FF_TX_D_10 => tx_disp_sel(0), +CH1_FF_TX_D_10 => GND, +CH0_FF_TX_D_11 => GND, +CH1_FF_TX_D_11 => GND, +CH0_FF_TX_D_12 => GND, +CH1_FF_TX_D_12 => GND, +CH0_FF_TX_D_13 => GND, +CH1_FF_TX_D_13 => GND, +CH0_FF_TX_D_14 => GND, +CH1_FF_TX_D_14 => GND, +CH0_FF_TX_D_15 => GND, +CH1_FF_TX_D_15 => GND, +CH0_FF_TX_D_16 => GND, +CH1_FF_TX_D_16 => GND, +CH0_FF_TX_D_17 => GND, +CH1_FF_TX_D_17 => GND, +CH0_FF_TX_D_18 => GND, +CH1_FF_TX_D_18 => GND, +CH0_FF_TX_D_19 => GND, +CH1_FF_TX_D_19 => GND, +CH0_FF_TX_D_20 => GND, +CH1_FF_TX_D_20 => GND, +CH0_FF_TX_D_21 => GND, +CH1_FF_TX_D_21 => GND, +CH0_FF_TX_D_22 => GND, +CH1_FF_TX_D_22 => GND, +CH0_FF_TX_D_23 => GND, +CH1_FF_TX_D_23 => GND, +CH0_FFC_EI_EN => tx_idle_c, +CH1_FFC_EI_EN => GND, +CH0_FFC_PCIE_DET_EN => GND, +CH1_FFC_PCIE_DET_EN => GND, +CH0_FFC_PCIE_CT => GND, +CH1_FFC_PCIE_CT => GND, +CH0_FFC_SB_INV_RX => GND, +CH1_FFC_SB_INV_RX => GND, +CH0_FFC_ENABLE_CGALIGN => GND, +CH1_FFC_ENABLE_CGALIGN => GND, +CH0_FFC_SIGNAL_DETECT => signal_detect_c, +CH1_FFC_SIGNAL_DETECT => GND, +CH0_FFC_FB_LOOPBACK => GND, +CH1_FFC_FB_LOOPBACK => GND, +CH0_FFC_SB_PFIFO_LP => GND, +CH1_FFC_SB_PFIFO_LP => GND, +CH0_FFC_PFIFO_CLR => GND, +CH1_FFC_PFIFO_CLR => GND, +CH0_FFC_RATE_MODE_RX => GND, +CH1_FFC_RATE_MODE_RX => GND, +CH0_FFC_RATE_MODE_TX => GND, +CH1_FFC_RATE_MODE_TX => GND, +CH0_FFC_DIV11_MODE_RX => GND, +CH1_FFC_DIV11_MODE_RX => GND, +CH0_FFC_RX_GEAR_MODE => GND, +CH1_FFC_RX_GEAR_MODE => GND, +CH0_FFC_TX_GEAR_MODE => GND, +CH1_FFC_TX_GEAR_MODE => GND, +CH0_FFC_DIV11_MODE_TX => GND, +CH1_FFC_DIV11_MODE_TX => GND, +CH0_FFC_LDR_CORE2TX_EN => GND, +CH1_FFC_LDR_CORE2TX_EN => GND, +CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C, +CH1_FFC_LANE_TX_RST => GND, +CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C, +CH1_FFC_LANE_RX_RST => GND, +CH0_FFC_RRST => RSL_RX_SERDES_RST_C, +CH1_FFC_RRST => GND, +CH0_FFC_TXPWDNB => tx_pwrup_c, +CH1_FFC_TXPWDNB => GND, +CH0_FFC_RXPWDNB => rx_pwrup_c, +CH1_FFC_RXPWDNB => GND, +CH0_LDR_CORE2TX => GND, +CH1_LDR_CORE2TX => GND, +D_SCIWDATA0 => sci_wrdata(0), +D_SCIWDATA1 => sci_wrdata(1), +D_SCIWDATA2 => sci_wrdata(2), +D_SCIWDATA3 => sci_wrdata(3), +D_SCIWDATA4 => sci_wrdata(4), +D_SCIWDATA5 => sci_wrdata(5), +D_SCIWDATA6 => sci_wrdata(6), +D_SCIWDATA7 => sci_wrdata(7), +D_SCIADDR0 => sci_addr(0), +D_SCIADDR1 => sci_addr(1), +D_SCIADDR2 => sci_addr(2), +D_SCIADDR3 => sci_addr(3), +D_SCIADDR4 => sci_addr(4), +D_SCIADDR5 => sci_addr(5), +D_SCIENAUX => sci_en_dual, +D_SCISELAUX => sci_sel_dual, +CH0_SCIEN => sci_en, +CH1_SCIEN => GND, +CH0_SCISEL => sci_sel, +CH1_SCISEL => GND, +D_SCIRD => sci_rd, +D_SCIWSTN => sci_wrn, +D_CYAWSTN => cyawstn, +D_FFC_SYNC_TOGGLE => GND, +D_FFC_DUAL_RST => rst_dual_c, +D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C, +D_FFC_MACROPDB => serdes_pdb, +D_FFC_TRST => RSL_TX_SERDES_RST_C, +CH0_FFC_CDR_EN_BITSLIP => GND, +CH1_FFC_CDR_EN_BITSLIP => GND, +D_SCAN_ENABLE => GND, +D_SCAN_IN_0 => GND, +D_SCAN_IN_1 => GND, +D_SCAN_IN_2 => GND, +D_SCAN_IN_3 => GND, +D_SCAN_IN_4 => GND, +D_SCAN_IN_5 => GND, +D_SCAN_IN_6 => GND, +D_SCAN_IN_7 => GND, +D_SCAN_MODE => GND, +D_SCAN_RESET => GND, +D_CIN0 => GND, +D_CIN1 => GND, +D_CIN2 => GND, +D_CIN3 => GND, +D_CIN4 => GND, +D_CIN5 => GND, +D_CIN6 => GND, +D_CIN7 => GND, +D_CIN8 => GND, +D_CIN9 => GND, +D_CIN10 => GND, +D_CIN11 => GND, +CH0_HDOUTP => hdoutp, +CH1_HDOUTP => N50_1, +CH0_HDOUTN => hdoutn, +CH1_HDOUTN => N51_1, +D_TXBIT_CLKP_TO_ND => N1_1, +D_TXBIT_CLKN_TO_ND => N2_1, +D_SYNC_PULSE2ND => N3_1, +D_TXPLL_LOL_TO_ND => N4_1, +CH0_FF_RX_F_CLK => N5_1, +CH1_FF_RX_F_CLK => N52_1, +CH0_FF_RX_H_CLK => N6_1, +CH1_FF_RX_H_CLK => N53_1, +CH0_FF_TX_F_CLK => N7_1, +CH1_FF_TX_F_CLK => N54_1, +CH0_FF_TX_H_CLK => N8_1, +CH1_FF_TX_H_CLK => N55_1, +CH0_FF_RX_PCLK => RX_PCLK_11, +CH1_FF_RX_PCLK => N56_1, +CH0_FF_TX_PCLK => TX_PCLK_I, +CH1_FF_TX_PCLK => N57_1, +CH0_FF_RX_D_0 => rxdata(0), +CH1_FF_RX_D_0 => N58_1, +CH0_FF_RX_D_1 => rxdata(1), +CH1_FF_RX_D_1 => N59_1, +CH0_FF_RX_D_2 => rxdata(2), +CH1_FF_RX_D_2 => N60_1, +CH0_FF_RX_D_3 => rxdata(3), +CH1_FF_RX_D_3 => N61_1, +CH0_FF_RX_D_4 => rxdata(4), +CH1_FF_RX_D_4 => N62_1, +CH0_FF_RX_D_5 => rxdata(5), +CH1_FF_RX_D_5 => N63_1, +CH0_FF_RX_D_6 => rxdata(6), +CH1_FF_RX_D_6 => N64_1, +CH0_FF_RX_D_7 => rxdata(7), +CH1_FF_RX_D_7 => N65_1, +CH0_FF_RX_D_8 => rx_k(0), +CH1_FF_RX_D_8 => N66_1, +CH0_FF_RX_D_9 => rx_disp_err(0), +CH1_FF_RX_D_9 => N67_1, +CH0_FF_RX_D_10 => rx_cv_err(0), +CH1_FF_RX_D_10 => N68_1, +CH0_FF_RX_D_11 => N9_1, +CH1_FF_RX_D_11 => N69_1, +CH0_FF_RX_D_12 => N70_1, +CH1_FF_RX_D_12 => N71_1, +CH0_FF_RX_D_13 => N72_1, +CH1_FF_RX_D_13 => N73_1, +CH0_FF_RX_D_14 => N74_1, +CH1_FF_RX_D_14 => N75_1, +CH0_FF_RX_D_15 => N76_1, +CH1_FF_RX_D_15 => N77_1, +CH0_FF_RX_D_16 => N78_1, +CH1_FF_RX_D_16 => N79_1, +CH0_FF_RX_D_17 => N80_1, +CH1_FF_RX_D_17 => N81_1, +CH0_FF_RX_D_18 => N82_1, +CH1_FF_RX_D_18 => N83_1, +CH0_FF_RX_D_19 => N84_1, +CH1_FF_RX_D_19 => N85_1, +CH0_FF_RX_D_20 => N86_1, +CH1_FF_RX_D_20 => N87_1, +CH0_FF_RX_D_21 => N88_1, +CH1_FF_RX_D_21 => N89_1, +CH0_FF_RX_D_22 => N90_1, +CH1_FF_RX_D_22 => N91_1, +CH0_FF_RX_D_23 => N10_1, +CH1_FF_RX_D_23 => N92_1, +CH0_FFS_PCIE_DONE => N11_1, +CH1_FFS_PCIE_DONE => N93_1, +CH0_FFS_PCIE_CON => N12_1, +CH1_FFS_PCIE_CON => N94_1, +CH0_FFS_RLOS => RX_LOS_LOW_S_13, +CH1_FFS_RLOS => N95_1, +CH0_FFS_LS_SYNC_STATUS => lsm_status_s, +CH1_FFS_LS_SYNC_STATUS => N96_1, +CH0_FFS_CC_UNDERRUN => N13_1, +CH1_FFS_CC_UNDERRUN => N97_1, +CH0_FFS_CC_OVERRUN => N14_1, +CH1_FFS_CC_OVERRUN => N98_1, +CH0_FFS_RXFBFIFO_ERROR => N15_1, +CH1_FFS_RXFBFIFO_ERROR => N99_1, +CH0_FFS_TXFBFIFO_ERROR => N16_1, +CH1_FFS_TXFBFIFO_ERROR => N100_1, +CH0_FFS_RLOL => RX_CDR_LOL_S_14, +CH1_FFS_RLOL => N101_1, +CH0_FFS_SKP_ADDED => N17_1, +CH1_FFS_SKP_ADDED => N102_1, +CH0_FFS_SKP_DELETED => N18_1, +CH1_FFS_SKP_DELETED => N103_1, +CH0_LDR_RX2CORE => N104_1, +CH1_LDR_RX2CORE => N115_1, +D_SCIRDATA0 => sci_rddata(0), +D_SCIRDATA1 => sci_rddata(1), +D_SCIRDATA2 => sci_rddata(2), +D_SCIRDATA3 => sci_rddata(3), +D_SCIRDATA4 => sci_rddata(4), +D_SCIRDATA5 => sci_rddata(5), +D_SCIRDATA6 => sci_rddata(6), +D_SCIRDATA7 => sci_rddata(7), +D_SCIINT => sci_int, +D_SCAN_OUT_0 => N19_1, +D_SCAN_OUT_1 => N20_1, +D_SCAN_OUT_2 => N21_1, +D_SCAN_OUT_3 => N22_1, +D_SCAN_OUT_4 => N23_1, +D_SCAN_OUT_5 => N24_1, +D_SCAN_OUT_6 => N25_1, +D_SCAN_OUT_7 => N26_1, +D_COUT0 => N27_1, +D_COUT1 => N28_1, +D_COUT2 => N29_1, +D_COUT3 => N30_1, +D_COUT4 => N31_1, +D_COUT5 => N32_1, +D_COUT6 => N33_1, +D_COUT7 => N34_1, +D_COUT8 => N35_1, +D_COUT9 => N36_1, +D_COUT10 => N37_1, +D_COUT11 => N38_1, +D_COUT12 => N39_1, +D_COUT13 => N40_1, +D_COUT14 => N41_1, +D_COUT15 => N42_1, +D_COUT16 => N43_1, +D_COUT17 => N44_1, +D_COUT18 => N45_1, +D_COUT19 => N46_1, +D_REFCLKI => pll_refclki, +D_FFS_PLOL => N49_1); +SLL_INST: serdes_sync_1sll_core_Z1_layer1 port map ( +tx_pclk => TX_PCLK_12, +sli_rst => sli_rst, +pll_refclki => pll_refclki, +pll_lock_i => \SLL_INST.PLL_LOCK_I_15\); +RSL_INST: serdes_sync_1rsl_core_Z2_layer1 port map ( +rx_pcs_rst_c => rx_pcs_rst_c, +serdes_rst_dual_c => serdes_rst_dual_c, +tx_serdes_rst_c => tx_serdes_rst_c, +rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C, +rst_dual_c => rst_dual_c, +rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C, +rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C, +rsl_tx_rdy => rsl_tx_rdy, +pll_lock_i => \SLL_INST.PLL_LOCK_I_15\, +pll_refclki => pll_refclki, +rsl_rx_rdy => rsl_rx_rdy, +rx_cdr_lol_s => RX_CDR_LOL_S_14, +rx_los_low_s => RX_LOS_LOW_S_13, +rsl_rst => rsl_rst, +rxrefclk => rxrefclk, +rx_serdes_rst_c => rx_serdes_rst_c, +rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C, +rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C, +rsl_disable => rsl_disable, +tx_pcs_rst_c => tx_pcs_rst_c); +rx_pclk <= RX_PCLK_11; +tx_pclk <= TX_PCLK_12; +rx_los_low_s <= RX_LOS_LOW_S_13; +rx_cdr_lol_s <= RX_CDR_LOL_S_14; +pll_lol <= \SLL_INST.PLL_LOCK_I_15\; +end beh; + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vm new file mode 100644 index 0000000..8c03aad --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vm @@ -0,0 +1,6580 @@ +// +// Written by Synplify Pro +// Product Version "M-2017.03L-SP1-1" +// Program "Synplify Pro", Mapper "maplat, Build 1796R" +// Fri May 10 10:23:37 2019 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " +// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " +// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " +// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " +// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " +// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " +// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " +// file 8 "\/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd " +// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " +// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v " +// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v " +// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v " +// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v " +// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v " +// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh " +// file 16 "\/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v " +// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " +// file 18 "\/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc " + +`timescale 100 ps/100 ps +module sync_0s ( + phb, + rhb_sync, + sli_rst, + pll_refclki +) +; +input phb ; +output rhb_sync ; +input sli_rst ; +input pll_refclki ; +wire phb ; +wire rhb_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_0 ; +wire VCC ; +wire data_p1_QN_0 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(phb), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s */ + +module sync_0s_6 ( + rtc_pul, + ppul_sync, + sli_rst, + tx_pclk +) +; +input rtc_pul ; +output ppul_sync ; +input sli_rst ; +input tx_pclk ; +wire rtc_pul ; +wire ppul_sync ; +wire sli_rst ; +wire tx_pclk ; +wire data_p1 ; +wire data_p2_QN ; +wire VCC ; +wire data_p1_QN ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(rtc_pul), + .CK(tx_pclk), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_6 */ + +module sync_0s_0 ( + ppul_sync, + pdiff_sync, + sli_rst, + pll_refclki +) +; +input ppul_sync ; +output pdiff_sync ; +input sli_rst ; +input pll_refclki ; +wire ppul_sync ; +wire pdiff_sync ; +wire sli_rst ; +wire pll_refclki ; +wire data_p1 ; +wire data_p2_QN_1 ; +wire VCC ; +wire data_p1_QN_1 ; +wire GND ; +// @16:1988 + FD1S3DX data_p2 ( + .D(data_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync) +); +// @16:1988 + FD1S3DX data_p1_reg ( + .D(ppul_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(data_p1) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* sync_0s_0 */ + +module serdes_sync_1sll_core_Z1_layer1 ( + tx_pclk, + sli_rst, + pll_refclki, + pll_lock_i +) +; +input tx_pclk ; +input sli_rst ; +input pll_refclki ; +output pll_lock_i ; +wire tx_pclk ; +wire sli_rst ; +wire pll_refclki ; +wire pll_lock_i ; +wire [2:0] phb_cnt; +wire [2:0] phb_cnt_i; +wire [15:0] rcount; +wire [21:0] pcount; +wire [0:0] un1_pcount_diff_i; +wire [1:1] sll_state; +wire [1:1] sll_state_QN; +wire [7:0] rhb_wait_cnt_s; +wire [7:0] rhb_wait_cnt; +wire [7:0] rhb_wait_cnt_QN; +wire [15:0] rcount_s; +wire [15:0] rcount_QN; +wire [2:0] phb_cnt_QN; +wire [2:1] phb_cnt_RNO; +wire [21:0] pcount_diff_QN; +wire [21:0] pcount_s; +wire [21:0] pcount_QN; +wire [2:2] rdiff_comp_lock; +wire [2:2] rdiff_comp_lock_QN; +wire [1:1] sll_state_ns_i_0_m3; +wire [0:0] un1_pcount_diff; +wire [20:0] pcount_cry; +wire [0:0] pcount_cry_0_S0; +wire [21:21] pcount_s_0_COUT; +wire [21:21] pcount_s_0_S1; +wire [14:0] rcount_cry; +wire [0:0] rcount_cry_0_S0; +wire [15:15] rcount_s_0_COUT; +wire [15:15] rcount_s_0_S1; +wire [6:0] rhb_wait_cnt_cry; +wire [0:0] rhb_wait_cnt_cry_0_S0; +wire [7:7] rhb_wait_cnt_s_0_COUT; +wire [7:7] rhb_wait_cnt_s_0_S1; +wire pll_lock ; +wire rtc_ctrl4_0_a3_1 ; +wire un13_lock_20 ; +wire ppul_sync_p2 ; +wire ppul_sync_p1 ; +wire un1_pcount_diff_1_axb_20 ; +wire un13_lock_19 ; +wire un1_pcount_diff_1_axb_19 ; +wire un13_lock_18 ; +wire un1_pcount_diff_1_axb_18 ; +wire un13_lock_17 ; +wire un1_pcount_diff_1_cry_17_0_RNO ; +wire un13_lock_16 ; +wire un1_pcount_diff_1_axb_16 ; +wire un13_lock_15 ; +wire un1_pcount_diff_1_axb_15 ; +wire un13_lock_14 ; +wire un1_pcount_diff_1_axb_14 ; +wire un13_lock_13 ; +wire un1_pcount_diff_1_axb_13 ; +wire un13_lock_12 ; +wire un1_pcount_diff_1_axb_12 ; +wire un13_lock_11 ; +wire un1_pcount_diff_1_axb_11 ; +wire un13_lock_10 ; +wire un1_pcount_diff_1_axb_10 ; +wire un13_lock_9 ; +wire un1_pcount_diff_1_axb_9 ; +wire un13_lock_8 ; +wire un1_pcount_diff_1_axb_8 ; +wire un13_lock_7 ; +wire un1_pcount_diff_1_axb_7 ; +wire un13_lock_6 ; +wire un1_pcount_diff_1_axb_6 ; +wire un13_lock_5 ; +wire un1_pcount_diff_1_axb_5 ; +wire un13_lock_4 ; +wire un1_pcount_diff_1_axb_4 ; +wire un13_lock_3 ; +wire un1_pcount_diff_1_axb_3 ; +wire un13_lock_2 ; +wire un1_pcount_diff_1_axb_2 ; +wire un13_lock_1 ; +wire un1_pcount_diff_1_axb_1 ; +wire un13_lock_21 ; +wire ppul_sync_p3 ; +wire N_7 ; +wire un13_lock_0 ; +wire rtc_ctrl4 ; +wire rtc_ctrl ; +wire VCC ; +wire N_2136_0 ; +wire unlock_5 ; +wire unlock_1_sqmuxa_i_0 ; +wire unlock ; +wire unlock_QN ; +wire N_89_i ; +wire rtc_pul ; +wire rtc_pul_p1 ; +wire rtc_pul_p1_QN ; +wire rtc_pul5 ; +wire rtc_pul_QN ; +wire rtc_ctrl_QN ; +wire rstat_pclk_2 ; +wire rstat_pclk ; +wire rstat_pclk_QN ; +wire rhb_sync_p1 ; +wire rhb_sync_p2 ; +wire rhb_sync_p2_QN ; +wire rhb_sync ; +wire rhb_sync_p1_QN ; +wire ppul_sync_p3_QN ; +wire ppul_sync_p2_QN ; +wire ppul_sync ; +wire ppul_sync_p1_QN ; +wire pll_lock_QN ; +wire phb ; +wire phb_QN ; +wire pdiff_sync ; +wire pdiff_sync_p1 ; +wire pdiff_sync_p1_QN ; +wire un1_pcount_diff_1_cry_1_0_S0 ; +wire un1_pcount_diff_1_cry_1_0_S1 ; +wire un1_pcount_diff_1_cry_3_0_S0 ; +wire un1_pcount_diff_1_cry_3_0_S1 ; +wire un1_pcount_diff_1_cry_5_0_S0 ; +wire un1_pcount_diff_1_cry_5_0_S1 ; +wire un1_pcount_diff_1_cry_7_0_S0 ; +wire un1_pcount_diff_1_cry_7_0_S1 ; +wire un1_pcount_diff_1_cry_9_0_S0 ; +wire un1_pcount_diff_1_cry_9_0_S1 ; +wire un1_pcount_diff_1_cry_11_0_S0 ; +wire un1_pcount_diff_1_cry_11_0_S1 ; +wire un1_pcount_diff_1_cry_13_0_S0 ; +wire un1_pcount_diff_1_cry_13_0_S1 ; +wire un1_pcount_diff_1_cry_15_0_S0 ; +wire un1_pcount_diff_1_cry_15_0_S1 ; +wire un1_pcount_diff_1_cry_17_0_S0 ; +wire un1_pcount_diff_1_cry_17_0_S1 ; +wire un1_pcount_diff_1_cry_19_0_S0 ; +wire un1_pcount_diff_1_cry_19_0_S1 ; +wire un1_pcount_diff_1_s_21_0_S0 ; +wire lock_5 ; +wire lock_1_sqmuxa_i_0 ; +wire lock ; +wire lock_QN ; +wire rtc_pul5_0_o3 ; +wire rtc_pul5_0_a3_6 ; +wire rtc_pul5_0_a3_7 ; +wire un1_rcount_1_0_a3 ; +wire un1_rhb_wait_cnt ; +wire N_12 ; +wire rtc_ctrl4_0_a3_12_4 ; +wire rtc_ctrl4_0_a3_12_5 ; +wire rtc_ctrl4_10 ; +wire un1_rcount_1_0_a3_1 ; +wire N_6 ; +wire un1_rhb_wait_cnt_3 ; +wire un1_rhb_wait_cnt_4 ; +wire rtc_pul5_0_a3_5 ; +wire un13_lock_cry_21_i ; +wire un13_unlock_cry_21 ; +wire N_8 ; +wire un1_pcount_diff_1_cry_0 ; +wire un1_pcount_diff_1_cry_0_0_S0 ; +wire un1_pcount_diff_1_cry_0_0_S1 ; +wire un1_pcount_diff_1_cry_2 ; +wire un1_pcount_diff_1_cry_4 ; +wire un1_pcount_diff_1_cry_6 ; +wire un1_pcount_diff_1_cry_8 ; +wire un1_pcount_diff_1_cry_10 ; +wire un1_pcount_diff_1_cry_12 ; +wire un1_pcount_diff_1_cry_14 ; +wire un1_pcount_diff_1_cry_16 ; +wire un1_pcount_diff_1_cry_18 ; +wire un1_pcount_diff_1_cry_20 ; +wire un1_pcount_diff_1_s_21_0_COUT ; +wire un1_pcount_diff_1_s_21_0_S1 ; +wire un13_lock_cry_0 ; +wire un13_lock_cry_0_0_S0 ; +wire un13_lock_cry_0_0_S1 ; +wire un13_lock_cry_2 ; +wire un13_lock_cry_1_0_S0 ; +wire un13_lock_cry_1_0_S1 ; +wire un13_lock_cry_4 ; +wire un13_lock_cry_3_0_S0 ; +wire un13_lock_cry_3_0_S1 ; +wire un13_lock_cry_6 ; +wire un13_lock_cry_5_0_S0 ; +wire un13_lock_cry_5_0_S1 ; +wire un13_lock_cry_8 ; +wire un13_lock_cry_7_0_S0 ; +wire un13_lock_cry_7_0_S1 ; +wire un13_lock_cry_10 ; +wire un13_lock_cry_9_0_S0 ; +wire un13_lock_cry_9_0_S1 ; +wire un13_lock_cry_12 ; +wire un13_lock_cry_11_0_S0 ; +wire un13_lock_cry_11_0_S1 ; +wire un13_lock_cry_14 ; +wire un13_lock_cry_13_0_S0 ; +wire un13_lock_cry_13_0_S1 ; +wire un13_lock_cry_16 ; +wire un13_lock_cry_15_0_S0 ; +wire un13_lock_cry_15_0_S1 ; +wire un13_lock_cry_18 ; +wire un13_lock_cry_17_0_S0 ; +wire un13_lock_cry_17_0_S1 ; +wire un13_lock_cry_20 ; +wire un13_lock_cry_19_0_S0 ; +wire un13_lock_cry_19_0_S1 ; +wire un13_lock_cry_21_0_COUT ; +wire un13_lock_cry_21_0_S0 ; +wire un13_unlock_cry_0 ; +wire un13_unlock_cry_0_0_S0 ; +wire un13_unlock_cry_0_0_S1 ; +wire un13_unlock_cry_2 ; +wire un13_unlock_cry_1_0_S0 ; +wire un13_unlock_cry_1_0_S1 ; +wire un13_unlock_cry_4 ; +wire un13_unlock_cry_3_0_S0 ; +wire un13_unlock_cry_3_0_S1 ; +wire un13_unlock_cry_6 ; +wire un13_unlock_cry_5_0_S0 ; +wire un13_unlock_cry_5_0_S1 ; +wire un13_unlock_cry_8 ; +wire un13_unlock_cry_7_0_S0 ; +wire un13_unlock_cry_7_0_S1 ; +wire un13_unlock_cry_10 ; +wire un13_unlock_cry_9_0_S0 ; +wire un13_unlock_cry_9_0_S1 ; +wire un13_unlock_cry_12 ; +wire un13_unlock_cry_11_0_S0 ; +wire un13_unlock_cry_11_0_S1 ; +wire un13_unlock_cry_14 ; +wire un13_unlock_cry_13_0_S0 ; +wire un13_unlock_cry_13_0_S1 ; +wire un13_unlock_cry_16 ; +wire un13_unlock_cry_15_0_S0 ; +wire un13_unlock_cry_15_0_S1 ; +wire un13_unlock_cry_18 ; +wire un13_unlock_cry_17_0_S0 ; +wire un13_unlock_cry_17_0_S1 ; +wire un13_unlock_cry_20 ; +wire un13_unlock_cry_19_0_S0 ; +wire un13_unlock_cry_19_0_S1 ; +wire un13_unlock_cry_21_0_COUT ; +wire un13_unlock_cry_21_0_S0 ; +wire N_96 ; +wire N_20 ; +wire N_19 ; +wire N_18 ; +wire N_14 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_9 ; + INV phb_RNO ( + .A(phb_cnt[2]), + .Z(phb_cnt_i[2]) +); + INV \phb_cnt_RNO[0] ( + .A(phb_cnt[0]), + .Z(phb_cnt_i[0]) +); + INV pll_lock_RNI6JK9 ( + .A(pll_lock), + .Z(pll_lock_i) +); + LUT4 rtc_ctrl4_0_a3_RNO ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(rtc_ctrl4_0_a3_1) +); +defparam rtc_ctrl4_0_a3_RNO.init=16'h2000; + LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 ( + .A(un13_lock_20), + .B(pcount[20]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_20) +); +defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_19_0_RNO ( + .A(un13_lock_19), + .B(pcount[19]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_19) +); +defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 ( + .A(un13_lock_18), + .B(pcount[18]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_18) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_17_0_RNO_cZ ( + .A(un13_lock_17), + .B(pcount[17]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_cry_17_0_RNO) +); +defparam un1_pcount_diff_1_cry_17_0_RNO_cZ.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO_0 ( + .A(un13_lock_16), + .B(pcount[16]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_16) +); +defparam un1_pcount_diff_1_cry_15_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_15_0_RNO ( + .A(un13_lock_15), + .B(pcount[15]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_15) +); +defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 ( + .A(un13_lock_14), + .B(pcount[14]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_14) +); +defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_13_0_RNO ( + .A(un13_lock_13), + .B(pcount[13]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_13) +); +defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 ( + .A(un13_lock_12), + .B(pcount[12]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_12) +); +defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_11_0_RNO ( + .A(un13_lock_11), + .B(pcount[11]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_11) +); +defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 ( + .A(un13_lock_10), + .B(pcount[10]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_10) +); +defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_9_0_RNO ( + .A(un13_lock_9), + .B(pcount[9]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_9) +); +defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 ( + .A(un13_lock_8), + .B(pcount[8]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_8) +); +defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_7_0_RNO ( + .A(un13_lock_7), + .B(pcount[7]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_7) +); +defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 ( + .A(un13_lock_6), + .B(pcount[6]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_6) +); +defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_5_0_RNO ( + .A(un13_lock_5), + .B(pcount[5]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_5) +); +defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 ( + .A(un13_lock_4), + .B(pcount[4]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_4) +); +defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_3_0_RNO ( + .A(un13_lock_3), + .B(pcount[3]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_3) +); +defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 ( + .A(un13_lock_2), + .B(pcount[2]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_2) +); +defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355; + LUT4 un1_pcount_diff_1_cry_1_0_RNO ( + .A(un13_lock_1), + .B(pcount[1]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff_1_axb_1) +); +defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355; + LUT4 ppul_sync_p3_RNIU65C ( + .A(un13_lock_21), + .B(ppul_sync_p3), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(N_7) +); +defparam ppul_sync_p3_RNIU65C.init=16'h2F20; + LUT4 \pcount_diff_RNO[0] ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(pcount[0]), + .D(un13_lock_0), + .Z(un1_pcount_diff_i[0]) +); +defparam \pcount_diff_RNO[0] .init=16'hFD20; +// @16:1304 + LUT4 rtc_ctrl_0 ( + .A(rtc_ctrl4), + .B(rtc_ctrl), + .C(VCC), + .D(VCC), + .Z(N_2136_0) +); +defparam rtc_ctrl_0.init=16'hEEEE; +// @16:1278 + FD1P3DX unlock_reg ( + .D(unlock_5), + .SP(unlock_1_sqmuxa_i_0), + .CK(pll_refclki), + .CD(sli_rst), + .Q(unlock) +); +// @16:1801 + FD1S3DX \sll_state_reg[1] ( + .D(N_89_i), + .CK(pll_refclki), + .CD(sli_rst), + .Q(sll_state[1]) +); +// @16:1304 + FD1S3DX rtc_pul_p1_reg ( + .D(rtc_pul), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul_p1) +); +// @16:1304 + FD1P3DX rtc_pul_reg ( + .D(rtc_pul5), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_pul) +); +// @16:1304 + FD1S3DX rtc_ctrl_reg ( + .D(N_2136_0), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rtc_ctrl) +); +// @16:1350 + FD1P3DX rstat_pclk_reg ( + .D(rstat_pclk_2), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rstat_pclk) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[0] ( + .D(rhb_wait_cnt_s[0]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[0]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[1] ( + .D(rhb_wait_cnt_s[1]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[1]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[2] ( + .D(rhb_wait_cnt_s[2]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[2]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[3] ( + .D(rhb_wait_cnt_s[3]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[3]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[4] ( + .D(rhb_wait_cnt_s[4]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[4]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[5] ( + .D(rhb_wait_cnt_s[5]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[5]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[6] ( + .D(rhb_wait_cnt_s[6]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[6]) +); +// @16:1350 + FD1P3DX \rhb_wait_cnt_reg[7] ( + .D(rhb_wait_cnt_s[7]), + .SP(rtc_ctrl), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_wait_cnt[7]) +); +// @16:1350 + FD1S3DX rhb_sync_p2_reg ( + .D(rhb_sync_p1), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p2) +); +// @16:1350 + FD1S3DX rhb_sync_p1_reg ( + .D(rhb_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rhb_sync_p1) +); +// @16:1304 + FD1S3DX \rcount_reg[0] ( + .D(rcount_s[0]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[0]) +); +// @16:1304 + FD1S3DX \rcount_reg[1] ( + .D(rcount_s[1]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[1]) +); +// @16:1304 + FD1S3DX \rcount_reg[2] ( + .D(rcount_s[2]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[2]) +); +// @16:1304 + FD1S3DX \rcount_reg[3] ( + .D(rcount_s[3]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[3]) +); +// @16:1304 + FD1S3DX \rcount_reg[4] ( + .D(rcount_s[4]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[4]) +); +// @16:1304 + FD1S3DX \rcount_reg[5] ( + .D(rcount_s[5]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[5]) +); +// @16:1304 + FD1S3DX \rcount_reg[6] ( + .D(rcount_s[6]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[6]) +); +// @16:1304 + FD1S3DX \rcount_reg[7] ( + .D(rcount_s[7]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[7]) +); +// @16:1304 + FD1S3DX \rcount_reg[8] ( + .D(rcount_s[8]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[8]) +); +// @16:1304 + FD1S3DX \rcount_reg[9] ( + .D(rcount_s[9]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[9]) +); +// @16:1304 + FD1S3DX \rcount_reg[10] ( + .D(rcount_s[10]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[10]) +); +// @16:1304 + FD1S3DX \rcount_reg[11] ( + .D(rcount_s[11]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[11]) +); +// @16:1304 + FD1S3DX \rcount_reg[12] ( + .D(rcount_s[12]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[12]) +); +// @16:1304 + FD1S3DX \rcount_reg[13] ( + .D(rcount_s[13]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[13]) +); +// @16:1304 + FD1S3DX \rcount_reg[14] ( + .D(rcount_s[14]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[14]) +); +// @16:1304 + FD1S3DX \rcount_reg[15] ( + .D(rcount_s[15]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rcount[15]) +); +// @16:1408 + FD1S3DX ppul_sync_p3_reg ( + .D(ppul_sync_p2), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p3) +); +// @16:1408 + FD1S3DX ppul_sync_p2_reg ( + .D(ppul_sync_p1), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p2) +); +// @16:1408 + FD1S3DX ppul_sync_p1_reg ( + .D(ppul_sync), + .CK(tx_pclk), + .CD(sli_rst), + .Q(ppul_sync_p1) +); +// @16:1879 + FD1S3DX pll_lock_reg ( + .D(sll_state[1]), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pll_lock) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[0] ( + .D(phb_cnt_i[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[0]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[1] ( + .D(phb_cnt_RNO[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[1]) +); +// @16:1759 + FD1S3DX \phb_cnt_reg[2] ( + .D(phb_cnt_RNO[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb_cnt[2]) +); +// @16:1759 + FD1S3DX phb_reg ( + .D(phb_cnt_i[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(phb) +); +// @16:1278 + FD1S3DX pdiff_sync_p1_reg ( + .D(pdiff_sync), + .CK(pll_refclki), + .CD(sli_rst), + .Q(pdiff_sync_p1) +); +// @16:1759 + FD1P3BX \pcount_diff[0] ( + .D(un1_pcount_diff_i[0]), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_0) +); +// @16:1759 + FD1S3DX \pcount_reg[0] ( + .D(pcount_s[0]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[0]) +); +// @16:1759 + FD1S3DX \pcount_reg[1] ( + .D(pcount_s[1]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[1]) +); +// @16:1759 + FD1P3BX \pcount_diff[1] ( + .D(un1_pcount_diff_1_cry_1_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_1) +); +// @16:1759 + FD1P3BX \pcount_diff[2] ( + .D(un1_pcount_diff_1_cry_1_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_2) +); +// @16:1759 + FD1S3DX \pcount_reg[2] ( + .D(pcount_s[2]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[2]) +); +// @16:1759 + FD1S3DX \pcount_reg[3] ( + .D(pcount_s[3]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[3]) +); +// @16:1759 + FD1P3BX \pcount_diff[3] ( + .D(un1_pcount_diff_1_cry_3_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_3) +); +// @16:1759 + FD1P3BX \pcount_diff[4] ( + .D(un1_pcount_diff_1_cry_3_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_4) +); +// @16:1759 + FD1S3DX \pcount_reg[4] ( + .D(pcount_s[4]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[4]) +); +// @16:1759 + FD1S3DX \pcount_reg[5] ( + .D(pcount_s[5]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[5]) +); +// @16:1759 + FD1P3BX \pcount_diff[5] ( + .D(un1_pcount_diff_1_cry_5_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_5) +); +// @16:1759 + FD1P3BX \pcount_diff[6] ( + .D(un1_pcount_diff_1_cry_5_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_6) +); +// @16:1759 + FD1S3DX \pcount_reg[6] ( + .D(pcount_s[6]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[6]) +); +// @16:1759 + FD1P3BX \pcount_diff[7] ( + .D(un1_pcount_diff_1_cry_7_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_7) +); +// @16:1759 + FD1S3DX \pcount_reg[7] ( + .D(pcount_s[7]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[7]) +); +// @16:1759 + FD1S3DX \pcount_reg[8] ( + .D(pcount_s[8]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[8]) +); +// @16:1759 + FD1P3BX \pcount_diff[8] ( + .D(un1_pcount_diff_1_cry_7_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_8) +); +// @16:1759 + FD1P3BX \pcount_diff[9] ( + .D(un1_pcount_diff_1_cry_9_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_9) +); +// @16:1759 + FD1S3DX \pcount_reg[9] ( + .D(pcount_s[9]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[9]) +); +// @16:1759 + FD1S3DX \pcount_reg[10] ( + .D(pcount_s[10]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[10]) +); +// @16:1759 + FD1P3BX \pcount_diff[10] ( + .D(un1_pcount_diff_1_cry_9_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_10) +); +// @16:1759 + FD1P3BX \pcount_diff[11] ( + .D(un1_pcount_diff_1_cry_11_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_11) +); +// @16:1759 + FD1S3DX \pcount_reg[11] ( + .D(pcount_s[11]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[11]) +); +// @16:1759 + FD1S3DX \pcount_reg[12] ( + .D(pcount_s[12]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[12]) +); +// @16:1759 + FD1P3BX \pcount_diff[12] ( + .D(un1_pcount_diff_1_cry_11_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_12) +); +// @16:1759 + FD1S3DX \pcount_reg[13] ( + .D(pcount_s[13]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[13]) +); +// @16:1759 + FD1P3BX \pcount_diff[13] ( + .D(un1_pcount_diff_1_cry_13_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_13) +); +// @16:1759 + FD1P3BX \pcount_diff[14] ( + .D(un1_pcount_diff_1_cry_13_0_S1), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_14) +); +// @16:1759 + FD1S3DX \pcount_reg[14] ( + .D(pcount_s[14]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[14]) +); +// @16:1759 + FD1P3BX \pcount_diff[15] ( + .D(un1_pcount_diff_1_cry_15_0_S0), + .SP(N_7), + .CK(tx_pclk), + .PD(sli_rst), + .Q(un13_lock_15) +); +// @16:1759 + FD1S3DX \pcount_reg[15] ( + .D(pcount_s[15]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[15]) +); +// @16:1759 + FD1S3DX \pcount_reg[16] ( + .D(pcount_s[16]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[16]) +); +// @16:1759 + FD1P3DX \pcount_diff[16] ( + .D(un1_pcount_diff_1_cry_15_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_16) +); +// @16:1759 + FD1P3DX \pcount_diff[17] ( + .D(un1_pcount_diff_1_cry_17_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_17) +); +// @16:1759 + FD1S3DX \pcount_reg[17] ( + .D(pcount_s[17]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[17]) +); +// @16:1759 + FD1S3DX \pcount_reg[18] ( + .D(pcount_s[18]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[18]) +); +// @16:1759 + FD1P3DX \pcount_diff[18] ( + .D(un1_pcount_diff_1_cry_17_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_18) +); +// @16:1759 + FD1S3DX \pcount_reg[19] ( + .D(pcount_s[19]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[19]) +); +// @16:1759 + FD1P3DX \pcount_diff[19] ( + .D(un1_pcount_diff_1_cry_19_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_19) +); +// @16:1759 + FD1P3DX \pcount_diff[20] ( + .D(un1_pcount_diff_1_cry_19_0_S1), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_20) +); +// @16:1759 + FD1S3DX \pcount_reg[20] ( + .D(pcount_s[20]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[20]) +); +// @16:1759 + FD1S3DX \pcount_reg[21] ( + .D(pcount_s[21]), + .CK(tx_pclk), + .CD(sli_rst), + .Q(pcount[21]) +); +// @16:1759 + FD1P3DX \pcount_diff[21] ( + .D(un1_pcount_diff_1_s_21_0_S0), + .SP(N_7), + .CK(tx_pclk), + .CD(sli_rst), + .Q(un13_lock_21) +); +// @16:1278 + FD1P3DX lock_reg ( + .D(lock_5), + .SP(lock_1_sqmuxa_i_0), + .CK(pll_refclki), + .CD(sli_rst), + .Q(lock) +); +// @16:1739 + FD1S3DX \genblk5.rdiff_comp_lock[2] ( + .D(VCC), + .CK(pll_refclki), + .CD(sli_rst), + .Q(rdiff_comp_lock[2]) +); +// @16:1334 + LUT4 rtc_pul5_0_0 ( + .A(rtc_pul5_0_o3), + .B(rtc_pul5_0_a3_6), + .C(rtc_pul5_0_a3_7), + .D(un1_rcount_1_0_a3), + .Z(rtc_pul5) +); +defparam rtc_pul5_0_0.init=16'hFF80; +// @16:1389 + LUT4 rstat_pclk_2_iv_0_0 ( + .A(un1_rhb_wait_cnt), + .B(rhb_sync_p1), + .C(rhb_sync_p2), + .D(rstat_pclk), + .Z(rstat_pclk_2) +); +defparam rstat_pclk_2_iv_0_0.init=16'h5D0C; +// @16:1801 + LUT4 \sll_state_RNO[1] ( + .A(sll_state_ns_i_0_m3[1]), + .B(rstat_pclk), + .C(sll_state[1]), + .D(unlock), + .Z(N_89_i) +); +defparam \sll_state_RNO[1] .init=16'h4044; +// @16:1389 + LUT4 un1_rhb_wait_cnt12_1_i_0_a3 ( + .A(un1_rhb_wait_cnt), + .B(rhb_sync_p1), + .C(rhb_sync_p2), + .D(VCC), + .Z(N_12) +); +defparam un1_rhb_wait_cnt12_1_i_0_a3.init=16'h5151; +// @16:1328 + LUT4 rtc_ctrl4_0_a3 ( + .A(rtc_ctrl4_0_a3_1), + .B(rtc_ctrl4_0_a3_12_4), + .C(rtc_ctrl4_0_a3_12_5), + .D(rtc_ctrl4_10), + .Z(rtc_ctrl4) +); +defparam rtc_ctrl4_0_a3.init=16'h8000; +// @16:1319 + LUT4 un1_rcount_1_0_a3_cZ ( + .A(rtc_ctrl4_0_a3_12_4), + .B(rtc_ctrl4_0_a3_12_5), + .C(rtc_ctrl4_10), + .D(un1_rcount_1_0_a3_1), + .Z(un1_rcount_1_0_a3) +); +defparam un1_rcount_1_0_a3_cZ.init=16'h8000; +// @16:1334 + LUT4 rtc_pul5_0_o3_cZ ( + .A(N_6), + .B(rcount[1]), + .C(rcount[2]), + .D(rcount[3]), + .Z(rtc_pul5_0_o3) +); +defparam rtc_pul5_0_o3_cZ.init=16'hAAAB; +// @16:1393 + LUT4 un1_rhb_wait_cnt_cZ ( + .A(rhb_wait_cnt[4]), + .B(rhb_wait_cnt[5]), + .C(un1_rhb_wait_cnt_3), + .D(un1_rhb_wait_cnt_4), + .Z(un1_rhb_wait_cnt) +); +defparam un1_rhb_wait_cnt_cZ.init=16'h8000; +// @16:1334 + LUT4 rtc_pul5_0_a3_7_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rtc_pul5_0_a3_5), + .D(VCC), + .Z(rtc_pul5_0_a3_7) +); +defparam rtc_pul5_0_a3_7_cZ.init=16'h1010; +// @16:1801 + LUT4 \sll_state_ns_i_0_m3_cZ[1] ( + .A(lock), + .B(rtc_pul), + .C(rtc_pul_p1), + .D(sll_state[1]), + .Z(sll_state_ns_i_0_m3[1]) +); +defparam \sll_state_ns_i_0_m3_cZ[1] .init=16'h10DF; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[2] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(phb_cnt[2]), + .D(VCC), + .Z(phb_cnt_RNO[2]) +); +defparam \phb_cnt_RNO_cZ[2] .init=16'h7878; +// @16:1287 + LUT4 unlock_1_sqmuxa_i_0_cZ ( + .A(pdiff_sync), + .B(pdiff_sync_p1), + .C(unlock), + .D(VCC), + .Z(unlock_1_sqmuxa_i_0) +); +defparam unlock_1_sqmuxa_i_0_cZ.init=16'h4F4F; +// @16:1287 + LUT4 lock_1_sqmuxa_i_0_cZ ( + .A(lock), + .B(pdiff_sync), + .C(pdiff_sync_p1), + .D(VCC), + .Z(lock_1_sqmuxa_i_0) +); +defparam lock_1_sqmuxa_i_0_cZ.init=16'h7575; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_10 ( + .A(rcount[1]), + .B(rcount[3]), + .C(rcount[6]), + .D(rcount[15]), + .Z(rtc_ctrl4_10) +); +defparam rtc_ctrl4_0_a3_10.init=16'h8000; +// @16:1393 + LUT4 un1_rhb_wait_cnt_4_cZ ( + .A(rhb_wait_cnt[0]), + .B(rhb_wait_cnt[1]), + .C(rhb_wait_cnt[2]), + .D(rhb_wait_cnt[3]), + .Z(un1_rhb_wait_cnt_4) +); +defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_4_cZ ( + .A(rcount[11]), + .B(rcount[12]), + .C(rcount[13]), + .D(rcount[14]), + .Z(rtc_ctrl4_0_a3_12_4) +); +defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000; +// @16:1328 + LUT4 rtc_ctrl4_0_a3_12_5_cZ ( + .A(rcount[7]), + .B(rcount[8]), + .C(rcount[9]), + .D(rcount[10]), + .Z(rtc_ctrl4_0_a3_12_5) +); +defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000; +// @16:1334 + LUT4 rtc_pul5_0_a3_5_cZ ( + .A(rcount[6]), + .B(rcount[13]), + .C(rcount[14]), + .D(rcount[15]), + .Z(rtc_pul5_0_a3_5) +); +defparam rtc_pul5_0_a3_5_cZ.init=16'h0001; +// @16:1334 + LUT4 rtc_pul5_0_a3_6_cZ ( + .A(rcount[9]), + .B(rcount[10]), + .C(rcount[11]), + .D(rcount[12]), + .Z(rtc_pul5_0_a3_6) +); +defparam rtc_pul5_0_a3_6_cZ.init=16'h0001; +// @16:1292 + LUT4 lock_5_cZ ( + .A(pdiff_sync), + .B(un13_lock_cry_21_i), + .C(VCC), + .D(VCC), + .Z(lock_5) +); +defparam lock_5_cZ.init=16'h8888; +// @16:1286 + LUT4 unlock_5_cZ ( + .A(pdiff_sync), + .B(un13_unlock_cry_21), + .C(VCC), + .D(VCC), + .Z(unlock_5) +); +defparam unlock_5_cZ.init=16'h8888; +// @16:1768 + LUT4 pcount10_0_o3 ( + .A(ppul_sync_p1), + .B(ppul_sync_p2), + .C(VCC), + .D(VCC), + .Z(N_8) +); +defparam pcount10_0_o3.init=16'hDDDD; +// @16:1776 + LUT4 \phb_cnt_RNO_cZ[1] ( + .A(phb_cnt[0]), + .B(phb_cnt[1]), + .C(VCC), + .D(VCC), + .Z(phb_cnt_RNO[1]) +); +defparam \phb_cnt_RNO_cZ[1] .init=16'h6666; +// @16:1328 + LUT4 rtc_ctrl4_0_o3 ( + .A(rcount[4]), + .B(rcount[5]), + .C(VCC), + .D(VCC), + .Z(N_6) +); +defparam rtc_ctrl4_0_o3.init=16'h7777; +// @16:1393 + LUT4 un1_rhb_wait_cnt_3_cZ ( + .A(rhb_wait_cnt[6]), + .B(rhb_wait_cnt[7]), + .C(VCC), + .D(VCC), + .Z(un1_rhb_wait_cnt_3) +); +defparam un1_rhb_wait_cnt_3_cZ.init=16'h8888; +// @16:1786 + LUT4 \un1_pcount_diff_cZ[0] ( + .A(un13_lock_0), + .B(pcount[0]), + .C(ppul_sync_p2), + .D(ppul_sync_p1), + .Z(un1_pcount_diff[0]) +); +defparam \un1_pcount_diff_cZ[0] .init=16'h5355; +// @16:1319 + LUT4 un1_rcount_1_0_a3_1_cZ ( + .A(rcount[2]), + .B(rcount[0]), + .C(rcount[5]), + .D(rcount[4]), + .Z(un1_rcount_1_0_a3_1) +); +defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000; + CCU2C \pcount_cry_0[0] ( + .A0(VCC), + .B0(N_8), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_9), + .COUT(pcount_cry[0]), + .S0(pcount_cry_0_S0[0]), + .S1(pcount_s[0]) +); +defparam \pcount_cry_0[0] .INIT0=16'h500c; +defparam \pcount_cry_0[0] .INIT1=16'h8000; +defparam \pcount_cry_0[0] .INJECT1_0="NO"; +defparam \pcount_cry_0[0] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[1] ( + .A0(N_8), + .B0(pcount[1]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[0]), + .COUT(pcount_cry[2]), + .S0(pcount_s[1]), + .S1(pcount_s[2]) +); +defparam \pcount_cry_0[1] .INIT0=16'h8000; +defparam \pcount_cry_0[1] .INIT1=16'h8000; +defparam \pcount_cry_0[1] .INJECT1_0="NO"; +defparam \pcount_cry_0[1] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[3] ( + .A0(N_8), + .B0(pcount[3]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[2]), + .COUT(pcount_cry[4]), + .S0(pcount_s[3]), + .S1(pcount_s[4]) +); +defparam \pcount_cry_0[3] .INIT0=16'h8000; +defparam \pcount_cry_0[3] .INIT1=16'h8000; +defparam \pcount_cry_0[3] .INJECT1_0="NO"; +defparam \pcount_cry_0[3] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[5] ( + .A0(N_8), + .B0(pcount[5]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[4]), + .COUT(pcount_cry[6]), + .S0(pcount_s[5]), + .S1(pcount_s[6]) +); +defparam \pcount_cry_0[5] .INIT0=16'h8000; +defparam \pcount_cry_0[5] .INIT1=16'h8000; +defparam \pcount_cry_0[5] .INJECT1_0="NO"; +defparam \pcount_cry_0[5] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[7] ( + .A0(N_8), + .B0(pcount[7]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[6]), + .COUT(pcount_cry[8]), + .S0(pcount_s[7]), + .S1(pcount_s[8]) +); +defparam \pcount_cry_0[7] .INIT0=16'h8000; +defparam \pcount_cry_0[7] .INIT1=16'h8000; +defparam \pcount_cry_0[7] .INJECT1_0="NO"; +defparam \pcount_cry_0[7] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[9] ( + .A0(N_8), + .B0(pcount[9]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[8]), + .COUT(pcount_cry[10]), + .S0(pcount_s[9]), + .S1(pcount_s[10]) +); +defparam \pcount_cry_0[9] .INIT0=16'h8000; +defparam \pcount_cry_0[9] .INIT1=16'h8000; +defparam \pcount_cry_0[9] .INJECT1_0="NO"; +defparam \pcount_cry_0[9] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[11] ( + .A0(N_8), + .B0(pcount[11]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[10]), + .COUT(pcount_cry[12]), + .S0(pcount_s[11]), + .S1(pcount_s[12]) +); +defparam \pcount_cry_0[11] .INIT0=16'h8000; +defparam \pcount_cry_0[11] .INIT1=16'h8000; +defparam \pcount_cry_0[11] .INJECT1_0="NO"; +defparam \pcount_cry_0[11] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[13] ( + .A0(N_8), + .B0(pcount[13]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[12]), + .COUT(pcount_cry[14]), + .S0(pcount_s[13]), + .S1(pcount_s[14]) +); +defparam \pcount_cry_0[13] .INIT0=16'h8000; +defparam \pcount_cry_0[13] .INIT1=16'h8000; +defparam \pcount_cry_0[13] .INJECT1_0="NO"; +defparam \pcount_cry_0[13] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[15] ( + .A0(N_8), + .B0(pcount[15]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[16]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[14]), + .COUT(pcount_cry[16]), + .S0(pcount_s[15]), + .S1(pcount_s[16]) +); +defparam \pcount_cry_0[15] .INIT0=16'h8000; +defparam \pcount_cry_0[15] .INIT1=16'h8000; +defparam \pcount_cry_0[15] .INJECT1_0="NO"; +defparam \pcount_cry_0[15] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[17] ( + .A0(N_8), + .B0(pcount[17]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[18]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[16]), + .COUT(pcount_cry[18]), + .S0(pcount_s[17]), + .S1(pcount_s[18]) +); +defparam \pcount_cry_0[17] .INIT0=16'h8000; +defparam \pcount_cry_0[17] .INIT1=16'h8000; +defparam \pcount_cry_0[17] .INJECT1_0="NO"; +defparam \pcount_cry_0[17] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_cry_0[19] ( + .A0(N_8), + .B0(pcount[19]), + .C0(VCC), + .D0(VCC), + .A1(N_8), + .B1(pcount[20]), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[18]), + .COUT(pcount_cry[20]), + .S0(pcount_s[19]), + .S1(pcount_s[20]) +); +defparam \pcount_cry_0[19] .INIT0=16'h8000; +defparam \pcount_cry_0[19] .INIT1=16'h8000; +defparam \pcount_cry_0[19] .INJECT1_0="NO"; +defparam \pcount_cry_0[19] .INJECT1_1="NO"; +// @16:1759 + CCU2C \pcount_s_0[21] ( + .A0(N_8), + .B0(pcount[21]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(pcount_cry[20]), + .COUT(pcount_s_0_COUT[21]), + .S0(pcount_s[21]), + .S1(pcount_s_0_S1[21]) +); +defparam \pcount_s_0[21] .INIT0=16'h800a; +defparam \pcount_s_0[21] .INIT1=16'h5003; +defparam \pcount_s_0[21] .INJECT1_0="NO"; +defparam \pcount_s_0[21] .INJECT1_1="NO"; + CCU2C \rcount_cry_0[0] ( + .A0(VCC), + .B0(un1_rcount_1_0_a3), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(rcount_cry[0]), + .S0(rcount_cry_0_S0[0]), + .S1(rcount_s[0]) +); +defparam \rcount_cry_0[0] .INIT0=16'h5003; +defparam \rcount_cry_0[0] .INIT1=16'h4000; +defparam \rcount_cry_0[0] .INJECT1_0="NO"; +defparam \rcount_cry_0[0] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[1] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[1]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[2]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[0]), + .COUT(rcount_cry[2]), + .S0(rcount_s[1]), + .S1(rcount_s[2]) +); +defparam \rcount_cry_0[1] .INIT0=16'h4000; +defparam \rcount_cry_0[1] .INIT1=16'h4000; +defparam \rcount_cry_0[1] .INJECT1_0="NO"; +defparam \rcount_cry_0[1] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[3] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[3]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[4]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[2]), + .COUT(rcount_cry[4]), + .S0(rcount_s[3]), + .S1(rcount_s[4]) +); +defparam \rcount_cry_0[3] .INIT0=16'h4000; +defparam \rcount_cry_0[3] .INIT1=16'h4000; +defparam \rcount_cry_0[3] .INJECT1_0="NO"; +defparam \rcount_cry_0[3] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[5] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[5]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[6]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[4]), + .COUT(rcount_cry[6]), + .S0(rcount_s[5]), + .S1(rcount_s[6]) +); +defparam \rcount_cry_0[5] .INIT0=16'h4000; +defparam \rcount_cry_0[5] .INIT1=16'h4000; +defparam \rcount_cry_0[5] .INJECT1_0="NO"; +defparam \rcount_cry_0[5] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[7] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[7]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[8]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[6]), + .COUT(rcount_cry[8]), + .S0(rcount_s[7]), + .S1(rcount_s[8]) +); +defparam \rcount_cry_0[7] .INIT0=16'h4000; +defparam \rcount_cry_0[7] .INIT1=16'h4000; +defparam \rcount_cry_0[7] .INJECT1_0="NO"; +defparam \rcount_cry_0[7] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[9] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[9]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[10]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[8]), + .COUT(rcount_cry[10]), + .S0(rcount_s[9]), + .S1(rcount_s[10]) +); +defparam \rcount_cry_0[9] .INIT0=16'h4000; +defparam \rcount_cry_0[9] .INIT1=16'h4000; +defparam \rcount_cry_0[9] .INJECT1_0="NO"; +defparam \rcount_cry_0[9] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[11] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[11]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[12]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[10]), + .COUT(rcount_cry[12]), + .S0(rcount_s[11]), + .S1(rcount_s[12]) +); +defparam \rcount_cry_0[11] .INIT0=16'h4000; +defparam \rcount_cry_0[11] .INIT1=16'h4000; +defparam \rcount_cry_0[11] .INJECT1_0="NO"; +defparam \rcount_cry_0[11] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_cry_0[13] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[13]), + .C0(VCC), + .D0(VCC), + .A1(un1_rcount_1_0_a3), + .B1(rcount[14]), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[12]), + .COUT(rcount_cry[14]), + .S0(rcount_s[13]), + .S1(rcount_s[14]) +); +defparam \rcount_cry_0[13] .INIT0=16'h4000; +defparam \rcount_cry_0[13] .INIT1=16'h4000; +defparam \rcount_cry_0[13] .INJECT1_0="NO"; +defparam \rcount_cry_0[13] .INJECT1_1="NO"; +// @16:1304 + CCU2C \rcount_s_0[15] ( + .A0(un1_rcount_1_0_a3), + .B0(rcount[15]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rcount_cry[14]), + .COUT(rcount_s_0_COUT[15]), + .S0(rcount_s[15]), + .S1(rcount_s_0_S1[15]) +); +defparam \rcount_s_0[15] .INIT0=16'h4005; +defparam \rcount_s_0[15] .INIT1=16'h5003; +defparam \rcount_s_0[15] .INJECT1_0="NO"; +defparam \rcount_s_0[15] .INJECT1_1="NO"; + CCU2C \rhb_wait_cnt_cry_0[0] ( + .A0(VCC), + .B0(N_12), + .C0(VCC), + .D0(VCC), + .A1(N_12), + .B1(rhb_wait_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rhb_wait_cnt_cry[0]), + .S0(rhb_wait_cnt_cry_0_S0[0]), + .S1(rhb_wait_cnt_s[0]) +); +defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c; +defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[1] ( + .A0(N_12), + .B0(rhb_wait_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(N_12), + .B1(rhb_wait_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[0]), + .COUT(rhb_wait_cnt_cry[2]), + .S0(rhb_wait_cnt_s[1]), + .S1(rhb_wait_cnt_s[2]) +); +defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[3] ( + .A0(N_12), + .B0(rhb_wait_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(N_12), + .B1(rhb_wait_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[2]), + .COUT(rhb_wait_cnt_cry[4]), + .S0(rhb_wait_cnt_s[3]), + .S1(rhb_wait_cnt_s[4]) +); +defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_cry_0[5] ( + .A0(N_12), + .B0(rhb_wait_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(N_12), + .B1(rhb_wait_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[4]), + .COUT(rhb_wait_cnt_cry[6]), + .S0(rhb_wait_cnt_s[5]), + .S1(rhb_wait_cnt_s[6]) +); +defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:1350 + CCU2C \rhb_wait_cnt_s_0[7] ( + .A0(N_12), + .B0(rhb_wait_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rhb_wait_cnt_cry[6]), + .COUT(rhb_wait_cnt_s_0_COUT[7]), + .S0(rhb_wait_cnt_s[7]), + .S1(rhb_wait_cnt_s_0_S1[7]) +); +defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a; +defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO"; +defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO"; + CCU2C un1_pcount_diff_1_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff[0]), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(un1_pcount_diff_1_cry_0), + .S0(un1_pcount_diff_1_cry_0_0_S0), + .S1(un1_pcount_diff_1_cry_0_0_S1) +); +defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003; +defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_1_0 ( + .A0(un1_pcount_diff_1_axb_1), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_2), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_0), + .COUT(un1_pcount_diff_1_cry_2), + .S0(un1_pcount_diff_1_cry_1_0_S0), + .S1(un1_pcount_diff_1_cry_1_0_S1) +); +defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_3_0 ( + .A0(un1_pcount_diff_1_axb_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_2), + .COUT(un1_pcount_diff_1_cry_4), + .S0(un1_pcount_diff_1_cry_3_0_S0), + .S1(un1_pcount_diff_1_cry_3_0_S1) +); +defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_5_0 ( + .A0(un1_pcount_diff_1_axb_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_4), + .COUT(un1_pcount_diff_1_cry_6), + .S0(un1_pcount_diff_1_cry_5_0_S0), + .S1(un1_pcount_diff_1_cry_5_0_S1) +); +defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_7_0 ( + .A0(un1_pcount_diff_1_axb_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_6), + .COUT(un1_pcount_diff_1_cry_8), + .S0(un1_pcount_diff_1_cry_7_0_S0), + .S1(un1_pcount_diff_1_cry_7_0_S1) +); +defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_9_0 ( + .A0(un1_pcount_diff_1_axb_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_8), + .COUT(un1_pcount_diff_1_cry_10), + .S0(un1_pcount_diff_1_cry_9_0_S0), + .S1(un1_pcount_diff_1_cry_9_0_S1) +); +defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_11_0 ( + .A0(un1_pcount_diff_1_axb_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_10), + .COUT(un1_pcount_diff_1_cry_12), + .S0(un1_pcount_diff_1_cry_11_0_S0), + .S1(un1_pcount_diff_1_cry_11_0_S1) +); +defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_13_0 ( + .A0(un1_pcount_diff_1_axb_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_12), + .COUT(un1_pcount_diff_1_cry_14), + .S0(un1_pcount_diff_1_cry_13_0_S0), + .S1(un1_pcount_diff_1_cry_13_0_S1) +); +defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_15_0 ( + .A0(un1_pcount_diff_1_axb_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_14), + .COUT(un1_pcount_diff_1_cry_16), + .S0(un1_pcount_diff_1_cry_15_0_S0), + .S1(un1_pcount_diff_1_cry_15_0_S1) +); +defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_17_0 ( + .A0(N_8), + .B0(rdiff_comp_lock[2]), + .C0(un1_pcount_diff_1_cry_17_0_RNO), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_16), + .COUT(un1_pcount_diff_1_cry_18), + .S0(un1_pcount_diff_1_cry_17_0_S0), + .S1(un1_pcount_diff_1_cry_17_0_S1) +); +defparam un1_pcount_diff_1_cry_17_0.INIT0=16'hb404; +defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_cry_19_0 ( + .A0(un1_pcount_diff_1_axb_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un1_pcount_diff_1_axb_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_18), + .COUT(un1_pcount_diff_1_cry_20), + .S0(un1_pcount_diff_1_cry_19_0_S0), + .S1(un1_pcount_diff_1_cry_19_0_S1) +); +defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO"; +// @16:1786 + CCU2C un1_pcount_diff_1_s_21_0 ( + .A0(pcount[21]), + .B0(un13_lock_21), + .C0(N_8), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un1_pcount_diff_1_cry_20), + .COUT(un1_pcount_diff_1_s_21_0_COUT), + .S0(un1_pcount_diff_1_s_21_0_S0), + .S1(un1_pcount_diff_1_s_21_0_S1) +); +defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a; +defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003; +defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO"; +defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO"; + CCU2C un13_lock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(un13_lock_cry_0), + .S0(un13_lock_cry_0_0_S0), + .S1(un13_lock_cry_0_0_S1) +); +defparam un13_lock_cry_0_0.INIT0=16'h5003; +defparam un13_lock_cry_0_0.INIT1=16'h900a; +defparam un13_lock_cry_0_0.INJECT1_0="NO"; +defparam un13_lock_cry_0_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_0), + .COUT(un13_lock_cry_2), + .S0(un13_lock_cry_1_0_S0), + .S1(un13_lock_cry_1_0_S1) +); +defparam un13_lock_cry_1_0.INIT0=16'h900a; +defparam un13_lock_cry_1_0.INIT1=16'h900a; +defparam un13_lock_cry_1_0.INJECT1_0="NO"; +defparam un13_lock_cry_1_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_3_0 ( + .A0(un13_lock_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_2), + .COUT(un13_lock_cry_4), + .S0(un13_lock_cry_3_0_S0), + .S1(un13_lock_cry_3_0_S1) +); +defparam un13_lock_cry_3_0.INIT0=16'h500a; +defparam un13_lock_cry_3_0.INIT1=16'h500a; +defparam un13_lock_cry_3_0.INJECT1_0="NO"; +defparam un13_lock_cry_3_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_5_0 ( + .A0(un13_lock_5), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_4), + .COUT(un13_lock_cry_6), + .S0(un13_lock_cry_5_0_S0), + .S1(un13_lock_cry_5_0_S1) +); +defparam un13_lock_cry_5_0.INIT0=16'h900a; +defparam un13_lock_cry_5_0.INIT1=16'h500a; +defparam un13_lock_cry_5_0.INJECT1_0="NO"; +defparam un13_lock_cry_5_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_6), + .COUT(un13_lock_cry_8), + .S0(un13_lock_cry_7_0_S0), + .S1(un13_lock_cry_7_0_S1) +); +defparam un13_lock_cry_7_0.INIT0=16'h500a; +defparam un13_lock_cry_7_0.INIT1=16'h500a; +defparam un13_lock_cry_7_0.INJECT1_0="NO"; +defparam un13_lock_cry_7_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_8), + .COUT(un13_lock_cry_10), + .S0(un13_lock_cry_9_0_S0), + .S1(un13_lock_cry_9_0_S1) +); +defparam un13_lock_cry_9_0.INIT0=16'h500a; +defparam un13_lock_cry_9_0.INIT1=16'h500a; +defparam un13_lock_cry_9_0.INJECT1_0="NO"; +defparam un13_lock_cry_9_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_10), + .COUT(un13_lock_cry_12), + .S0(un13_lock_cry_11_0_S0), + .S1(un13_lock_cry_11_0_S1) +); +defparam un13_lock_cry_11_0.INIT0=16'h500a; +defparam un13_lock_cry_11_0.INIT1=16'h500a; +defparam un13_lock_cry_11_0.INJECT1_0="NO"; +defparam un13_lock_cry_11_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_12), + .COUT(un13_lock_cry_14), + .S0(un13_lock_cry_13_0_S0), + .S1(un13_lock_cry_13_0_S1) +); +defparam un13_lock_cry_13_0.INIT0=16'h500a; +defparam un13_lock_cry_13_0.INIT1=16'h500a; +defparam un13_lock_cry_13_0.INJECT1_0="NO"; +defparam un13_lock_cry_13_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_14), + .COUT(un13_lock_cry_16), + .S0(un13_lock_cry_15_0_S0), + .S1(un13_lock_cry_15_0_S1) +); +defparam un13_lock_cry_15_0.INIT0=16'h500a; +defparam un13_lock_cry_15_0.INIT1=16'h500a; +defparam un13_lock_cry_15_0.INJECT1_0="NO"; +defparam un13_lock_cry_15_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_16), + .COUT(un13_lock_cry_18), + .S0(un13_lock_cry_17_0_S0), + .S1(un13_lock_cry_17_0_S1) +); +defparam un13_lock_cry_17_0.INIT0=16'h500a; +defparam un13_lock_cry_17_0.INIT1=16'h500a; +defparam un13_lock_cry_17_0.INJECT1_0="NO"; +defparam un13_lock_cry_17_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_18), + .COUT(un13_lock_cry_20), + .S0(un13_lock_cry_19_0_S0), + .S1(un13_lock_cry_19_0_S1) +); +defparam un13_lock_cry_19_0.INIT0=16'h500a; +defparam un13_lock_cry_19_0.INIT1=16'h500a; +defparam un13_lock_cry_19_0.INJECT1_0="NO"; +defparam un13_lock_cry_19_0.INJECT1_1="NO"; +// @16:1296 + CCU2C un13_lock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_lock_cry_20), + .COUT(un13_lock_cry_21_0_COUT), + .S0(un13_lock_cry_21_0_S0), + .S1(un13_lock_cry_21_i) +); +defparam un13_lock_cry_21_0.INIT0=16'h500f; +defparam un13_lock_cry_21_0.INIT1=16'ha003; +defparam un13_lock_cry_21_0.INJECT1_0="NO"; +defparam un13_lock_cry_21_0.INJECT1_1="NO"; + CCU2C un13_unlock_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_0), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(un13_unlock_cry_0), + .S0(un13_unlock_cry_0_0_S0), + .S1(un13_unlock_cry_0_0_S1) +); +defparam un13_unlock_cry_0_0.INIT0=16'h5003; +defparam un13_unlock_cry_0_0.INIT1=16'h500a; +defparam un13_unlock_cry_0_0.INJECT1_0="NO"; +defparam un13_unlock_cry_0_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_1_0 ( + .A0(un13_lock_1), + .B0(rdiff_comp_lock[2]), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_2), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_0), + .COUT(un13_unlock_cry_2), + .S0(un13_unlock_cry_1_0_S0), + .S1(un13_unlock_cry_1_0_S1) +); +defparam un13_unlock_cry_1_0.INIT0=16'h900a; +defparam un13_unlock_cry_1_0.INIT1=16'h900a; +defparam un13_unlock_cry_1_0.INJECT1_0="NO"; +defparam un13_unlock_cry_1_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_3_0 ( + .A0(un13_lock_3), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_4), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_2), + .COUT(un13_unlock_cry_4), + .S0(un13_unlock_cry_3_0_S0), + .S1(un13_unlock_cry_3_0_S1) +); +defparam un13_unlock_cry_3_0.INIT0=16'h500a; +defparam un13_unlock_cry_3_0.INIT1=16'h500a; +defparam un13_unlock_cry_3_0.INJECT1_0="NO"; +defparam un13_unlock_cry_3_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_5_0 ( + .A0(un13_lock_5), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_6), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_4), + .COUT(un13_unlock_cry_6), + .S0(un13_unlock_cry_5_0_S0), + .S1(un13_unlock_cry_5_0_S1) +); +defparam un13_unlock_cry_5_0.INIT0=16'h500a; +defparam un13_unlock_cry_5_0.INIT1=16'h500a; +defparam un13_unlock_cry_5_0.INJECT1_0="NO"; +defparam un13_unlock_cry_5_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_7_0 ( + .A0(un13_lock_7), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_8), + .B1(rdiff_comp_lock[2]), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_6), + .COUT(un13_unlock_cry_8), + .S0(un13_unlock_cry_7_0_S0), + .S1(un13_unlock_cry_7_0_S1) +); +defparam un13_unlock_cry_7_0.INIT0=16'h500a; +defparam un13_unlock_cry_7_0.INIT1=16'h900a; +defparam un13_unlock_cry_7_0.INJECT1_0="NO"; +defparam un13_unlock_cry_7_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_9_0 ( + .A0(un13_lock_9), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_10), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_8), + .COUT(un13_unlock_cry_10), + .S0(un13_unlock_cry_9_0_S0), + .S1(un13_unlock_cry_9_0_S1) +); +defparam un13_unlock_cry_9_0.INIT0=16'h500a; +defparam un13_unlock_cry_9_0.INIT1=16'h500a; +defparam un13_unlock_cry_9_0.INJECT1_0="NO"; +defparam un13_unlock_cry_9_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_11_0 ( + .A0(un13_lock_11), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_12), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_10), + .COUT(un13_unlock_cry_12), + .S0(un13_unlock_cry_11_0_S0), + .S1(un13_unlock_cry_11_0_S1) +); +defparam un13_unlock_cry_11_0.INIT0=16'h500a; +defparam un13_unlock_cry_11_0.INIT1=16'h500a; +defparam un13_unlock_cry_11_0.INJECT1_0="NO"; +defparam un13_unlock_cry_11_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_13_0 ( + .A0(un13_lock_13), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_14), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_12), + .COUT(un13_unlock_cry_14), + .S0(un13_unlock_cry_13_0_S0), + .S1(un13_unlock_cry_13_0_S1) +); +defparam un13_unlock_cry_13_0.INIT0=16'h500a; +defparam un13_unlock_cry_13_0.INIT1=16'h500a; +defparam un13_unlock_cry_13_0.INJECT1_0="NO"; +defparam un13_unlock_cry_13_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_15_0 ( + .A0(un13_lock_15), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_16), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_14), + .COUT(un13_unlock_cry_16), + .S0(un13_unlock_cry_15_0_S0), + .S1(un13_unlock_cry_15_0_S1) +); +defparam un13_unlock_cry_15_0.INIT0=16'h500a; +defparam un13_unlock_cry_15_0.INIT1=16'h500a; +defparam un13_unlock_cry_15_0.INJECT1_0="NO"; +defparam un13_unlock_cry_15_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_17_0 ( + .A0(un13_lock_17), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_18), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_16), + .COUT(un13_unlock_cry_18), + .S0(un13_unlock_cry_17_0_S0), + .S1(un13_unlock_cry_17_0_S1) +); +defparam un13_unlock_cry_17_0.INIT0=16'h500a; +defparam un13_unlock_cry_17_0.INIT1=16'h500a; +defparam un13_unlock_cry_17_0.INJECT1_0="NO"; +defparam un13_unlock_cry_17_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_19_0 ( + .A0(un13_lock_19), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(un13_lock_20), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_18), + .COUT(un13_unlock_cry_20), + .S0(un13_unlock_cry_19_0_S0), + .S1(un13_unlock_cry_19_0_S1) +); +defparam un13_unlock_cry_19_0.INIT0=16'h500a; +defparam un13_unlock_cry_19_0.INIT1=16'h500a; +defparam un13_unlock_cry_19_0.INJECT1_0="NO"; +defparam un13_unlock_cry_19_0.INJECT1_1="NO"; +// @16:1290 + CCU2C un13_unlock_cry_21_0 ( + .A0(un13_lock_21), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(un13_unlock_cry_20), + .COUT(un13_unlock_cry_21_0_COUT), + .S0(un13_unlock_cry_21_0_S0), + .S1(un13_unlock_cry_21) +); +defparam un13_unlock_cry_21_0.INIT0=16'h500f; +defparam un13_unlock_cry_21_0.INIT1=16'h5003; +defparam un13_unlock_cry_21_0.INJECT1_0="NO"; +defparam un13_unlock_cry_21_0.INJECT1_1="NO"; +//@8:425 +//@16:1801 +//@8:425 +// @16:1211 + sync_0s phb_sync_inst ( + .phb(phb), + .rhb_sync(rhb_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); +// @16:1220 + sync_0s_6 rtc_sync_inst ( + .rtc_pul(rtc_pul), + .ppul_sync(ppul_sync), + .sli_rst(sli_rst), + .tx_pclk(tx_pclk) +); +// @16:1228 + sync_0s_0 pdiff_sync_inst ( + .ppul_sync(ppul_sync), + .pdiff_sync(pdiff_sync), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* serdes_sync_1sll_core_Z1_layer1 */ + +module serdes_sync_1rsl_core_Z2_layer1 ( + rx_pcs_rst_c, + serdes_rst_dual_c, + tx_serdes_rst_c, + rsl_tx_pcs_rst_c, + rst_dual_c, + rsl_rx_pcs_rst_c, + rsl_tx_serdes_rst_c, + rsl_tx_rdy, + pll_lock_i, + pll_refclki, + rsl_rx_rdy, + rx_cdr_lol_s, + rx_los_low_s, + rsl_rst, + rxrefclk, + rx_serdes_rst_c, + rsl_rx_serdes_rst_c, + rsl_serdes_rst_dual_c, + rsl_disable, + tx_pcs_rst_c +) +; +input rx_pcs_rst_c ; +input serdes_rst_dual_c ; +input tx_serdes_rst_c ; +output rsl_tx_pcs_rst_c ; +input rst_dual_c ; +output rsl_rx_pcs_rst_c ; +output rsl_tx_serdes_rst_c ; +output rsl_tx_rdy ; +input pll_lock_i ; +input pll_refclki ; +output rsl_rx_rdy ; +input rx_cdr_lol_s ; +input rx_los_low_s ; +input rsl_rst ; +input rxrefclk ; +input rx_serdes_rst_c ; +output rsl_rx_serdes_rst_c ; +output rsl_serdes_rst_dual_c ; +input rsl_disable ; +input tx_pcs_rst_c ; +wire rx_pcs_rst_c ; +wire serdes_rst_dual_c ; +wire tx_serdes_rst_c ; +wire rsl_tx_pcs_rst_c ; +wire rst_dual_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_tx_serdes_rst_c ; +wire rsl_tx_rdy ; +wire pll_lock_i ; +wire pll_refclki ; +wire rsl_rx_rdy ; +wire rx_cdr_lol_s ; +wire rx_los_low_s ; +wire rsl_rst ; +wire rxrefclk ; +wire rx_serdes_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_disable ; +wire tx_pcs_rst_c ; +wire [2:0] plol0_cnt; +wire [2:0] plol0_cnt_3; +wire [0:0] rxsr_appd; +wire [1:0] rxs_cnt_3; +wire [1:0] rxs_cnt; +wire [1:0] rxs_cnt_QN; +wire [3:0] rlos_db_cnt; +wire [3:0] rlos_db_cnt_QN; +wire [17:0] rlols0_cnt_s; +wire [17:0] rlols0_cnt; +wire [17:0] rlols0_cnt_QN; +wire [3:0] rlol_db_cnt; +wire [3:0] rlol_db_cnt_QN; +wire [18:0] rlol1_cnt_s; +wire [18:0] rlol1_cnt; +wire [18:0] rlol1_cnt_QN; +wire [11:0] rxr_wt_cnt_s; +wire [11:0] rxr_wt_cnt; +wire [11:0] rxr_wt_cnt_QN; +wire [0:0] rxsr_appd_QN; +wire [0:0] rxpr_appd; +wire [0:0] rxpr_appd_QN; +wire [1:0] txs_cnt; +wire [1:0] txs_cnt_QN; +wire [1:1] txs_cnt_RNO; +wire [1:0] txp_cnt; +wire [1:0] txp_cnt_QN; +wire [1:1] txp_cnt_RNO; +wire [19:0] plol_cnt_s; +wire [19:0] plol_cnt; +wire [19:0] plol_cnt_QN; +wire [2:0] plol0_cnt_QN; +wire [11:0] txr_wt_cnt_s; +wire [11:0] txr_wt_cnt; +wire [11:0] txr_wt_cnt_QN; +wire [0:0] txpr_appd; +wire [0:0] txpr_appd_QN; +wire [0:0] un1_rlol_db_cnt_zero; +wire [0:0] un1_rlos_db_cnt_zero; +wire [0:0] un1_rlol_db_cnt_zero_bm; +wire [0:0] un1_rlol_db_cnt_zero_am; +wire [0:0] un1_rlos_db_cnt_zero_bm; +wire [0:0] un1_rlos_db_cnt_zero_am; +wire [16:0] rlol1_cnt_cry; +wire [0:0] rlol1_cnt_cry_0_S0; +wire [17:17] rlol1_cnt_cry_0_COUT; +wire [16:0] rlols0_cnt_cry; +wire [0:0] rlols0_cnt_cry_0_S0; +wire [17:17] rlols0_cnt_s_0_COUT; +wire [17:17] rlols0_cnt_s_0_S1; +wire [10:0] txr_wt_cnt_cry; +wire [0:0] txr_wt_cnt_cry_0_S0; +wire [11:11] txr_wt_cnt_s_0_COUT; +wire [11:11] txr_wt_cnt_s_0_S1; +wire [10:0] rxr_wt_cnt_cry; +wire [0:0] rxr_wt_cnt_cry_0_S0; +wire [11:11] rxr_wt_cnt_s_0_COUT; +wire [11:11] rxr_wt_cnt_s_0_S1; +wire [18:0] plol_cnt_cry; +wire [0:0] plol_cnt_cry_0_S0; +wire [19:19] plol_cnt_s_0_COUT; +wire [19:19] plol_cnt_s_0_S1; +wire txdpr_appd ; +wire txp_rst ; +wire un2_rdo_tx_pcs_rst_c ; +wire rlos_db_p1 ; +wire rlos_db ; +wire rxp_rst25 ; +wire plol0_cnt9 ; +wire waita_plol0 ; +wire dual_or_serd_rst ; +wire un18_txr_wt_tc_8 ; +wire un18_txr_wt_tc_7 ; +wire un18_txr_wt_tc_6 ; +wire un1_dual_or_serd_rst_1_1 ; +wire un1_rui_rst_dual_c_1_1 ; +wire un17_rxr_wt_tc_8 ; +wire un17_rxr_wt_tc_7 ; +wire un17_rxr_wt_tc_6 ; +wire un3_rx_all_well_1 ; +wire rlol1_cnt_tc_1 ; +wire rxs_rst ; +wire rlol1_cnt_scalar ; +wire un2_plol_fedge_5_1 ; +wire un2_plol_fedge_5_i ; +wire N_2175_0 ; +wire waita_rlols06 ; +wire un1_rlols0_cnt_tc ; +wire waita_rlols0 ; +wire waita_rlols0_QN ; +wire VCC ; +wire wait_calib_RNO ; +wire un1_rlos_fedge_1 ; +wire wait_calib ; +wire wait_calib_QN ; +wire rxs_rst6 ; +wire un1_rxs_cnt_tc ; +wire rxs_rst_QN ; +wire un2_rlos_redge_1_i ; +wire rxp_rst2 ; +wire rxp_rst2_QN ; +wire rlos_p1 ; +wire rlos_p2 ; +wire rlos_p2_QN ; +wire rlos_p1_QN ; +wire rlos_db_p1_QN ; +wire rlos_db_cnt_axb_0 ; +wire rlos_db_cnt_cry_1_0_S0 ; +wire rlos_db_cnt_cry_1_0_S1 ; +wire rlos_db_cnt_s_3_0_S0 ; +wire un1_rlos_db_cnt_max ; +wire rlos_db_QN ; +wire rlols0_cnte ; +wire rlol_p1 ; +wire rlol_p2 ; +wire rlol_p2_QN ; +wire rlol_p1_QN ; +wire rlol_db ; +wire rlol_db_p1 ; +wire rlol_db_p1_QN ; +wire rlol_db_cnt_axb_0 ; +wire rlol_db_cnt_cry_1_0_S0 ; +wire rlol_db_cnt_cry_1_0_S1 ; +wire rlol_db_cnt_s_3_0_S0 ; +wire un1_rlol_db_cnt_max ; +wire rlol_db_QN ; +wire rlol1_cnte ; +wire rxsdr_appd_2 ; +wire rxsdr_appd_4 ; +wire rxsdr_appd_QN ; +wire un1_dual_or_rserd_rst_2_i ; +wire rxr_wt_en ; +wire rxr_wt_en_QN ; +wire rxr_wt_cnte ; +wire un1_rui_rst_dual_c_1_i ; +wire rxdpr_appd ; +wire rxdpr_appd_QN ; +wire un3_rx_all_well_2 ; +wire rxr_wt_cnt9 ; +wire ruo_rx_rdyr_QN ; +wire un2_rdo_serdes_rst_dual_c_1 ; +wire un2_rdo_serdes_rst_dual_c_2_i ; +wire plol_fedge ; +wire un1_plol0_cnt_tc_1_i ; +wire waita_plol0_QN ; +wire un1_plol_cnt_tc ; +wire un2_plol_cnt_tc ; +wire txs_rst ; +wire txs_rst_QN ; +wire N_10_i ; +wire un9_plol0_cnt_tc ; +wire un1_plol0_cnt_tc_1 ; +wire txp_rst_QN ; +wire N_11_i ; +wire pll_lol_p2 ; +wire pll_lol_p3 ; +wire pll_lol_p3_QN ; +wire pll_lol_p1 ; +wire pll_lol_p2_QN ; +wire pll_lol_p1_QN ; +wire txsr_appd_2 ; +wire txsr_appd_4 ; +wire txsr_appd_QN ; +wire un1_dual_or_serd_rst_1_i ; +wire txr_wt_en ; +wire txr_wt_en_QN ; +wire txr_wt_cnte ; +wire un2_plol_fedge_2 ; +wire un2_plol_fedge_3_i ; +wire txdpr_appd_QN ; +wire ruo_tx_rdyr_QN ; +wire un2_plol_fedge_8_i ; +wire rlols0_cnt_tc_1 ; +wire rlos_redge ; +wire rlols0_cnt11_0 ; +wire plol_cnt_scalar ; +wire rlols0_cnt_scalar ; +wire un8_rxs_cnt_tc ; +wire un17_rxr_wt_tc ; +wire un1_dual_or_rserd_rst_2_0 ; +wire un1_rxsdr_or_sr_appd_0 ; +wire un2_rdo_serdes_rst_dual_c_2_0 ; +wire txr_wt_cnt9 ; +wire rx_any_rst ; +wire un18_txr_wt_tc ; +wire rlols0_cnt_tc_1_10 ; +wire rlols0_cnt_tc_1_11 ; +wire rlols0_cnt_tc_1_12 ; +wire rlols0_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_11 ; +wire rlol1_cnt_tc_1_12 ; +wire rlol1_cnt_tc_1_13 ; +wire rlol1_cnt_tc_1_14 ; +wire un1_plol_cnt_tc_11 ; +wire un1_plol_cnt_tc_12 ; +wire un1_plol_cnt_tc_13 ; +wire un1_plol_cnt_tc_14 ; +wire CO0_2 ; +wire rlols0_cnt_tc_1_9 ; +wire un1_plol_cnt_tc_10 ; +wire rlol1_cnt_tc_1_10 ; +wire un3_rx_all_well_2_1 ; +wire rlos_db_cnt_cry_0 ; +wire rlos_db_cnt_cry_0_0_S0 ; +wire rlos_db_cnt_cry_0_0_S1 ; +wire rlos_db_cnt_cry_2 ; +wire rlos_db_cnt_s_3_0_COUT ; +wire rlos_db_cnt_s_3_0_S1 ; +wire rlol_db_cnt_cry_0 ; +wire rlol_db_cnt_cry_0_0_S0 ; +wire rlol_db_cnt_cry_0_0_S1 ; +wire rlol_db_cnt_cry_2 ; +wire rlol_db_cnt_s_3_0_COUT ; +wire rlol_db_cnt_s_3_0_S1 ; +wire GND ; +wire N_1 ; +wire N_2 ; +wire N_3 ; +wire N_4 ; +wire N_5 ; +wire N_6 ; +wire N_7 ; + LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO_0[0] ( + .A(txdpr_appd), + .B(tx_pcs_rst_c), + .C(txp_rst), + .D(rsl_disable), + .Z(un2_rdo_tx_pcs_rst_c) +); +defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO_0[0] .init=16'hEEFE; + LUT4 \genblk2.rxp_rst2_RNO ( + .A(rsl_serdes_rst_dual_c), + .B(rsl_rx_serdes_rst_c), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rxp_rst25) +); +defparam \genblk2.rxp_rst2_RNO .init=16'hEFEE; + LUT4 \genblk1.plol0_cnt_RNO[1] ( + .A(plol0_cnt[1]), + .B(plol0_cnt9), + .C(waita_plol0), + .D(plol0_cnt[0]), + .Z(plol0_cnt_3[1]) +); +defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222; + LUT4 \genblk1.genblk2.un18_txr_wt_tc_6_RNI7IS21 ( + .A(dual_or_serd_rst), + .B(un18_txr_wt_tc_8), + .C(un18_txr_wt_tc_7), + .D(un18_txr_wt_tc_6), + .Z(un1_dual_or_serd_rst_1_1) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_6_RNI7IS21 .init=16'h1555; + LUT4 \genblk2.genblk3.rxr_wt_en_RNO ( + .A(un1_rui_rst_dual_c_1_1), + .B(un17_rxr_wt_tc_8), + .C(un17_rxr_wt_tc_7), + .D(un17_rxr_wt_tc_6), + .Z(un3_rx_all_well_1) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h2AAA; + LUT4 \genblk2.rlos_db_p1_RNIS0OP ( + .A(rlol1_cnt_tc_1), + .B(rxs_rst), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlol1_cnt_scalar) +); +defparam \genblk2.rlos_db_p1_RNIS0OP .init=16'h1011; + LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO ( + .A(un2_plol_fedge_5_1), + .B(un18_txr_wt_tc_8), + .C(un18_txr_wt_tc_7), + .D(un18_txr_wt_tc_6), + .Z(un2_plol_fedge_5_i) +); +defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hD555; + LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] ( + .A(rxsr_appd[0]), + .B(rx_serdes_rst_c), + .C(rxs_rst), + .D(rsl_disable), + .Z(N_2175_0) +); +defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE; +// @16:759 + FD1P3DX \genblk2.waita_rlols0 ( + .D(waita_rlols06), + .SP(un1_rlols0_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(waita_rlols0) +); +// @16:656 + FD1P3BX \genblk2.wait_calib ( + .D(wait_calib_RNO), + .SP(un1_rlos_fedge_1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(wait_calib) +); +// @16:694 + FD1P3DX \genblk2.rxs_rst ( + .D(rxs_rst6), + .SP(un1_rxs_cnt_tc), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_rst) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[0] ( + .D(rxs_cnt_3[0]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[0]) +); +// @16:694 + FD1S3DX \genblk2.rxs_cnt[1] ( + .D(rxs_cnt_3[1]), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxs_cnt[1]) +); +// @16:806 + FD1P3BX \genblk2.rxp_rst2 ( + .D(rxp_rst25), + .SP(un2_rlos_redge_1_i), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxp_rst2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p2 ( + .D(rlos_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p2) +); +// @16:567 + FD1S3DX \genblk2.rlos_p1 ( + .D(rx_los_low_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlos_p1) +); +// @16:567 + FD1S3BX \genblk2.rlos_db_p1 ( + .D(rlos_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_p1) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[0] ( + .D(rlos_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[0]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[1] ( + .D(rlos_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[1]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[2] ( + .D(rlos_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[2]) +); +// @16:640 + FD1S3BX \genblk2.rlos_db_cnt[3] ( + .D(rlos_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db_cnt[3]) +); +// @16:649 + FD1P3BX \genblk2.rlos_db ( + .D(rlos_db_cnt[1]), + .SP(un1_rlos_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlos_db) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[0] ( + .D(rlols0_cnt_s[0]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[0]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[1] ( + .D(rlols0_cnt_s[1]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[1]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[2] ( + .D(rlols0_cnt_s[2]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[2]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[3] ( + .D(rlols0_cnt_s[3]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[3]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[4] ( + .D(rlols0_cnt_s[4]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[4]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[5] ( + .D(rlols0_cnt_s[5]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[5]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[6] ( + .D(rlols0_cnt_s[6]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[6]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[7] ( + .D(rlols0_cnt_s[7]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[7]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[8] ( + .D(rlols0_cnt_s[8]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[8]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[9] ( + .D(rlols0_cnt_s[9]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[9]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[10] ( + .D(rlols0_cnt_s[10]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[10]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[11] ( + .D(rlols0_cnt_s[11]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[11]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[12] ( + .D(rlols0_cnt_s[12]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[12]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[13] ( + .D(rlols0_cnt_s[13]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[13]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[14] ( + .D(rlols0_cnt_s[14]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[14]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[15] ( + .D(rlols0_cnt_s[15]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[15]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[16] ( + .D(rlols0_cnt_s[16]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[16]) +); +// @16:778 + FD1P3DX \genblk2.rlols0_cnt[17] ( + .D(rlols0_cnt_s[17]), + .SP(rlols0_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlols0_cnt[17]) +); +// @16:567 + FD1S3DX \genblk2.rlol_p2 ( + .D(rlol_p1), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p2) +); +// @16:567 + FD1S3DX \genblk2.rlol_p1 ( + .D(rx_cdr_lol_s), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol_p1) +); +// @16:567 + FD1S3BX \genblk2.rlol_db_p1 ( + .D(rlol_db), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_p1) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[0] ( + .D(rlol_db_cnt_axb_0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[0]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[1] ( + .D(rlol_db_cnt_cry_1_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[1]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[2] ( + .D(rlol_db_cnt_cry_1_0_S1), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[2]) +); +// @16:624 + FD1S3BX \genblk2.rlol_db_cnt[3] ( + .D(rlol_db_cnt_s_3_0_S0), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db_cnt[3]) +); +// @16:633 + FD1P3BX \genblk2.rlol_db ( + .D(rlol_db_cnt[1]), + .SP(un1_rlol_db_cnt_max), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rlol_db) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[0] ( + .D(rlol1_cnt_s[0]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[0]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[1] ( + .D(rlol1_cnt_s[1]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[1]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[2] ( + .D(rlol1_cnt_s[2]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[2]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[3] ( + .D(rlol1_cnt_s[3]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[3]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[4] ( + .D(rlol1_cnt_s[4]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[4]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[5] ( + .D(rlol1_cnt_s[5]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[5]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[6] ( + .D(rlol1_cnt_s[6]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[6]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[7] ( + .D(rlol1_cnt_s[7]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[7]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[8] ( + .D(rlol1_cnt_s[8]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[8]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[9] ( + .D(rlol1_cnt_s[9]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[9]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[10] ( + .D(rlol1_cnt_s[10]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[10]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[11] ( + .D(rlol1_cnt_s[11]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[11]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[12] ( + .D(rlol1_cnt_s[12]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[12]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[13] ( + .D(rlol1_cnt_s[13]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[13]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[14] ( + .D(rlol1_cnt_s[14]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[14]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[15] ( + .D(rlol1_cnt_s[15]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[15]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[16] ( + .D(rlol1_cnt_s[16]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[16]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[17] ( + .D(rlol1_cnt_s[17]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[17]) +); +// @16:680 + FD1P3DX \genblk2.rlol1_cnt[18] ( + .D(rlol1_cnt_s[18]), + .SP(rlol1_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rlol1_cnt[18]) +); +// @16:865 + FD1S3BX \genblk2.genblk3.rxsdr_appd ( + .D(rxsdr_appd_2), + .CK(rxrefclk), + .PD(rsl_rst), + .Q(rxsdr_appd_4) +); +// @16:900 + FD1P3DX \genblk2.genblk3.rxr_wt_en ( + .D(un3_rx_all_well_1), + .SP(un1_dual_or_rserd_rst_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_en) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0] ( + .D(rxr_wt_cnt_s[0]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[0]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1] ( + .D(rxr_wt_cnt_s[1]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[1]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2] ( + .D(rxr_wt_cnt_s[2]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[2]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3] ( + .D(rxr_wt_cnt_s[3]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[3]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4] ( + .D(rxr_wt_cnt_s[4]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[4]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5] ( + .D(rxr_wt_cnt_s[5]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[5]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6] ( + .D(rxr_wt_cnt_s[6]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[6]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7] ( + .D(rxr_wt_cnt_s[7]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[7]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8] ( + .D(rxr_wt_cnt_s[8]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[8]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9] ( + .D(rxr_wt_cnt_s[9]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[9]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10] ( + .D(rxr_wt_cnt_s[10]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[10]) +); +// @16:909 + FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11] ( + .D(rxr_wt_cnt_s[11]), + .SP(rxr_wt_cnte), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxr_wt_cnt[11]) +); +// @16:871 + FD1P3DX \genblk2.genblk3.rxdpr_appd ( + .D(un1_rui_rst_dual_c_1_1), + .SP(un1_rui_rst_dual_c_1_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxdpr_appd) +); +// @16:920 + FD1P3DX \genblk2.genblk3.ruo_rx_rdyr ( + .D(un3_rx_all_well_2), + .SP(rxr_wt_cnt9), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rsl_rx_rdy) +); +// @16:882 + FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0] ( + .D(N_2175_0), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxsr_appd[0]) +); +// @16:888 + FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0] ( + .D(un2_rdo_serdes_rst_dual_c_1), + .SP(un2_rdo_serdes_rst_dual_c_2_i), + .CK(rxrefclk), + .CD(rsl_rst), + .Q(rxpr_appd[0]) +); +// @16:443 + FD1P3DX \genblk1.waita_plol0 ( + .D(plol_fedge), + .SP(un1_plol0_cnt_tc_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(waita_plol0) +); +// @16:422 + FD1P3DX \genblk1.txs_rst ( + .D(un1_plol_cnt_tc), + .SP(un2_plol_cnt_tc), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_rst) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[0] ( + .D(N_10_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[0]) +); +// @16:422 + FD1S3DX \genblk1.txs_cnt[1] ( + .D(txs_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txs_cnt[1]) +); +// @16:461 + FD1P3DX \genblk1.txp_rst ( + .D(un9_plol0_cnt_tc), + .SP(un1_plol0_cnt_tc_1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_rst) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[0] ( + .D(N_11_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[0]) +); +// @16:461 + FD1S3DX \genblk1.txp_cnt[1] ( + .D(txp_cnt_RNO[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txp_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[0] ( + .D(plol_cnt_s[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[0]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[1] ( + .D(plol_cnt_s[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[1]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[2] ( + .D(plol_cnt_s[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[2]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[3] ( + .D(plol_cnt_s[3]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[3]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[4] ( + .D(plol_cnt_s[4]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[4]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[5] ( + .D(plol_cnt_s[5]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[5]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[6] ( + .D(plol_cnt_s[6]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[6]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[7] ( + .D(plol_cnt_s[7]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[7]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[8] ( + .D(plol_cnt_s[8]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[8]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[9] ( + .D(plol_cnt_s[9]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[9]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[10] ( + .D(plol_cnt_s[10]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[10]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[11] ( + .D(plol_cnt_s[11]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[11]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[12] ( + .D(plol_cnt_s[12]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[12]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[13] ( + .D(plol_cnt_s[13]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[13]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[14] ( + .D(plol_cnt_s[14]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[14]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[15] ( + .D(plol_cnt_s[15]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[15]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[16] ( + .D(plol_cnt_s[16]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[16]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[17] ( + .D(plol_cnt_s[17]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[17]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[18] ( + .D(plol_cnt_s[18]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[18]) +); +// @16:412 + FD1S3DX \genblk1.plol_cnt[19] ( + .D(plol_cnt_s[19]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol_cnt[19]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[0] ( + .D(plol0_cnt_3[0]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[0]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[1] ( + .D(plol0_cnt_3[1]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[1]) +); +// @16:451 + FD1S3DX \genblk1.plol0_cnt[2] ( + .D(plol0_cnt_3[2]), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(plol0_cnt[2]) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p3 ( + .D(pll_lol_p2), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p3) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p2 ( + .D(pll_lol_p1), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p2) +); +// @16:398 + FD1S3DX \genblk1.pll_lol_p1 ( + .D(pll_lock_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(pll_lol_p1) +); +// @16:492 + FD1S3BX \genblk1.genblk2.txsr_appd ( + .D(txsr_appd_2), + .CK(pll_refclki), + .PD(rsl_rst), + .Q(txsr_appd_4) +); +// @16:519 + FD1P3DX \genblk1.genblk2.txr_wt_en ( + .D(un1_dual_or_serd_rst_1_1), + .SP(un1_dual_or_serd_rst_1_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_en) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[0] ( + .D(txr_wt_cnt_s[0]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[0]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[1] ( + .D(txr_wt_cnt_s[1]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[1]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[2] ( + .D(txr_wt_cnt_s[2]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[2]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[3] ( + .D(txr_wt_cnt_s[3]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[3]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[4] ( + .D(txr_wt_cnt_s[4]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[4]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[5] ( + .D(txr_wt_cnt_s[5]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[5]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[6] ( + .D(txr_wt_cnt_s[6]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[6]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[7] ( + .D(txr_wt_cnt_s[7]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[7]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[8] ( + .D(txr_wt_cnt_s[8]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[8]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[9] ( + .D(txr_wt_cnt_s[9]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[9]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[10] ( + .D(txr_wt_cnt_s[10]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[10]) +); +// @16:527 + FD1P3DX \genblk1.genblk2.txr_wt_cnt[11] ( + .D(txr_wt_cnt_s[11]), + .SP(txr_wt_cnte), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txr_wt_cnt[11]) +); +// @16:498 + FD1P3DX \genblk1.genblk2.txdpr_appd ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_3_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txdpr_appd) +); +// @16:537 + FD1P3DX \genblk1.genblk2.ruo_tx_rdyr ( + .D(un2_plol_fedge_5_1), + .SP(un2_plol_fedge_5_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(rsl_tx_rdy) +); +// @16:509 + FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0] ( + .D(un2_plol_fedge_2), + .SP(un2_plol_fedge_8_i), + .CK(pll_refclki), + .CD(rsl_rst), + .Q(txpr_appd[0]) +); +// @16:422 + LUT4 \genblk1.txs_cnt_RNO[0] ( + .A(txs_cnt[0]), + .B(txs_rst), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(N_10_i) +); +defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6; +// @16:434 + LUT4 \genblk1.txs_cnt_RNO[1] ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(txs_rst), + .D(un1_plol_cnt_tc), + .Z(txs_cnt_RNO[1]) +); +defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C; +// @16:806 + LUT4 \genblk2.rxp_rst2_RNO_0 ( + .A(rlols0_cnt_tc_1), + .B(rlos_redge), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un2_rlos_redge_1_i) +); +defparam \genblk2.rxp_rst2_RNO_0 .init=16'hFFFE; +// @16:519 + LUT4 \genblk1.genblk2.txr_wt_en_RNO ( + .A(txpr_appd[0]), + .B(pll_lol_p2), + .C(un1_dual_or_serd_rst_1_1), + .D(rsl_tx_rdy), + .Z(un1_dual_or_serd_rst_1_i) +); +defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F; +// @8:395 + LUT4 \genblk2.wait_calib_RNIKRP81 ( + .A(rxs_rst), + .B(wait_calib), + .C(rlol1_cnt_tc_1), + .D(rlos_redge), + .Z(rlol1_cnte) +); +defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE; +// @16:317 + LUT4 \genblk2.rxs_rst6 ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(rxs_rst6) +); +defparam \genblk2.rxs_rst6 .init=16'h2020; +// @8:395 + LUT4 \genblk2.waita_rlols0_RNI266C ( + .A(rlols0_cnt11_0), + .B(waita_rlols0), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(rlols0_cnte) +); +defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE; +// @8:395 + LUT4 \genblk2.genblk3.rxr_wt_en_RNI1B6E ( + .A(rxr_wt_cnt9), + .B(rxr_wt_en), + .C(VCC), + .D(VCC), + .Z(rxr_wt_cnte) +); +defparam \genblk2.genblk3.rxr_wt_en_RNI1B6E .init=16'hEEEE; +// @16:412 + LUT4 \genblk1.plol_cnt11_i ( + .A(pll_lol_p2), + .B(un1_plol_cnt_tc), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(plol_cnt_scalar) +); +defparam \genblk1.plol_cnt11_i .init=16'h0202; +// @16:778 + LUT4 \genblk2.rlols0_cnt11_i ( + .A(rlols0_cnt11_0), + .B(rlols0_cnt_tc_1), + .C(VCC), + .D(VCC), + .Z(rlols0_cnt_scalar) +); +defparam \genblk2.rlols0_cnt11_i .init=16'h1111; +// @16:317 + LUT4 \genblk2.un1_rxs_cnt_tc ( + .A(rlol_db), + .B(rlos_db), + .C(un8_rxs_cnt_tc), + .D(rlol1_cnt_tc_1), + .Z(un1_rxs_cnt_tc) +); +defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC; +// @8:395 + LUT4 \genblk2.wait_calib_RNO ( + .A(rlol_db), + .B(rlos_db), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(wait_calib_RNO) +); +defparam \genblk2.wait_calib_RNO .init=16'hA3A3; +// @16:509 + LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] ( + .A(dual_or_serd_rst), + .B(un2_rdo_tx_pcs_rst_c), + .C(pll_lol_p2), + .D(txsr_appd_4), + .Z(un2_plol_fedge_8_i) +); +defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFEFA; +// @16:900 + LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0 ( + .A(un17_rxr_wt_tc), + .B(un1_dual_or_rserd_rst_2_0), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un1_dual_or_rserd_rst_2_i) +); +defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFFFB; +// @16:888 + LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] ( + .A(un1_rxsdr_or_sr_appd_0), + .B(un2_rdo_serdes_rst_dual_c_2_0), + .C(rsl_rx_pcs_rst_c), + .D(rsl_rx_serdes_rst_c), + .Z(un2_rdo_serdes_rst_dual_c_2_i) +); +defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'hFFB3; +// @16:871 + LUT4 \genblk2.genblk3.rxdpr_appd_RNO ( + .A(un1_rui_rst_dual_c_1_1), + .B(rst_dual_c), + .C(VCC), + .D(VCC), + .Z(un1_rui_rst_dual_c_1_i) +); +defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'hDDDD; +// @16:259 + LUT4 \genblk1.un2_plol_cnt_tc ( + .A(txs_cnt[0]), + .B(txs_cnt[1]), + .C(un1_plol_cnt_tc), + .D(VCC), + .Z(un2_plol_cnt_tc) +); +defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8; +// @8:395 + LUT4 \genblk1.genblk2.txr_wt_en_RNI1JHS ( + .A(txr_wt_cnt9), + .B(txr_wt_en), + .C(VCC), + .D(VCC), + .Z(txr_wt_cnte) +); +defparam \genblk1.genblk2.txr_wt_en_RNI1JHS .init=16'hEEEE; +// @16:913 + LUT4 \genblk2.genblk3.rxr_wt_cnt9 ( + .A(un17_rxr_wt_tc), + .B(rlol_db), + .C(rlos_db), + .D(rx_any_rst), + .Z(rxr_wt_cnt9) +); +defparam \genblk2.genblk3.rxr_wt_cnt9 .init=16'hFFFE; +// @16:340 + LUT4 \genblk2.un1_rlols0_cnt_tc ( + .A(rlols0_cnt11_0), + .B(waita_rlols06), + .C(rlols0_cnt_tc_1), + .D(VCC), + .Z(un1_rlols0_cnt_tc) +); +defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE; +// @16:322 + LUT4 \genblk2.un1_rlos_fedge_1 ( + .A(rlos_db), + .B(rlos_db_p1), + .C(rlol1_cnt_tc_1), + .D(VCC), + .Z(un1_rlos_fedge_1) +); +defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6; +// @16:498 + LUT4 \genblk1.genblk2.txdpr_appd_RNO ( + .A(dual_or_serd_rst), + .B(pll_lol_p2), + .C(rst_dual_c), + .D(VCC), + .Z(un2_plol_fedge_3_i) +); +defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFEFE; +// @16:461 + LUT4 \genblk1.txp_cnt_RNO[0] ( + .A(txp_cnt[0]), + .B(txp_rst), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(N_11_i) +); +defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6; +// @16:473 + LUT4 \genblk1.txp_cnt_RNO[1] ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(txp_rst), + .D(un9_plol0_cnt_tc), + .Z(txp_cnt_RNO[1]) +); +defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C; +// @16:366 + LUT4 un3_rx_all_well_2_cZ ( + .A(rlol_db), + .B(rlos_db), + .C(rx_any_rst), + .D(VCC), + .Z(un3_rx_all_well_2) +); +defparam un3_rx_all_well_2_cZ.init=16'h0101; +// @16:530 + LUT4 \genblk1.genblk2.txr_wt_cnt9 ( + .A(dual_or_serd_rst), + .B(un18_txr_wt_tc), + .C(rsl_tx_pcs_rst_c), + .D(rst_dual_c), + .Z(txr_wt_cnt9) +); +defparam \genblk1.genblk2.txr_wt_cnt9 .init=16'hFFFE; +// @16:282 + LUT4 un2_plol_fedge_5_1_cZ ( + .A(dual_or_serd_rst), + .B(pll_lol_p2), + .C(rsl_tx_pcs_rst_c), + .D(rst_dual_c), + .Z(un2_plol_fedge_5_1) +); +defparam un2_plol_fedge_5_1_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_cZ ( + .A(rlols0_cnt_tc_1_10), + .B(rlols0_cnt_tc_1_11), + .C(rlols0_cnt_tc_1_12), + .D(rlols0_cnt_tc_1_13), + .Z(rlols0_cnt_tc_1) +); +defparam rlols0_cnt_tc_1_cZ.init=16'h8000; +// @16:387 + LUT4 rlol1_cnt_tc_1_cZ ( + .A(rlol1_cnt_tc_1_11), + .B(rlol1_cnt_tc_1_12), + .C(rlol1_cnt_tc_1_13), + .D(rlol1_cnt_tc_1_14), + .Z(rlol1_cnt_tc_1) +); +defparam rlol1_cnt_tc_1_cZ.init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc ( + .A(un1_plol_cnt_tc_11), + .B(un1_plol_cnt_tc_12), + .C(un1_plol_cnt_tc_13), + .D(un1_plol_cnt_tc_14), + .Z(un1_plol_cnt_tc) +); +defparam \genblk1.un1_plol_cnt_tc .init=16'h8000; +// @16:625 + LUT4 \un1_genblk2.rlol_db_cnt_axb_0 ( + .A(rlol_db_cnt[0]), + .B(un1_rlol_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlol_db_cnt_axb_0) +); +defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999; +// @16:641 + LUT4 \un1_genblk2.rlos_db_cnt_axb_0 ( + .A(rlos_db_cnt[0]), + .B(un1_rlos_db_cnt_zero[0]), + .C(VCC), + .D(VCC), + .Z(rlos_db_cnt_axb_0) +); +defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999; +// @16:443 + LUT4 \genblk1.waita_plol0_RNO ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1_i) +); +defparam \genblk1.waita_plol0_RNO .init=16'hF6F6; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[2] ( + .A(CO0_2), + .B(plol0_cnt9), + .C(plol0_cnt[1]), + .D(plol0_cnt[2]), + .Z(plol0_cnt_3[2]) +); +defparam \genblk1.plol0_cnt_3[2] .init=16'h1320; +// @16:452 + LUT4 \genblk1.plol0_cnt_3[0] ( + .A(plol0_cnt9), + .B(plol0_cnt[0]), + .C(waita_plol0), + .D(VCC), + .Z(plol0_cnt_3[0]) +); +defparam \genblk1.plol0_cnt_3[0] .init=16'h1414; +// @16:211 + LUT4 un1_rui_rst_dual_c_1_1_cZ ( + .A(rlol_db), + .B(rlos_db), + .C(rsl_rx_serdes_rst_c), + .D(rsl_serdes_rst_dual_c), + .Z(un1_rui_rst_dual_c_1_1) +); +defparam un1_rui_rst_dual_c_1_1_cZ.init=16'h0001; +// @16:891 + LUT4 un2_rdo_serdes_rst_dual_c_1_cZ ( + .A(rsl_rx_serdes_rst_c), + .B(rsl_serdes_rst_dual_c), + .C(rx_cdr_lol_s), + .D(rx_los_low_s), + .Z(un2_rdo_serdes_rst_dual_c_1) +); +defparam un2_rdo_serdes_rst_dual_c_1_cZ.init=16'h0001; +// @16:493 + LUT4 \genblk1.genblk2.txsr_appd_2 ( + .A(dual_or_serd_rst), + .B(txsr_appd_4), + .C(VCC), + .D(VCC), + .Z(txsr_appd_2) +); +defparam \genblk1.genblk2.txsr_appd_2 .init=16'hEEEE; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc ( + .A(un18_txr_wt_tc_6), + .B(un18_txr_wt_tc_7), + .C(un18_txr_wt_tc_8), + .D(VCC), + .Z(un18_txr_wt_tc) +); +defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080; +// @16:211 + LUT4 un2_plol_fedge_2_cZ ( + .A(pll_lol_p2), + .B(rsl_serdes_rst_dual_c), + .C(rsl_tx_serdes_rst_c), + .D(VCC), + .Z(un2_plol_fedge_2) +); +defparam un2_plol_fedge_2_cZ.init=16'h0101; +// @16:863 + LUT4 rx_any_rst_cZ ( + .A(rsl_rx_pcs_rst_c), + .B(rsl_rx_serdes_rst_c), + .C(rsl_serdes_rst_dual_c), + .D(rst_dual_c), + .Z(rx_any_rst) +); +defparam rx_any_rst_cZ.init=16'hFFFE; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc ( + .A(un17_rxr_wt_tc_6), + .B(un17_rxr_wt_tc_7), + .C(un17_rxr_wt_tc_8), + .D(VCC), + .Z(un17_rxr_wt_tc) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_bm[0]) +); +defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlol_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlol_db_cnt_zero_bm[0]), + .BLUT(un1_rlol_db_cnt_zero_am[0]), + .C0(rlol_p2), + .Z(un1_rlol_db_cnt_zero[0]) +); +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_bm[0]) +); +defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000; +// @16:219 + PFUMX \un1_rlos_db_cnt_zero_cZ[0] ( + .ALUT(un1_rlos_db_cnt_zero_bm[0]), + .BLUT(un1_rlos_db_cnt_zero_am[0]), + .C0(rlos_p2), + .Z(un1_rlos_db_cnt_zero[0]) +); +// @16:708 + LUT4 \rxs_cnt_3_cZ[1] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[1]) +); +defparam \rxs_cnt_3_cZ[1] .init=16'h6464; +// @16:269 + LUT4 \genblk1.un1_plol0_cnt_tc_1 ( + .A(txp_cnt[0]), + .B(txp_cnt[1]), + .C(un9_plol0_cnt_tc), + .D(VCC), + .Z(un1_plol0_cnt_tc_1) +); +defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8; +// @16:309 + LUT4 \genblk2.un1_rlol_db_cnt_max ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_max) +); +defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001; +// @16:315 + LUT4 \genblk2.un1_rlos_db_cnt_max ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_max) +); +defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001; +// @16:764 + LUT4 \genblk2.waita_rlols06 ( + .A(rlol_db), + .B(rlol_db_p1), + .C(rlos_db), + .D(rlos_db_p1), + .Z(waita_rlols06) +); +defparam \genblk2.waita_rlols06 .init=16'h0504; +// @16:388 + LUT4 rlols0_cnt_tc_1_13_cZ ( + .A(rlols0_cnt[16]), + .B(rlols0_cnt[17]), + .C(rlols0_cnt_tc_1_9), + .D(VCC), + .Z(rlols0_cnt_tc_1_13) +); +defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_14 ( + .A(plol_cnt[5]), + .B(plol_cnt[10]), + .C(plol_cnt[18]), + .D(un1_plol_cnt_tc_10), + .Z(un1_plol_cnt_tc_14) +); +defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_14_cZ ( + .A(rlol1_cnt[12]), + .B(rlol1_cnt[13]), + .C(rlol1_cnt[18]), + .D(rlol1_cnt_tc_1_10), + .Z(rlol1_cnt_tc_1_14) +); +defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100; +// @16:891 + LUT4 un2_rdo_serdes_rst_dual_c_2_0_cZ ( + .A(rsl_serdes_rst_dual_c), + .B(rx_cdr_lol_s), + .C(rx_los_low_s), + .D(VCC), + .Z(un2_rdo_serdes_rst_dual_c_2_0) +); +defparam un2_rdo_serdes_rst_dual_c_2_0_cZ.init=16'h0101; +// @16:904 + LUT4 un1_dual_or_rserd_rst_2_0_cZ ( + .A(un3_rx_all_well_2_1), + .B(rlol_db), + .C(rlos_db), + .D(VCC), + .Z(un1_dual_or_rserd_rst_2_0) +); +defparam un1_dual_or_rserd_rst_2_0_cZ.init=16'h0101; +// @16:708 + LUT4 \rxs_cnt_3_cZ[0] ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(rxs_rst), + .D(VCC), + .Z(rxs_cnt_3[0]) +); +defparam \rxs_cnt_3_cZ[0] .init=16'h5252; +// @16:743 + LUT4 \rdo_rx_serdes_rst_c_1[0] ( + .A(rsl_disable), + .B(rxs_rst), + .C(rx_serdes_rst_c), + .D(VCC), + .Z(rsl_rx_serdes_rst_c) +); +defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4; +// @16:479 + LUT4 \rdo_tx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(txp_rst), + .C(tx_pcs_rst_c), + .D(VCC), + .Z(rsl_tx_pcs_rst_c) +); +defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:438 + LUT4 rdo_tx_serdes_rst_c ( + .A(rsl_disable), + .B(txs_rst), + .C(tx_serdes_rst_c), + .D(VCC), + .Z(rsl_tx_serdes_rst_c) +); +defparam rdo_tx_serdes_rst_c.init=16'hF4F4; +// @16:375 + LUT4 rdo_serdes_rst_dual_c ( + .A(rsl_disable), + .B(rsl_rst), + .C(serdes_rst_dual_c), + .D(VCC), + .Z(rsl_serdes_rst_dual_c) +); +defparam rdo_serdes_rst_dual_c.init=16'hF4F4; +// @16:906 + LUT4 \genblk2.genblk3.un3_rx_all_well_2_1 ( + .A(rxpr_appd[0]), + .B(rxdpr_appd), + .C(rsl_rx_rdy), + .D(VCC), + .Z(un3_rx_all_well_2_1) +); +defparam \genblk2.genblk3.un3_rx_all_well_2_1 .init=16'h0E0E; +// @16:852 + LUT4 \rdo_rx_pcs_rst_c_1[0] ( + .A(rsl_disable), + .B(rxp_rst2), + .C(rx_pcs_rst_c), + .D(VCC), + .Z(rsl_rx_pcs_rst_c) +); +defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4; +// @16:459 + LUT4 \genblk1.un9_plol0_cnt_tc ( + .A(plol0_cnt[0]), + .B(plol0_cnt[1]), + .C(plol0_cnt[2]), + .D(VCC), + .Z(un9_plol0_cnt_tc) +); +defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010; +// @16:893 + LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd_0 ( + .A(rxsr_appd[0]), + .B(rlol_db), + .C(rlos_db), + .D(rxsdr_appd_4), + .Z(un1_rxsdr_or_sr_appd_0) +); +defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd_0 .init=16'hFCA8; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_6 ( + .A(txr_wt_cnt[0]), + .B(txr_wt_cnt[8]), + .C(txr_wt_cnt[9]), + .D(txr_wt_cnt[11]), + .Z(un18_txr_wt_tc_6) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_7 ( + .A(txr_wt_cnt[3]), + .B(txr_wt_cnt[4]), + .C(txr_wt_cnt[5]), + .D(txr_wt_cnt[7]), + .Z(un18_txr_wt_tc_7) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000; +// @16:535 + LUT4 \genblk1.genblk2.un18_txr_wt_tc_8 ( + .A(txr_wt_cnt[1]), + .B(txr_wt_cnt[2]), + .C(txr_wt_cnt[6]), + .D(txr_wt_cnt[10]), + .Z(un18_txr_wt_tc_8) +); +defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6 ( + .A(rxr_wt_cnt[3]), + .B(rxr_wt_cnt[4]), + .C(rxr_wt_cnt[5]), + .D(rxr_wt_cnt[7]), + .Z(un17_rxr_wt_tc_6) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h8000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7 ( + .A(rxr_wt_cnt[0]), + .B(rxr_wt_cnt[8]), + .C(rxr_wt_cnt[9]), + .D(rxr_wt_cnt[11]), + .Z(un17_rxr_wt_tc_7) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h4000; +// @16:535 + LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8 ( + .A(rxr_wt_cnt[1]), + .B(rxr_wt_cnt[2]), + .C(rxr_wt_cnt[6]), + .D(rxr_wt_cnt[10]), + .Z(un17_rxr_wt_tc_8) +); +defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_9_cZ ( + .A(rlols0_cnt[9]), + .B(rlols0_cnt[11]), + .C(rlols0_cnt[12]), + .D(rlols0_cnt[13]), + .Z(rlols0_cnt_tc_1_9) +); +defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_10_cZ ( + .A(rlols0_cnt[5]), + .B(rlols0_cnt[6]), + .C(rlols0_cnt[7]), + .D(rlols0_cnt[8]), + .Z(rlols0_cnt_tc_1_10) +); +defparam rlols0_cnt_tc_1_10_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_11_cZ ( + .A(rlols0_cnt[1]), + .B(rlols0_cnt[2]), + .C(rlols0_cnt[3]), + .D(rlols0_cnt[4]), + .Z(rlols0_cnt_tc_1_11) +); +defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001; +// @16:388 + LUT4 rlols0_cnt_tc_1_12_cZ ( + .A(rlols0_cnt[0]), + .B(rlols0_cnt[10]), + .C(rlols0_cnt[14]), + .D(rlols0_cnt[15]), + .Z(rlols0_cnt_tc_1_12) +); +defparam rlols0_cnt_tc_1_12_cZ.init=16'h4000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_10 ( + .A(plol_cnt[1]), + .B(plol_cnt[6]), + .C(plol_cnt[7]), + .D(plol_cnt[12]), + .Z(un1_plol_cnt_tc_10) +); +defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h0080; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_11 ( + .A(plol_cnt[8]), + .B(plol_cnt[9]), + .C(plol_cnt[11]), + .D(plol_cnt[13]), + .Z(un1_plol_cnt_tc_11) +); +defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_12 ( + .A(plol_cnt[14]), + .B(plol_cnt[15]), + .C(plol_cnt[16]), + .D(plol_cnt[17]), + .Z(un1_plol_cnt_tc_12) +); +defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000; +// @16:386 + LUT4 \genblk1.un1_plol_cnt_tc_13 ( + .A(plol_cnt[2]), + .B(plol_cnt[3]), + .C(plol_cnt[4]), + .D(plol_cnt[19]), + .Z(un1_plol_cnt_tc_13) +); +defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0100; +// @16:387 + LUT4 rlol1_cnt_tc_1_10_cZ ( + .A(rlol1_cnt[14]), + .B(rlol1_cnt[15]), + .C(rlol1_cnt[16]), + .D(rlol1_cnt[17]), + .Z(rlol1_cnt_tc_1_10) +); +defparam rlol1_cnt_tc_1_10_cZ.init=16'h0800; +// @16:387 + LUT4 rlol1_cnt_tc_1_11_cZ ( + .A(rlol1_cnt[0]), + .B(rlol1_cnt[1]), + .C(rlol1_cnt[2]), + .D(rlol1_cnt[3]), + .Z(rlol1_cnt_tc_1_11) +); +defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_12_cZ ( + .A(rlol1_cnt[4]), + .B(rlol1_cnt[5]), + .C(rlol1_cnt[6]), + .D(rlol1_cnt[7]), + .Z(rlol1_cnt_tc_1_12) +); +defparam rlol1_cnt_tc_1_12_cZ.init=16'h0001; +// @16:387 + LUT4 rlol1_cnt_tc_1_13_cZ ( + .A(rlol1_cnt[8]), + .B(rlol1_cnt[9]), + .C(rlol1_cnt[10]), + .D(rlol1_cnt[11]), + .Z(rlol1_cnt_tc_1_13) +); +defparam rlol1_cnt_tc_1_13_cZ.init=16'h0001; +// @16:457 + LUT4 \genblk1.plol0_cnt_3_RNO[2] ( + .A(plol0_cnt[0]), + .B(waita_plol0), + .C(VCC), + .D(VCC), + .Z(CO0_2) +); +defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888; +// @16:441 + LUT4 plol_fedge_cZ ( + .A(pll_lol_p2), + .B(pll_lol_p3), + .C(VCC), + .D(VCC), + .Z(plol_fedge) +); +defparam plol_fedge_cZ.init=16'h4444; +// @16:436 + LUT4 \genblk2.un8_rxs_cnt_tc ( + .A(rxs_cnt[0]), + .B(rxs_cnt[1]), + .C(VCC), + .D(VCC), + .Z(un8_rxs_cnt_tc) +); +defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888; +// @16:757 + LUT4 rlos_redge_cZ ( + .A(rlos_db), + .B(rlos_db_p1), + .C(VCC), + .D(VCC), + .Z(rlos_redge) +); +defparam rlos_redge_cZ.init=16'h2222; +// @16:866 + LUT4 \genblk2.genblk3.rxsdr_appd_2 ( + .A(rxsdr_appd_4), + .B(serdes_rst_dual_c), + .C(VCC), + .D(VCC), + .Z(rxsdr_appd_2) +); +defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE; +// @16:219 + LUT4 \un1_rlos_db_cnt_zero_am_cZ[0] ( + .A(rlos_db_cnt[0]), + .B(rlos_db_cnt[1]), + .C(rlos_db_cnt[2]), + .D(rlos_db_cnt[3]), + .Z(un1_rlos_db_cnt_zero_am[0]) +); +defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:219 + LUT4 \un1_rlol_db_cnt_zero_am_cZ[0] ( + .A(rlol_db_cnt[0]), + .B(rlol_db_cnt[1]), + .C(rlol_db_cnt[2]), + .D(rlol_db_cnt[3]), + .Z(un1_rlol_db_cnt_zero_am[0]) +); +defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001; +// @16:488 + LUT4 dual_or_serd_rst_cZ ( + .A(rsl_serdes_rst_dual_c), + .B(tx_serdes_rst_c), + .C(txs_rst), + .D(rsl_disable), + .Z(dual_or_serd_rst) +); +defparam dual_or_serd_rst_cZ.init=16'hEEFE; +// @16:454 + LUT4 \genblk1.plol0_cnt9 ( + .A(pll_lol_p2), + .B(plol0_cnt[2]), + .C(plol0_cnt[1]), + .D(plol0_cnt[0]), + .Z(plol0_cnt9) +); +defparam \genblk1.plol0_cnt9 .init=16'hAAAE; +// @16:783 + LUT4 \genblk2.rlols0_cnt11_0 ( + .A(rlol_db_p1), + .B(rlol_db), + .C(rlos_db_p1), + .D(rlos_db), + .Z(rlols0_cnt11_0) +); +defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44; + CCU2C \genblk2.rlol1_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlol1_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_7), + .COUT(rlol1_cnt_cry[0]), + .S0(rlol1_cnt_cry_0_S0[0]), + .S1(rlol1_cnt_s[0]) +); +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[1] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[0]), + .COUT(rlol1_cnt_cry[2]), + .S0(rlol1_cnt_s[1]), + .S1(rlol1_cnt_s[2]) +); +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[3] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[2]), + .COUT(rlol1_cnt_cry[4]), + .S0(rlol1_cnt_s[3]), + .S1(rlol1_cnt_s[4]) +); +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[5] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[4]), + .COUT(rlol1_cnt_cry[6]), + .S0(rlol1_cnt_s[5]), + .S1(rlol1_cnt_s[6]) +); +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[7] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[6]), + .COUT(rlol1_cnt_cry[8]), + .S0(rlol1_cnt_s[7]), + .S1(rlol1_cnt_s[8]) +); +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[9] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[8]), + .COUT(rlol1_cnt_cry[10]), + .S0(rlol1_cnt_s[9]), + .S1(rlol1_cnt_s[10]) +); +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[11] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[10]), + .COUT(rlol1_cnt_cry[12]), + .S0(rlol1_cnt_s[11]), + .S1(rlol1_cnt_s[12]) +); +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[13] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[12]), + .COUT(rlol1_cnt_cry[14]), + .S0(rlol1_cnt_s[13]), + .S1(rlol1_cnt_s[14]) +); +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[15] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[14]), + .COUT(rlol1_cnt_cry[16]), + .S0(rlol1_cnt_s[15]), + .S1(rlol1_cnt_s[16]) +); +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:680 + CCU2C \genblk2.rlol1_cnt_cry_0[17] ( + .A0(rlol1_cnt_scalar), + .B0(rlol1_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(rlol1_cnt_scalar), + .B1(rlol1_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(rlol1_cnt_cry[16]), + .COUT(rlol1_cnt_cry_0_COUT[17]), + .S0(rlol1_cnt_s[17]), + .S1(rlol1_cnt_s[18]) +); +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO"; + CCU2C \genblk2.rlols0_cnt_cry_0[0] ( + .A0(VCC), + .B0(rlols0_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_6), + .COUT(rlols0_cnt_cry[0]), + .S0(rlols0_cnt_cry_0_S0[0]), + .S1(rlols0_cnt_s[0]) +); +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[1] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[0]), + .COUT(rlols0_cnt_cry[2]), + .S0(rlols0_cnt_s[1]), + .S1(rlols0_cnt_s[2]) +); +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[3] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[2]), + .COUT(rlols0_cnt_cry[4]), + .S0(rlols0_cnt_s[3]), + .S1(rlols0_cnt_s[4]) +); +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[5] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[4]), + .COUT(rlols0_cnt_cry[6]), + .S0(rlols0_cnt_s[5]), + .S1(rlols0_cnt_s[6]) +); +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[7] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[6]), + .COUT(rlols0_cnt_cry[8]), + .S0(rlols0_cnt_s[7]), + .S1(rlols0_cnt_s[8]) +); +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[9] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[8]), + .COUT(rlols0_cnt_cry[10]), + .S0(rlols0_cnt_s[9]), + .S1(rlols0_cnt_s[10]) +); +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[11] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[10]), + .COUT(rlols0_cnt_cry[12]), + .S0(rlols0_cnt_s[11]), + .S1(rlols0_cnt_s[12]) +); +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[13] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[12]), + .COUT(rlols0_cnt_cry[14]), + .S0(rlols0_cnt_s[13]), + .S1(rlols0_cnt_s[14]) +); +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_cry_0[15] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(rlols0_cnt_scalar), + .B1(rlols0_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[14]), + .COUT(rlols0_cnt_cry[16]), + .S0(rlols0_cnt_s[15]), + .S1(rlols0_cnt_s[16]) +); +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:778 + CCU2C \genblk2.rlols0_cnt_s_0[17] ( + .A0(rlols0_cnt_scalar), + .B0(rlols0_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlols0_cnt_cry[16]), + .COUT(rlols0_cnt_s_0_COUT[17]), + .S0(rlols0_cnt_s[17]), + .S1(rlols0_cnt_s_0_S1[17]) +); +defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a; +defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO"; +defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO"; + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(txr_wt_cnt9), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt9), + .B1(txr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_5), + .COUT(txr_wt_cnt_cry[0]), + .S0(txr_wt_cnt_cry_0_S0[0]), + .S1(txr_wt_cnt_s[0]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h5003; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1] ( + .A0(txr_wt_cnt9), + .B0(txr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt9), + .B1(txr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[0]), + .COUT(txr_wt_cnt_cry[2]), + .S0(txr_wt_cnt_s[1]), + .S1(txr_wt_cnt_s[2]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3] ( + .A0(txr_wt_cnt9), + .B0(txr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt9), + .B1(txr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[2]), + .COUT(txr_wt_cnt_cry[4]), + .S0(txr_wt_cnt_s[3]), + .S1(txr_wt_cnt_s[4]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5] ( + .A0(txr_wt_cnt9), + .B0(txr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt9), + .B1(txr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[4]), + .COUT(txr_wt_cnt_cry[6]), + .S0(txr_wt_cnt_s[5]), + .S1(txr_wt_cnt_s[6]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7] ( + .A0(txr_wt_cnt9), + .B0(txr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt9), + .B1(txr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[6]), + .COUT(txr_wt_cnt_cry[8]), + .S0(txr_wt_cnt_s[7]), + .S1(txr_wt_cnt_s[8]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9] ( + .A0(txr_wt_cnt9), + .B0(txr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(txr_wt_cnt9), + .B1(txr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[8]), + .COUT(txr_wt_cnt_cry[10]), + .S0(txr_wt_cnt_s[9]), + .S1(txr_wt_cnt_s[10]) +); +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h4000; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:527 + CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11] ( + .A0(txr_wt_cnt9), + .B0(txr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(txr_wt_cnt_cry[10]), + .COUT(txr_wt_cnt_s_0_COUT[11]), + .S0(txr_wt_cnt_s[11]), + .S1(txr_wt_cnt_s_0_S1[11]) +); +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h4005; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0] ( + .A0(VCC), + .B0(rxr_wt_cnt9), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_4), + .COUT(rxr_wt_cnt_cry[0]), + .S0(rxr_wt_cnt_cry_0_S0[0]), + .S1(rxr_wt_cnt_s[0]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[0]), + .COUT(rxr_wt_cnt_cry[2]), + .S0(rxr_wt_cnt_s[1]), + .S1(rxr_wt_cnt_s[2]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[2]), + .COUT(rxr_wt_cnt_cry[4]), + .S0(rxr_wt_cnt_s[3]), + .S1(rxr_wt_cnt_s[4]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[4]), + .COUT(rxr_wt_cnt_cry[6]), + .S0(rxr_wt_cnt_s[5]), + .S1(rxr_wt_cnt_s[6]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[6]), + .COUT(rxr_wt_cnt_cry[8]), + .S0(rxr_wt_cnt_s[7]), + .S1(rxr_wt_cnt_s[8]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(rxr_wt_cnt9), + .B1(rxr_wt_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[8]), + .COUT(rxr_wt_cnt_cry[10]), + .S0(rxr_wt_cnt_s[9]), + .S1(rxr_wt_cnt_s[10]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:909 + CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11] ( + .A0(rxr_wt_cnt9), + .B0(rxr_wt_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rxr_wt_cnt_cry[10]), + .COUT(rxr_wt_cnt_s_0_COUT[11]), + .S0(rxr_wt_cnt_s[11]), + .S1(rxr_wt_cnt_s_0_S1[11]) +); +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO"; +defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO"; + CCU2C \genblk1.plol_cnt_cry_0[0] ( + .A0(VCC), + .B0(plol_cnt_scalar), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_3), + .COUT(plol_cnt_cry[0]), + .S0(plol_cnt_cry_0_S0[0]), + .S1(plol_cnt_s[0]) +); +defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c; +defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[1] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[1]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[2]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[0]), + .COUT(plol_cnt_cry[2]), + .S0(plol_cnt_s[1]), + .S1(plol_cnt_s[2]) +); +defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[3] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[3]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[4]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[2]), + .COUT(plol_cnt_cry[4]), + .S0(plol_cnt_s[3]), + .S1(plol_cnt_s[4]) +); +defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[5] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[5]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[6]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[4]), + .COUT(plol_cnt_cry[6]), + .S0(plol_cnt_s[5]), + .S1(plol_cnt_s[6]) +); +defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[7] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[7]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[8]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[6]), + .COUT(plol_cnt_cry[8]), + .S0(plol_cnt_s[7]), + .S1(plol_cnt_s[8]) +); +defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[9] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[9]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[10]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[8]), + .COUT(plol_cnt_cry[10]), + .S0(plol_cnt_s[9]), + .S1(plol_cnt_s[10]) +); +defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[11] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[11]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[12]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[10]), + .COUT(plol_cnt_cry[12]), + .S0(plol_cnt_s[11]), + .S1(plol_cnt_s[12]) +); +defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[13] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[13]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[14]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[12]), + .COUT(plol_cnt_cry[14]), + .S0(plol_cnt_s[13]), + .S1(plol_cnt_s[14]) +); +defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[15] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[15]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[16]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[14]), + .COUT(plol_cnt_cry[16]), + .S0(plol_cnt_s[15]), + .S1(plol_cnt_s[16]) +); +defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_cry_0[17] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[17]), + .C0(VCC), + .D0(VCC), + .A1(plol_cnt_scalar), + .B1(plol_cnt[18]), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[16]), + .COUT(plol_cnt_cry[18]), + .S0(plol_cnt_s[17]), + .S1(plol_cnt_s[18]) +); +defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO"; +// @16:412 + CCU2C \genblk1.plol_cnt_s_0[19] ( + .A0(plol_cnt_scalar), + .B0(plol_cnt[19]), + .C0(VCC), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(plol_cnt_cry[18]), + .COUT(plol_cnt_s_0_COUT[19]), + .S0(plol_cnt_s[19]), + .S1(plol_cnt_s_0_S1[19]) +); +defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a; +defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO"; +defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlos_db_cnt[0]), + .B1(un1_rlos_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_2), + .COUT(rlos_db_cnt_cry_0), + .S0(rlos_db_cnt_cry_0_0_S0), + .S1(rlos_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0 ( + .A0(un1_rlos_db_cnt_zero[0]), + .B0(rlos_p2), + .C0(rlos_db_cnt[1]), + .D0(VCC), + .A1(un1_rlos_db_cnt_zero[0]), + .B1(rlos_p2), + .C1(rlos_db_cnt[2]), + .D1(VCC), + .CIN(rlos_db_cnt_cry_0), + .COUT(rlos_db_cnt_cry_2), + .S0(rlos_db_cnt_cry_1_0_S0), + .S1(rlos_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:641 + CCU2C \un1_genblk2.rlos_db_cnt_s_3_0 ( + .A0(rlos_db_cnt[3]), + .B0(rlos_p2), + .C0(un1_rlos_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlos_db_cnt_cry_2), + .COUT(rlos_db_cnt_s_3_0_COUT), + .S0(rlos_db_cnt_s_3_0_S0), + .S1(rlos_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO"; + CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0 ( + .A0(VCC), + .B0(VCC), + .C0(VCC), + .D0(VCC), + .A1(rlol_db_cnt[0]), + .B1(un1_rlol_db_cnt_zero[0]), + .C1(VCC), + .D1(VCC), + .CIN(N_1), + .COUT(rlol_db_cnt_cry_0), + .S0(rlol_db_cnt_cry_0_0_S0), + .S1(rlol_db_cnt_cry_0_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0 ( + .A0(un1_rlol_db_cnt_zero[0]), + .B0(rlol_p2), + .C0(rlol_db_cnt[1]), + .D0(VCC), + .A1(un1_rlol_db_cnt_zero[0]), + .B1(rlol_p2), + .C1(rlol_db_cnt[2]), + .D1(VCC), + .CIN(rlol_db_cnt_cry_0), + .COUT(rlol_db_cnt_cry_2), + .S0(rlol_db_cnt_cry_1_0_S0), + .S1(rlol_db_cnt_cry_1_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO"; +// @16:625 + CCU2C \un1_genblk2.rlol_db_cnt_s_3_0 ( + .A0(rlol_db_cnt[3]), + .B0(rlol_p2), + .C0(un1_rlol_db_cnt_zero[0]), + .D0(VCC), + .A1(VCC), + .B1(VCC), + .C1(VCC), + .D1(VCC), + .CIN(rlol_db_cnt_cry_2), + .COUT(rlol_db_cnt_s_3_0_COUT), + .S0(rlol_db_cnt_s_3_0_S0), + .S1(rlol_db_cnt_s_3_0_S1) +); +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO"; +defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO"; +//@16:865 +//@16:492 + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + VLO GND_cZ ( + .Z(GND) +); +endmodule /* serdes_sync_1rsl_core_Z2_layer1 */ + +module serdes_sync_1 ( + hdoutp, + hdoutn, + hdinp, + hdinn, + rxrefclk, + rx_pclk, + tx_pclk, + txdata, + tx_k, + tx_force_disp, + tx_disp_sel, + rxdata, + rx_k, + rx_disp_err, + rx_cv_err, + tx_idle_c, + signal_detect_c, + rx_los_low_s, + lsm_status_s, + rx_cdr_lol_s, + sli_rst, + tx_pwrup_c, + rx_pwrup_c, + sci_wrdata, + sci_addr, + sci_rddata, + sci_en_dual, + sci_sel_dual, + sci_en, + sci_sel, + sci_rd, + sci_wrn, + sci_int, + cyawstn, + serdes_pdb, + pll_refclki, + rsl_disable, + rsl_rst, + serdes_rst_dual_c, + rst_dual_c, + tx_serdes_rst_c, + tx_pcs_rst_c, + pll_lol, + rsl_tx_rdy, + rx_serdes_rst_c, + rx_pcs_rst_c, + rsl_rx_rdy +) +; +output hdoutp ; +output hdoutn ; +input hdinp ; +input hdinn ; +input rxrefclk ; +output rx_pclk ; +output tx_pclk ; +input [7:0] txdata ; +input [0:0] tx_k ; +input [0:0] tx_force_disp ; +input [0:0] tx_disp_sel ; +output [7:0] rxdata ; +output [0:0] rx_k ; +output [0:0] rx_disp_err ; +output [0:0] rx_cv_err ; +input tx_idle_c ; +input signal_detect_c ; +output rx_los_low_s ; +output lsm_status_s ; +output rx_cdr_lol_s ; +input sli_rst ; +input tx_pwrup_c ; +input rx_pwrup_c ; +input [7:0] sci_wrdata ; +input [5:0] sci_addr ; +output [7:0] sci_rddata ; +input sci_en_dual ; +input sci_sel_dual ; +input sci_en ; +input sci_sel ; +input sci_rd ; +input sci_wrn ; +output sci_int ; +input cyawstn ; +input serdes_pdb ; +input pll_refclki ; +input rsl_disable ; +input rsl_rst ; +input serdes_rst_dual_c ; +input rst_dual_c ; +input tx_serdes_rst_c ; +input tx_pcs_rst_c ; +output pll_lol ; +output rsl_tx_rdy ; +input rx_serdes_rst_c ; +input rx_pcs_rst_c ; +output rsl_rx_rdy ; +wire hdoutp ; +wire hdoutn ; +wire hdinp ; +wire hdinn ; +wire rxrefclk ; +wire rx_pclk ; +wire tx_pclk ; +wire tx_idle_c ; +wire signal_detect_c ; +wire rx_los_low_s ; +wire lsm_status_s ; +wire rx_cdr_lol_s ; +wire sli_rst ; +wire tx_pwrup_c ; +wire rx_pwrup_c ; +wire sci_en_dual ; +wire sci_sel_dual ; +wire sci_en ; +wire sci_sel ; +wire sci_rd ; +wire sci_wrn ; +wire sci_int ; +wire cyawstn ; +wire serdes_pdb ; +wire pll_refclki ; +wire rsl_disable ; +wire rsl_rst ; +wire serdes_rst_dual_c ; +wire rst_dual_c ; +wire tx_serdes_rst_c ; +wire tx_pcs_rst_c ; +wire pll_lol ; +wire rsl_tx_rdy ; +wire rx_serdes_rst_c ; +wire rx_pcs_rst_c ; +wire rsl_rx_rdy ; +wire rsl_tx_pcs_rst_c ; +wire rsl_rx_pcs_rst_c ; +wire rsl_rx_serdes_rst_c ; +wire rsl_serdes_rst_dual_c ; +wire rsl_tx_serdes_rst_c ; +wire n50_1 ; +wire n51_1 ; +wire n1_1 ; +wire n2_1 ; +wire n3_1 ; +wire n4_1 ; +wire n5_1 ; +wire n52_1 ; +wire n6_1 ; +wire n53_1 ; +wire n7_1 ; +wire n54_1 ; +wire n8_1 ; +wire n55_1 ; +wire n56_1 ; +wire n57_1 ; +wire n58_1 ; +wire n59_1 ; +wire n60_1 ; +wire n61_1 ; +wire n62_1 ; +wire n63_1 ; +wire n64_1 ; +wire n65_1 ; +wire n66_1 ; +wire n67_1 ; +wire n68_1 ; +wire n9_1 ; +wire n69_1 ; +wire n70_1 ; +wire n71_1 ; +wire n72_1 ; +wire n73_1 ; +wire n74_1 ; +wire n75_1 ; +wire n76_1 ; +wire n77_1 ; +wire n78_1 ; +wire n79_1 ; +wire n80_1 ; +wire n81_1 ; +wire n82_1 ; +wire n83_1 ; +wire n84_1 ; +wire n85_1 ; +wire n86_1 ; +wire n87_1 ; +wire n88_1 ; +wire n89_1 ; +wire n90_1 ; +wire n91_1 ; +wire n10_1 ; +wire n92_1 ; +wire n11_1 ; +wire n93_1 ; +wire n12_1 ; +wire n94_1 ; +wire n95_1 ; +wire n96_1 ; +wire n13_1 ; +wire n97_1 ; +wire n14_1 ; +wire n98_1 ; +wire n15_1 ; +wire n99_1 ; +wire n16_1 ; +wire n100_1 ; +wire n101_1 ; +wire n17_1 ; +wire n102_1 ; +wire n18_1 ; +wire n103_1 ; +wire n104_1 ; +wire n115_1 ; +wire n19_1 ; +wire n20_1 ; +wire n21_1 ; +wire n22_1 ; +wire n23_1 ; +wire n24_1 ; +wire n25_1 ; +wire n26_1 ; +wire n27_1 ; +wire n28_1 ; +wire n29_1 ; +wire n30_1 ; +wire n31_1 ; +wire n32_1 ; +wire n33_1 ; +wire n34_1 ; +wire n35_1 ; +wire n36_1 ; +wire n37_1 ; +wire n38_1 ; +wire n39_1 ; +wire n40_1 ; +wire n41_1 ; +wire n42_1 ; +wire n43_1 ; +wire n44_1 ; +wire n45_1 ; +wire n46_1 ; +wire n49_1 ; +wire GND ; +wire VCC ; + VLO GND_0 ( + .Z(GND) +); + VHI VCC_0 ( + .Z(VCC) +); +// @16:865 + PUR PUR_INST ( + .PUR(VCC) +); +// @16:865 + GSR GSR_INST ( + .GSR(VCC) +); +// @8:160 +(* CHAN="CH0" *) DCUA DCU0_inst ( + .CH0_HDINP(hdinp), + .CH1_HDINP(GND), + .CH0_HDINN(hdinn), + .CH1_HDINN(GND), + .D_TXBIT_CLKP_FROM_ND(GND), + .D_TXBIT_CLKN_FROM_ND(GND), + .D_SYNC_ND(GND), + .D_TXPLL_LOL_FROM_ND(GND), + .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(GND), + .CH0_FF_RXI_CLK(rx_pclk), + .CH1_FF_RXI_CLK(VCC), + .CH0_FF_TXI_CLK(tx_pclk), + .CH1_FF_TXI_CLK(VCC), + .CH0_FF_EBRD_CLK(VCC), + .CH1_FF_EBRD_CLK(VCC), + .CH0_FF_TX_D_0(txdata[0]), + .CH1_FF_TX_D_0(GND), + .CH0_FF_TX_D_1(txdata[1]), + .CH1_FF_TX_D_1(GND), + .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(GND), + .CH0_FF_TX_D_3(txdata[3]), + .CH1_FF_TX_D_3(GND), + .CH0_FF_TX_D_4(txdata[4]), + .CH1_FF_TX_D_4(GND), + .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(GND), + .CH0_FF_TX_D_6(txdata[6]), + .CH1_FF_TX_D_6(GND), + .CH0_FF_TX_D_7(txdata[7]), + .CH1_FF_TX_D_7(GND), + .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(GND), + .CH0_FF_TX_D_9(tx_force_disp[0]), + .CH1_FF_TX_D_9(GND), + .CH0_FF_TX_D_10(tx_disp_sel[0]), + .CH1_FF_TX_D_10(GND), + .CH0_FF_TX_D_11(GND), + .CH1_FF_TX_D_11(GND), + .CH0_FF_TX_D_12(GND), + .CH1_FF_TX_D_12(GND), + .CH0_FF_TX_D_13(GND), + .CH1_FF_TX_D_13(GND), + .CH0_FF_TX_D_14(GND), + .CH1_FF_TX_D_14(GND), + .CH0_FF_TX_D_15(GND), + .CH1_FF_TX_D_15(GND), + .CH0_FF_TX_D_16(GND), + .CH1_FF_TX_D_16(GND), + .CH0_FF_TX_D_17(GND), + .CH1_FF_TX_D_17(GND), + .CH0_FF_TX_D_18(GND), + .CH1_FF_TX_D_18(GND), + .CH0_FF_TX_D_19(GND), + .CH1_FF_TX_D_19(GND), + .CH0_FF_TX_D_20(GND), + .CH1_FF_TX_D_20(GND), + .CH0_FF_TX_D_21(GND), + .CH1_FF_TX_D_21(GND), + .CH0_FF_TX_D_22(GND), + .CH1_FF_TX_D_22(GND), + .CH0_FF_TX_D_23(GND), + .CH1_FF_TX_D_23(GND), + .CH0_FFC_EI_EN(tx_idle_c), + .CH1_FFC_EI_EN(GND), + .CH0_FFC_PCIE_DET_EN(GND), + .CH1_FFC_PCIE_DET_EN(GND), + .CH0_FFC_PCIE_CT(GND), + .CH1_FFC_PCIE_CT(GND), + .CH0_FFC_SB_INV_RX(GND), + .CH1_FFC_SB_INV_RX(GND), + .CH0_FFC_ENABLE_CGALIGN(GND), + .CH1_FFC_ENABLE_CGALIGN(GND), + .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(GND), + .CH0_FFC_FB_LOOPBACK(GND), + .CH1_FFC_FB_LOOPBACK(GND), + .CH0_FFC_SB_PFIFO_LP(GND), + .CH1_FFC_SB_PFIFO_LP(GND), + .CH0_FFC_PFIFO_CLR(GND), + .CH1_FFC_PFIFO_CLR(GND), + .CH0_FFC_RATE_MODE_RX(GND), + .CH1_FFC_RATE_MODE_RX(GND), + .CH0_FFC_RATE_MODE_TX(GND), + .CH1_FFC_RATE_MODE_TX(GND), + .CH0_FFC_DIV11_MODE_RX(GND), + .CH1_FFC_DIV11_MODE_RX(GND), + .CH0_FFC_RX_GEAR_MODE(GND), + .CH1_FFC_RX_GEAR_MODE(GND), + .CH0_FFC_TX_GEAR_MODE(GND), + .CH1_FFC_TX_GEAR_MODE(GND), + .CH0_FFC_DIV11_MODE_TX(GND), + .CH1_FFC_DIV11_MODE_TX(GND), + .CH0_FFC_LDR_CORE2TX_EN(GND), + .CH1_FFC_LDR_CORE2TX_EN(GND), + .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), + .CH1_FFC_LANE_TX_RST(GND), + .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), + .CH1_FFC_LANE_RX_RST(GND), + .CH0_FFC_RRST(rsl_rx_serdes_rst_c), + .CH1_FFC_RRST(GND), + .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(GND), + .CH0_FFC_RXPWDNB(rx_pwrup_c), + .CH1_FFC_RXPWDNB(GND), + .CH0_LDR_CORE2TX(GND), + .CH1_LDR_CORE2TX(GND), + .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), + .D_SCIWDATA2(sci_wrdata[2]), + .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), + .D_SCIWDATA5(sci_wrdata[5]), + .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), + .D_SCIADDR0(sci_addr[0]), + .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), + .D_SCIADDR3(sci_addr[3]), + .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), + .D_SCIENAUX(sci_en_dual), + .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), + .CH1_SCIEN(GND), + .CH0_SCISEL(sci_sel), + .CH1_SCISEL(GND), + .D_SCIRD(sci_rd), + .D_SCIWSTN(sci_wrn), + .D_CYAWSTN(cyawstn), + .D_FFC_SYNC_TOGGLE(GND), + .D_FFC_DUAL_RST(rst_dual_c), + .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), + .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(GND), + .CH1_FFC_CDR_EN_BITSLIP(GND), + .D_SCAN_ENABLE(GND), + .D_SCAN_IN_0(GND), + .D_SCAN_IN_1(GND), + .D_SCAN_IN_2(GND), + .D_SCAN_IN_3(GND), + .D_SCAN_IN_4(GND), + .D_SCAN_IN_5(GND), + .D_SCAN_IN_6(GND), + .D_SCAN_IN_7(GND), + .D_SCAN_MODE(GND), + .D_SCAN_RESET(GND), + .D_CIN0(GND), + .D_CIN1(GND), + .D_CIN2(GND), + .D_CIN3(GND), + .D_CIN4(GND), + .D_CIN5(GND), + .D_CIN6(GND), + .D_CIN7(GND), + .D_CIN8(GND), + .D_CIN9(GND), + .D_CIN10(GND), + .D_CIN11(GND), + .CH0_HDOUTP(hdoutp), + .CH1_HDOUTP(n50_1), + .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n51_1), + .D_TXBIT_CLKP_TO_ND(n1_1), + .D_TXBIT_CLKN_TO_ND(n2_1), + .D_SYNC_PULSE2ND(n3_1), + .D_TXPLL_LOL_TO_ND(n4_1), + .CH0_FF_RX_F_CLK(n5_1), + .CH1_FF_RX_F_CLK(n52_1), + .CH0_FF_RX_H_CLK(n6_1), + .CH1_FF_RX_H_CLK(n53_1), + .CH0_FF_TX_F_CLK(n7_1), + .CH1_FF_TX_F_CLK(n54_1), + .CH0_FF_TX_H_CLK(n8_1), + .CH1_FF_TX_H_CLK(n55_1), + .CH0_FF_RX_PCLK(rx_pclk), + .CH1_FF_RX_PCLK(n56_1), + .CH0_FF_TX_PCLK(tx_pclk), + .CH1_FF_TX_PCLK(n57_1), + .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n58_1), + .CH0_FF_RX_D_1(rxdata[1]), + .CH1_FF_RX_D_1(n59_1), + .CH0_FF_RX_D_2(rxdata[2]), + .CH1_FF_RX_D_2(n60_1), + .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n61_1), + .CH0_FF_RX_D_4(rxdata[4]), + .CH1_FF_RX_D_4(n62_1), + .CH0_FF_RX_D_5(rxdata[5]), + .CH1_FF_RX_D_5(n63_1), + .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n64_1), + .CH0_FF_RX_D_7(rxdata[7]), + .CH1_FF_RX_D_7(n65_1), + .CH0_FF_RX_D_8(rx_k[0]), + .CH1_FF_RX_D_8(n66_1), + .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n67_1), + .CH0_FF_RX_D_10(rx_cv_err[0]), + .CH1_FF_RX_D_10(n68_1), + .CH0_FF_RX_D_11(n9_1), + .CH1_FF_RX_D_11(n69_1), + .CH0_FF_RX_D_12(n70_1), + .CH1_FF_RX_D_12(n71_1), + .CH0_FF_RX_D_13(n72_1), + .CH1_FF_RX_D_13(n73_1), + .CH0_FF_RX_D_14(n74_1), + .CH1_FF_RX_D_14(n75_1), + .CH0_FF_RX_D_15(n76_1), + .CH1_FF_RX_D_15(n77_1), + .CH0_FF_RX_D_16(n78_1), + .CH1_FF_RX_D_16(n79_1), + .CH0_FF_RX_D_17(n80_1), + .CH1_FF_RX_D_17(n81_1), + .CH0_FF_RX_D_18(n82_1), + .CH1_FF_RX_D_18(n83_1), + .CH0_FF_RX_D_19(n84_1), + .CH1_FF_RX_D_19(n85_1), + .CH0_FF_RX_D_20(n86_1), + .CH1_FF_RX_D_20(n87_1), + .CH0_FF_RX_D_21(n88_1), + .CH1_FF_RX_D_21(n89_1), + .CH0_FF_RX_D_22(n90_1), + .CH1_FF_RX_D_22(n91_1), + .CH0_FF_RX_D_23(n10_1), + .CH1_FF_RX_D_23(n92_1), + .CH0_FFS_PCIE_DONE(n11_1), + .CH1_FFS_PCIE_DONE(n93_1), + .CH0_FFS_PCIE_CON(n12_1), + .CH1_FFS_PCIE_CON(n94_1), + .CH0_FFS_RLOS(rx_los_low_s), + .CH1_FFS_RLOS(n95_1), + .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n96_1), + .CH0_FFS_CC_UNDERRUN(n13_1), + .CH1_FFS_CC_UNDERRUN(n97_1), + .CH0_FFS_CC_OVERRUN(n14_1), + .CH1_FFS_CC_OVERRUN(n98_1), + .CH0_FFS_RXFBFIFO_ERROR(n15_1), + .CH1_FFS_RXFBFIFO_ERROR(n99_1), + .CH0_FFS_TXFBFIFO_ERROR(n16_1), + .CH1_FFS_TXFBFIFO_ERROR(n100_1), + .CH0_FFS_RLOL(rx_cdr_lol_s), + .CH1_FFS_RLOL(n101_1), + .CH0_FFS_SKP_ADDED(n17_1), + .CH1_FFS_SKP_ADDED(n102_1), + .CH0_FFS_SKP_DELETED(n18_1), + .CH1_FFS_SKP_DELETED(n103_1), + .CH0_LDR_RX2CORE(n104_1), + .CH1_LDR_RX2CORE(n115_1), + .D_SCIRDATA0(sci_rddata[0]), + .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), + .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), + .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n19_1), + .D_SCAN_OUT_1(n20_1), + .D_SCAN_OUT_2(n21_1), + .D_SCAN_OUT_3(n22_1), + .D_SCAN_OUT_4(n23_1), + .D_SCAN_OUT_5(n24_1), + .D_SCAN_OUT_6(n25_1), + .D_SCAN_OUT_7(n26_1), + .D_COUT0(n27_1), + .D_COUT1(n28_1), + .D_COUT2(n29_1), + .D_COUT3(n30_1), + .D_COUT4(n31_1), + .D_COUT5(n32_1), + .D_COUT6(n33_1), + .D_COUT7(n34_1), + .D_COUT8(n35_1), + .D_COUT9(n36_1), + .D_COUT10(n37_1), + .D_COUT11(n38_1), + .D_COUT12(n39_1), + .D_COUT13(n40_1), + .D_COUT14(n41_1), + .D_COUT15(n42_1), + .D_COUT16(n43_1), + .D_COUT17(n44_1), + .D_COUT18(n45_1), + .D_COUT19(n46_1), + .D_REFCLKI(pll_refclki), + .D_FFS_PLOL(n49_1) +); +defparam DCU0_inst.D_MACROPDB = "0b1"; +defparam DCU0_inst.D_IB_PWDNB = "0b1"; +defparam DCU0_inst.D_XGE_MODE = "0b0"; +defparam DCU0_inst.D_LOW_MARK = "0d4"; +defparam DCU0_inst.D_HIGH_MARK = "0d12"; +defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; +defparam DCU0_inst.D_CDR_LOL_SET = "0b11"; +defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; +defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; +defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; +defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; +defparam DCU0_inst.CH0_UC_MODE = "0b1"; +defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; +defparam DCU0_inst.CH0_RIO_MODE = "0b0"; +defparam DCU0_inst.CH0_WA_MODE = "0b0"; +defparam DCU0_inst.CH0_INVERT_RX = "0b0"; +defparam DCU0_inst.CH0_INVERT_TX = "0b0"; +defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; +defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0"; +defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; +defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; +defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; +defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; +defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; +defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; +defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; +defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; +defparam DCU0_inst.CH0_CTC_BYPASS = "0b1"; +defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; +defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; +defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b0"; +defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b1"; +defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; +defparam DCU0_inst.CH0_CC_MATCH_1 = "0x1BC"; +defparam DCU0_inst.CH0_CC_MATCH_2 = "0x11C"; +defparam DCU0_inst.CH0_CC_MATCH_3 = "0x11C"; +defparam DCU0_inst.CH0_CC_MATCH_4 = "0x11C"; +defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x0ff"; +defparam DCU0_inst.CH0_UDF_COMMA_A = "0x083"; +defparam DCU0_inst.CH0_UDF_COMMA_B = "0x07C"; +defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010"; +defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; +defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00"; +defparam DCU0_inst.CH0_REQ_EN = "0b1"; +defparam DCU0_inst.CH0_RTERM_RX = "0d22"; +defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; +defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; +defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; +defparam DCU0_inst.CH0_TPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0"; +defparam DCU0_inst.CH0_RTERM_TX = "0d19"; +defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; +defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00"; +defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b000"; +defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; +defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11"; +defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b01"; +defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; +defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; +defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_RPWDNB = "0b1"; +defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0"; +defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; +defparam DCU0_inst.CH0_RX_LOS_LVL = "0b100"; +defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; +defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; +defparam DCU0_inst.CH0_RX_LOS_EN = "0b1"; +defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; +defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b1"; +defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; +defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; +defparam DCU0_inst.CH0_RX_RATE_SEL = "0d10"; +defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; +defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; +defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; +defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; +defparam DCU0_inst.CH0_RXIN_CM = "0b11"; +defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; +defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; +defparam DCU0_inst.D_TX_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25"; +defparam DCU0_inst.CH0_TXAMPLITUDE = "0d800"; +defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; +defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; +defparam DCU0_inst.CH0_PROTOCOL = "G8B10B"; +defparam DCU0_inst.D_ISETLOS = "0d0"; +defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; +defparam DCU0_inst.D_SETICONST_AUX = "0b00"; +defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; +defparam DCU0_inst.D_SETICONST_CH = "0b00"; +defparam DCU0_inst.D_REQ_ISET = "0b000"; +defparam DCU0_inst.D_PD_ISET = "0b00"; +defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; +defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; +defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; +defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; +defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; +defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; +defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; +defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; +defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; +defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; +defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; +defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; +defparam DCU0_inst.CH0_DCOSTEP = "0b00"; +defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; +defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; +defparam DCU0_inst.CH0_DCOITUNE = "0b00"; +defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; +defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; +defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; +defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; +defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; +defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; +defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; +defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; +defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; +defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; +defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; +defparam DCU0_inst.D_SETPLLRC = "0d1"; +defparam DCU0_inst.D_REFCK_MODE = "0b001"; +defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; +defparam DCU0_inst.D_PLL_LOL_SET = "0b01"; +defparam DCU0_inst.D_RG_EN = "0b0"; +defparam DCU0_inst.D_RG_SET = "0b00"; +defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; +defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; +defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; +defparam DCU0_inst.D_CMUSETZGM = "0b000"; +defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; +defparam DCU0_inst.D_CMUSETP1GM = "0b000"; +defparam DCU0_inst.D_CMUSETI4CPZ = "0d0"; +defparam DCU0_inst.D_CMUSETI4CPP = "0d0"; +defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; +defparam DCU0_inst.D_CMUSETICP4P = "0b11"; +defparam DCU0_inst.D_CMUSETBIASI = "0b00"; +// @8:425 + serdes_sync_1sll_core_Z1_layer1 sll_inst ( + .tx_pclk(tx_pclk), + .sli_rst(sli_rst), + .pll_refclki(pll_refclki), + .pll_lock_i(pll_lol) +); +// @8:395 + serdes_sync_1rsl_core_Z2_layer1 rsl_inst ( + .rx_pcs_rst_c(rx_pcs_rst_c), + .serdes_rst_dual_c(serdes_rst_dual_c), + .tx_serdes_rst_c(tx_serdes_rst_c), + .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c), + .rst_dual_c(rst_dual_c), + .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c), + .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rsl_tx_rdy(rsl_tx_rdy), + .pll_lock_i(pll_lol), + .pll_refclki(pll_refclki), + .rsl_rx_rdy(rsl_rx_rdy), + .rx_cdr_lol_s(rx_cdr_lol_s), + .rx_los_low_s(rx_los_low_s), + .rsl_rst(rsl_rst), + .rxrefclk(rxrefclk), + .rx_serdes_rst_c(rx_serdes_rst_c), + .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c), + .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c), + .rsl_disable(rsl_disable), + .tx_pcs_rst_c(tx_pcs_rst_c) +); +endmodule /* serdes_sync_1 */ + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_cck.rpt.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..029fa7a6cf9014af50ee9d4aa843536a1f7b5c42 GIT binary patch literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP literal 0 HcmV?d00001 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify.lpf new file mode 100644 index 0000000..9cbac38 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify.lpf @@ -0,0 +1,29 @@ +# +# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. +# + +# Period Constraints +#FREQUENCY PORT "pll_refclki" 100.0 MHz; +#FREQUENCY PORT "rxrefclk" 100.0 MHz; +#FREQUENCY NET "tx_pclk" 100.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk"; +#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk"; +#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp2.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp4.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp8.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer0.tlg.rptmap new file mode 100644 index 0000000..3910cac --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer0.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer1.tlg.rptmap new file mode 100644 index 0000000..af92e0b --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer1.tlg.rptmap @@ -0,0 +1 @@ +./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/linker.rpt.rptmap new file mode 100644 index 0000000..708d195 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/linker.rpt.rptmap @@ -0,0 +1 @@ +./synwork/serdes_sync_1_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/metrics.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/metrics.db new file mode 100644 index 0000000000000000000000000000000000000000..331403430b3ebe0c4be37c68ac99a74e31551523 GIT binary patch literal 20480 zcmeI3O>fgk7{_gBi49DKibGXZ5rYDRA`()kX^XZJbfGFQEeNQDIH1UJCh1Un9LAGK zTvlpN@I|=paX-RJE6%%LV7~+x#AC;Kt3mf7qeeE;2bel@3Gh{o0-{s-aIHIHg_97U=G^C=Ofiq<90_zj>B@YHqU-B=^r$rYuPU+ z@Lv!uBLO6U1dsp{Kmter2_OL^fCP{L68H{*HOnIT8IpT!>rlIXtqDu@XmK@Nw5y%C zlgUm{=Zb|*_Tc^&6SCdWED5Y;EK;B(_e+``gpCg5FMTUL9bZ3Vks_pR+t4AJf;VbE zn8{M*hOs$qkp<9rJ=91nIp3Q5koAF5y#7B!&l&U|`a6A3>vS0!Sdah`Kmter2_OL^ zfCP{L5vj#G&^9F}NA&34PJ1#Y{|)s1r& z$t9tRyM7w$EIP{*Vy~P{WakF5i=}c>QrWiRAbQnK6d|gwI5F%RY*>KD+=y6pX|;U2 znu_(8{{`5Z0D}-Wlv{RImIgP|4~*CU7I|yXKj{Zr&Hk1BEt?~spaTmMKmter2_OL^ zfCP{L5k;X};7{lda%x#Sep8*_H|>@S-fF$?0<^)xWVvLV#pA4@ zM3+lef5(#4TP-fRibYs2NGr~xN5mqxV1k!p`pMAb369Vb=fUhnFgs&=@z)+k%sS3w zwTX6RD2u&mlG-HO&tdr=+is1`l-RCJ{PX>Q<{E4hT%~00sV%%#O>ylC2~R_BcVPG+ zJiNEbd{=wBJYw+JFxWf@yS%Xi+Xs2b-b}NT&Lfl4#CZL0(!UM(!GZ*k01`j~NB{{S w0VIF~kN^@u0!RP}oG1d*O + + + + + /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr + Synopsys HDL Compiler + + + Completed + + + + 15 + /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_notes.txt + + + 77 + /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt + + + 0 + /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_errors.txt + + + - + + + 00h:00m:02s + + + - + + + 1557476612 + + + \ No newline at end of file diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt new file mode 100644 index 0000000..6622b46 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt @@ -0,0 +1,78 @@ +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml new file mode 100644 index 0000000..8fa1b06 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_resourceusage.rpt +Resource Usage + + +220 + + +0 + + +0 + + +0 + + +150 + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt new file mode 100644 index 0000000..2d9eda0 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt @@ -0,0 +1,23 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..2137e39 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +3 / 0 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..dc0003e --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +23 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt + + + +4 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt + + + +0h:00m:03s + + +0h:00m:03s + + +152MB + + +1557476618 + + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..ae318a5 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml @@ -0,0 +1,41 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +serdes_sync_1|pll_refclki +100.0 MHz +168.9 MHz +4.079 + + +serdes_sync_1|rxrefclk +100.0 MHz +170.5 MHz +4.136 + + +serdes_sync_1|tx_pclk_inferred_clock +100.0 MHz +237.5 MHz +5.789 + + +System +100.0 MHz +840.7 MHz +8.810 + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt new file mode 100644 index 0000000..08dea66 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt @@ -0,0 +1,4 @@ +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt new file mode 100644 index 0000000..ff38fdb --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt @@ -0,0 +1,8 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml new file mode 100644 index 0000000..e63e0c3 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +8 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt + + + +3 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt + + + +0 + +/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +145MB + + +1557476614 + + + diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt new file mode 100644 index 0000000..b332633 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt @@ -0,0 +1,3 @@ +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr new file mode 100644 index 0000000..471f88d --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr @@ -0,0 +1,357 @@ +Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 10:23:30 2019 + +###########################################################] +Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + + +Process completed successfully. +# Fri May 10 10:23:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps +@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling +File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling +VHDL syntax check successful! +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1. +Post processing for work.serdes_sync_1.v1 + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) + + +Process completed successfully. +# Fri May 10 10:23:31 2019 + +###########################################################] +Running on host :lxhadeb07 +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) +@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) +@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) +Verilog syntax check successful! +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work. + + PPROTOCOL=48'b010001110011100001000010001100010011000001000010 + PLOL_SETTING=32'b00000000000000000000000000000001 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = serdes_sync_1sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=48'b010001110011100001000010001100010011000001000010 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = serdes_sync_1rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. +@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. +Extracted state machine for register sll_state +State machine has 3 reachable states with original encodings of: + 00 + 01 + 11 + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) + + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 +@N|Running in 64-bit mode +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling +File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling + +======================================================================================= +For a summary of linker messages for components that did not bind, please see log file: +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog +======================================================================================= + + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri May 10 10:23:32 2019 + +###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..b41afd23ba561957247397e61c5ae2f6545ea0dd GIT binary patch literal 32768 zcmeHQOLN=S6$U9$)SI@O)JapPH>%qtu0rBLP$Uw!k!4v?E!Pjp?MyWp3`9Z_DiA;b zP^4VSF4@WSJ(+aTPP6T%UGx|94|LO2yYDiaZqi3IZKg9l_ku4trfiu2D73(cxFiLV z_`dtV`OdxPVEy)*V#{b-H_MWZIO+@)i&1YPL{U@%9^>$6Z!vf>+I|5ge*L&DLA~~` zAI`v0vDA+#_=~oPfrx>Kfrx>Kfrx>Kfrx>Kfrx>Kfrx>Kf&X&`>{#;rg$uF9>$bF| z%4ONIq#fC6m+_@L%ZnS!Xk+op+A?at`-)OR`;uAQmCSjhD%xK6RqK%M8+(e@bFcxQ zR5bflEb9-SsZUZLr#?#kHTB`-`xEbt|19~Fu^%OVF#7Ju_v7D-9a8tat)M1# zZv1@Xu<_0d@ufAE&d+6b^|G9iN~R)dnH|N>*ya{*6*IP6HdM)$Glr>uM=rwqvSo|b zwvn-9vm{%hb)XeR+VzTYzY;Bd+g9}*rI_BI6PN|AAka?1*B4b4nX&{N0_{k$EM-S4 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zj*O^~=ub3jVzFd`2S63AO^z%F0Ga5dgh``Ck}D9Ayn^@+3P^%fg59rzHz28?wu2MH z;Itl{AA&3(a#ub!ledP(1ThX+8jOP{U_#X`V4~_L6E}y(1dmNzmgXPBM1`~oqiA7a zBNlyY6O-S-Of(Zi=p9*yiLAgg$Mp_}iB?7xf5}MR7+SL+z9N7oIq)iq^%rsivh5-;%BJrb< z1X(!qtgMx=BURp&_7xqn*FxIY{oawX3Jz85MI{+-!Ix^yV{fXYwFc5{Q!kTo)z%H9 z%KNg~GooI+J|vp5Iq(Pwc>j2sn6&M<8;3{J*M~(D3vMFtd9hDO({NkU>?)z@Ebeqn zAwX9(Ca6u*O(%h{lbfxTUl{j0CoM5|4Vkq^Em5o)F^8-(-Uz zWMxQ%^bX6%6Vfv%`%g$izlI5E1fRo^&w+6-;C*)hemH}p(`A4VY|t8`{Sux=Tf{)bK*T`AK*T`AK*T`AK*T_p7-%eh6EbQa zei!n2!+oWg;AWPXJPjeEko_A9zP@1|kj&pYl54gp!D>=)q(J`vGTdrP(a0^gJNE)W zIQu*KcRSsC^)68v!K*9x&9VC31)*~{tWJ;xvjDDMFZ9*@4T7BH=L%F;o)Gz`?gN(d zhJYrwjtOYu1;J}3-Q>!=#IJQ5 new code + 00 -> 00 + 01 -> 01 + 11 -> 10 +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 5.35ns 151 / 220 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 90 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount_diff[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri May 10 10:23:38 2019 +# + + +Top view: serdes_sync_1 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.079 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------------- +serdes_sync_1|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +serdes_sync_1|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 +serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +=========================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System serdes_sync_1|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki System | 10.000 8.307 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +serdes_sync_1|pll_refclki serdes_sync_1|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk System | 10.000 8.193 | No paths - | No paths - | No paths - +serdes_sync_1|rxrefclk serdes_sync_1|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +=================================================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: serdes_sync_1|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[6] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[7] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[2] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[3] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 +======================================================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + The end point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[1] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[9] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[11] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[12] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[12] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[13] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +rsl_inst.genblk2\.rlol1_cnt[1] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.rlols0_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +rsl_inst.genblk2\.rlols0_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 +rsl_inst.genblk2\.rlols0_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 +rsl_inst.genblk2\.rlol1_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 +rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 +rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 +=========================================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.809 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.136 + + Number of logic level(s): 14 + Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q + Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D + The start point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - +rlol1_cnt[14] Net - - - - 2 +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - +rlol1_cnt_tc_1_10 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - +rlol1_cnt_tc_1_14 Net - - - - 1 +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - +rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - +rlol1_cnt_tc_1 Net - - - - 6 +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - +rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - +rlol1_cnt Net - - - - 20 +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - +rlol1_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - +rlol1_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - +rlol1_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - +rlol1_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - +rlol1_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - +rlol1_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - +rlol1_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - +rlol1_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - +rlol1_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - +rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - +rlol1_cnt_s[18] Net - - - - 1 +rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - +======================================================================================================== + + + + +==================================== +Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +=========================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] serdes_sync_1|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +============================================================================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +DCU0_inst System DCUA CH0_FF_RX_PCLK rx_pclk 0.000 10.000 +=========================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D un2_rdo_serdes_rst_dual_c_1 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +DCU0_inst System DCUA CH0_FF_RXI_CLK rx_pclk 10.000 10.000 +========================================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 B In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_2_0 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +================================================================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 220 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 96 +GSR: 1 +INV: 3 +ORCALUT4: 150 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Fri May 10 10:23:38 2019 + +###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..f91149b0137889f30b1864304ece9560b909c129 GIT binary patch literal 16384 zcmeHNPjA~c6t|tUNt32&yQNuI1mJQ?fJTv=*m2y;(ljZC^>31`YtuoXCCcV3lNw3e zaodZ1>IMuOu*GHFkl!k4E)a-Q0bw`si}1Pn!=@!)QFV0Ol0qzS>0G$*;+$e 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc +@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt +Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB) + +@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. +@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist serdes_sync_1 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------------------------------------------- +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - serdes_sync_1|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 92 + +0 - serdes_sync_1|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 + +0 - serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 +========================================================================================================================= + +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB) + +Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 11 -> 10 + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri May 10 10:23:34 2019 + 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diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg new file mode 100644 index 0000000..a777b88 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg @@ -0,0 +1,28 @@ +@P: Worst Slack : 4.079 +@P: serdes_sync_1|pll_refclki - Estimated Frequency : 168.9 MHz +@P: serdes_sync_1|pll_refclki - Requested Frequency : 100.0 MHz +@P: serdes_sync_1|pll_refclki - Estimated Period : 5.921 +@P: serdes_sync_1|pll_refclki - Requested Period : 10.000 +@P: serdes_sync_1|pll_refclki - Slack : 4.079 +@P: serdes_sync_1|rxrefclk - Estimated Frequency : 170.5 MHz +@P: serdes_sync_1|rxrefclk - Requested Frequency : 100.0 MHz +@P: serdes_sync_1|rxrefclk - Estimated Period : 5.864 +@P: serdes_sync_1|rxrefclk - Requested Period : 10.000 +@P: serdes_sync_1|rxrefclk - Slack : 4.136 +@P: serdes_sync_1|tx_pclk_inferred_clock - Estimated Frequency : 237.5 MHz +@P: serdes_sync_1|tx_pclk_inferred_clock - Requested Frequency : 100.0 MHz +@P: serdes_sync_1|tx_pclk_inferred_clock - Estimated Period : 4.211 +@P: serdes_sync_1|tx_pclk_inferred_clock - Requested Period : 10.000 +@P: serdes_sync_1|tx_pclk_inferred_clock - Slack : 5.789 +@P: System - Estimated Frequency : 840.7 MHz +@P: System - Requested Frequency : 100.0 MHz +@P: System - Estimated Period : 1.190 +@P: System - Requested Period : 10.000 +@P: System - Slack : 8.810 +@P: Total Area : 153.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: Total Area : 0.0 +@P: CPU Time : 0h:00m:03s diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm new file mode 100644 index 0000000..e476d77 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm @@ -0,0 +1,1167 @@ +

    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 10:23:30 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : serdes_sync_1.vhd(30) | Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:30 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : serdes_sync_1.vhd(30) | Top entity is set to serdes_sync_1.
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+@N:CD630 : serdes_sync_1.vhd(30) | Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : serdes_sync_1_softlogic.v(1968) | Synthesizing module sync in library work.
+
+	PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:CG364 : serdes_sync_1_softlogic.v(1051) | Synthesizing module serdes_sync_1sll_core in library work.
+
+	PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+	PLOL_SETTING=32'b00000000000000000000000000000001
+	PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+	PPCIE_MAX_RATE=24'b001100100010111000110101
+	PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+	PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
+	PPCLK_TC=32'b00000000000000100000000000000000
+	PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+	PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+	PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+	LPLL_LOSS_ST=2'b00
+	LPLL_PRELOSS_ST=2'b01
+	LPLL_PRELOCK_ST=2'b10
+	LPLL_LOCK_ST=2'b11
+	LRCLK_TC=16'b1111111111111111
+	LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+	LHB_WAIT_CNT=8'b11111111
+	LPCLK_TC_0=32'b00000000000000001000000000000000
+	LPCLK_TC_1=32'b00000000000000010000000000000000
+	LPCLK_TC_2=32'b00000000000000100000000000000000
+	LPCLK_TC_3=32'b00000000000000101000000000000000
+	LPCLK_TC_4=32'b00000000000000010000000000000000
+	LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+	LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+	LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+	LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+	LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+	LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+	LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+	LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+	LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+	LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+	LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+	LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+	LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+	LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+	LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+	LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+	LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+	LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+	LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N:CG179 : serdes_sync_1_softlogic.v(1287) | Removing redundant assignment.
+@N:CG179 : serdes_sync_1_softlogic.v(1293) | Removing redundant assignment.
+@W:CL169 : serdes_sync_1_softlogic.v(1350) | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : serdes_sync_1_softlogic.v(1739) | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : serdes_sync_1_softlogic.v(92) | Synthesizing module serdes_sync_1rsl_core in library work.
+
+	pnum_channels=32'b00000000000000000000000000000001
+	pprotocol=48'b010001110011100001000010001100010011000001000010
+	pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+	pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_tx_rdy=32'b00000000000000000000101110111000
+	pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_rx_rdy=32'b00000000000000000000101110111000
+	wa_num_cycles=32'b00000000000000000000010000000000
+	dac_num_cycles=32'b00000000000000000000000000000011
+	lreset_pwidth=32'b00000000000000000000000000000011
+	lwait_b4_trst=32'b00000000000010111110101111000010
+	lwait_b4_trst_s=32'b00000000000000000000001100001101
+	lplol_cnt_width=32'b00000000000000000000000000010100
+	lwait_after_plol0=32'b00000000000000000000000000000100
+	lwait_b4_rrst=32'b00000000000000101100000000000000
+	lrrst_wait_width=32'b00000000000000000000000000010100
+	lwait_after_rrst=32'b00000000000011000011010100000000
+	lwait_b4_rrst_s=32'b00000000000000000000000111001100
+	lrlol_cnt_width=32'b00000000000000000000000000010011
+	lwait_after_lols=32'b00000000000000001100010000000000
+	lwait_after_lols_s=32'b00000000000000000000000010010110
+	llols_cnt_width=32'b00000000000000000000000000010010
+	lrdb_max=32'b00000000000000000000000000001111
+	ltxr_wait_width=32'b00000000000000000000000000001100
+	lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+@W:CG133 : serdes_sync_1_softlogic.v(326) | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : serdes_sync_1_softlogic.v(327) | Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W:CG133 : serdes_sync_1_softlogic.v(328) | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : serdes_sync_1_softlogic.v(341) | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : serdes_sync_1_softlogic.v(342) | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : serdes_sync_1_softlogic.v(343) | Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W:CG133 : serdes_sync_1_softlogic.v(346) | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : serdes_sync_1_softlogic.v(347) | Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W:CG360 : serdes_sync_1_softlogic.v(350) | Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W:CG133 : serdes_sync_1_softlogic.v(351) | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : serdes_sync_1_softlogic.v(352) | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : serdes_sync_1_softlogic.v(353) | Removing wire data_loop_b_tc, as there is no assignment to it.
+@W:CL169 : serdes_sync_1_softlogic.v(806) | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W:CL169 : serdes_sync_1_softlogic.v(567) | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W:CL169 : serdes_sync_1_softlogic.v(567) | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W:CL190 : serdes_sync_1_softlogic.v(694) | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : serdes_sync_1_softlogic.v(461) | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : serdes_sync_1_softlogic.v(422) | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL260 : serdes_sync_1_softlogic.v(422) | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : serdes_sync_1_softlogic.v(461) | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : serdes_sync_1_softlogic.v(694) | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL246 : serdes_sync_1_softlogic.v(200) | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : serdes_sync_1_softlogic.v(204) | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : serdes_sync_1_softlogic.v(205) | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : serdes_sync_1_softlogic.v(206) | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : serdes_sync_1_softlogic.v(207) | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL279 : serdes_sync_1_softlogic.v(1739) | Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL279 : serdes_sync_1_softlogic.v(1739) | Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL169 : serdes_sync_1_softlogic.v(1739) | Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
+@W:CL169 : serdes_sync_1_softlogic.v(1739) | Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N:CL201 : serdes_sync_1_softlogic.v(1801) | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: serdes_sync_1_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+
+
    +
    +
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:33 2019
+
+###########################################################]
+
+
     +
    +
+# Fri May 10 10:23:33 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+Linked File: serdes_sync_1_scck.rpt
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
+
+@N:BN362 : serdes_sync_1_softlogic.v(1408) | Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:BN115 : serdes_sync_1_softlogic.v(1244) | Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:BN115 : serdes_sync_1_softlogic.v(1252) | Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:BN115 : serdes_sync_1_softlogic.v(1236) | Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:BN115 : serdes_sync_1_softlogic.v(1268) | Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:BN115 : serdes_sync_1_softlogic.v(1260) | Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist serdes_sync_1
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                    Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                    Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------------------------------
+0 -       System                                   100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                         
+0 -       serdes_sync_1|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     92   
+                                                                                                                         
+0 -       serdes_sync_1|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                         
+0 -       serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+=========================================================================================================================
+
+@W:MT529 : serdes_sync_1_softlogic.v(1988) | Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : serdes_sync_1_softlogic.v(567) | Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W:MT529 : serdes_sync_1_softlogic.v(1988) | Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 10:23:34 2019
+
+###########################################################]
+
+
     +
    +
+# Fri May 10 10:23:34 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+@N:MO231 : serdes_sync_1_softlogic.v(1350) | Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:MO231 : serdes_sync_1_softlogic.v(1304) | Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:MO231 : serdes_sync_1_softlogic.v(1759) | Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:BN362 : serdes_sync_1_softlogic.v(1801) | Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N:MO231 : serdes_sync_1_softlogic.v(412) | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:MO231 : serdes_sync_1_softlogic.v(909) | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:MO231 : serdes_sync_1_softlogic.v(527) | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:MO231 : serdes_sync_1_softlogic.v(778) | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:MO231 : serdes_sync_1_softlogic.v(680) | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N:FX1019 : serdes_sync_1_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:FX1019 : serdes_sync_1_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:FX1019 : serdes_sync_1_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     5.35ns		 151 /       220
+@N:FX1019 : serdes_sync_1_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:FX1019 : serdes_sync_1_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:FX1019 : serdes_sync_1_softlogic.v(1988) | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+ClockId0001        pll_refclki         port                   90         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+ClockId0002        rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+ClockId0003        DCU0_inst           DCUA                   53         sll_inst.pcount_diff[21]                          
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn 
+M-2017.03L-SP1-1
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+@W:MT246 : serdes_sync_1.vhd(160) | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W:MT420 :  | Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" 
+@W:MT420 :  | Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" 
+@W:MT420 :  | Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 10:23:38 2019
+#
+
+
+Top view:               serdes_sync_1
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                                         Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                           Frequency     Frequency     Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------------------------
+serdes_sync_1|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+serdes_sync_1|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                   100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+===========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                              Ending                                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                                System                                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System                                serdes_sync_1|rxrefclk                |  10.000      8.811   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             System                                |  10.000      8.307   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|pll_refclki             |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|tx_pclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                System                                |  10.000      8.193   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                serdes_sync_1|rxrefclk                |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|pll_refclki             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|tx_pclk_inferred_clock  |  10.000      5.789   |  No paths    -      |  No paths    -      |  No paths    -    
+===================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                           Arrival          
+Instance                           Reference                     Type        Pin     Net              Time        Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+=======================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                             Required          
+Instance                           Reference                     Type        Pin     Net                Time         Slack
+                                   Clock                                                                                  
+--------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+==========================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                          Arrival          
+Instance                             Reference                  Type        Pin     Net                Time        Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[9]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[12]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[12]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[13]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                            Required          
+Instance                             Reference                  Type        Pin     Net                  Time         Slack
+                                     Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+===========================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                      Arrival          
+Instance                    Reference                                Type        Pin     Net              Time        Slack
+                            Clock                                                                                          
+---------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+===========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                     Required          
+Instance                     Reference                                Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                          
+--------------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+============================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FF_RX_PCLK     rx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                                       Required           
+Instance                                               Reference     Type        Pin                Net                               Time         Slack 
+                                                       Clock                                                                                             
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP                 un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810 
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D                  un2_rdo_serdes_rst_dual_c_1       9.946        9.556 
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D                  rx_cdr_lol_s                      9.946        9.946 
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D                  rx_los_low_s                      9.946        9.946 
+DCU0_inst                                              System        DCUA        CH0_FF_RXI_CLK     rx_pclk                           10.000       10.000
+=========================================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                                          Pin              Pin               Arrival     No. of    
+Name                                                       Type         Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                  DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                               Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     B                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_2_0                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]         FD1P3DX      SP               In      0.000     0.996       -         
+=================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       150
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 10:23:38 2019
+
+###########################################################]
+
+
     diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm new file mode 100644 index 0000000..9abc35f --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..1a6a0b4 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html @@ -0,0 +1,115 @@ + + + Project Status Summary Page + + + + + + +
    + + + + + + + + + + +
    Project Settings
    Project Name serdes_sync_1 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module serdes_sync_1
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete15770-00m:02s-5/10/19
    10:23 AM
    (premap)Complete8300m:00s0m:00s145MB5/10/19
    10:23 AM
    (fpga_mapper)Complete23400m:03s0m:03s152MB5/10/19
    10:23 AM
    Multi-srs GeneratorComplete5/10/19
    10:23 AM
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 220I/O cells 0
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 150

    + + + + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    serdes_sync_1|pll_refclki100.0 MHz168.9 MHz4.079
    serdes_sync_1|rxrefclk100.0 MHz170.5 MHz4.136
    serdes_sync_1|tx_pclk_inferred_clock100.0 MHz237.5 MHz5.789
    System100.0 MHz840.7 MHz8.810
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 3 / 0

    +
    +
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b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg @@ -0,0 +1,2 @@ +@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1. +Post processing for work.serdes_sync_1.v1 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg.db new file mode 100644 index 0000000000000000000000000000000000000000..8bff0103ceb1593b4eeee3641fcb7f248eb15909 GIT binary patch literal 8192 zcmeI#F;Buk6bJBYW8!3RF-{~GCQY-8 z0VWey{x9vlzL$4x`r9sk>Pai;xYPx=G$O~u^T<7=gb;sqyYv&DTMt&x%e1Wj3ZGnl zeH^(dul7mYg@6DAAOHafKmY;|fB*y_009W>xq$T!PwRDWacB8xDhgo?&xBcLzw_K} z_q(*;e&}`Sx_c&5I^#OYxxS!NsV19hHL__;q}m#;+)k3S!8?C6>x>+va?Rz{|HWx;|NtMypQcr^I OcZI<$3{>g9Q+)&X5NuWe literal 0 HcmV?d00001 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep new file mode 100644 index 0000000..b1d0c36 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep @@ -0,0 +1,22 @@ +#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile|-top|work.serdes_sync_1sll_core|-top|work.serdes_sync_1rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work" +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761 +#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile":1557476610 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630 +#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630 +#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1557476609 +#numinternalfiles:6 +#defaultlanguage:verilog +0 "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" verilog +#Dependency Lists(Uses List) +0 -1 +#Dependency Lists(Users Of) +0 -1 +#Design Unit to File Association +module work serdes_sync_1rsl_core 0 +module work sync 0 +module work serdes_sync_1sll_core 0 +#Unbound instances to file Association. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdepxmr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdepxmr new file mode 100644 index 0000000..37d628b --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdepxmr @@ -0,0 +1 @@ +#XMR Information diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info new file mode 100644 index 0000000..de9b528 --- /dev/null +++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info @@ -0,0 +1,2 @@ +|work.serdes_sync_1rsl_core|parameter pnum_channels 1;,parameter pprotocol "G8B10B";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;| +|work.serdes_sync_1sll_core|parameter PPROTOCOL "G8B10B";,parameter PLOL_SETTING 1;,parameter PDYN_RATE_CTRL "DISABLED";,parameter PPCIE_MAX_RATE "2.5";,parameter PDIFF_VAL_LOCK 39;,parameter PDIFF_VAL_UNLOCK 262;,parameter PPCLK_TC 131072;,parameter PDIFF_DIV11_VAL_LOCK 0;,parameter PDIFF_DIV11_VAL_UNLOCK 0;,parameter PPCLK_DIV11_TC 0;| diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs new file mode 100644 index 0000000000000000000000000000000000000000..85e7f2798c46139606eb456535d3225c96b14e58 GIT binary patch literal 20214 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insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. + + PDATA_RST_VAL=32'b00000000000000000000000000000000 + Generated name = sync_0s +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work. + + PPROTOCOL=48'b010001110011100001000010001100010011000001000010 + PLOL_SETTING=32'b00000000000000000000000000000001 + PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 + PPCIE_MAX_RATE=24'b001100100010111000110101 + PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 + PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110 + PPCLK_TC=32'b00000000000000100000000000000000 + PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 + PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 + PPCLK_DIV11_TC=32'b00000000000000000000000000000000 + LPLL_LOSS_ST=2'b00 + LPLL_PRELOSS_ST=2'b01 + LPLL_PRELOCK_ST=2'b10 + LPLL_LOCK_ST=2'b11 + LRCLK_TC=16'b1111111111111111 + LRCLK_TC_PUL_WIDTH=16'b0000000000110010 + LHB_WAIT_CNT=8'b11111111 + LPCLK_TC_0=32'b00000000000000001000000000000000 + LPCLK_TC_1=32'b00000000000000010000000000000000 + LPCLK_TC_2=32'b00000000000000100000000000000000 + LPCLK_TC_3=32'b00000000000000101000000000000000 + LPCLK_TC_4=32'b00000000000000010000000000000000 + LPDIFF_LOCK_00=32'b00000000000000000000000000001001 + LPDIFF_LOCK_10=32'b00000000000000000000000000010011 + LPDIFF_LOCK_20=32'b00000000000000000000000000100111 + LPDIFF_LOCK_30=32'b00000000000000000000000000110001 + LPDIFF_LOCK_40=32'b00000000000000000000000000010011 + LPDIFF_LOCK_01=32'b00000000000000000000000000001001 + LPDIFF_LOCK_11=32'b00000000000000000000000000010011 + LPDIFF_LOCK_21=32'b00000000000000000000000000100111 + LPDIFF_LOCK_31=32'b00000000000000000000000000110001 + LPDIFF_LOCK_41=32'b00000000000000000000000000010011 + LPDIFF_LOCK_02=32'b00000000000000000000000000110001 + LPDIFF_LOCK_12=32'b00000000000000000000000001100010 + LPDIFF_LOCK_22=32'b00000000000000000000000011000100 + LPDIFF_LOCK_32=32'b00000000000000000000000011110101 + LPDIFF_LOCK_42=32'b00000000000000000000000001100010 + LPDIFF_LOCK_03=32'b00000000000000000000000010000011 + LPDIFF_LOCK_13=32'b00000000000000000000000100000110 + LPDIFF_LOCK_23=32'b00000000000000000000001000001100 + LPDIFF_LOCK_33=32'b00000000000000000000001010001111 + LPDIFF_LOCK_43=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 + LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 + LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 + LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 + LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 + LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 + LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 + LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 + LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 + LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 + LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 + LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 + LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 + LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 + LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 + LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 + LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 + Generated name = serdes_sync_1sll_core_Z1_layer1 +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment. +@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +Could not match passed parameter, trying a case insensitive search ... +@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work. + + pnum_channels=32'b00000000000000000000000000000001 + pprotocol=48'b010001110011100001000010001100010011000001000010 + pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 + pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_tx_rdy=32'b00000000000000000000101110111000 + pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 + pwait_rx_rdy=32'b00000000000000000000101110111000 + wa_num_cycles=32'b00000000000000000000010000000000 + dac_num_cycles=32'b00000000000000000000000000000011 + lreset_pwidth=32'b00000000000000000000000000000011 + lwait_b4_trst=32'b00000000000010111110101111000010 + lwait_b4_trst_s=32'b00000000000000000000001100001101 + lplol_cnt_width=32'b00000000000000000000000000010100 + lwait_after_plol0=32'b00000000000000000000000000000100 + lwait_b4_rrst=32'b00000000000000101100000000000000 + lrrst_wait_width=32'b00000000000000000000000000010100 + lwait_after_rrst=32'b00000000000011000011010100000000 + lwait_b4_rrst_s=32'b00000000000000000000000111001100 + lrlol_cnt_width=32'b00000000000000000000000000010011 + lwait_after_lols=32'b00000000000000001100010000000000 + lwait_after_lols_s=32'b00000000000000000000000010010110 + llols_cnt_width=32'b00000000000000000000000000010010 + lrdb_max=32'b00000000000000000000000000001111 + ltxr_wait_width=32'b00000000000000000000000000001100 + lrxr_wait_width=32'b00000000000000000000000000001100 + Generated name = serdes_sync_1rsl_core_Z2_layer1 +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. +@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. +@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. +@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. 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zO{;#h#F-)9T(ifHE&gpecE*nvvJ~HCXFM+75gC3<(&c+$yT4`g?l)$ z%QwiP>o>?;hu-1;0f%o&WbfksSN6_B>%WA&;;l3{|9_ywTWN0Ptu(j(R$B8~+JZm- c3jhHB|Kf5`-~s>u0RR6309A!GRlltR06hvJ5C8xG literal 0 HcmV?d00001 diff --git a/gbe/trb5sc_gbe.prj b/gbe/trb5sc_gbe.prj index 7559ba8..c9745c9 100644 --- a/gbe/trb5sc_gbe.prj +++ b/gbe/trb5sc_gbe.prj @@ -63,7 +63,7 @@ add_file -vhdl -lib work "tdc_release/tdc_version.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" -#add_file -vhdl -lib work "./project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" +#add_file -vhdl -lib work "./cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" @@ -142,8 +142,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" #channel 1, SFP add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" -add_file -vhdl -lib work "./project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" -add_file -verilog -lib work "./project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" +add_file -vhdl -lib work "./cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" +add_file -verilog -lib work "./cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" @@ -216,7 +216,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_ecp5_txpllLoLdeleted.vhd" -#add_file -vhdl -lib work "./project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" #200MHz +#add_file -vhdl -lib work "./cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" #200MHz add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/pcs_sync_reset.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.vhd" @@ -227,14 +227,14 @@ add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v" -#add_file -verilog -lib work "./project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"#200MHz +#add_file -verilog -lib work "./cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"#200MHz #add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/tsmac35.v" #add_file -vhdl -lib work "/opt/lattice/diamond/3.10_x64/cae_library/synthesis/vhdl/ecp5um.vhd" #GbE ExtRefClk -#add_file -vhdl -lib work "./project/GbePcsExtrefclk/GbePcsExtrefclk.vhd" -#add_file -vhdl -lib work "./project/GbePcsExtrefclk/extref/extref.vhd" -#add_file -vhdl -lib work "./project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" +#add_file -vhdl -lib work "./cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd" +#add_file -vhdl -lib work "./cores/GbePcsExtrefclk/extref/extref.vhd" +#add_file -vhdl -lib work "./cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" #END GbE ExtRefClk add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" @@ -301,7 +301,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" -add_file -vhdl -lib work "./project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" +add_file -vhdl -lib work "./cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" add_file -vhdl -lib work "./trb5sc_gbe.vhd" #add_file -fpga_constraint "./synplify.fdc" -- 2.43.0 

    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 09:02:09 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : sgmii_ecp5.vhd(30) | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:09 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : sgmii_ecp5.vhd(30) | Top entity is set to sgmii_ecp5.
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+@N:CD630 : sgmii_ecp5.vhd(30) | Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : sgmii_ecp5_softlogic.v(1968) | Synthesizing module sync in library work.
+
+	PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:CG364 : sgmii_ecp5_softlogic.v(1051) | Synthesizing module sgmii_ecp5sll_core in library work.
+
+	PPROTOCOL=24'b010001110100001001000101
+	PLOL_SETTING=32'b00000000000000000000000000000000
+	PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+	PPCIE_MAX_RATE=24'b001100100010111000110101
+	PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+	PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+	PPCLK_TC=32'b00000000000000100000000000000000
+	PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+	PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+	PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+	LPLL_LOSS_ST=2'b00
+	LPLL_PRELOSS_ST=2'b01
+	LPLL_PRELOCK_ST=2'b10
+	LPLL_LOCK_ST=2'b11
+	LRCLK_TC=16'b1111111111111111
+	LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+	LHB_WAIT_CNT=8'b11111111
+	LPCLK_TC_0=32'b00000000000000001000000000000000
+	LPCLK_TC_1=32'b00000000000000010000000000000000
+	LPCLK_TC_2=32'b00000000000000100000000000000000
+	LPCLK_TC_3=32'b00000000000000101000000000000000
+	LPCLK_TC_4=32'b00000000000000010000000000000000
+	LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+	LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+	LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+	LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+	LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+	LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+	LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+	LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+	LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+	LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+	LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+	LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+	LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+	LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+	LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+	LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+	LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+	LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+	LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+	LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+	LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+	LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+	LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+	LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+	LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+	LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+	LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+	LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N:CG179 : sgmii_ecp5_softlogic.v(1287) | Removing redundant assignment.
+@N:CG179 : sgmii_ecp5_softlogic.v(1293) | Removing redundant assignment.
+@W:CL169 : sgmii_ecp5_softlogic.v(1350) | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W:CL208 : sgmii_ecp5_softlogic.v(1739) | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : sgmii_ecp5_softlogic.v(92) | Synthesizing module sgmii_ecp5rsl_core in library work.
+
+	pnum_channels=32'b00000000000000000000000000000001
+	pprotocol=24'b010001110100001001000101
+	pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+	pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_tx_rdy=32'b00000000000000000000101110111000
+	pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+	pwait_rx_rdy=32'b00000000000000000000101110111000
+	wa_num_cycles=32'b00000000000000000000010000000000
+	dac_num_cycles=32'b00000000000000000000000000000011
+	lreset_pwidth=32'b00000000000000000000000000000011
+	lwait_b4_trst=32'b00000000000010111110101111000010
+	lwait_b4_trst_s=32'b00000000000000000000001100001101
+	lplol_cnt_width=32'b00000000000000000000000000010100
+	lwait_after_plol0=32'b00000000000000000000000000000100
+	lwait_b4_rrst=32'b00000000000000101100000000000000
+	lrrst_wait_width=32'b00000000000000000000000000010100
+	lwait_after_rrst=32'b00000000000011000011010100000000
+	lwait_b4_rrst_s=32'b00000000000000000000000111001100
+	lrlol_cnt_width=32'b00000000000000000000000000010011
+	lwait_after_lols=32'b00000000000000001100010000000000
+	lwait_after_lols_s=32'b00000000000000000000000010010110
+	llols_cnt_width=32'b00000000000000000000000000010010
+	lrdb_max=32'b00000000000000000000000000001111
+	ltxr_wait_width=32'b00000000000000000000000000001100
+	lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W:CG133 : sgmii_ecp5_softlogic.v(326) | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(327) | Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(328) | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(341) | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(342) | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(343) | Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(346) | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(347) | Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W:CG360 : sgmii_ecp5_softlogic.v(350) | Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W:CG133 : sgmii_ecp5_softlogic.v(351) | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : sgmii_ecp5_softlogic.v(352) | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : sgmii_ecp5_softlogic.v(353) | Removing wire data_loop_b_tc, as there is no assignment to it.
+@W:CL169 : sgmii_ecp5_softlogic.v(806) | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(567) | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(567) | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W:CL190 : sgmii_ecp5_softlogic.v(694) | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : sgmii_ecp5_softlogic.v(461) | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : sgmii_ecp5_softlogic.v(422) | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL260 : sgmii_ecp5_softlogic.v(422) | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : sgmii_ecp5_softlogic.v(461) | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : sgmii_ecp5_softlogic.v(694) | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL246 : sgmii_ecp5_softlogic.v(200) | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(204) | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(205) | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(206) | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : sgmii_ecp5_softlogic.v(207) | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL279 : sgmii_ecp5_softlogic.v(1739) | Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL279 : sgmii_ecp5_softlogic.v(1739) | Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W:CL169 : sgmii_ecp5_softlogic.v(1739) | Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W:CL169 : sgmii_ecp5_softlogic.v(1739) | Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N:CL201 : sgmii_ecp5_softlogic.v(1801) | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+
+
    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 15:07:25 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : pll_in125_out125_out33.vhd(12) | Top entity is set to pll_in125_out125_out33.
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+@N:CD630 : pll_in125_out125_out33.vhd(12) | Synthesizing work.pll_in125_out125_out33.structure.
+@N:CD630 : ecp5um.vhd(2083) | Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N:CD630 : ecp5um.vhd(832) | Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N:CD630 : ecp5um.vhd(825) | Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+@W:CL168 : pll_in125_out125_out33.vhd(46) | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:25 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+
+
    +
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Tue Apr 30 12:09:44 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : PCSD.vhd(24) | Top entity is set to PCSD.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:44 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:CD720 : std.vhd(123) | Setting time resolution to ps
+@N: : PCSD.vhd(24) | Top entity is set to PCSD.
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+@N:CD630 : PCSD.vhd(24) | Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:CG364 : PCSD_softlogic.v(92) | Synthesizing module PCSDrsl_core in library work.
+
+	pnum_channels=32'b00000000000000000000000000000001
+	pprotocol=24'b010001110100001001000101
+	pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+	pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+	pwait_tx_rdy=32'b00000000000000000000101110111000
+	pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+	pwait_rx_rdy=32'b00000000000000000000101110111000
+	wa_num_cycles=32'b00000000000000000000010000000000
+	dac_num_cycles=32'b00000000000000000000000000000011
+	lreset_pwidth=32'b00000000000000000000000000000011
+	lwait_b4_trst=32'b00000000000010111110101111000010
+	lwait_b4_trst_s=32'b00000000000000000000001100001101
+	lplol_cnt_width=32'b00000000000000000000000000010100
+	lwait_after_plol0=32'b00000000000000000000000000000100
+	lwait_b4_rrst=32'b00000000000000101100000000000000
+	lrrst_wait_width=32'b00000000000000000000000000010100
+	lwait_after_rrst=32'b00000000000011000011010100000000
+	lwait_b4_rrst_s=32'b00000000000000000000000111001100
+	lrlol_cnt_width=32'b00000000000000000000000000010011
+	lwait_after_lols=32'b00000000000000001100010000000000
+	lwait_after_lols_s=32'b00000000000000000000000010010110
+	llols_cnt_width=32'b00000000000000000000000000010010
+	lrdb_max=32'b00000000000000000000000000001111
+	ltxr_wait_width=32'b00000000000000000000000000001100
+	lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z1_layer1
+@W:CG360 : PCSD_softlogic.v(274) | Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W:CG360 : PCSD_softlogic.v(275) | Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W:CG360 : PCSD_softlogic.v(276) | Removing wire tx_any_rst, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(277) | Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(278) | Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(279) | Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(280) | Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(281) | Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(282) | Removing wire txr_wt_tc, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(283) | Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(326) | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(327) | Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(328) | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(341) | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(342) | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(343) | Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(346) | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(347) | Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W:CG360 : PCSD_softlogic.v(350) | Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(351) | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(352) | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(353) | Removing wire data_loop_b_tc, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(356) | Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(357) | Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(358) | Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(359) | Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(360) | Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W:CG360 : PCSD_softlogic.v(361) | Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W:CG360 : PCSD_softlogic.v(362) | Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W:CG360 : PCSD_softlogic.v(363) | Removing wire rx_any_rst, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(364) | Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(365) | Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG360 : PCSD_softlogic.v(366) | Removing wire rxr_wt_tc, as there is no assignment to it.
+@W:CG133 : PCSD_softlogic.v(367) | Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(507) | Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W:CG133 : PCSD_softlogic.v(880) | Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W:CL169 : PCSD_softlogic.v(806) | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W:CL169 : PCSD_softlogic.v(567) | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W:CL169 : PCSD_softlogic.v(567) | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W:CL190 : PCSD_softlogic.v(694) | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : PCSD_softlogic.v(461) | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL190 : PCSD_softlogic.v(422) | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W:CL260 : PCSD_softlogic.v(422) | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : PCSD_softlogic.v(461) | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL260 : PCSD_softlogic.v(694) | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W:CL246 : PCSD_softlogic.v(200) | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : PCSD_softlogic.v(204) | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : PCSD_softlogic.v(205) | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : PCSD_softlogic.v(206) | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W:CL246 : PCSD_softlogic.v(207) | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N: :  | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: PCSD_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+
+

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zwnrea&&}vj2>kA1G#LVaF@Pyhl&3I!42l|h8L3dzG{$Hu6g7)8dK`)*VS56KE>hVx z4T{7V4%4Bijn1|iP;{ke<4Gv$$R?NxMY50KEGW88W%Lvj-6Y~Y4Mjb4wmkzyw~D&Y zLecFq+h#*iKT-ENC>o@)%?CwyiMr22(cL=R=0MRX52F{LXpGEgE)~6R1eI;` zp=gq*`yv!Q#wJ(*MNf#jFG10hG8BjQE80PQYb3d87+gN zu&Dbs6h$SrEr+67f!=|ln8LOdP_#wVEr6nJ0Jh^eGekp2 zl)i)Fe-uXFLrK2Q=m#h{T(tHhlpO718~*Yj0Q>|cW25$cOR5AOECHcN~AcW zU!mk&nbCeIxxmZlHz>Iz#^?Z)T&6Sn9ZK3tjQ)U<4lYK2LP;k-qrae}i^k}0D7ldV z9E6f?!ut=D^mLOE&z?$pNsRKKq%Q%;YXBt!;*9d4lF2HgqoHJ~@E!vt(*-&fN}f{KdmNO^))={<2)0)kwT56vf!aV&CKKdc0m19zjM_r*CW%oy2zC=(u7u#tD%;va(Bop% z0fN2UjIM%UABj;%2=){0UJb#4GTS;q@J@}H@*hE=Jcv z@P3)m^$?txU~~fn9}%`2Avi_UxCw%flN0i~LU6j5Q8x(A6sS7{pZ2q@2L#1PlXo)& z=V)xZ1%mTkjCw-wC6$o}g0B*Qyjvlti72;0aFK}83xZ2@_TB+OaVC@34}w85L0*3d z>N2AN5Uh+b8VJFNK!YGyBhZ}?d{3ak5ZvP8atZ{u33L|(w+l1`f^mU{Lh!2umm3Db zJp$bg!EXf`4#6K)_KtwyK7mF;@Hc_(f#9Dydq+X=AA#d1rSEweX;8XZX7mP>iZi3UMNoB&@V*IE$NSm47^+V4FaXbn`ETXii|-Q{81I;gr^)L0KyBNA-e09E(uj0&M@Y@AU5s>W%I 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ziBTa$8*7XL5It69RD^G7A^;7FA=*S`R07eHHAX>*HkBBaLiEfSqYy;T_A@HOckGDu z&>`9~!M1XUULeX<;45T2Y^#K5D`BgG=w*JkRpT2{yo|ySZJS^efoOYC&cGLdc-R(& zXeVLY2+_`>Tn)b8!pq)Th~6MY#v%Hsuzdm1$3(d=Av)E^-mf4!SD>8`ebLLd zT@ZaK!Du%`7Yf@Rh`#P&+g^w+axwZEqKkcuzJcgcQSMuazMWv(cMx46Y~Mq4l_>WE zMAx|3`y)ix30ndm84~4wf@o2Ky+1=V7-zH(qGcXNzd*EHXY?yXD>X*@AzH06`VFFy zIHLm)jp~ekhiHw)=nsCl24RCg`N0}OfAK>#g#P9SY6u$j`hGI*cE2A=HSUXd!esKfprh2!39L5I&-EzlH$vkK(6M z2sP%1PY4~&&zcaz$7Y_F5kUU2{3HpXFo_<0m!9hQE=1 z>SZrJF%(HKItypfD2yb2G6P}$+5A)nq2@pjVGufppSd8^0_T*t*mf>IQ9-tr`~U@^ z^Z0oQLg(}25ri(_ry&Sk$PYgdx`>~3AcW5_{2|)7gr8&}TPuEWfzYM=oB|=7J$s}N z0pwrCPazO$%?}+AYQxVM5W1WnDIjzOKS4l<9vbi>fc$p+d;p;d4Om5V{&?4X6kpzY{+LKcNVLaEK(A_-Gp3rcfV^3%V&#xzhkFqSl|A_A4dG&-w@tk@>_wsyt zLZf*uJ)!$}9zCHkJcpjpSe`#m2xn-E^NsxbdEPwP#_^naLJt7VmnSry=gJd$kmt!0 z!Y6LTnQ#6?o*z%Phj?y0p@(^1JfTTEC!WwFJRhFWqdXU$&}5zmPiP9yfhY7B&wnSR z^4xbqQ+eJyp~rd7JE13dzB?g&w&rsc0pw5TdG3T}@EmtSPxAbBLNj@8JE2)Tubt3S zJg1$|(>$M@&@()jozSy9kDbtLp2JS)Ii9~x$j5Wn2|dsA)(OqwIqQU80Gh8(XfDrH zCp3@esS}#dbJPjF$n(<)E#SH7gkIu#>4aY9Iq8I6;rZx<7V=zlLa*{XbV9H39CSjj z^Zau{8qYl^^ajs6C$xy?oD+JJ=bIB+%yZ2NE#Z0Qgx=yg=7g5={BlCecy2kNw|QPU zq2)ZMoX|TwpPbMNo=Z-sfaj4DTFG"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103, + CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103, + CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103, + CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103, + CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103, + CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103, + CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103, + CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103, + D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2), + D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5), + D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0), + D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3), + D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual, + D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103, + CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn, + D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103, + CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44, + D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44, + D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44, + D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44, + D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44, + CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6, + CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8, + CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c, + CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1), + CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3), + CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5), + CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7), + CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0), + CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66, + CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69, + CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73, + CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77, + CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81, + CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85, + CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89, + CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91, + CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c, + CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94, + CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s, + CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97, + CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c, + CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100, + CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19, + D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23, + D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29, + D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35, + D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40, + D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n103 <= '0' ; + n102 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n112 <= 'Z' ; + rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122, + rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122, + rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122, + rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116, + rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n111 <= '1' ; + n110 <= '0' ; + n122 <= '0' ; + n121 <= '1' ; + n113 <= 'Z' ; + n114 <= 'Z' ; + n115 <= 'Z' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n124 <= '1' ; + n123 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_ngd.asd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v new file mode 100644 index 0000000..69a023d --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module sgmii_ecp5rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_ecp5sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/.recordref b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_CMD_.CML b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_CMD_.CML new file mode 100644 index 0000000..5a64106 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_CMD_.CML @@ -0,0 +1 @@ + -osyn /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs -top sgmii_ecp5 -hdllog /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/ -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib -v2001 -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v -devicelib /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -lib work /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_cmd._cml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_cmd._cml new file mode 100644 index 0000000..fd034f6 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top sgmii_ecp5 -osyn /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.srs \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm/layer0.xdm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm/layer0.xdm new file mode 100644 index 0000000..eca8c09 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm/layer0.xdm @@ -0,0 +1,548 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +SS1SS1SS1S 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a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt new file mode 100644 index 0000000..db46984 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt @@ -0,0 +1,76 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt +#-- Written on Mon May 13 09:09:03 2019 + + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "sgmii_ecp5" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./sgmii_ecp5.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf" +impl -active "syn_results" diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scemi_cfg.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scemi_cfg.txt new file mode 100644 index 0000000..868d437 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scemi_cfg.txt @@ -0,0 +1,3 @@ +## UMR3 MESSAGE PORT CONFIGURATION FILE +## ************************************ +XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs new file mode 100644 index 0000000..7cf9f4b --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs @@ -0,0 +1,74 @@ +#-- Synopsys, Inc. +#-- Version M-2017.03L-SP1-1 +#-- Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" +add_file -verilog "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" +add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc" + + + +#implementation: "syn_results" +impl -add /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "sgmii_ecp5" + +# hdl_compiler_options +set_option -distributed_compile 0 + +# mapper_without_write_options +set_option -frequency 100 +set_option -srs_instrumentation 1 + +# mapper_options +set_option -write_verilog 1 +set_option -write_vhdl 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# NFilter +set_option -no_sequential_opt 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn" + +#set log file +set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf" +impl -active "syn_results" diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr new file mode 100644 index 0000000..c3d63b8 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr @@ -0,0 +1,97 @@ +---------------------------------------------------------------------- +Report for cell sgmii_ecp5.v1 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + Cell usage: + cell count Res Usage(%) + CCU2C 113 100.0 + DCUA 1 100.0 + FD1P3BX 20 100.0 + FD1P3DX 92 100.0 + FD1S3BX 12 100.0 + FD1S3DX 97 100.0 + GSR 1 100.0 + INV 3 100.0 + ORCALUT4 154 100.0 + PFUMX 2 100.0 + PUR 1 100.0 + VHI 6 100.0 + VLO 6 100.0 +SUB MODULES + sgmii_ecp5rsl_core_Z2_layer1 1 100.0 + sgmii_ecp5sll_core_Z1_layer1 1 100.0 + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 513 +---------------------------------------------------------------------- +Report for cell sgmii_ecp5rsl_core_Z2_layer1.netlist + Instance path: rsl_inst + Cell usage: + cell count Res Usage(%) + CCU2C 51 45.1 + FD1P3BX 4 20.0 + FD1P3DX 74 80.4 + FD1S3BX 12 100.0 + FD1S3DX 37 38.1 + ORCALUT4 100 64.9 + PFUMX 2 100.0 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 282 +---------------------------------------------------------------------- +Report for cell sgmii_ecp5sll_core_Z1_layer1.netlist + Instance path: sll_inst + Cell usage: + cell count Res Usage(%) + CCU2C 62 54.9 + FD1P3BX 16 80.0 + FD1P3DX 18 19.6 + FD1S3DX 60 61.9 + INV 3 100.0 + ORCALUT4 54 35.1 + VHI 4 66.7 + VLO 4 66.7 +SUB MODULES + sync_0s 1 100.0 + sync_0s_0 1 100.0 + sync_0s_6 1 100.0 + + TOTAL 224 +---------------------------------------------------------------------- +Report for cell sync_0s_0.netlist + Original Cell name sync_0s + Instance path: sll_inst.pdiff_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s_6.netlist + Original Cell name sync_0s + Instance path: sll_inst.rtc_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 +---------------------------------------------------------------------- +Report for cell sync_0s.netlist + Original Cell name sync_0s + Instance path: sll_inst.phb_sync_inst + Cell usage: + cell count Res Usage(%) + FD1S3DX 2 2.1 + VHI 1 16.7 + VLO 1 16.7 + + TOTAL 4 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.fse b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.fse new file mode 100644 index 0000000..cc147f0 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.fse @@ -0,0 +1,12 @@ + +fsm_encoding {61801018011} sequential + +fsm_state_encoding {61801018011} LPLL_LOSS_ST {00} + +fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01} + +fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10} + +fsm_state_encoding {61801018011} LPLL_LOCK_ST {11} + +fsm_registers {61801018011} {sll_state[1]} {sll_state[0]} diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.htm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.htm new file mode 100644 index 0000000..31d89ed --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.htm @@ -0,0 +1,9 @@ + + + syntmp/sgmii_ecp5_srr.htm log file + + + + + + diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj new file mode 100644 index 0000000..8e1a1a9 --- /dev/null +++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj @@ -0,0 +1,47 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj +#-- Written on Mon May 13 09:09:03 2019 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work 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zd;7BXp(`i&n@y+RN4maNpV*s1uM#xcKO^NTVWr?({iP(-X(j=r!rT-s*`p>^Z{OB( z{{)M&spP+Rk)VL-lq_N&>j}6zi=PDSZ#5BT4JL2)_c+o{1@E4@vX<3*FG3%j|8mRk zm8|HMNoU+7#y^PrpVp8%G(B>GE4)R>!7JM`zx-KzrC|%KWLYFituByc(qsb`EeqDGp?nI*n7=({GtNKd8GE)d!OzRaw7@=7>fKj zprW7j_UdS1N3#anvMTQBb{=9AOxSU}Ox!s&vFoP!zwTElkAx|Msun)0)^rVSVd;*} z!~`lQnQ)xEaai7PKg$cR%9xHb9nx!?M##RpA zLG;)~tb{I+f6TB>mr)Q0U&haBV;N&-;;U<(-388p`P-QUyLps7thC*#ztpq0djI~u z<67+`d|%ttvZf<{Afl&R#(=xuH+^D=$;1@T%M)a5G^xk4SqO&tZ)@9?L&QDDe=2zR zfr0laok))e33IkMgUg4X&e9G6kCp2Sc!Gts(fUtUeJQUO?ejc=zxRYdj29nhJO&=< nkK`6}&uV<*QvM&n|IcqP2U#w%{!erpaE@s7w*OJgU+4ZGx new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Mon May 13 09:09:07 2019 + +###########################################################] +Map & Optimize Report + +# Mon May 13 09:09:07 2019 + +Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 +Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version M-2017.03L-SP1-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) + +Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) +original code -> new code + 00 -> 00 + 01 -> 01 + 10 -> 10 + 11 -> 11 +@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] +@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) + +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s 4.90ns 155 / 221 +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). +@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================================= Non-Gated/Non-Generated Clocks ============================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------------------------------- +@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] +@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] +@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] +========================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB) + +Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn +M-2017.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" +@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" +@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Mon May 13 09:09:11 2019 +# + + +Top view: sgmii_ecp5 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 4.043 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------------- +sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 +sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 +sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 +System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup +======================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------------------------ +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------------------------ +System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - +sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - +sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - +sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - +============================================================================================================================================================ + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|pll_refclki +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 +rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 +rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 +==================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 +rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 +rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 +rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 +rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 +rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 +======================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.867 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 4.079 + + Number of logic level(s): 15 + Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q + Ending point: rsl_inst.genblk1\.plol_cnt[19] / D + The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------- +rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - +plol_cnt[2] Net - - - - 2 +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - +rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - +un1_plol_cnt_tc_10 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - +rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - +un1_plol_cnt_tc_14 Net - - - - 1 +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - +rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - +un1_plol_cnt_tc Net - - - - 5 +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - +rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - +plol_cnt Net - - - - 21 +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - +rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - +plol_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - +rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - +plol_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - +rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - +plol_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - +rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - +plol_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - +rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - +plol_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - +rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - +plol_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - +rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - +plol_cnt_cry[12] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - +rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - +plol_cnt_cry[14] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - +rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - +plol_cnt_cry[16] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - +rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - +plol_cnt_cry[18] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - +rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - +plol_cnt_s[19] Net - - - - 1 +rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - +======================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|rxrefclk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 +rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 +rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 +rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 +rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 +rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 +=================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 +rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 +rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 +rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 +rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 +rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 +================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 5.902 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 4.043 + + Number of logic level(s): 11 + Starting point: rsl_inst.genblk2\.rxs_rst / Q + Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D + The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - +rxs_rst Net - - - - 6 +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - +rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - +rsl_rx_serdes_rst_c Net - - - - 3 +rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - +rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - +dual_or_rserd_rst Net - - - - 9 +rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - +rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - +rx_any_rst Net - - - - 2 +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - +rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - +rxr_wt_cnt9 Net - - - - 14 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - +rxr_wt_cnt_cry[0] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - +rxr_wt_cnt_cry[2] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - +rxr_wt_cnt_cry[4] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - +rxr_wt_cnt_cry[6] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - +rxr_wt_cnt_cry[8] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - +rxr_wt_cnt_cry[10] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - +rxr_wt_cnt_s[11] Net - - - - 1 +rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - +================================================================================================================= + + + + +==================================== +Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------------------ +sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 +sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 +sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 +sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 +sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 +sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 +sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 +sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 +sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 +sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 +======================================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------------------------------------- +sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 +sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 +sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 +sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 +sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 +sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 +sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 +sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 +sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 +sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 +========================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.946 + + - Propagation time: 4.157 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 5.789 + + Number of logic level(s): 13 + Starting point: sll_inst.ppul_sync_p1 / Q + Ending point: sll_inst.pcount[21] / D + The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - +ppul_sync_p1 Net - - - - 25 +sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - +sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - +N_8 Net - - - - 25 +sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - +sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - +pcount_cry[0] Net - - - - 1 +sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - +sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - +pcount_cry[2] Net - - - - 1 +sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - +sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - +pcount_cry[4] Net - - - - 1 +sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - +sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - +pcount_cry[6] Net - - - - 1 +sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - +sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - +pcount_cry[8] Net - - - - 1 +sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - +sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - +pcount_cry[10] Net - - - - 1 +sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - +sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - +pcount_cry[12] Net - - - - 1 +sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - +sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - +pcount_cry[14] Net - - - - 1 +sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - +sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - +pcount_cry[16] Net - - - - 1 +sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - +sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - +pcount_cry[18] Net - - - - 1 +sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - +sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - +pcount_cry[20] Net - - - - 1 +sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - +sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - +pcount_s[21] Net - - - - 1 +sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 +DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------------------------------------- +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 +rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 +rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 +============================================================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.194 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.806 + + - Propagation time: 0.996 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 8.810 + + Number of logic level(s): 2 + Starting point: DCU0_inst / CH0_FFS_RLOL + Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP + The start point is clocked by System [rising] + The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------------------------------------- +DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - +rx_cdr_lol_s Net - - - - 4 +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - +rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - +un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - +un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 +rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - +=================================================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 221 of 24288 (1%) +PIC Latch: 0 +I/O cells: 0 + + +Details: +CCU2C: 113 +DCUA: 1 +FD1P3BX: 20 +FD1P3DX: 92 +FD1S3BX: 12 +FD1S3DX: 97 +GSR: 1 +INV: 3 +ORCALUT4: 154 +PFUMX: 2 +PUR: 1 +VHI: 6 +VLO: 6 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Mon May 13 09:09:11 2019 + +###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srm new file mode 100644 index 0000000000000000000000000000000000000000..c431948d3e731f98541a5231f3f6979cb6e4156a GIT binary patch literal 31486 zcmY(qcTf|~^8l*y5u__9y@;rQbm?8BOA`yd_ue}JM3mmEv`_`5g&KN7?+|(mgie4E z0)!p{&)@gWyqR~if9&4w-p$?K?akiZvc^8T_rF5$>Fd|8oSeh_YMOjulYhC69kL|; z8dFsNAM@_+pySxBSo%c#273;AH}rwg+t2tT&#s8!-ut?Mx=*Q3QHAhe?{uXCZBETk zo@wW}El}tHAvL4M`*ZBAe??p5cXZaVzcfpbEfX5Vfyb9(k1bNH-#xyr@UmI8H{ig_ z;!h=aT?d^-!5I~NSsEFe4j%?t?cbULw2<}!z%!1OoRG5mJ;->!P~A&zr__`~+av86 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