From f0fe17758d0c0b372fba19983b7c8aa24ef7a4d6 Mon Sep 17 00:00:00 2001 From: Cahit Date: Fri, 13 Jun 2014 10:08:05 +0200 Subject: [PATCH] Standard AddOn Project is brought up to date with tdc_v1.6.2 --- ADA_Addon/compile_constraints.pl | 2 + ADA_Addon/compile_periph_gsi.pl | 22 +- ADA_Addon/config.vhd | 10 +- ADA_Addon/currentRelease | 2 +- ADA_Addon/trb3_periph_ADA.vhd | 449 +++++++++++++++++++++---------- 5 files changed, 334 insertions(+), 151 deletions(-) diff --git a/ADA_Addon/compile_constraints.pl b/ADA_Addon/compile_constraints.pl index 9b30454..44a9c03 100755 --- a/ADA_Addon/compile_constraints.pl +++ b/ADA_Addon/compile_constraints.pl @@ -10,4 +10,6 @@ my $TOPNAME = "trb3_periph_ADA"; #Name of top-level entity system("cp ../base/trb3_periph_ADA.lpf diamond/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); system("cat currentRelease/tdc_constraints_64.lpf >> diamond/$TOPNAME.lpf"); +system("cat currentRelease/unimportant_lines_constraints.lpf >> diamond/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> diamond/$TOPNAME.lpf"); diff --git a/ADA_Addon/compile_periph_gsi.pl b/ADA_Addon/compile_periph_gsi.pl index f543c45..fa37e33 100755 --- a/ADA_Addon/compile_periph_gsi.pl +++ b/ADA_Addon/compile_periph_gsi.pl @@ -100,8 +100,10 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + #generate timestamp my $t=time; my $fh = new FileHandle(">version.vhd"); @@ -184,21 +186,22 @@ if($map==1 || $all==1){ print "# !!!Possible Placement Errors!!! #\n"; print "#################################################\n\n"; - my $c="egrep \"WARNING|FC_|HitInvert|ff_en_\" par.log"; + my $c="egrep 'WARNING.*hitBuf_|Channels/hit_buf_RNO|WARNING.*FC_|Channels/Channel200/SimAdderNo_FC|WARNING.*ff_en_|Channels/Channel200/ff_array_en_i_1_i'"." $TOPNAME"."_mrp.html"; system($c); last; } } } - if($par==1 || $all==1){ system("rm $TOPNAME.ncd"); #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; if ($isMultiPar) { - $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -t 1 -e 100 -exp parDisablePgroup=0:parUseNBR=1:parCDP=1:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; execute($c); # find and copy the .ncd file which has met the timing constraints $fh = new FileHandle("<$TOPNAME".".par"); @@ -232,17 +235,19 @@ if($par==1 || $all==1){ } else { - $c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + $c=qq|par -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; execute($c); my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; system($c); } my $c="cat $TOPNAME.par"; system($c); + } -if($timing==1){ +if($timing==1 || $all==1){ # IOR IO Timing Report $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); @@ -259,6 +264,7 @@ if($timing==1){ my $c="cat $TOPNAME.par"; system($c); + } if($bitgen==1 || $all==1){ @@ -267,6 +273,12 @@ if($bitgen==1 || $all==1){ execute($c); } +$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|; +execute($c); + +$c=qq|firefox $TOPNAME.html|; +execute($c); + chdir ".."; exit; diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd index ec9c21e..75eac72 100644 --- a/ADA_Addon/config.vhd +++ b/ADA_Addon/config.vhd @@ -11,8 +11,8 @@ package config is ------------------------------------------------------------------------------ --Include GbE logic - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant USE_DOUBLE_EDGE : integer := c_YES; --Include SPI on AddOn connector @@ -21,6 +21,12 @@ package config is --Add logic to generate configurable trigger signal from input signals. constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; +--Do histos of all inputs + constant INCLUDE_STATISTICS : integer := c_YES; + +--number of real inputs to the FPGA + constant PHYSICAL_INPUTS : integer := 16; + --Define ringbuffer size for TDC channels: 32-64-128 constant RING_BUFFER_SIZE : integer range 32 to 128 := 128; diff --git a/ADA_Addon/currentRelease b/ADA_Addon/currentRelease index 260a94e..ef8072e 120000 --- a/ADA_Addon/currentRelease +++ b/ADA_Addon/currentRelease @@ -1 +1 @@ -../tdc_releases/tdc_v1.6 \ No newline at end of file +../tdc_releases/tdc_v1.6.2 \ No newline at end of file diff --git a/ADA_Addon/trb3_periph_ADA.vhd b/ADA_Addon/trb3_periph_ADA.vhd index 1f990f8..ea69565 100644 --- a/ADA_Addon/trb3_periph_ADA.vhd +++ b/ADA_Addon/trb3_periph_ADA.vhd @@ -171,19 +171,30 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal timer_ticks : std_logic_vector(1 downto 0); --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; + --signal spictrl_read_en : std_logic; + --signal spictrl_write_en : std_logic; + --signal spictrl_data_in : std_logic_vector(31 downto 0); + --signal spictrl_addr : std_logic; + --signal spictrl_data_out : std_logic_vector(31 downto 0); + --signal spictrl_ack : std_logic; + --signal spictrl_busy : std_logic; + --signal spimem_read_en : std_logic; + --signal spimem_write_en : std_logic; + --signal spimem_data_in : std_logic_vector(31 downto 0); + --signal spimem_addr : std_logic_vector(5 downto 0); + --signal spimem_data_out : std_logic_vector(31 downto 0); + --signal spimem_ack : std_logic; + + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(8 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_dataready_out : std_logic; + signal spimem_no_more_data_out : std_logic; + signal spimem_unknown_addr_out : std_logic; + signal spimem_write_ack_out : std_logic; + signal spidac_read_en : std_logic; signal spidac_write_en : std_logic; signal spidac_data_in : std_logic_vector(31 downto 0); @@ -206,6 +217,14 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal srb_data_ready : std_logic; signal srb_invalid : std_logic; + signal cdb_read_en : std_logic; + signal cdb_write_en : std_logic; + signal cdb_data_in : std_logic_vector(31 downto 0); + signal cdb_addr : std_logic_vector(6 downto 0); + signal cdb_data_out : std_logic_vector(31 downto 0); + signal cdb_data_ready : std_logic; + signal cdb_invalid : std_logic; + signal lhb_read_en : std_logic; signal lhb_write_en : std_logic; signal lhb_addr : std_logic_vector(6 downto 0); @@ -233,7 +252,7 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal tdc_ctrl_addr : std_logic_vector(2 downto 0); signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); + signal tdc_ctrl_reg : std_logic_vector(5*32+31 downto 0); signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); @@ -249,6 +268,23 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal trig_nack : std_logic := '0'; signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal stat_din : std_logic_vector(31 downto 0); + signal stat_dout : std_logic_vector(31 downto 0); + signal stat_write : std_logic := '0'; + signal stat_read : std_logic := '0'; + signal stat_ack : std_logic := '0'; + signal stat_nack : std_logic := '0'; + signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); + + signal sed_error : std_logic; + signal sed_din : std_logic_vector(31 downto 0); + signal sed_dout : std_logic_vector(31 downto 0); + signal sed_write : std_logic := '0'; + signal sed_read : std_logic := '0'; + signal sed_ack : std_logic := '0'; + signal sed_nack : std_logic := '0'; + signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + --TDC signal hit_in_i : std_logic_vector(64 downto 1); signal logic_analyser_i : std_logic_vector(15 downto 0); @@ -464,9 +500,11 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 10, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, others => 0) + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"cf80", 2 => x"d400", 3 => x"c000", 4 => x"c100", + 5 => x"c800", 6 => x"cf00", 7 => x"d500", 8 => x"c200", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, + 5 => 3, 6 => 6, 7 => 4, 8 => 7, others => 0) ) port map( CLK => clk_100_i, @@ -483,30 +521,54 @@ begin DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + ----Bus Handler (SPI CTRL) + --BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + --BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + --BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + --BUS_ADDR_OUT(0*16) => spictrl_addr, + --BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + --BUS_TIMEOUT_OUT(0) => open, + --BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + --BUS_DATAREADY_IN(0) => spictrl_ack, + --BUS_WRITE_ACK_IN(0) => spictrl_ack, + --BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + --BUS_UNKNOWN_ADDR_IN(0) => '0', + ----Bus Handler (SPI Memory) + --BUS_READ_ENABLE_OUT(1) => spimem_read_en, + --BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + --BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + --BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + --BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + --BUS_TIMEOUT_OUT(1) => open, + --BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + --BUS_DATAREADY_IN(1) => spimem_ack, + --BUS_WRITE_ACK_IN(1) => spimem_ack, + --BUS_NO_MORE_DATA_IN(1) => '0', + --BUS_UNKNOWN_ADDR_IN(1) => '0', + + --Bus Handler (SPI Flash control) + BUS_READ_ENABLE_OUT(0) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in, + BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, + BUS_DATAREADY_IN(0) => spimem_dataready_out, + BUS_WRITE_ACK_IN(0) => spimem_write_ack_out, + BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out, + BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out, + --Input statistics + BUS_READ_ENABLE_OUT(1) => stat_read, + BUS_WRITE_ENABLE_OUT(1) => stat_write, + BUS_DATA_OUT(1*32+31 downto 1*32) => stat_din, + BUS_ADDR_OUT(1*16+15 downto 1*16) => stat_addr, BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_DATA_IN(1*32+31 downto 1*32) => stat_dout, + BUS_DATAREADY_IN(1) => stat_ack, + BUS_WRITE_ACK_IN(1) => stat_ack, BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => stat_nack, --Bus Handler (SPI DAC) BUS_READ_ENABLE_OUT(2) => spidac_read_en, BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, @@ -543,65 +605,90 @@ begin BUS_WRITE_ACK_IN(4) => '0', BUS_NO_MORE_DATA_IN(4) => '0', BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, - --Encoder Start Registers - BUS_READ_ENABLE_OUT(5) => esb_read_en, - BUS_WRITE_ENABLE_OUT(5) => esb_write_en, - BUS_DATA_OUT(5*32+31 downto 5*32) => open, - BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, - BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + ----Encoder Start Registers + --BUS_READ_ENABLE_OUT(5) => esb_read_en, + --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + --BUS_DATA_OUT(5*32+31 downto 5*32) => open, + --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + --BUS_TIMEOUT_OUT(5) => open, + --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + --BUS_DATAREADY_IN(5) => esb_data_ready, + --BUS_WRITE_ACK_IN(5) => '0', + --BUS_NO_MORE_DATA_IN(5) => '0', + --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + ----Fifo Write Registers + --BUS_READ_ENABLE_OUT(6) => efb_read_en, + --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + --BUS_DATA_OUT(6*32+31 downto 6*32) => open, + --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + --BUS_TIMEOUT_OUT(6) => open, + --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + --BUS_DATAREADY_IN(6) => efb_data_ready, + --BUS_WRITE_ACK_IN(6) => '0', + --BUS_NO_MORE_DATA_IN(6) => '0', + --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + ----Lost Hit Registers + --BUS_READ_ENABLE_OUT(7) => lhb_read_en, + --BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, + --BUS_DATA_OUT(7*32+31 downto 7*32) => open, + --BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, + --BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + --BUS_TIMEOUT_OUT(7) => open, + --BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, + --BUS_DATAREADY_IN(7) => lhb_data_ready, + --BUS_WRITE_ACK_IN(7) => '0', + --BUS_NO_MORE_DATA_IN(7) => '0', + --BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write, + BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open, BUS_TIMEOUT_OUT(5) => open, - BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, - BUS_DATAREADY_IN(5) => esb_data_ready, - BUS_WRITE_ACK_IN(5) => '0', + BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(5) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(5) => tdc_ctrl_write, BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, - --Fifo Write Registers - BUS_READ_ENABLE_OUT(6) => efb_read_en, - BUS_WRITE_ENABLE_OUT(6) => efb_write_en, - BUS_DATA_OUT(6*32+31 downto 6*32) => open, - BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, - BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + BUS_UNKNOWN_ADDR_IN(5) => '0', + --Trigger logic registers + BUS_READ_ENABLE_OUT(6) => trig_read, + BUS_WRITE_ENABLE_OUT(6) => trig_write, + BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din, + BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr, BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, - BUS_DATAREADY_IN(6) => efb_data_ready, - BUS_WRITE_ACK_IN(6) => '0', + BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout, + BUS_DATAREADY_IN(6) => trig_ack, + BUS_WRITE_ACK_IN(6) => trig_ack, BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, - --Lost Hit Registers - BUS_READ_ENABLE_OUT(7) => lhb_read_en, - BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, - BUS_DATA_OUT(7*32+31 downto 7*32) => open, - BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, - BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + BUS_UNKNOWN_ADDR_IN(6) => trig_nack, + --SEU Detection + BUS_READ_ENABLE_OUT(7) => sed_read, + BUS_WRITE_ENABLE_OUT(7) => sed_write, + BUS_DATA_OUT(7*32+31 downto 7*32) => sed_din, + BUS_ADDR_OUT(7*16+15 downto 7*16) => sed_addr, BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, - BUS_DATAREADY_IN(7) => lhb_data_ready, - BUS_WRITE_ACK_IN(7) => '0', + BUS_DATA_IN(7*32+31 downto 7*32) => sed_dout, + BUS_DATAREADY_IN(7) => sed_ack, + BUS_WRITE_ACK_IN(7) => sed_ack, BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, - --TDC config registers - BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, - BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, + BUS_UNKNOWN_ADDR_IN(7) => sed_nack, + --Channel Debug Registers + BUS_READ_ENABLE_OUT(8) => cdb_read_en, + BUS_WRITE_ENABLE_OUT(8) => cdb_write_en, + BUS_DATA_OUT(8*32+31 downto 8*32) => open, + BUS_ADDR_OUT(8*16+6 downto 8*16) => cdb_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+7) => open, BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, - BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, - BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, + BUS_DATA_IN(8*32+31 downto 8*32) => cdb_data_out, + BUS_DATAREADY_IN(8) => cdb_data_ready, + BUS_WRITE_ACK_IN(8) => '0', BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => '0', - --Trigger logic registers - BUS_READ_ENABLE_OUT(9) => trig_read, - BUS_WRITE_ENABLE_OUT(9) => trig_write, - BUS_DATA_OUT(9*32+31 downto 9*32) => trig_din, - BUS_ADDR_OUT(9*16+15 downto 9*16) => trig_addr, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATA_IN(9*32+31 downto 9*32) => trig_dout, - BUS_DATAREADY_IN(9) => trig_ack, - BUS_WRITE_ACK_IN(9) => trig_ack, - BUS_NO_MORE_DATA_IN(9) => '0', - BUS_UNKNOWN_ADDR_IN(9) => trig_nack, + BUS_UNKNOWN_ADDR_IN(8) => cdb_invalid, + + STAT_DEBUG => open ); @@ -622,51 +709,75 @@ begin -- SPI / Flash --------------------------------------------------------------------------- - THE_SPI_MASTER : spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); - - -- data memory for SPI accesses - THE_SPI_MEMORY : spi_databus_memory + --THE_SPI_MASTER : spi_master + -- port map( + -- CLK_IN => clk_100_i, + -- RESET_IN => reset_i, + -- -- Slave bus + -- BUS_READ_IN => spictrl_read_en, + -- BUS_WRITE_IN => spictrl_write_en, + -- BUS_BUSY_OUT => spictrl_busy, + -- BUS_ACK_OUT => spictrl_ack, + -- BUS_ADDR_IN(0) => spictrl_addr, + -- BUS_DATA_IN => spictrl_data_in, + -- BUS_DATA_OUT => spictrl_data_out, + -- -- SPI connections + -- SPI_CS_OUT => FLASH_CS, + -- SPI_SDI_IN => FLASH_DOUT, + -- SPI_SDO_OUT => FLASH_DIN, + -- SPI_SCK_OUT => FLASH_CLK, + -- -- BRAM for read/write data + -- BRAM_A_OUT => spi_bram_addr, + -- BRAM_WR_D_IN => spi_bram_wr_d, + -- BRAM_RD_D_OUT => spi_bram_rd_d, + -- BRAM_WE_OUT => spi_bram_we, + -- -- Status lines + -- STAT => open + -- ); + + ---- data memory for SPI accesses + --THE_SPI_MEMORY : spi_databus_memory + -- port map( + -- CLK_IN => clk_100_i, + -- RESET_IN => reset_i, + -- -- Slave bus + -- BUS_ADDR_IN => spimem_addr, + -- BUS_READ_IN => spimem_read_en, + -- BUS_WRITE_IN => spimem_write_en, + -- BUS_ACK_OUT => spimem_ack, + -- BUS_DATA_IN => spimem_data_in, + -- BUS_DATA_OUT => spimem_data_out, + -- -- state machine connections + -- BRAM_ADDR_IN => spi_bram_addr, + -- BRAM_WR_D_OUT => spi_bram_wr_d, + -- BRAM_RD_D_IN => spi_bram_rd_d, + -- BRAM_WE_IN => spi_bram_we, + -- -- Status lines + -- STAT => open + -- ); + + THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open + CLK_IN => clk_100_i, + RESET_IN => reset_i, + + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_DATAREADY_OUT => spimem_dataready_out, + BUS_WRITE_ACK_OUT => spimem_write_ack_out, + BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out, + BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + + DO_REBOOT_IN => common_ctrl_reg(15), + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_DIN, + SPI_SDI_IN => FLASH_DOUT ); ------------------------------------------------------------------------------- @@ -697,15 +808,15 @@ begin -- Trigger logic --------------------------------------------------------------------------- gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate - THE_TRIG_LOGIC : input_to_trigger_logic + THE_TRIG_LOGIC : entity work.input_to_trigger_logic generic map( - INPUTS => 32, + INPUTS => PHYSICAL_INPUTS, OUTPUTS => 4 ) port map( CLK => clk_100_i, - INPUT => INP(32 downto 1), + INPUT => INP(PHYSICAL_INPUTS-1 downto 0), OUTPUT => trig_out, DATA_IN => trig_din, @@ -716,18 +827,58 @@ begin NACK_OUT => trig_nack, ADDR_IN => trig_addr ); - FPGA5_COMM(10 downto 7) <= trig_out; end generate; --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- - THE_FPGA_REBOOT : fpga_reboot + --THE_FPGA_REBOOT : fpga_reboot + -- port map( + -- CLK => clk_100_i, + -- RESET => reset_i, + -- DO_REBOOT => common_ctrl_reg(15), + -- PROGRAMN => PROGRAMN + -- ); + +--------------------------------------------------------------------------- +-- Input Statistics +--------------------------------------------------------------------------- + gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate + + THE_STAT_LOGIC : entity work.input_statistics + generic map( + INPUTS => PHYSICAL_INPUTS + ) + port map( + CLK => clk_100_i, + + INPUT => INP(PHYSICAL_INPUTS-1 downto 0), + + DATA_IN => stat_din, + DATA_OUT => stat_dout, + WRITE_IN => stat_write, + READ_IN => stat_read, + ACK_OUT => stat_ack, + NACK_OUT => stat_nack, + ADDR_IN => stat_addr + ); + end generate; + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck port map( CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN + ERROR_OUT => sed_error, + + DATA_IN => sed_din, + DATA_OUT => sed_dout, + WRITE_IN => sed_write, + READ_IN => sed_read, + ACK_OUT => sed_ack, + NACK_OUT => sed_nack, + ADDR_IN => sed_addr ); --------------------------------------------------------------------------- @@ -751,8 +902,8 @@ begin THE_TDC : TDC generic map ( CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels - STATUS_REG_NR => 20, -- Number of status regs - CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr + STATUS_REG_NR => 22, -- Number of status regs + CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr TDC_VERSION => TDC_VERSION, -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) @@ -802,6 +953,13 @@ begin SRB_DATA_OUT => srb_data_out, -- bus data SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Channel Debug Bus + CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe + CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe + CDB_ADDR_IN => cdb_addr, -- bus address + CDB_DATA_OUT => cdb_data_out, -- bus data + CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe + CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr --Encoder Start Registers Bus ESB_READ_EN_IN => esb_read_en, -- bus read en strobe ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe @@ -840,4 +998,9 @@ begin end generate Gen_Hit_In_Signals; end generate; + -- Trigger on a TDC Channel + FPGA5_COMM(10 downto 7) <= trig_out; + FPGA5_COMM(6 downto 3) <= (others => 'Z'); + FPGA5_COMM(1) <= 'Z'; + end architecture; -- 2.43.0