From f13356cd6bcf9fdfb814385a451a3e4ccd3253e2 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 23 Apr 2024 19:23:29 +0200 Subject: [PATCH] add empty design for new ADC AddOn --- adc/compile.pl | 1 + adc/config.vhd | 122 ++++++++++ adc/config_compile_frankfurt.pl | 25 ++ adc/par.p2t | 69 ++++++ adc/trb5sc_adc.lpf | 40 ++++ adc/trb5sc_adc.prj | 277 ++++++++++++++++++++++ adc/trb5sc_adc.vhd | 392 ++++++++++++++++++++++++++++++++ pinout/trb5sc_adc.lpf | 380 +++++++++++++++++++++++++++++++ 8 files changed, 1306 insertions(+) create mode 120000 adc/compile.pl create mode 100644 adc/config.vhd create mode 100644 adc/config_compile_frankfurt.pl create mode 100644 adc/par.p2t create mode 100644 adc/trb5sc_adc.lpf create mode 100644 adc/trb5sc_adc.prj create mode 100644 adc/trb5sc_adc.vhd create mode 100644 pinout/trb5sc_adc.lpf diff --git a/adc/compile.pl b/adc/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/adc/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/adc/config.vhd b/adc/config.vhd new file mode 100644 index 0000000..4f233b9 --- /dev/null +++ b/adc/config.vhd @@ -0,0 +1,122 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "85KUM"; +-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement +-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module +-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons +-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 +-- -- 0: single edge only, +-- -- 1: same channel, +-- -- 2: alternating channels, +-- -- 3: same channel with stretcher +-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size +-- -- mode: 0, 1, 2, 3, 7 +-- -- size: 32, 64, 96, 128, dyn +-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC +-- -- 0: Single fine time as the sum of the two transitions +-- -- 1: Double fine time, individual transitions +-- -- 13: Debug - fine time + (if 0x3ff full chain) +-- -- 14: Debug - single fine time and the ROM addresses for the two transitions +-- -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 2000; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_NO; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F586"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000200"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + +-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); +-- t(15) := '1'; --TDC +-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1)); + + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/adc/config_compile_frankfurt.pl b/adc/config_compile_frankfurt.pl new file mode 100644 index 0000000..1c3992f --- /dev/null +++ b/adc/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_mimosis", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_hdmi', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/adc/par.p2t b/adc/par.p2t new file mode 100644 index 0000000..4e8a89b --- /dev/null +++ b/adc/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 9 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/adc/trb5sc_adc.lpf b/adc/trb5sc_adc.lpf new file mode 100644 index 0000000..b2047a0 --- /dev/null +++ b/adc/trb5sc_adc.lpf @@ -0,0 +1,40 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + diff --git a/adc/trb5sc_adc.prj b/adc/trb5sc_adc.prj new file mode 100644 index 0000000..f1510b0 --- /dev/null +++ b/adc/trb5sc_adc.prj @@ -0,0 +1,277 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_adc" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_adc.edf" +set_option log_file "workdir/trb5sc_adc.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" + + + + + + + + + +add_file -vhdl -lib work "./trb5sc_adc.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/adc/trb5sc_adc.vhd b/adc/trb5sc_adc.vhd new file mode 100644 index 0000000..8bdd6af --- /dev/null +++ b/adc/trb5sc_adc.vhd @@ -0,0 +1,392 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_adc is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn + -- FE_GPIO : inout std_logic_vector(11 downto 0); + -- FE_CLK : out std_logic_vector( 2 downto 1); + -- FE_DIFF : inout std_logic_vector(63 downto 0); + -- INP : inout std_logic_vector(63 downto 0); + -- LED_ADDON : out std_logic_vector(5 downto 0); + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(4 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + +architecture arch of trb5sc_adc is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal out_data : std_logic_vector(15 downto 0); + signal out_i : std_logic_vector( 7 downto 0); + signal inp_i : std_logic_vector( 7 downto 0); + signal gbe_status : std_logic_vector(15 downto 0); + + +begin + + trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + USE_NEW_ECP5_RESET => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => BROADCAST_BITMASK, + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16, + USE_GBE => USE_GBE + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_125 => CLK_125, + CLEAR_N => GSR_N, + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer, + STATUS_GBE_OUT=> gbe_status + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busadc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busadc_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + HEADER_IO(7) => HDR_IO(6), + HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9); + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + + + + +end architecture; diff --git a/pinout/trb5sc_adc.lpf b/pinout/trb5sc_adc.lpf new file mode 100644 index 0000000..d670366 --- /dev/null +++ b/pinout/trb5sc_adc.lpf @@ -0,0 +1,380 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON +BANK 0 VCCIO 2.5 V; +BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 4 VCCIO 3.3 V; +BANK 6 VCCIO 2.5 V; +BANK 7 VCCIO 2.5 V; +BANK 8 VCCIO 3.3 V; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_125" SITE "AD1"; #was "OSC_CORE_125" +LOCATE COMP "CLK_200" SITE "AD32"; #was "OSC_CORE_200" +LOCATE COMP "CLK_EXT" SITE "C28"; #was "EXT_CLOCK" +LOCATE COMP "CLK_GPIO" SITE "N27"; #on HDR IO +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100; + + +# LOCATE COMP "ENPIRION_CLOCK" SITE "AM31"; +# IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33; + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TRIG_IN_BACKPL" SITE "AD3"; +LOCATE COMP "TRIG_IN_RJ45" SITE "AC2"; +DEFINE PORT GROUP "TRIG_IN_group" "TRIG_IN*" ; +IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100; + + +LOCATE COMP "SPARE_0" SITE "AC3"; +LOCATE COMP "SPARE_1" SITE "AB1"; +DEFINE PORT GROUP "SPARE_group" "SPARE*" ; +IOBUF GROUP "SPARE_group" IO_TYPE=LVDS ; + +################################################################# +# SFP +################################################################# +LOCATE COMP "SFP_TX_DIS" SITE "AH28"; +LOCATE COMP "SFP_LOS" SITE "AK29"; +LOCATE COMP "SFP_MOD_0" SITE "AG28"; +IOBUF PORT "SFP_TX_DIS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +# LOCATE COMP "SFP_RATE_SEL" SITE "AG30"; +# LOCATE COMP "SFP_TX_FAULT" SITE "AH30"; +# LOCATE COMP "SFP_MOD_1" SITE "AG29"; +# LOCATE COMP "SFP_MOD_2" SITE "AJ28"; + + +################################################################# +# Frontend +################################################################# +LOCATE COMP "CS_1" SITE "A18"; #"FE_GPIO_0" +LOCATE COMP "CS_2" SITE "C18"; #"FE_GPIO_1" +LOCATE COMP "MISO_1" SITE "D18"; #"FE_GPIO_2" +LOCATE COMP "MISO_2" SITE "F18"; #"FE_GPIO_3" +LOCATE COMP "CS_3" SITE "A19"; #"FE_GPIO_4" +LOCATE COMP "CS_4" SITE "B19"; #"FE_GPIO_5" +LOCATE COMP "MISO_3" SITE "C19"; #"FE_GPIO_6" +LOCATE COMP "MISO_4" SITE "D19"; #"FE_GPIO_7" +DEFINE PORT GROUP "MISO_group" "MISO*" ; +IOBUF GROUP "MISO_group" IO_TYPE=LVTTL33; +DEFINE PORT GROUP "CS_group" "CS*" ; +IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25; + + +LOCATE COMP "SFP_ADD_LOS" SITE "E19"; #"FE_GPIO_8" +LOCATE COMP "SFP_ADD_MOD0" SITE "F19"; #"FE_GPIO_9" +LOCATE COMP "SFP_ADD_TX_DIS" SITE "A20"; #"FE_GPIO_10" +LOCATE COMP "SFP_ADD_LED" SITE "C20"; #"FE_GPIO_11" +IOBUF PORT "SFP_ADD_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_ADD_TX_DIS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "SFP_ADD_MOD0" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_ADD_LED" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "FE_GPIO_0" SITE "A18"; +LOCATE COMP "FE_GPIO_1" SITE "C18"; +LOCATE COMP "FE_GPIO_2" SITE "D18"; +LOCATE COMP "FE_GPIO_3" SITE "F18"; +LOCATE COMP "FE_GPIO_4" SITE "A19"; +LOCATE COMP "FE_GPIO_5" SITE "B19"; +LOCATE COMP "FE_GPIO_6" SITE "C19"; +LOCATE COMP "FE_GPIO_7" SITE "D19"; +LOCATE COMP "FE_GPIO_8" SITE "E19"; +LOCATE COMP "FE_GPIO_9" SITE "F19"; +LOCATE COMP "FE_GPIO_10" SITE "A20"; +LOCATE COMP "FE_GPIO_11" SITE "C20"; +DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; +IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +LOCATE COMP "SCK" SITE "C5";#"FE_CLK_1" +LOCATE COMP "MOSI" SITE "P5";#"FE_CLK_2" +IOBUF PORT "SCK" IO_TYPE=LVDS ; +IOBUF PORT "MOSI" IO_TYPE=LVDS ; + +# DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ; +# IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "GPIO_0" SITE "R29" ; #"FE_DIFF[0]" +LOCATE COMP "GPIO_4" SITE "T29" ; #"FE_DIFF[1]" +LOCATE COMP "GPIO_1" SITE "P31" ; #"FE_DIFF[2]" +LOCATE COMP "GPIO_2" SITE "R30" ; #"FE_DIFF[3]" +# LOCATE COMP "" SITE "N32" ; #"FE_DIFF[4]" +LOCATE COMP "GPIO_3" SITE "U31" ; #"FE_DIFF[5]" +LOCATE COMP "ADDON_LED_1" SITE "R32" ; #"FE_DIFF[6]" +LOCATE COMP "GPIO_5" SITE "W30" ; #"FE_DIFF[7]" +LOCATE COMP "ADDON_LED_3" SITE "T32" ; #"FE_DIFF[8]" +# LOCATE COMP "" SITE "V32" ; #"FE_DIFF[9]" +LOCATE COMP "ADDON_LED_5" SITE "Y26" ; #"FE_DIFF[10]" +LOCATE COMP "SDIO_A" SITE "Y28" ; #"FE_DIFF[11]" +LOCATE COMP "ADDON_LED_7" SITE "Y29" ; #"FE_DIFF[12]" +LOCATE COMP "SCLK_A" SITE "AB26" ; #"FE_DIFF[13]" +LOCATE COMP "ADDON_LED_RJ_1" SITE "AB28" ; #"FE_DIFF[14]" +LOCATE COMP "CSB_A" SITE "AC26" ; #"FE_DIFF[15]" +LOCATE COMP "FCO_A" SITE "D29" ; #"FE_DIFF[16]" +LOCATE COMP "DATA_A_0" SITE "F29" ; #"FE_DIFF[17]" +LOCATE COMP "DCO_A" SITE "B32" ; #"FE_DIFF[18]" +LOCATE COMP "DATA_A_1" SITE "D30" ; #"FE_DIFF[19]" +LOCATE COMP "DATA_A_3" SITE "F30" ; #"FE_DIFF[20]" +LOCATE COMP "DATA_A_2" SITE "C32" ; #"FE_DIFF[21]" +# LOCATE COMP "" SITE "F31" ; #"FE_DIFF[22]" +# LOCATE COMP "" SITE "F32" ; #"FE_DIFF[23]" +# LOCATE COMP "" SITE "H31" ; #"FE_DIFF[24]" +# LOCATE COMP "" SITE "J30" ; #"FE_DIFF[25]" +# LOCATE COMP "" SITE "K31" ; #"FE_DIFF[26]" +# LOCATE COMP "" SITE "K32" ; #"FE_DIFF[27]" +LOCATE COMP "CLK_A" SITE "L31" ; #"FE_DIFF[28]" +LOCATE COMP "LEMO_OUT_0" SITE "J29" ; #"FE_DIFF[29]" +LOCATE COMP "CNV_B" SITE "H27" ; #"FE_DIFF[30]" +LOCATE COMP "LEMO_OE_0" SITE "K27" ; #"FE_DIFF[31]" +LOCATE COMP "CLK_B" SITE "D4" ; #"FE_DIFF[32]" +LOCATE COMP "TESTPAT_B" SITE "F4" ; #"FE_DIFF[33]" +LOCATE COMP "DCO_B" SITE "B1" ; #"FE_DIFF[34]" +LOCATE COMP "LEMO_OUT_1" SITE "D3" ; #"FE_DIFF[35]" +LOCATE COMP "DATA_B" SITE "F3" ; #"FE_DIFF[36]" +LOCATE COMP "LEMO_OE_1" SITE "C1" ; #"FE_DIFF[37]" +LOCATE COMP "ADDON_RJ_1" SITE "F2" ; #"FE_DIFF[38]" +LOCATE COMP "LEMO_TTL_0" SITE "F1" ; #"FE_DIFF[39]" +LOCATE COMP "ADDON_RJ_3" SITE "H2" ; #"FE_DIFF[40]" +LOCATE COMP "LEMO_NIM_0" SITE "J3" ; #"FE_DIFF[41]" +LOCATE COMP "ADDON_RJ_2" SITE "K2" ; #"FE_DIFF[42]" +LOCATE COMP "LEMO_TTL_1" SITE "K1" ; #"FE_DIFF[43]" +LOCATE COMP "ADDON_RJ_0" SITE "L2" ; #"FE_DIFF[44]" +LOCATE COMP "LEMO_NIM_1" SITE "J4" ; #"FE_DIFF[45]" +LOCATE COMP "USB_TXD" SITE "H6" ; #"FE_DIFF[46]" +LOCATE COMP "USB_RXD" SITE "K6" ; #"FE_DIFF[47]" +# LOCATE COMP "" SITE "R4" ; #"FE_DIFF[48]" +LOCATE COMP "USB_OEn" SITE "T4" ; #"FE_DIFF[49]" +LOCATE COMP "USB_RDn" SITE "P2" ; #"FE_DIFF[50]" +LOCATE COMP "USB_CLK" SITE "R3" ; #"FE_DIFF[51]" +LOCATE COMP "USB_TXEn" SITE "N1" ; #"FE_DIFF[52]" +LOCATE COMP "USB_WRn" SITE "U2" ; #"FE_DIFF[53]" +LOCATE COMP "USB_D_7" SITE "R1" ; #"FE_DIFF[54]" +LOCATE COMP "USB_SIWU" SITE "W3" ; #"FE_DIFF[55]" +LOCATE COMP "USB_D_6" SITE "T1" ; #"FE_DIFF[56]" +LOCATE COMP "USB_RXFn" SITE "V1" ; #"FE_DIFF[57]" +LOCATE COMP "USB_D_2" SITE "Y7" ; #"FE_DIFF[58]" +LOCATE COMP "USB_D_3" SITE "Y5" ; #"FE_DIFF[59]" +LOCATE COMP "USB_D_1" SITE "Y4" ; #"FE_DIFF[60]" +LOCATE COMP "USB_D_4" SITE "AB7" ; #"FE_DIFF[61]" +LOCATE COMP "USB_D_0" SITE "AB5" ; #"FE_DIFF[62]" +LOCATE COMP "USB_D_5" SITE "AC7" ; #"FE_DIFF[63]" + +LOCATE COMP "ADDON_LED_2" SITE "T31"; #"FE_DIFF_6_N" +LOCATE COMP "ADDON_LED_4" SITE "U32"; #"FE_DIFF_8_N" +LOCATE COMP "ADDON_LED_6" SITE "Y27"; #"FE_DIFF_10_N" +LOCATE COMP "ADDON_LED_RJ_0" SITE "W29"; #"FE_DIFF_12_N" + +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS DIFFRESISTOR=100; + +IOBUF PORT "GPIO_0" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "GPIO_1" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "GPIO_2" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "GPIO_3" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "GPIO_4" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "GPIO_5" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +IOBUF PORT "SDIO_A" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "SCLK_A" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "CSB_A" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +IOBUF PORT "LEMO_OUT_0" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "LEMO_OE_0" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "LEMO_OUT_1" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "LEMO_OE_1" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "TESTPAT_B" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF PORT "LEMO_TTL_0" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "LEMO_NIM_0" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "LEMO_TTL_1" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "LEMO_NIM_1" IO_TYPE=LVDS DIFFRESISTOR=100 ; + + +IOBUF PORT "FCO_A" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DCO_A" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DATA_A_0" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DATA_A_1" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DATA_A_2" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DATA_A_3" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DATA_B" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "CLK_A" IO_TYPE=LVDS ; +IOBUF PORT "CLK_B" IO_TYPE=LVDS ; +IOBUF PORT "CNV_B" IO_TYPE=LVDS ; + +DEFINE PORT GROUP "ADDON_RJ_group" "ADDON_RJ*" ; +IOBUF GROUP "ADDON_RJ_group" IO_TYPE=LVDS DIFFRESISTOR=100; +DEFINE PORT GROUP "ADDON_LED_group" "ADDON_LED*" ; +IOBUF GROUP "ADDON_LED_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +DEFINE PORT GROUP "USB_group" "USB*" ; +IOBUF GROUP "USB_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +################################################################# +# Temperature, Flash & ID +################################################################# +LOCATE COMP "I2C_SDA" SITE "A11"; +LOCATE COMP "I2C_SCL" SITE "B11"; +LOCATE COMP "TMP_ALERT" SITE "C11"; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "PROGRAMN" SITE "AH1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16"; +IOBUF PORT "IN_SELECT_EXT_CLOCK" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "FLASH_HOLD" SITE "AL1"; +LOCATE COMP "FLASH_MISO" SITE "AJ2"; +LOCATE COMP "FLASH_MOSI" SITE "AK2"; +LOCATE COMP "FLASH_NCS" SITE "AJ3"; +LOCATE COMP "FLASH_SCLK" SITE "AJ1"; +LOCATE COMP "FLASH_WP" SITE "AM2"; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; + + +LOCATE COMP "ADC_MISO" SITE "AK3"; +LOCATE COMP "ADC_MOSI" SITE "AL3"; +LOCATE COMP "ADC_NCS" SITE "AH3"; +LOCATE COMP "ADC_SCLK" SITE "AG3"; +IOBUF PORT "ADC_SCLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_NCS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MOSI" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MISO" IO_TYPE=LVTTL33 PULLMODE=UP ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_SFP_YELLOW" SITE "AG32"; +LOCATE COMP "LED_SFP_GREEN" SITE "AK30"; +LOCATE COMP "LED_SFP_RED" SITE "AH32"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_1" SITE "A26"; +LOCATE COMP "LED_2" SITE "B26"; +LOCATE COMP "LED_3" SITE "A28"; +LOCATE COMP "LED_4" SITE "A29"; +LOCATE COMP "LED_5" SITE "A30"; +LOCATE COMP "LED_6" SITE "A31"; +LOCATE COMP "LED_7" SITE "B29"; +LOCATE COMP "LED_8" SITE "B30"; +IOBUF PORT "LED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_3" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_4" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_5" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_6" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_7" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_8" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "LED_RJ_GREEN_0" SITE "AK32"; +LOCATE COMP "LED_RJ_RED_0" SITE "AJ32"; +LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "AM30"; +LOCATE COMP "LED_RJ_RED_1" SITE "AL30"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVTTL33 ; + +################################################################# +# Test & Other IO (v2) +################################################################# + #connector pin on v1 +LOCATE COMP "HDR_IO_0" SITE "A23"; #on HDR_0 +LOCATE COMP "HDR_IO_1" SITE "A22"; #on HDR_1 +LOCATE COMP "HDR_IO_2" SITE "C22"; #on HDR_6 +LOCATE COMP "HDR_IO_3" SITE "A24"; #on HDR_3 +LOCATE COMP "HDR_IO_4" SITE "B23"; #on HDR_5 +LOCATE COMP "HDR_IO_5" SITE "A25"; #n/a +LOCATE COMP "HDR_IO_6" SITE "B22"; #on HDR_2 +LOCATE COMP "HDR_IO_7" SITE "D24"; #on HDR_9 +LOCATE COMP "HDR_IO_8" SITE "C23"; #on HDR_4 +LOCATE COMP "HDR_IO_9" SITE "C24"; #on HDR_7 +LOCATE COMP "HDR_IO_10" SITE "D25"; #n/a +LOCATE COMP "HDR_IO_11" SITE "D26"; #n/a +LOCATE COMP "HDR_IO_12" SITE "B25"; #n/a +LOCATE COMP "HDR_IO_13" SITE "C25"; #n/a +LOCATE COMP "HDR_IO_14" SITE "E25"; #n/a +LOCATE COMP "HDR_IO_15" SITE "F24"; #n/a +LOCATE COMP "HDR_IO_16" SITE "F23"; #on HDR_12 +LOCATE COMP "HDR_IO_17" SITE "D23"; #on HDR_8 +LOCATE COMP "HDR_IO_18" SITE "E23"; #on HDR_10 +LOCATE COMP "HDR_IO_19" SITE "E22"; #on HDR_13 +LOCATE COMP "HDR_IO_20" SITE "D22"; #on HDR_11 +LOCATE COMP "HDR_IO_21" SITE "F25"; #n/a +LOCATE COMP "HDR_IO_22" SITE "F22"; #on HDR_15 +LOCATE COMP "HDR_IO_23" SITE "F20"; #on HDR_14 + +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + +################################################################# +# Test & Other IO - from version 1 boards (TEST pins have not been reassigned) +################################################################# +LOCATE COMP "TEST_1" SITE "A7"; +LOCATE COMP "TEST_2" SITE "A5"; +LOCATE COMP "TEST_3" SITE "A4"; +LOCATE COMP "TEST_4" SITE "A3"; +LOCATE COMP "TEST_5" SITE "A2"; +LOCATE COMP "TEST_6" SITE "B3"; +LOCATE COMP "TEST_7" SITE "B4"; +LOCATE COMP "TEST_8" SITE "B7"; +LOCATE COMP "TEST_9" SITE "C7"; +LOCATE COMP "TEST_10" SITE "C8"; +LOCATE COMP "TEST_11" SITE "D7"; +LOCATE COMP "TEST_12" SITE "D8"; +LOCATE COMP "TEST_13" SITE "E8"; +LOCATE COMP "TEST_14" SITE "F8"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8; + + +#LOCATE COMP "HDR_IO_0" SITE "A23"; +#LOCATE COMP "HDR_IO_1" SITE "A22"; +#LOCATE COMP "HDR_IO_2" SITE "B22"; +#LOCATE COMP "HDR_IO_3" SITE "A24"; +#LOCATE COMP "HDR_IO_4" SITE "C23"; +#LOCATE COMP "HDR_IO_5" SITE "B23"; +#LOCATE COMP "HDR_IO_6" SITE "C22"; +#LOCATE COMP "HDR_IO_7" SITE "C24"; +#LOCATE COMP "HDR_IO_8" SITE "D23"; +#LOCATE COMP "HDR_IO_9" SITE "D24"; +#LOCATE COMP "HDR_IO_10" SITE "E23"; +#LOCATE COMP "HDR_IO_11" SITE "D22"; +#LOCATE COMP "HDR_IO_12" SITE "F23"; +#LOCATE COMP "HDR_IO_13" SITE "E22"; +#LOCATE COMP "HDR_IO_14" SITE "F20"; +#LOCATE COMP "HDR_IO_15" SITE "F22"; +#DEFINE PORT GROUP "HDR_group" "HDR*" ; +#IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + + + +LOCATE COMP "BACK_GPIO_0" SITE "P28"; +LOCATE COMP "BACK_GPIO_1" SITE "P29"; +LOCATE COMP "BACK_GPIO_2" SITE "R27"; +LOCATE COMP "BACK_GPIO_3" SITE "T27"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; -- 2.43.0