From f13f9b72f39539d0b810c8e90ad3ff0ab617e3af Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 21 Sep 2009 10:00:47 +0000 Subject: [PATCH] *** empty log message *** --- basics/signal_sync.vhd | 6 + media_interfaces/trb_net16_med_ecp_fot_4.vhd | 6 + special/spi_databus_memory.vhd | 39 +-- special/spi_master.vhd | 327 ++++++++++--------- special/spi_slim.vhd | 211 ++++++------ trb_net16_endpoint_hades_full.vhd | 181 ++++++++-- trb_net16_hub_base.vhd | 25 +- trb_net16_hub_ipu_logic.vhd | 45 ++- trb_net16_hub_logic.vhd | 9 +- trb_net16_ibuf.vhd | 12 +- trb_net16_io_multiplexer.vhd | 104 ++---- trb_net16_iobuf.vhd | 3 +- trb_net16_med_16_CC.vhd | 28 +- trb_net16_obuf.vhd | 2 + trb_net16_regIO.vhd | 94 ++---- trb_net16_term_buf.vhd | 2 +- trb_net_components.vhd | 127 ++++++- trb_net_onewire_listener.vhd | 7 + trb_net_sbuf.vhd | 79 ++--- 19 files changed, 759 insertions(+), 548 deletions(-) diff --git a/basics/signal_sync.vhd b/basics/signal_sync.vhd index 8a800c2..2ec31a7 100644 --- a/basics/signal_sync.vhd +++ b/basics/signal_sync.vhd @@ -23,6 +23,12 @@ architecture behavioral of signal_sync is signal sync_q : std_logic_vector((DEPTH+1)*WIDTH-1 downto 0); + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_keep of sync_q : signal is true; + attribute syn_preserve of sync_q : signal is true; + + begin sync_q(WIDTH-1 downto 0) <= D_IN; D_OUT <= sync_q((DEPTH+1)*WIDTH-1 downto DEPTH*WIDTH); diff --git a/media_interfaces/trb_net16_med_ecp_fot_4.vhd b/media_interfaces/trb_net16_med_ecp_fot_4.vhd index f9b615a..b63b85c 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4.vhd @@ -306,7 +306,13 @@ component serdes_fot_full_quad is attribute syn_keep : boolean; + attribute syn_preserve : boolean; + attribute syn_keep of led_counter : signal is true; + attribute syn_preserve of led_counter : signal is true; + attribute syn_keep of byte_waiting : signal is true; + attribute syn_preserve of byte_waiting : signal is true; + begin gen_normal_serdes : if REVERSE_ORDER = c_NO generate diff --git a/special/spi_databus_memory.vhd b/special/spi_databus_memory.vhd index 0debd28..2ee9542 100644 --- a/special/spi_databus_memory.vhd +++ b/special/spi_databus_memory.vhd @@ -9,20 +9,20 @@ use work.trb_net_components.all; entity spi_databus_memory is port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; + CLK_IN : in std_logic; + RESET_IN : in std_logic; -- Slave bus - BUS_ADDR_IN : in std_logic_vector(5 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; + BUS_ADDR_IN : in std_logic_vector(5 downto 0); + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; BUS_ACK_OUT : out std_logic; - BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- state machine connections - BRAM_ADDR_IN : in std_logic_vector(7 downto 0); + BRAM_ADDR_IN : in std_logic_vector(7 downto 0); BRAM_WR_D_OUT : out std_logic_vector(7 downto 0); - BRAM_RD_D_IN : in std_logic_vector(7 downto 0); - BRAM_WE_IN : in std_logic; + BRAM_RD_D_IN : in std_logic_vector(7 downto 0); + BRAM_WE_IN : in std_logic; -- Status lines STAT : out std_logic_vector(63 downto 0) -- DEBUG ); @@ -30,25 +30,18 @@ end entity; architecture Behavioral of spi_databus_memory is - -- Signals type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); signal CURRENT_STATE, NEXT_STATE: STATES; -- slave bus signals - signal BUS_ack_x : std_logic; - signal BUS_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked - signal wr_data : std_logic_vector(15 downto 0); - signal wr_we : std_logic; - signal buf_BUS_data_out : std_logic_vector(31 downto 0); - - signal onewire_bsm : std_logic_vector(7 downto 0); + signal bus_ack_x : std_logic; + signal bus_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + signal buf_bus_data_out : std_logic_vector(31 downto 0); begin diff --git a/special/spi_master.vhd b/special/spi_master.vhd index d0ba922..614690f 100755 --- a/special/spi_master.vhd +++ b/special/spi_master.vhd @@ -9,28 +9,28 @@ use work.trb_net_components.all; entity spi_master is port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; + CLK_IN : in std_logic; + RESET_IN : in std_logic; -- Slave bus - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - BUS_BUSY_OUT : out std_logic; - BUS_ACK_OUT : out std_logic; - BUS_ADDR_IN : in std_logic_vector(0 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(0 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; -- BRAM for read/write data - BRAM_A_OUT : out std_logic_vector(7 downto 0); - BRAM_WR_D_IN : in std_logic_vector(7 downto 0); - BRAM_RD_D_OUT : out std_logic_vector(7 downto 0); - BRAM_WE_OUT : out std_logic; + BRAM_A_OUT : out std_logic_vector(7 downto 0); + BRAM_WR_D_IN : in std_logic_vector(7 downto 0); + BRAM_RD_D_OUT : out std_logic_vector(7 downto 0); + BRAM_WE_OUT : out std_logic; -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG + STAT : out std_logic_vector(31 downto 0) -- DEBUG ); end entity; @@ -41,28 +41,29 @@ architecture Behavioral of spi_master is type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); signal CURRENT_STATE, NEXT_STATE: STATES; - signal status_data : std_logic_vector(31 downto 0); - signal spi_busy : std_logic; + signal status_data : std_logic_vector(31 downto 0); + signal spi_busy : std_logic; signal reg_ctrl_data : std_logic_vector(31 downto 0); -- CMD, ADH, ADM, ADL - signal reg_status_data : std_logic_vector(31 downto 0); -- MAX + signal reg_status_data : std_logic_vector(31 downto 0); -- MAX - signal reg_BUS_data_out : std_logic_vector(31 downto 0); -- readback + signal reg_bus_data_out : std_logic_vector(31 downto 0); -- readback - signal spi_bsm : std_logic_vector(7 downto 0); + signal spi_bsm : std_logic_vector(7 downto 0); + signal spi_debug : std_logic_vector(31 downto 0); - signal spi_start_x : std_logic; + signal spi_start_x : std_logic; signal spi_start : std_logic; -- State machine signals - signal BUS_busy_x : std_logic; - signal BUS_busy : std_logic; - signal BUS_ack_x : std_logic; - signal BUS_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; + signal bus_busy_x : std_logic; + signal bus_busy : std_logic; + signal bus_ack_x : std_logic; + signal bus_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; begin @@ -71,120 +72,126 @@ begin --------------------------------------------------------- THE_SPI_SLIM: spi_slim - port map( - SYSCLK => clk_in, - RESET => reset_in, - -- Command interface - START_IN => spi_start, -- not really nice, but should work - BUSY_OUT => spi_busy, - CMD_IN => reg_ctrl_data(31 downto 24), - ADH_IN => reg_ctrl_data(23 downto 16), - ADM_IN => reg_ctrl_data(15 downto 8), - ADL_IN => reg_ctrl_data(7 downto 0), - MAX_IN => reg_status_data(31 downto 24), - TXDATA_IN => bram_wr_d_in, - TX_RD_OUT => open, -- not needed - RXDATA_OUT => bram_rd_d_out, - RX_WR_OUT => bram_we_out, - TX_RX_A_OUT => bram_a_out, - -- SPI interface - SPI_SCK_OUT => spi_sck_out, - SPI_CS_OUT => spi_cs_out, - SPI_SDI_IN => spi_sdi_in, - SPI_SDO_OUT => spi_sdo_out, - -- DEBUG - CLK_EN_OUT => open, -- not needed - BSM_OUT => spi_bsm, - DEBUG_OUT => open -- BUG - ); +port map( + SYSCLK => clk_in, + RESET => reset_in, + -- Command interface + START_IN => spi_start, -- not really nice, but should work + BUSY_OUT => spi_busy, + CMD_IN => reg_ctrl_data(31 downto 24), + ADH_IN => reg_ctrl_data(23 downto 16), + ADM_IN => reg_ctrl_data(15 downto 8), + ADL_IN => reg_ctrl_data(7 downto 0), + MAX_IN => reg_status_data(31 downto 24), + TXDATA_IN => bram_wr_d_in, + TX_RD_OUT => open, -- not needed + RXDATA_OUT => bram_rd_d_out, + RX_WR_OUT => bram_we_out, + TX_RX_A_OUT => bram_a_out, + -- SPI interface + SPI_SCK_OUT => spi_sck_out, + SPI_CS_OUT => spi_cs_out, + SPI_SDI_IN => spi_sdi_in, + SPI_SDO_OUT => spi_sdo_out, + -- DEBUG + CLK_EN_OUT => open, -- not needed + BSM_OUT => spi_bsm, + DEBUG_OUT => spi_debug --open -- BUG +); --------------------------------------------------------- -- Statemachine -- --------------------------------------------------------- - STATE_MEM: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - BUS_busy <= '0'; - BUS_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - BUS_busy <= BUS_busy_x; - BUS_ack <= BUS_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; - end process STATE_MEM; - - TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in, spi_busy ) - begin - NEXT_STATE <= SLEEP; - BUS_busy_x <= '0'; - BUS_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => - if ( (spi_busy = '0') and (BUS_read_in = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (spi_busy = '0') and (BUS_write_in = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; - elsif( (spi_busy = '1') and (BUS_read_in = '1') ) then - NEXT_STATE <= RD_BSY; - BUS_busy_x <= '1'; - elsif( (spi_busy = '1') and (BUS_write_in = '1') ) then - NEXT_STATE <= WR_BSY; - BUS_busy_x <= '1'; - else - NEXT_STATE <= SLEEP; - end if; - when RD_RDY => +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + bus_busy <= '0'; + bus_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + bus_busy <= bus_busy_x; + bus_ack <= bus_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +TRANSFORM: process(CURRENT_STATE, bus_read_in, bus_write_in, spi_busy, bus_addr_in ) +begin + NEXT_STATE <= SLEEP; + bus_busy_x <= '0'; + bus_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => + if ( (spi_busy = '0') and (bus_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (spi_busy = '0') and (bus_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then + NEXT_STATE <= RD_BSY; -- CMD register is busy protected + bus_busy_x <= '1'; + elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then + NEXT_STATE <= WR_BSY; -- CMD register is busy protected + bus_busy_x <= '1'; + elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then + NEXT_STATE <= RD_RDY; -- STATUS register is not + store_rd_x <= '1'; + elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then + NEXT_STATE <= WR_RDY; -- STATUS register is not + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => + NEXT_STATE <= RD_ACK; + bus_ack_x <= '1'; + when WR_RDY => + NEXT_STATE <= WR_ACK; + bus_ack_x <= '1'; + when RD_ACK => + if( bus_read_in = '0' ) then + NEXT_STATE <= DONE; + else NEXT_STATE <= RD_ACK; - BUS_ack_x <= '1'; - when WR_RDY => + bus_ack_x <= '1'; + end if; + when WR_ACK => + if( bus_write_in = '0' ) then + NEXT_STATE <= DONE; + else NEXT_STATE <= WR_ACK; - BUS_ack_x <= '1'; - when RD_ACK => - if( BUS_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_ACK; - BUS_ack_x <= '1'; - end if; - when WR_ACK => - if( BUS_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_ACK; - BUS_ack_x <= '1'; - end if; - when RD_BSY => - if( BUS_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_BSY; - BUS_busy_x <= '1'; - end if; - when WR_BSY => - if( BUS_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_BSY; - BUS_busy_x <= '1'; - end if; - when DONE => - NEXT_STATE <= SLEEP; + bus_ack_x <= '1'; + end if; + when RD_BSY => + if( bus_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + bus_busy_x <= '1'; + end if; + when WR_BSY => + if( bus_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + bus_busy_x <= '1'; + end if; + when DONE => + NEXT_STATE <= SLEEP; - when others => - NEXT_STATE <= SLEEP; - end case; - end process TRANSFORM; + when others => + NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; --------------------------------------------------------- -- data handling -- @@ -198,30 +205,33 @@ THE_WRITE_REG_PROC: process( clk_in ) reg_ctrl_data <= (others => '0'); reg_status_data <= (others => '0'); spi_start <= '0'; - elsif( (store_wr = '1') and (BUS_addr_in(0) = '0') ) then - reg_ctrl_data <= BUS_data_in; - elsif( (store_wr = '1') and (BUS_addr_in(0) = '1') ) then - reg_status_data <= BUS_data_in; + elsif( (store_wr = '1') and (bus_addr_in(0) = '0') ) then + reg_ctrl_data <= bus_data_in; + spi_start <= spi_start_x; + elsif( (store_wr = '1') and (bus_addr_in(0) = '1') ) then + reg_status_data <= bus_data_in; + spi_start <= spi_start_x; + else + spi_start <= spi_start_x; end if; - spi_start <= spi_start_x; end if; end process THE_WRITE_REG_PROC; -spi_start_x <= '1' when ( (store_wr = '1') and (BUS_addr_in(0) = '0') ) else '0'; +spi_start_x <= '1' when ( (store_wr = '1') and (bus_addr_in(0) = '0') ) else '0'; -- register read THE_READ_REG_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if ( reset_in = '1' ) then - reg_BUS_data_out <= (others => '0'); - elsif( (store_rd = '1') and (BUS_addr_in(0) = '0') ) then - reg_BUS_data_out <= reg_ctrl_data; - elsif( (store_rd = '1') and (BUS_addr_in(0) = '1') ) then - reg_BUS_data_out(31 downto 24) <= reg_status_data(31 downto 24); - reg_BUS_data_out(23 downto 16) <= x"00"; - reg_BUS_data_out(15 downto 8) <= x"00"; - reg_BUS_data_out(7 downto 0) <= spi_bsm; + reg_bus_data_out <= (others => '0'); + elsif( (store_rd = '1') and (bus_addr_in(0) = '0') ) then + reg_bus_data_out <= reg_ctrl_data; + elsif( (store_rd = '1') and (bus_addr_in(0) = '1') ) then + reg_bus_data_out(31 downto 24) <= reg_status_data(31 downto 24); + reg_bus_data_out(23 downto 16) <= x"00"; + reg_bus_data_out(15 downto 8) <= x"00"; + reg_bus_data_out(7 downto 0) <= spi_bsm; end if; end if; end process THE_READ_REG_PROC; @@ -232,9 +242,12 @@ status_data(23) <= spi_start; status_data(22 downto 0) <= (others => '0'); -- output signals -BUS_ack_out <= BUS_ack; -BUS_busy_out <= BUS_busy; -BUS_data_out <= reg_BUS_data_out; -stat <= status_data; +bus_ack_out <= bus_ack; +bus_busy_out <= bus_busy; +bus_data_out <= reg_bus_data_out; +stat(31 downto 3) <= spi_debug(31 downto 3); --status_data; +stat(2) <= spi_start; +stat(1) <= bus_write_in; +stat(0) <= bus_read_in; end Behavioral; diff --git a/special/spi_slim.vhd b/special/spi_slim.vhd index 18f80e6..f0d2a92 100755 --- a/special/spi_slim.vhd +++ b/special/spi_slim.vhd @@ -15,107 +15,100 @@ entity spi_slim is RESET : in std_logic; -- synchronous reset -- Command interface START_IN : in std_logic; -- one start pulse - BUSY_OUT : out std_logic; -- SPI transactions are ongoing + BUSY_OUT : out std_logic; -- SPI transactions are ongoing CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte ADL_IN : in std_logic_vector(7 downto 0); -- low address byte ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte ADH_IN : in std_logic_vector(7 downto 0); -- high address byte MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD) TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next - TX_RD_OUT : out std_logic; - RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte - RX_WR_OUT : out std_logic; - TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD + TX_RD_OUT : out std_logic; + RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte + RX_WR_OUT : out std_logic; + TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD -- SPI interface - SPI_SCK_OUT : out std_logic; - SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; -- DEBUG - CLK_EN_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; architecture Behavioral of spi_slim is -- new clock divider -signal div_counter : std_logic_vector(1 downto 0); -signal div_done_x : std_logic; -signal div_done : std_logic; -- same as clk_en -signal clk_en : std_logic; -- same as div_done +signal div_counter : std_logic_vector(1 downto 0); +signal div_done_x : std_logic; +signal div_done : std_logic; -- same as clk_en +signal clk_en : std_logic; -- same as div_done -- Statemachine signals type state_t is (IDLE,CSL,TXCMD,TXADD_H,TXADD_M,TXADD_L,TXDATA,RXDATA, WAIT1,WAIT2,WAIT3,WAIT4,WAIT5,WAIT6,WAIT7,WAIT8,CSH); signal STATE, NEXT_STATE : state_t; -signal rx_ena_x : std_logic; -signal rx_ena : std_logic; -signal tx_ena_x : std_logic; -signal tx_ena : std_logic; -signal busy_x : std_logic; -signal busy : std_logic; -signal spi_cs_x : std_logic; -- SPI chip select (low active) -signal spi_cs : std_logic; -signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter) -signal spi_sck : std_logic; -signal tx_load_x : std_logic; -- load TX shift register -signal tx_load : std_logic; -signal tx_done_x : std_logic; -- one memory byte sent -signal tx_done : std_logic; -signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content -signal tx_sel : std_logic_vector(2 downto 0); -signal rx_store_x : std_logic; -- store RX shift register -signal rx_store : std_logic; -signal rx_complete : std_logic; -signal rst_addr_x : std_logic; -- reset address counter -signal rst_addr : std_logic; - -signal inc_addr_rx_x : std_logic; -signal inc_addr_rx : std_logic; -signal inc_addr_tx_x : std_logic; -signal inc_addr_tx : std_logic; -signal ce_addr_x : std_logic; -signal ce_addr : std_logic; - -signal addr_ctr : std_logic_vector(7 downto 0); -signal data_done_x : std_logic; -signal data_done : std_logic_vector(2 downto 0); - -signal last_tx_bit_x : std_logic; -signal last_tx_bit : std_logic; -signal is_data_x : std_logic; -signal is_data : std_logic; +signal rx_ena_x : std_logic; +signal rx_ena : std_logic; +signal tx_ena_x : std_logic; +signal tx_ena : std_logic; +signal busy_x : std_logic; +signal busy : std_logic; +signal spi_cs_x : std_logic; -- SPI chip select (low active) +signal spi_cs : std_logic; +signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter) +signal spi_sck : std_logic; +signal tx_load_x : std_logic; -- load TX shift register +signal tx_load : std_logic; +signal tx_done_x : std_logic; -- one memory byte sent +signal tx_done : std_logic; +signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content +signal tx_sel : std_logic_vector(2 downto 0); +signal rx_store_x : std_logic; -- store RX shift register +signal rx_store : std_logic; +signal rx_complete : std_logic; +signal rst_addr_x : std_logic; -- reset address counter +signal rst_addr : std_logic; + +signal inc_addr_rx_x : std_logic; +signal inc_addr_rx : std_logic; +signal inc_addr_tx_x : std_logic; +signal inc_addr_tx : std_logic; +signal ce_addr_x : std_logic; +signal ce_addr : std_logic; + +signal addr_ctr : std_logic_vector(7 downto 0); +signal data_done_x : std_logic; +signal data_done : std_logic_vector(2 downto 0); + +signal last_tx_bit_x : std_logic; +signal last_tx_bit : std_logic; +signal is_data_x : std_logic; +signal is_data : std_logic; -- debug signals -signal bsm_x : std_logic_vector(7 downto 0); -signal debug_x : std_logic_vector(31 downto 0); +signal bsm_x : std_logic_vector(7 downto 0); +signal debug_x : std_logic_vector(31 downto 0); -signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine -signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes -signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes -signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes -signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes -signal max_int : std_logic_vector(7 downto 0); +signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine +signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes +signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes +signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes +signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes +signal max_int : std_logic_vector(7 downto 0); -- transmitter -signal tx_sreg : std_logic_vector(7 downto 0); -signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer -signal tx_bit_cnt : std_logic_vector(3 downto 0); +signal tx_sreg : std_logic_vector(7 downto 0); +signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer +signal tx_bit_cnt : std_logic_vector(3 downto 0); -- receiver -signal rx_sreg : std_logic_vector(7 downto 0); -signal rx_ready_set : std_logic; -signal rx_bit_cnt_clr : std_logic; -signal rx_bit_cnt : std_logic_vector(3 downto 0); - -signal rd_data : std_logic; -signal rd_data1 : std_logic; -signal rd_data2 : std_logic; - - +signal rx_sreg : std_logic_vector(7 downto 0); +signal rx_bit_cnt_clr : std_logic; +signal rx_bit_cnt : std_logic_vector(3 downto 0); -- registers signal rx_data : std_logic_vector(7 downto 0); @@ -123,26 +116,26 @@ signal rx_data : std_logic_vector(7 downto 0); -- FLASH commands -- single byte commands constant NOP : std_logic_vector(7 downto 0) := x"FF"; -- no cmd to execute -constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD -constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD -constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD +constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD +constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD +constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD constant DPD : std_logic_vector(7 downto 0) := x"b9"; -- deep powerdown -- OK -- CMD -constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD +constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD -constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n) -constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n) +constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n) +constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n) -constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1) +constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1) -constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL -constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL +constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL +constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL constant SE4 : std_logic_vector(7 downto 0) := x"20"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL -constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL -constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL +constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL +constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL -constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n) -constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n) -constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n) +constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n) +constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n) +constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n) begin @@ -150,11 +143,11 @@ begin ----------------------------------------------------------- -- Debug signals ----------------------------------------------------------- -debug_x(31 downto 24) <= tx_sreg; --(others => '0'); +debug_x(31 downto 24) <= bsm_x; --(others => '0'); debug_x(23 downto 20) <= tx_bit_cnt; --(others => '0'); debug_x(19 downto 16) <= rx_bit_cnt; --(others => '0'); -debug_x(15) <= '0'; -debug_x(14) <= '0'; +debug_x(15) <= busy; +debug_x(14) <= start; debug_x(13) <= inc_addr_tx; debug_x(12) <= inc_addr_rx; debug_x(11) <= last_tx_bit; @@ -494,24 +487,24 @@ begin rx_bit_cnt_clr <= '1'; case STATE is - when IDLE => bsm_x <= x"00"; - when CSL => bsm_x <= x"09"; - when TXCMD => bsm_x <= x"01"; - when TXDATA => bsm_x <= x"02"; - when TXADD_H => bsm_x <= x"03"; - when TXADD_M => bsm_x <= x"04"; - when TXADD_L => bsm_x <= x"05"; - when RXDATA => bsm_x <= x"07"; - when WAIT1 => bsm_x <= x"10"; - when WAIT2 => bsm_x <= x"11"; - when WAIT3 => bsm_x <= x"12"; - when WAIT4 => bsm_x <= x"13"; - when WAIT8 => bsm_x <= x"17"; - when WAIT6 => bsm_x <= x"15"; - when WAIT5 => bsm_x <= x"14"; - when WAIT7 => bsm_x <= x"16"; - when CSH => bsm_x <= x"08"; - when others => bsm_x <= x"ff"; + when IDLE => bsm_x <= x"00"; + when CSL => bsm_x <= x"09"; + when TXCMD => bsm_x <= x"01"; + when TXDATA => bsm_x <= x"02"; + when TXADD_H => bsm_x <= x"03"; + when TXADD_M => bsm_x <= x"04"; + when TXADD_L => bsm_x <= x"05"; + when RXDATA => bsm_x <= x"07"; + when WAIT1 => bsm_x <= x"10"; + when WAIT2 => bsm_x <= x"11"; + when WAIT3 => bsm_x <= x"12"; + when WAIT4 => bsm_x <= x"13"; + when WAIT8 => bsm_x <= x"17"; + when WAIT6 => bsm_x <= x"15"; + when WAIT5 => bsm_x <= x"14"; + when WAIT7 => bsm_x <= x"16"; + when CSH => bsm_x <= x"08"; + when others => bsm_x <= x"ff"; end case; end process THE_STATEMACHINE_OUT; @@ -527,7 +520,7 @@ begin when "101" => tx_reg_comb <= x"ee"; -- unused when "110" => tx_reg_comb <= x"00"; -- fixed value when "111" => tx_reg_comb <= x"ff"; -- fixed value - when others => tx_reg_comb <= x"00"; + when others => tx_reg_comb <= x"00"; end case; end process THE_TXREG_MUX; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index e15e24f..8be6d01 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -75,6 +75,7 @@ entity trb_net16_endpoint_hades_full is LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0); LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; LVL1_TRG_RELEASE_IN : in std_logic := '0'; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --Data Port @@ -99,6 +100,10 @@ entity trb_net16_endpoint_hades_full is REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); --following ports only used when using internal data port REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); REGIO_READ_ENABLE_OUT : out std_logic; @@ -166,8 +171,8 @@ signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); -- for the connection to the multiplexer signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); -signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); +signal MED_IO_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0); signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); @@ -212,6 +217,25 @@ signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); signal buf_IDRAM_WR_IN : std_logic; signal reset_no_link : std_logic; + signal buf_COMMON_STAT_REG_STROBE : std_logic_vector(2**(std_COMSTATREG)-1 downto 0); + signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + signal buf_STAT_REG_STROBE : std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + signal buf_CTRL_REG_STROBE : std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + signal int_trigger_num : std_logic_vector(15 downto 0); + + signal buf_LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0); + signal buf_LVL1_TRG_RECEIVED_OUT : std_logic; + signal buf_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0); + signal buf_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0); + signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0); + signal last_LVL1_TRG_RECEIVED_OUT : std_logic; + signal LVL1_TRG_RECEIVED_OUT_rising : std_logic; + signal buf_LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); + + signal temperature : std_logic_vector(11 downto 0); + signal got_timing_trigger : std_logic; + signal trigger_number_match : std_logic; + begin reset_no_link <= MED_STAT_OP_IN(14) or RESET; @@ -247,8 +271,8 @@ begin MED_INIT_READ_IN => MED_IO_READ_IN(i*2), MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), - MED_DATA_IN => MED_IO_DATA_IN, - MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_OUT => MED_IO_READ_OUT(i), MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0), @@ -404,13 +428,13 @@ begin INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_READ_OUT => buf_to_apl_INIT_READ(i), - TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT, - TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, - TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, - TRG_CODE_OUT => LVL1_TRG_CODE_OUT, - TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, + TRG_RECEIVED_OUT => buf_LVL1_TRG_RECEIVED_OUT, + TRG_TYPE_OUT => buf_LVL1_TRG_TYPE_OUT, + TRG_NUMBER_OUT => buf_LVL1_TRG_NUMBER_OUT, + TRG_CODE_OUT => buf_LVL1_TRG_CODE_OUT, + TRG_INFORMATION_OUT => buf_LVL1_TRG_INFORMATION_OUT, TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, - TRG_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN + TRG_ERROR_PATTERN_IN => buf_LVL1_ERROR_PATTERN_IN ); end generate; @@ -517,6 +541,10 @@ begin --Custom Register in / out REGISTERS_IN => REGIO_REGISTERS_IN, REGISTERS_OUT => REGIO_REGISTERS_OUT, + COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE, + COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE, + STAT_REG_STROBE => buf_STAT_REG_STROBE, + CTRL_REG_STROBE => buf_CTRL_REG_STROBE, --following ports only used when no internal register is accessed DAT_ADDR_OUT => REGIO_ADDR_OUT, DAT_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, @@ -538,12 +566,10 @@ begin REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT; REGIO_ONEWIRE_INOUT <= '0'; REGIO_ONEWIRE_MONITOR_OUT <= '0'; - buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; + end generate; gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate - buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0); - buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <= - REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32); + REGIO_IDRAM_DATA_OUT <= (others => '0'); @@ -562,14 +588,11 @@ begin DATA_OUT => buf_IDRAM_DATA_IN, ADDR_OUT => buf_IDRAM_ADDR_IN, WRITE_OUT=> buf_IDRAM_WR_IN, - TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20), + TEMP_OUT => temperature, STAT => STAT_ONEWIRE ); end generate; gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate - buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0); - buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <= - REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32); REGIO_IDRAM_DATA_OUT <= (others => '0'); REGIO_ONEWIRE_MONITOR_OUT <= '0'; @@ -584,7 +607,7 @@ begin DATA_OUT => buf_IDRAM_DATA_IN, ADDR_OUT => buf_IDRAM_ADDR_IN, WRITE_OUT=> buf_IDRAM_WR_IN, - TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20), + TEMP_OUT => temperature, STAT => STAT_ONEWIRE ); end generate; @@ -639,8 +662,8 @@ begin RESET => reset_no_link, CLK_EN => CLK_EN, MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), - MED_DATA_IN => MED_IO_DATA_IN, - MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_OUT => MED_IO_READ_OUT(i), MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), @@ -681,16 +704,108 @@ begin CTRL => CTRL_MPLEX ); -buf_CTRL_GEN <= IOBUF_CTRL_GEN; -REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT; - -STAT_DEBUG_1 <= REGIO_REGIO_STAT; -STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16); -STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16); -STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3); -STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3); -STAT_DEBUG_2(15 downto 12) <= (others => '0'); -STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32); - -end trb_net16_endpoint_hades_full_arch; + proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num) + begin + buf_COMMON_STAT_REG_IN(3 downto 0) <= REGIO_COMMON_STAT_REG_IN(3 downto 0); + buf_COMMON_STAT_REG_IN(4) <= not trigger_number_match; + buf_COMMON_STAT_REG_IN(19 downto 5) <= REGIO_COMMON_STAT_REG_IN(19 downto 5); + if REGIO_USE_1WIRE_INTERFACE = c_NO then + buf_COMMON_STAT_REG_IN(31 downto 20) <= REGIO_COMMON_STAT_REG_IN(31 downto 20); + else + buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature; + end if; + buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num; + buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 48) <= + REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 48); + end process; + +------------------------------------------------- +-- Check LVL1 trigger number +------------------------------------------------- + proc_internal_trigger_number : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + int_trigger_num <= (others => '1'); + else + if buf_COMMON_CTRL_REG_STROBE(1) = '1' then + int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32); + elsif TRIGGER_MONITOR_IN = '1' then + int_trigger_num <= int_trigger_num + 1; + end if; + end if; + end if; + end process; + + proc_check_trigger_number : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + trigger_number_match <= '1'; + else + if LVL1_TRG_RECEIVED_OUT_rising = '1' then + if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then + trigger_number_match <= '1'; + else + trigger_number_match <= '0'; + end if; + end if; + end if; + end if; + end process; + + + proc_detect_trigger_receive : process(CLK) + begin + if rising_edge(CLK) then + last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; + LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT; + + if RESET = '1' or LVL1_TRG_RELEASE_IN = '1' then + got_timing_trigger <= '0'; + elsif TRIGGER_MONITOR_IN = '1' then + got_timing_trigger <= '1'; + end if; + end if; + end process; + + + proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger ) + begin + buf_LVL1_ERROR_PATTERN_IN <= LVL1_ERROR_PATTERN_IN; + buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match; + buf_LVL1_ERROR_PATTERN_IN(17) <= not got_timing_trigger or LVL1_ERROR_PATTERN_IN(17); + end process; + + +------------------------------------------------- +-- Connect Outputs +------------------------------------------------- + + LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; + LVL1_TRG_TYPE_OUT <= buf_LVL1_TRG_TYPE_OUT; + LVL1_TRG_NUMBER_OUT <= buf_LVL1_TRG_NUMBER_OUT; + LVL1_TRG_CODE_OUT <= buf_LVL1_TRG_CODE_OUT; + LVL1_TRG_INFORMATION_OUT <= buf_LVL1_TRG_INFORMATION_OUT; + LVL1_INT_TRG_NUMBER_OUT <= int_trigger_num; + + COMMON_STAT_REG_STROBE <= buf_COMMON_STAT_REG_STROBE; + COMMON_CTRL_REG_STROBE <= buf_COMMON_CTRL_REG_STROBE; + STAT_REG_STROBE <= buf_STAT_REG_STROBE; + CTRL_REG_STROBE <= buf_CTRL_REG_STROBE; + + + + buf_CTRL_GEN <= IOBUF_CTRL_GEN; + REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT; + + STAT_DEBUG_1 <= REGIO_REGIO_STAT; + STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16); + STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16); + STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3); + STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3); + STAT_DEBUG_2(15 downto 12) <= (others => '0'); + STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32); + +end architecture; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 7da8692..3e6838c 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -110,8 +110,8 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0); - signal m_DATA_IN : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); + signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0); signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3-1 downto 0); @@ -227,6 +227,15 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal DAT_UNKNOWN_ADDR_IN : std_logic := '0'; signal DAT_TIMEOUT_OUT : std_logic; + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve of m_DATA_IN : signal is true; + attribute syn_keep of m_DATA_IN : signal is true; + attribute syn_preserve of m_DATAREADY_IN : signal is true; + attribute syn_keep of m_DATAREADY_IN : signal is true; + + + begin @@ -281,8 +290,8 @@ begin MED_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_IN => MED_READ_IN(i), INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)), - INT_DATA_OUT => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_DATA_OUT => m_DATA_IN((i+1)*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2**(c_MUX_WIDTH-1)), + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH*2**(c_MUX_WIDTH-1)), INT_READ_IN => m_READ_OUT((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)), INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), INT_DATA_IN => m_DATA_OUT((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH), @@ -335,8 +344,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), MED_REPLY_READ_IN => m_READ_IN(i*2+1), MED_DATAREADY_IN => m_DATAREADY_IN(i), - MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), - MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + MED_DATA_IN => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_OUT => m_READ_OUT(i), MED_ERROR_IN => m_ERROR_IN((j+1)*3-1 downto j*3), @@ -397,8 +406,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), MED_REPLY_READ_IN => m_READ_IN(i*2+1), MED_DATAREADY_IN => m_DATAREADY_IN(i), - MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), - MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + MED_DATA_IN => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_OUT => m_READ_OUT(i) ); end generate; diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 63c1250..a3e5441 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -169,9 +169,9 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal reply_compare_start : std_logic; signal reg_reply_compare_start : std_logic; signal reply_compare_finished : std_logic; - signal reply_compare_result : std_logic_vector(17-1 downto 0); - signal reply_compare_flag : std_logic; - signal reply_compare_input : std_logic_vector(17-1 downto 0); + --signal reply_compare_result : std_logic_vector(17-1 downto 0); + --signal reply_compare_flag : std_logic; + --signal reply_compare_input : std_logic_vector(17-1 downto 0); signal dhdr_addr : std_logic_vector(2 downto 0); signal dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0); @@ -200,6 +200,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal timeout_counter : timeout_counter_t; signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0); signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0); + signal timeout_found : std_logic; signal saved_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0); signal last_REPLY_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*3-1 downto 0); @@ -412,7 +413,8 @@ begin or reg_current_reply_reading_HDR(i) --current_reply_reading_HDR(i) or reg_current_reply_auto_reading_DHDR(i) or saved_reading_padding(i) - or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2)); + or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2)) + or not locked; -- or (reply_fsm_state(4) and reply_reading_H0(i)); @@ -499,7 +501,7 @@ begin PROC_auto_read_DHDR : process(reg_current_reply_reading_HDR, enable_packing, - last_REPLY_PACKET_NUM_IN, saved_auto_reading_DHDR) + last_REPLY_PACKET_NUM_IN,reg_current_reply_reading_dhdr) begin reg_current_reply_auto_reading_DHDR(i) <= '0'; if reg_current_reply_reading_HDR(i) = '1' then @@ -536,10 +538,10 @@ begin begin if rising_edge(CLK) then connection_timed_out(i) <= '0'; + timeout_found <= or_all(connection_timed_out); if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' then timeout_counter(i) <= (others => '0'); elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then - timeout_counter(i) <= timeout_counter(i); connection_timed_out(i) <= '1'; else timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); @@ -554,7 +556,7 @@ begin --saving (D)HDR ---------------------------------- gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate - hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i); + hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i) and REPLY_DATAREADY_IN(i); hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH); hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0'; @@ -653,7 +655,12 @@ begin tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F2(i) and reg_current_reply_reading_TRM(i)); tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F3(i) and reg_current_reply_reading_TRM(i)); end loop; - reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1; + if j = 3 then + reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1 or timeout_found; + else + reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1; + end if; + reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2; reply_combined_trm_F3(j) <= reply_combined_trm_F3(j) or tmpF3; end if; @@ -762,7 +769,11 @@ begin begin if rising_edge(CLK) then if reply_data_counter_reset = '1' then - reply_data_counter <= (others => '0'); --length/source word is not included in word count, so this is word -1 + if enable_packing = '0' or DISABLE_PACKING = 1 then + reply_data_counter <= (others => '0'); + else + reply_data_counter <= (0 => '1', others => '0'); + end if; elsif enable_reply_data_counter = '1' then reply_data_counter <= reply_data_counter + 1; end if; @@ -904,7 +915,7 @@ begin next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints and not (reg_current_reply_reading_DHDR and reply_reading_F2); dhdr_addr <= "000"; - next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints; +-- next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints; next_reply_adder_start <= '0'; reply_arbiter_enable <= '0'; next_reply_compare_start <= '0'; @@ -916,7 +927,7 @@ begin case current_state is when IDLE => --wait for init transfer next_waiting_for_DHDR_word <= not (locking_point or not real_activepoints); - next_current_waiting_for_reply <= not (locking_point or not real_activepoints); +-- next_current_waiting_for_reply <= not (locking_point or not real_activepoints); if locked = '1' then next_state <= WAIT_FOR_REPLY; end if; @@ -937,7 +948,7 @@ begin comb_REPLY_POOL_DATA <= MY_ADDRESS_IN; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; when c_F1 => - comb_REPLY_POOL_DATA <= x"FFFF"; --sender address is not known! + comb_REPLY_POOL_DATA <= x"FFFF"; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; when c_F2 => comb_REPLY_POOL_DATAREADY <= '0'; @@ -1153,16 +1164,16 @@ begin current_state <= IDLE; REPLY_POOL_next_read <= '0'; waiting_for_DHDR_word <= (others => '1'); - current_waiting_for_reply <= (others => '1'); - got_all_reply_starts <= '0'; +-- current_waiting_for_reply <= (others => '1'); +-- got_all_reply_starts <= '0'; reply_adder_final_result <= (others => '0'); last_reply_adder_ready <= '0'; else current_state <= next_state; REPLY_POOL_next_read <= comb_REPLY_POOL_next_read; waiting_for_DHDR_word <= next_waiting_for_DHDR_word; - current_waiting_for_reply <= next_current_waiting_for_reply; - got_all_reply_starts <= not or_all(current_waiting_for_reply); +-- current_waiting_for_reply <= next_current_waiting_for_reply; +-- got_all_reply_starts <= not or_all(current_waiting_for_reply); not_reading_HDR <= not or_all(current_reply_reading_HDR); number_of_replies <= to_unsigned(count_ones(expected_replies),5); expected_replies <= real_activepoints and not locking_point; @@ -1236,7 +1247,7 @@ begin STAT_DEBUG(25) <= reg_current_reply_reading_DHDR(1); STAT_DEBUG(26) <= reg_current_reply_reading_HDR(1); STAT_DEBUG(27) <= got_all_DHDR; - STAT_DEBUG(28) <= got_all_reply_starts; + STAT_DEBUG(28) <= '0'; --got_all_reply_starts; STAT_DEBUG(31 downto 29) <= last_REPLY_PACKET_NUM_IN(5 downto 3); --STAT(15 downto 8) <= data_counter; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 223b740..945f51b 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -135,6 +135,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal timeout_counter : timeout_counter_t; signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0); signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0); + signal timeout_found : std_logic; begin @@ -433,7 +434,11 @@ begin tmpF3 := tmpF3 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF3(i)); end loop; REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1; - REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2; + if j = 6 then + reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2 or timeout_found; + else + reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2; + end if; REPLY_combined_trm_F3(j) <= REPLY_combined_trm_F3(j) or tmpF3; end if; end if; @@ -479,10 +484,10 @@ begin begin if rising_edge(CLK) then connection_timed_out(i) <= '0'; + timeout_found <= or_all(connection_timed_out); if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' then timeout_counter(i) <= (others => '0'); elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then - timeout_counter(i) <= timeout_counter(i); connection_timed_out(i) <= '1'; else timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index adbd30d..35e4263 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -60,7 +60,6 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal fifo_write, fifo_read : std_logic; signal fifo_full, fifo_empty : std_logic; - signal current_packet_type : std_logic_vector(3 downto 0); signal saved_packet_type : std_logic_vector(3 downto 0); signal current_fifo_packet_type : std_logic_vector(3 downto 0); signal saved_fifo_packet_type : std_logic_vector(3 downto 0); @@ -108,6 +107,8 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal reply_word_waiting : std_logic; signal init_word_waiting : std_logic; + signal is_h0 : std_logic; + attribute syn_preserve : boolean; attribute syn_keep : boolean; attribute syn_sharing : string; @@ -121,10 +122,14 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is attribute syn_keep of reg_med_dataready_in : signal is true; attribute syn_keep of reg_med_packet_num_in : signal is true; attribute syn_keep of saved_packet_type : signal is true; + attribute syn_keep of is_h0 : signal is true; attribute syn_preserve of reg_med_data_in : signal is true; attribute syn_preserve of reg_med_dataready_in : signal is true; attribute syn_preserve of reg_med_packet_num_in : signal is true; attribute syn_preserve of saved_packet_type : signal is true; + attribute syn_preserve of is_h0 : signal is true; + + begin @@ -135,12 +140,15 @@ counter_match <= '1'; --check incoming data for ACK & fifo status check ------------------------ + is_h0 <= MED_PACKET_NUM_IN(2) and not MED_PACKET_NUM_IN(1) and not MED_PACKET_NUM_IN(0); + --'1' when MED_PACKET_NUM_IN = c_H0 else '0'; + proc_store_input_packet_type : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then saved_packet_type <= '1' & TYPE_ILLEGAL; - elsif MED_PACKET_NUM_IN = c_H0 then + elsif is_h0 = '1' then saved_packet_type <= MED_DATA_IN(3 downto 0); end if; end if; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index ba7e64a..eecf12a 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -5,6 +5,7 @@ USE IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_io_multiplexer is @@ -26,14 +27,14 @@ entity trb_net16_io_multiplexer is MED_READ_IN : in STD_LOGIC; -- Internal direction port - INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0); INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); -- Status and control port @@ -47,48 +48,6 @@ end trb_net16_io_multiplexer; architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is - - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; - COMB_next_READ_OUT: out STD_LOGIC; - COMB_READ_IN : in STD_LOGIC; - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - - component trb_net_priority_arbiter is - generic ( - WIDTH : integer := 8 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in std_logic_vector (WIDTH-1 downto 0); - RESULT_OUT: out std_logic_vector (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL : in std_logic_vector (9 downto 0) - ); - end component; - signal current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH-1)-1 downto 0); signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); signal buf_INT_DATAREADY_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); @@ -102,8 +61,8 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal current_mux_packet_number : std_logic_vector (c_NUM_WIDTH-1 downto 0) := c_H0; signal last_mux_enable : std_logic; signal arbiter_CLK_EN : std_logic; - signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); signal sbuf_status : std_logic; -- Placer Directives @@ -111,6 +70,19 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- for whole architecture attribute HGROUP of trb_net16_io_multiplexer_arch : architecture is "MUX_group"; + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve of buf_INT_DATA_OUT : signal is true; + attribute syn_keep of buf_INT_DATA_OUT : signal is true; + attribute syn_preserve of buf_INT_DATAREADY_OUT : signal is true; + attribute syn_keep of buf_INT_DATAREADY_OUT : signal is true; + attribute syn_preserve of current_INT_READ_OUT : signal is true; + attribute syn_keep of current_INT_READ_OUT : signal is true; + attribute syn_preserve of final_INT_READ_OUT : signal is true; + attribute syn_keep of final_INT_READ_OUT : signal is true; + + attribute syn_hier : string; + attribute syn_hier of trb_net16_io_multiplexer_arch : architecture is "firm"; begin ------------------------------------------------------------------------------- -- DEMUX @@ -120,15 +92,11 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= (others => '0'); - buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= (others => '0'); - else - buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= MED_DATA_IN; - buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= MED_PACKET_NUM_IN; - end if; + buf_INT_DATA_OUT <= MED_DATA_IN & MED_DATA_IN & MED_DATA_IN & MED_DATA_IN; + buf_INT_PACKET_NUM_OUT <= MED_PACKET_NUM_IN & MED_PACKET_NUM_IN & MED_PACKET_NUM_IN & MED_PACKET_NUM_IN; end if; end process; + G2: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate process(CLK) begin @@ -174,14 +142,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- define next DRx -- the output of the pattern generator is only valid for packet number 00! --- DEFDR: trb_net_pattern_gen --- generic map ( --- WIDTH => c_MUX_WIDTH-1 --- ) --- port map ( --- INPUT_IN => MED_DATA_IN(4+c_MUX_WIDTH-2 downto 4), --- RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case --- ); + gen_no_demux : if c_MUX_WIDTH = 1 generate next_demux_dr_tmp <= (others => '1'); end generate; @@ -242,17 +203,6 @@ ARBITER: trb_net_priority_arbiter end if; end process; --- process(CLK) --- begin --- if rising_edge(CLK) then --- if RESET = '1' then --- final_INT_READ_OUT <= (others => '0'); --- elsif endpoint_locked = '0' then --- final_INT_READ_OUT <= tmp_INT_READ_OUT; --- end if; --- end if; --- end process; - process(CLK) begin if rising_edge(CLK) then @@ -266,13 +216,13 @@ ARBITER: trb_net_priority_arbiter process(final_INT_READ_OUT, last_mux_enable) begin - current_INT_READ_OUT <= final_INT_READ_OUT; if last_mux_enable = '0' then current_INT_READ_OUT <= (others => '0'); + else + current_INT_READ_OUT <= final_INT_READ_OUT; end if; end process; --- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0' --- else final_INT_READ_OUT; + STAT(7 downto 0) <= INT_DATAREADY_IN(7 downto 0); STAT(15 downto 8) <= current_INT_READ_OUT(7 downto 0); diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 81760a3..263831c 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -82,7 +82,8 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is -- attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group"; - + attribute syn_hier : string; + attribute syn_hier of trb_net16_iobuf_arch : architecture is "firm"; -- internal signals for the INITIBUF signal IBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed! diff --git a/trb_net16_med_16_CC.vhd b/trb_net16_med_16_CC.vhd index 1e75707..da48b81 100644 --- a/trb_net16_med_16_CC.vhd +++ b/trb_net16_med_16_CC.vhd @@ -36,6 +36,14 @@ entity trb_net16_med_16_CC is CTRL_OP : in std_logic_vector(15 downto 0); STAT_DEBUG : out std_logic_vector(63 downto 0) ); + attribute syn_useioff : boolean; + attribute syn_useioff of DATA_OUT : signal is true; + attribute syn_useioff of DATA_VALID_OUT : signal is true; + attribute syn_useioff of DATA_CTRL_OUT : signal is true; + attribute syn_useioff of DATA_IN : signal is true; + attribute syn_useioff of DATA_VALID_IN : signal is true; + attribute syn_useioff of DATA_CTRL_IN : signal is true; + end entity; architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is @@ -54,6 +62,9 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is ); end component; + signal buf_DATA_IN : std_logic_vector(15 downto 0); + signal buf_DATA_VALID_IN : std_logic; + signal buf_DATA_CTRL_IN : std_logic; signal reg_DATA_IN : std_logic_vector(15 downto 0); signal reg_DATA_VALID_IN : std_logic; @@ -90,11 +101,22 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is signal state_bits : std_logic_vector(2 downto 0); signal make_reset : std_logic; + begin ----------------------- --Receiver ----------------------- + + PROC_RX_INPUT : process(CLK) + begin + if rising_edge(CLK) then + buf_DATA_IN <= DATA_IN; + buf_DATA_VALID_IN <= DATA_VALID_IN; + buf_DATA_CTRL_IN <= DATA_CTRL_IN; + end if; + end process; + THE_RX_SIGNAL_SYNC: signal_sync generic map( DEPTH => 2, @@ -102,9 +124,9 @@ begin ) port map( RESET => RESET, - D_IN(15 downto 0) => DATA_IN, - D_IN(16) => DATA_VALID_IN, - D_IN(17) => DATA_CTRL_IN, + D_IN(15 downto 0) => buf_DATA_IN, + D_IN(16) => buf_DATA_VALID_IN, + D_IN(17) => buf_DATA_CTRL_IN, CLK0 => CLK, CLK1 => CLK, D_OUT(15 downto 0) => reg_DATA_IN, diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index d19dc09..7bd1190 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -45,6 +45,8 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is attribute HGROUP : string; -- for whole architecture attribute HGROUP of trb_net16_obuf_arch : architecture is "OBUF_group"; + attribute syn_hier : string; + attribute syn_hier of trb_net16_obuf_arch : architecture is "flatten, firm"; component trb_net16_sbuf is generic ( diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 47ce6fd..aee03d5 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -4,6 +4,7 @@ USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; @@ -73,6 +74,11 @@ entity trb_net16_regIO is --Custom Register in / out REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + --strobes for r/w operations on regio registers + COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); --Internal Data Port DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); DAT_READ_ENABLE_OUT : out std_logic; @@ -99,64 +105,6 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is attribute HGROUP of trb_net16_regIO_arch : architecture is "RegIO_group"; - component trb_net_pattern_gen is - generic ( - WIDTH : integer := 6 - ); - port( - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) - ); - end component; - - component trb_net16_addresses is - generic( - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" - ); - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - RAM_DATA_IN : in std_logic_vector(15 downto 0); - RAM_DATA_OUT : out std_logic_vector(15 downto 0); - RAM_ADDR_IN : in std_logic_vector(2 downto 0); - RAM_WR_IN : in std_logic; - API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - ADDRESS_REJECTED : out std_logic; - DONT_UNDERSTAND_OUT : out std_logic; - API_SEND_OUT : out std_logic; - ADDRESS_OUT : out std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(15 downto 0) - ); - end component; - - component rom_16x8 is - generic( - INIT0 : std_logic_vector(15 downto 0) := x"0000"; - INIT1 : std_logic_vector(15 downto 0) := x"0000"; - INIT2 : std_logic_vector(15 downto 0) := x"0000"; - INIT3 : std_logic_vector(15 downto 0) := x"0000"; - INIT4 : std_logic_vector(15 downto 0) := x"0000"; - INIT5 : std_logic_vector(15 downto 0) := x"0000"; - INIT6 : std_logic_vector(15 downto 0) := x"0000"; - INIT7 : std_logic_vector(15 downto 0) := x"0000" - ); - port( - CLK : in std_logic; - a : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(15 downto 0) - ); - end component; type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE, MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV, @@ -235,7 +183,12 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is signal local_time_i : std_logic_vector(7 downto 0) := (others => '0'); signal us_tick_i : std_logic := '0'; signal global_time_write, next_global_time_write : std_logic; - + signal next_COMMON_STAT_REG_STROBE : std_logic_vector(2**(std_COMSTATREG)-1 downto 0); + signal next_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + signal next_next_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + signal next_STAT_REG_STROBE : std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); + signal next_CTRL_REG_STROBE : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); + signal next_next_CTRL_REG_STROBE : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); begin @@ -337,6 +290,10 @@ begin next_API_READ_OUT <= '1'; next_dat_data_counter <= dat_data_counter; next_global_time_write <= '0'; + next_COMMON_STAT_REG_STROBE <= (others => '0'); + next_next_COMMON_CTRL_REG_STROBE <= (others => '0'); + next_STAT_REG_STROBE <= (others => '0'); + next_next_CTRL_REG_STROBE <= (others => '0'); case current_state is when IDLE => @@ -443,8 +400,10 @@ begin case address(7 downto 4) is when x"C" | x"D" | x"E" | x"F" => next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0); + next_next_CTRL_REG_STROBE(regnum_CTRL) <= API_READ_IN; when x"2" | x"3" => next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0); + next_next_COMMON_CTRL_REG_STROBE(regnum_cCTRL) <= API_READ_IN; when x"5" => if address(3 downto 0) = x"0" then next_global_time_write <= '1'; @@ -508,6 +467,7 @@ begin case address(7 downto 4) is when x"0" | x"1" => next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+15 downto regnum_cSTAT*c_REGIO_REG_WIDTH); + next_COMMON_STAT_REG_STROBE(regnum_cSTAT) <= API_READ_IN; when x"2" | x"3" => next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+15 downto regnum_cCTRL*c_REGIO_REG_WIDTH); when x"4" => @@ -521,6 +481,7 @@ begin end case; when x"8" | x"9" | x"A" | x"B" => next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+15 downto regnum_STAT*c_REGIO_REG_WIDTH); + next_STAT_REG_STROBE(regnum_STAT) <= API_READ_IN; when x"C" | x"D" | x"E" | x"F" => next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+15 downto regnum_CTRL*c_REGIO_REG_WIDTH); when others => @@ -1006,6 +967,21 @@ begin REGISTERS_OUT <= buf_REGISTERS_OUT; COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT; + + PROC_STROBES : process(CLK) + begin + if rising_edge(CLK) then + COMMON_STAT_REG_STROBE <= next_COMMON_STAT_REG_STROBE; + COMMON_CTRL_REG_STROBE <= next_COMMON_CTRL_REG_STROBE; + STAT_REG_STROBE <= next_STAT_REG_STROBE; + CTRL_REG_STROBE <= next_CTRL_REG_STROBE; + next_COMMON_CTRL_REG_STROBE <= next_next_COMMON_CTRL_REG_STROBE; + next_CTRL_REG_STROBE <= next_next_CTRL_REG_STROBE; + end if; + end process; + + + buf_DAT_ADDR_OUT <= address; buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low; diff --git a/trb_net16_term_buf.vhd b/trb_net16_term_buf.vhd index 106e851..cd66a74 100644 --- a/trb_net16_term_buf.vhd +++ b/trb_net16_term_buf.vhd @@ -38,7 +38,7 @@ architecture trb_net16_term_buf_arch of trb_net16_term_buf is -- Placer Directives attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_term_buf_arch : architecture is "IOBUF_group"; + attribute HGROUP of trb_net16_term_buf_arch : architecture is "TRMBUF_group"; signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0); signal saved_packet_type : std_logic_vector(3 downto 0); diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 8261b9e..6cf00ee 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -51,6 +51,42 @@ package trb_net_components is + component trb_net16_addresses is + generic( + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_ADDR_IN : in std_logic_vector(2 downto 0); + RAM_WR_IN : in std_logic; + API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + ADDRESS_REJECTED : out std_logic; + DONT_UNDERSTAND_OUT : out std_logic; + API_SEND_OUT : out std_logic; + ADDRESS_OUT : out std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(15 downto 0) + ); + end component; + + + + + + component trb_net16_api_base is generic ( API_TYPE : integer range 0 to 1 := c_API_PASSIVE; @@ -307,7 +343,7 @@ package trb_net_components is LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0); LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; LVL1_TRG_RELEASE_IN : in std_logic := '0'; - + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --Data Port IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); @@ -331,6 +367,11 @@ package trb_net_components is REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + + COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); --following ports only used when using internal data port REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); REGIO_READ_ENABLE_OUT : out std_logic; @@ -458,6 +499,9 @@ package trb_net_components is + + + component fifo_dualclock_width_16_reg is port ( Data: in std_logic_vector(17 downto 0); @@ -473,6 +517,11 @@ package trb_net_components is end component; + + + + + component trb_net16_ibuf is generic ( DEPTH : integer range 0 to 7 := c_FIFO_BRAM; @@ -612,8 +661,8 @@ package trb_net_components is MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); MED_READ_IN : in STD_LOGIC; -- Internal direction port - INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); @@ -1143,6 +1192,39 @@ package trb_net_components is + component trb_net16_med_16_IC is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_CLK_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + DATA_CLK_IN : in std_logic; + + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) + ); + end component; + + + component trb_net16_med_tlk is port ( @@ -1322,6 +1404,20 @@ package trb_net_components is + component trb_net_pattern_gen is + generic ( + WIDTH : integer := 6 + ); + port( + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) + ); + end component; + + + + + component trb_net_priority_arbiter is generic ( @@ -1446,6 +1542,10 @@ package trb_net_components is --Custom Register in / out REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); --Internal Data Port DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); DAT_READ_ENABLE_OUT : out std_logic; @@ -1508,6 +1608,27 @@ package trb_net_components is + component rom_16x8 is + generic( + INIT0 : std_logic_vector(15 downto 0) := x"0000"; + INIT1 : std_logic_vector(15 downto 0) := x"0000"; + INIT2 : std_logic_vector(15 downto 0) := x"0000"; + INIT3 : std_logic_vector(15 downto 0) := x"0000"; + INIT4 : std_logic_vector(15 downto 0) := x"0000"; + INIT5 : std_logic_vector(15 downto 0) := x"0000"; + INIT6 : std_logic_vector(15 downto 0) := x"0000"; + INIT7 : std_logic_vector(15 downto 0) := x"0000" + ); + port( + CLK : in std_logic; + a : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(15 downto 0) + ); + end component; + + + + component trb_net16_sbuf is generic ( diff --git a/trb_net_onewire_listener.vhd b/trb_net_onewire_listener.vhd index fc0958f..a538274 100644 --- a/trb_net_onewire_listener.vhd +++ b/trb_net_onewire_listener.vhd @@ -55,6 +55,13 @@ architecture arch of trb_net_onewire_listener is signal state : state_t; signal state_bits : std_logic_vector(3 downto 0); + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of arch : architecture is "ONEWIRE_group"; + + begin diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd index 8daf501..62d90de 100644 --- a/trb_net_sbuf.vhd +++ b/trb_net_sbuf.vhd @@ -66,6 +66,16 @@ architecture trb_net_sbuf_arch of trb_net_sbuf is signal combined_COMB_DATAREADY_IN: std_logic; signal use_current_b1_buffer: std_logic; + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true; + attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true; + attribute syn_preserve of current_next_READ_OUT : signal is true; + attribute syn_keep of current_next_READ_OUT : signal is true; + attribute syn_hier : string; + attribute syn_hier of trb_net_sbuf_arch : architecture is "flatten, firm"; + + begin SYN_DATA_OUT <= current_b2_buffer; @@ -75,9 +85,8 @@ begin combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN); - GEN1: if VERSION = 0 generate - MUX: process (use_current_b1_buffer, - COMB_DATA_IN, current_b1_buffer) + MUX: process (use_current_b1_buffer, + COMB_DATA_IN, current_b1_buffer) begin -- simple MUX if use_current_b1_buffer = '1' then next_b2_buffer <= current_b1_buffer; @@ -85,11 +94,7 @@ begin next_b2_buffer <= COMB_DATA_IN; end if; end process; - end generate; - GEN2: if VERSION = 1 generate - next_b2_buffer <= COMB_DATA_IN; - end generate; COMB: process (current_buffer_state, SYN_READ_IN, COMB_DATA_IN, current_SYN_DATAREADY_OUT, current_got_overflow, @@ -97,10 +102,8 @@ begin begin -- process COMB next_buffer_state <= current_buffer_state; next_next_READ_OUT <= '1'; - if VERSION = 0 then - next_b1_buffer <= COMB_DATA_IN; - move_b1_buffer <= '0'; - end if; + next_b1_buffer <= COMB_DATA_IN; + move_b1_buffer <= '0'; use_current_b1_buffer <= '0'; --by default COMB_DATA_IN; move_b2_buffer <= '0'; @@ -112,9 +115,6 @@ begin if combined_COMB_DATAREADY_IN = '1' then -- COMB logic is writing into the sbuf next_buffer_state <= BUFFER_B2_FULL; - if VERSION = 1 then - next_next_READ_OUT <= '0'; - end if; move_b2_buffer <= '1'; next_SYN_DATAREADY_OUT <= '1'; end if; @@ -123,9 +123,6 @@ begin if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then -- COMB logic is writing into the sbuf -- at the same time syn port is reading - if VERSION = 1 then - next_next_READ_OUT <= '0'; - end if; move_b2_buffer <= '1'; next_SYN_DATAREADY_OUT <= '1'; elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then @@ -166,20 +163,6 @@ begin end if; end if; - - -- for version1 it is more complicated: we have to gate - -- the signal: when somebody is writing, we have to stop - -- all the activity. I do this in the following way: If I - -- promised to take the data, I stop the data taking in the - -- following cycle. This reduces the bandwidth by a factor of - -- 2 - - if VERSION = 1 then - if current_next_READ_OUT = '1' then - next_next_READ_OUT <= '0'; - end if; - end if; - end process COMB; -- the next lines are an emergency stop @@ -193,14 +176,10 @@ begin EM_STOP : process(current_next_READ_OUT, SYN_READ_IN, current_SYN_DATAREADY_OUT, current_buffer_state) begin - if VERSION = 0 then - if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B2_FULL then - COMB_next_READ_OUT <= '0'; - elsif SYN_READ_IN = '1' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B1_FULL then - COMB_next_READ_OUT <= '1'; - else - COMB_next_READ_OUT <= current_next_READ_OUT; - end if; + if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B2_FULL then + COMB_next_READ_OUT <= '0'; + elsif SYN_READ_IN = '1' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B1_FULL then + COMB_next_READ_OUT <= '1'; else COMB_next_READ_OUT <= current_next_READ_OUT; end if; @@ -223,26 +202,20 @@ begin end if; end process; - GEN6: if VERSION = 0 generate - REG2 : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_b1_buffer <= (others => '0'); - elsif move_b1_buffer = '1' then - current_b1_buffer <= next_b1_buffer; - end if; + REG2 : process(CLK) + begin + if rising_edge(CLK) then + if move_b1_buffer = '1' then + current_b1_buffer <= next_b1_buffer; end if; - end process; - end generate; + end if; + end process; REG3 : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - current_b2_buffer <= (others => '0'); - elsif move_b2_buffer = '1' then + if move_b2_buffer = '1' then current_b2_buffer <= next_b2_buffer; end if; end if; -- 2.43.0