From f26c7f4febcf8dc9fb483c34e1174aacdffd121e Mon Sep 17 00:00:00 2001 From: hadaq Date: Wed, 16 Nov 2011 10:40:46 +0000 Subject: [PATCH] *** empty log message *** --- tdc_test/nodes_lxhadeb05.txt | 7 +++++++ tdc_test/trb3_periph.vhd | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-) create mode 100644 tdc_test/nodes_lxhadeb05.txt diff --git a/tdc_test/nodes_lxhadeb05.txt b/tdc_test/nodes_lxhadeb05.txt new file mode 100644 index 0000000..62a4fb3 --- /dev/null +++ b/tdc_test/nodes_lxhadeb05.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[lxhadeb05] +SYSTEM = linux +CORENUM = 24 +ENV = /home/cugur/hades27/bin/diamond_setup.sh +WORKDIR = /home/cugur/hades27/Projects/TDC_on_TRB3/trb3/tdc_test/diamond/trb3_periph \ No newline at end of file diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd index 70d14d3..82325d8 100644 --- a/tdc_test/trb3_periph.vhd +++ b/tdc_test/trb3_periph.vhd @@ -590,7 +590,7 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 8, -- Number of TDC channels + CHANNEL_NUMBER => 16, -- Number of TDC channels TRG_WIN_PRE => x"0023", -- Pre-Trigger window width TRG_WIN_POST => x"0023") -- Post-Trigger window width port map ( @@ -598,7 +598,7 @@ begin CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => DQLL(6 downto 0), -- Channel start signals + HIT_IN => DQLL(14 downto 0), -- Channel start signals TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal -- from trbnet VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger -- 2.43.0