From f2e139b6d4a4cebdb27ed85c18d3d966cf04739f Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 4 Dec 2014 10:08:12 +0100 Subject: [PATCH] trigger window bug fix and constraints update for v2.0.0 --- tdc_releases/ReleaseNotes.txt | 4 +- tdc_releases/tdc_v2.0/Readout.vhd | 54 +------- tdc_releases/tdc_v2.0/TriggerHandler.vhd | 8 +- tdc_releases/tdc_v2.0/tdc_constraints_64.lpf | 130 +++++++++---------- tdc_releases/tdc_v_stretcher/Stretcher.vhd | 4 +- 5 files changed, 74 insertions(+), 126 deletions(-) diff --git a/tdc_releases/ReleaseNotes.txt b/tdc_releases/ReleaseNotes.txt index d155d2e..77cc39e 100644 --- a/tdc_releases/ReleaseNotes.txt +++ b/tdc_releases/ReleaseNotes.txt @@ -3,9 +3,7 @@ Version Release Date Release Notes tdc_v2.0 01.12.2014 Double edge detection in a single channel is implemented. -tdc_v1.7.3 15.08.2014 Dead time in the encoder is increased 5ns for - easier placement. - Hit scaler register size is increased to 31 bits. +tdc_v1.7.3 15.08.2014 Hit scaler register size is increased to 31 bits. tdc_v1.7.1 29.07.2014 Feature Bit support. Tidy up the entities. diff --git a/tdc_releases/tdc_v2.0/Readout.vhd b/tdc_releases/tdc_v2.0/Readout.vhd index 7995f3f..e2996a2 100644 --- a/tdc_releases/tdc_v2.0/Readout.vhd +++ b/tdc_releases/tdc_v2.0/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2014-10-22 +-- Last update: 2014-12-02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -93,30 +93,6 @@ architecture behavioral of Readout is signal trig_win_post : unsigned(10 downto 0); signal trig_win_en : std_logic; signal trig_time_i : std_logic_vector(38 downto 0); - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - signal coarse_cntr_2reg : std_logic_vector(10 downto 0); - signal coarse_cntr_3reg : std_logic_vector(10 downto 0); - signal coarse_cntr_4reg : std_logic_vector(10 downto 0); - signal coarse_cntr_5reg : std_logic_vector(10 downto 0); - signal coarse_cntr_6reg : std_logic_vector(10 downto 0); - signal coarse_cntr_7reg : std_logic_vector(10 downto 0); - signal coarse_cntr_8reg : std_logic_vector(10 downto 0); - signal coarse_cntr_9reg : std_logic_vector(10 downto 0); - signal coarse_cntr_10reg : std_logic_vector(10 downto 0); - signal coarse_cntr_11reg : std_logic_vector(10 downto 0); - signal coarse_cntr_12reg : std_logic_vector(10 downto 0); - signal epoch_cntr_reg : std_logic_vector(27 downto 0); - signal epoch_cntr_2reg : std_logic_vector(27 downto 0); - signal epoch_cntr_3reg : std_logic_vector(27 downto 0); - signal epoch_cntr_4reg : std_logic_vector(27 downto 0); - signal epoch_cntr_5reg : std_logic_vector(27 downto 0); - signal epoch_cntr_6reg : std_logic_vector(27 downto 0); - signal epoch_cntr_7reg : std_logic_vector(27 downto 0); - signal epoch_cntr_8reg : std_logic_vector(27 downto 0); - signal epoch_cntr_9reg : std_logic_vector(27 downto 0); - signal epoch_cntr_10reg : std_logic_vector(27 downto 0); - signal epoch_cntr_11reg : std_logic_vector(27 downto 0); - signal epoch_cntr_12reg : std_logic_vector(27 downto 0); signal TW_pre : std_logic_vector(38 downto 0); signal TW_post : std_logic_vector(38 downto 0); signal trig_win_l : std_logic; @@ -272,36 +248,10 @@ begin -- behavioral if RESET_200 = '1' then trig_time_i <= (others => '0'); elsif TRIGGER_TDC_IN = '1' then - trig_time_i <= TRIG_TIME_IN; --epoch_cntr_12reg & coarse_cntr_12reg; + trig_time_i <= TRIG_TIME_IN; end if; end if; end process DefineTriggerTime; - coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); - coarse_cntr_2reg <= coarse_cntr_reg when rising_edge(CLK_200); - coarse_cntr_3reg <= coarse_cntr_2reg when rising_edge(CLK_200); - coarse_cntr_4reg <= coarse_cntr_3reg when rising_edge(CLK_200); - coarse_cntr_5reg <= coarse_cntr_4reg when rising_edge(CLK_200); - coarse_cntr_6reg <= coarse_cntr_5reg when rising_edge(CLK_200); - coarse_cntr_7reg <= coarse_cntr_6reg when rising_edge(CLK_200); - coarse_cntr_8reg <= coarse_cntr_7reg when rising_edge(CLK_200); - coarse_cntr_9reg <= coarse_cntr_8reg when rising_edge(CLK_200); - coarse_cntr_10reg <= coarse_cntr_9reg when rising_edge(CLK_200); - coarse_cntr_11reg <= coarse_cntr_10reg when rising_edge(CLK_200); - coarse_cntr_12reg <= coarse_cntr_11reg when rising_edge(CLK_200); - - epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); - epoch_cntr_2reg <= epoch_cntr_reg when rising_edge(CLK_200); - epoch_cntr_3reg <= epoch_cntr_2reg when rising_edge(CLK_200); - epoch_cntr_4reg <= epoch_cntr_3reg when rising_edge(CLK_200); - epoch_cntr_5reg <= epoch_cntr_4reg when rising_edge(CLK_200); - epoch_cntr_6reg <= epoch_cntr_5reg when rising_edge(CLK_200); - epoch_cntr_7reg <= epoch_cntr_6reg when rising_edge(CLK_200); - epoch_cntr_8reg <= epoch_cntr_7reg when rising_edge(CLK_200); - epoch_cntr_9reg <= epoch_cntr_8reg when rising_edge(CLK_200); - epoch_cntr_10reg <= epoch_cntr_9reg when rising_edge(CLK_200); - epoch_cntr_11reg <= epoch_cntr_10reg when rising_edge(CLK_200); - epoch_cntr_12reg <= epoch_cntr_11reg when rising_edge(CLK_200); - -- Channel Hit Time Determination ChannelHitTime : process (CLK_100) diff --git a/tdc_releases/tdc_v2.0/TriggerHandler.vhd b/tdc_releases/tdc_v2.0/TriggerHandler.vhd index 4e1b08d..9de1188 100644 --- a/tdc_releases/tdc_v2.0/TriggerHandler.vhd +++ b/tdc_releases/tdc_v2.0/TriggerHandler.vhd @@ -4,7 +4,7 @@ -- File : TriggerHandler.vhd -- Author : Cahit Ugur c.ugur@gsi.de -- Created : 2013-03-13 --- Last update: 2014-05-06 +-- Last update: 2014-12-02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -107,8 +107,8 @@ begin -- architecture behavioral PULSE_B_OUT => trigger_pulse_rdo(i)); end generate GEN_TDC; - TRIGGER_RDO_OUT <= trigger_pulse_rdo; - TRIGGER_TDC_OUT <= trigger_pulse_tdc; + TRIGGER_RDO_OUT <= trigger_pulse_rdo when rising_edge(CLK_RDO); + TRIGGER_TDC_OUT <= trigger_pulse_tdc when rising_edge(CLK_TDC); -- A Moore machine's outputs are dependent only on the current state. -- The output is written only when the state changes. (State @@ -185,7 +185,7 @@ begin -- architecture behavioral trigger_time_i <= EPOCH_COUNTER_IN & COARSE_COUNTER_IN; end if; if trigger_pulse_tdc(0) = '1' then - TRIGGER_TIME_OUT <= trigger_time_i; + TRIGGER_TIME_OUT <= std_logic_vector(unsigned(trigger_time_i) - to_unsigned(2,39)); end if; end if; end process TriggerTime; diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf index aaf69d6..d633d7c 100644 --- a/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf +++ b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf @@ -727,192 +727,192 @@ LOCATE UGROUP "ff_en_64" SITE "R84C83D" ; ############################################################################## UGROUP "EF_LT2" BBOX 10 54 BLKNAME THE_TDC/ReferenceChannel/Channel200 - BLKNAME THE_TDC/ReferenceChannel/Buffer_64.The_Buffer + BLKNAME THE_TDC/ReferenceChannel/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT2" SITE "R24C2D" ; UGROUP "EF_LC1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.2.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.2.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.3.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.3.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.4.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.4.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.5.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.5.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LC1" SITE "R35C2D" ; UGROUP "EF_LC3" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.6.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.6.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.7.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.7.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.8.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.8.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.9.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.9.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LC3" SITE "R71C2D" ; UGROUP "EF_LB1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.10.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.10.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.11.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.11.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.12.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.12.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LB1" SITE "R89C2D" ; UGROUP "EF_LT1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.13.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.13.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.14.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.14.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.15.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.15.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.16.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.16.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT1" SITE "R8C2D" ; UGROUP "EF_CB1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.17.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.17.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.18.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.18.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.19.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.19.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.20.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.20.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_CB1" SITE "R89C56D" ; UGROUP "EF_CB2" BBOX 10 54 BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.21.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.21.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.22.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.22.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_CB2" SITE "R105C56D" ; UGROUP "EF_LC2" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.23.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.23.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.24.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.24.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.25.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.25.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.26.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.26.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LC2" SITE "R53C2D" ; UGROUP "EF_LB2" BBOX 10 54 BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.27.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.27.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.28.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.28.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LB2" SITE "R105C2D" ; UGROUP "EF_CT1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.29.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.29.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.30.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.30.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.31.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.31.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.32.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.32.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_CT1" SITE "R8C56D" ; UGROUP "EF_CT2" BBOX 10 54 BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.33.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.33.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.34.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.34.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_CT2" SITE "R24C56D" ; UGROUP "EF_CC1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.35.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.35.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.36.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.36.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.37.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.37.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.38.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.38.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_CC1" SITE "R35C56D" ; UGROUP "EF_RB1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.39.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.39.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.40.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.40.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.41.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.41.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.42.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.42.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RB1" SITE "R89C128D" ; UGROUP "EF_RC3" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.43.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.43.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.44.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.44.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.45.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.45.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.46.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.46.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RC3" SITE "R71C128D" ; UGROUP "EF_RB2" BBOX 10 54 BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.47.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.47.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.48.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.48.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RB2" SITE "R105C128D" ; UGROUP "EF_RT1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.49.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.49.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.50.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.50.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.51.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.51.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.52.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.52.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RT1" SITE "R8C128D" ; UGROUP "EF_RT2" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.53.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.53.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.54.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.54.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RT2" SITE "R24C128D" ; UGROUP "EF_RC1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.55.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.55.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.56.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.56.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.57.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.57.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.58.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.58.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RC1" SITE "R35C128D" ; UGROUP "EF_RC2" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.59.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.59.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.60.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.60.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.61.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.61.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.62.Channels/Buffer_64.The_Buffer + BLKNAME THE_TDC/GEN_Channels.62.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_RC2" SITE "R53C128D" ; UGROUP "EF_CC3" BBOX 10 54 BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.63.Channels/Buffer_64.The_Buffer - BLKNAME THE_TDC/GEN_Channels.64.Channels/Buffer_64.The_Buffer; + BLKNAME THE_TDC/GEN_Channels.63.Channels/Buffer_128.The_Buffer + BLKNAME THE_TDC/GEN_Channels.64.Channels/Buffer_128.The_Buffer; LOCATE UGROUP "EF_CC3" SITE "R78C56D" ; ############################################################################# diff --git a/tdc_releases/tdc_v_stretcher/Stretcher.vhd b/tdc_releases/tdc_v_stretcher/Stretcher.vhd index 370f86e..53b824b 100644 --- a/tdc_releases/tdc_v_stretcher/Stretcher.vhd +++ b/tdc_releases/tdc_v_stretcher/Stretcher.vhd @@ -5,7 +5,7 @@ -- File : Stretcher.vhd -- Author : cugur@gsi.de -- Created : 2012-11-07 --- Last update: 2012-11-08 +-- Last update: 2014-08-26 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -66,6 +66,6 @@ begin -- behavioral end if; end process TheStretcher; - PULSE_OUT <= pulse_latch; + PULSE_OUT <= pulse_latch after 30 ns; end behavioral; -- 2.43.0