From f3bc613188cfbccba536340b632e452d40fffad1 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Mon, 14 Oct 2013 10:52:49 +0200 Subject: [PATCH] Added Link Tester Modules (cannot synthesize) Added Debugging Tools for 4ns issue Some cleaning up to prevent some synplifiy warnings Reduced output to stdout when compiling (drop not "has no load" warning) --- cbmnet/code/cbmnet_interface_pkg.vhd | 109 +++++++- cbmnet/code/cbmnet_phy_ecp3.vhd | 83 +++++- cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd | 7 +- cbmnet/compile_periph_frankfurt.pl | 2 +- cbmnet/trb3_periph_cbmnet.prj | 10 +- cbmnet/trb3_periph_cbmnet.vhd | 266 ++++++++++++++----- cbmnet/trb3_periph_cbmnet_constraints.lpf | 10 +- 7 files changed, 389 insertions(+), 98 deletions(-) diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index 9c2b5dd..02a9c43 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -126,9 +126,114 @@ package cbmnet_interface_pkg is SERDES_ready : in std_logic -- signalize when PHY ready ); end component; + - - + component link_tester_be is + generic ( + MIN_CTRL_PACKET_SIZE : integer := 12; + MAX_CTRL_PACKET_SIZE : integer := 60; + + DATAWIDTH : integer := 16; + SINGLE_DEST : integer := 1; + DATA_PADDING : integer := 0; + CTRL_PADDING : integer := 16#A5A5#; + + ROC_ADDR : std_logic_vector(15 downto 0) := "00000000XXXXXXXX"; + OWN_ADDR : std_logic_vector(15 downto 0) := "1000000000000000" + ); + port ( + clk : in std_logic; + res_n : in std_logic; + link_active : in std_logic; + + ctrl_en : in std_logic; --enable ctrl packet generation + dlm_en : in std_logic; --enable dlm generation + force_rec_data_stop : in std_logic; --force data flow to stop + force_rec_ctrl_stop : in std_logic; --force ctrl flow to stop + + ctrl2send_stop : in std_logic; + ctrl2send_start : out std_logic; + ctrl2send_end : out std_logic; + ctrl2send : out std_logic_vector(15 downto 0); + + + dlm2send_valid : out std_logic; + dlm2send : out std_logic_vector(3 downto 0); + + dlm_rec : in std_logic_vector(3 downto 0); + dlm_rec_valid : in std_logic; + + data_rec_start : in std_logic; + data_rec_end : in std_logic; + data_rec : in std_logic_vector(DATAWIDTH-1 downto 0); + data_rec_stop : out std_logic; + + ctrl_rec_start : in std_logic; + ctrl_rec_end : in std_logic; + ctrl_rec : in std_logic_vector(15 downto 0); + ctrl_rec_stop : out std_logic; + + data_valid : out std_logic; + ctrl_valid : out std_logic; + dlm_valid : out std_logic + ); + end component; + + component link_tester_fe + generic ( + MIN_PACKET_SIZE : integer := 8; + MAX_PACKET_SIZE : integer := 64; + PACKET_GRAN : integer := 2; + + MIN_CTRL_PACKET_SIZE : integer := 12; + MAX_CTRL_PACKET_SIZE : integer := 60; + + DATAWIDTH : integer := 16; + SINGLE_DEST : integer := 1; + DATA_PADDING : integer := 0; + CTRL_PADDING : integer := 16#A5A5#; + + ROC_ADDR : std_logic_vector(15 downto 0) := "0000000000000000"; + OWN_ADDR : std_logic_vector(15 downto 0) := "1000000000000000"; + + PACKET_MODE : integer := 1 --if enabled generates another packet size order to test further corner cases + ); + port ( + clk : in std_logic; + res_n : in std_logic; + link_active : in std_logic; + + data_en : in std_logic; -- enable data packet generation + ctrl_en : in std_logic; -- enable ctrl packet generation + force_rec_ctrl_stop : in std_logic; -- force ctrl flow to stop + + ctrl2send_stop : in std_logic; + ctrl2send_start : out std_logic; + ctrl2send_end : out std_logic; + ctrl2send : out std_logic_vector(15 downto 0); + + data2send_stop : in std_logic; + data2send_start : out std_logic; + data2send_end : out std_logic; + data2send : out std_logic_vector(15 downto 0); + + dlm2send_valid : out std_logic; + dlm2send : out std_logic_vector(3 downto 0); + + dlm_rec : in std_logic_vector(3 downto 0); + dlm_rec_valid : in std_logic; + + data_rec_start : in std_logic; + data_rec_end : in std_logic; + data_rec : in std_logic_vector(15 downto 0); + data_rec_stop : out std_logic; + + ctrl_rec_start : in std_logic; + ctrl_rec_end : in std_logic; + ctrl_rec : in std_logic_vector(15 downto 0); + ctrl_rec_stop : std_logic + ); + end component; end package cbmnet_interface_pkg; package body cbmnet_interface_pkg is diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index 1f902cf..6a5963f 100644 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -102,8 +102,6 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rx_serdes_rst_i : std_logic; signal rx_pcs_rst_i : std_logic; - - -- data signal tx_data_to_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES signal rx_data_from_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES @@ -134,6 +132,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rx_rst_fsm_ready_i : std_logic; + signal serdes_ready_i : std_logic; + -- SCI Logic to obtain the barrel shifter position type sci_ctrl is (IDLE, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); signal sci_state : sci_ctrl; @@ -181,6 +181,10 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal tx_data_debug_i : std_logic_vector(17 downto 0); signal tx_data_debug_state_i : std_logic; + signal low_level_rx_see_dlm0 : std_logic; + signal low_level_tx_see_dlm0 : std_logic; + signal low_level_tx_see_dlm0_125 : std_logic; + begin clk_125_local <= CLK; @@ -369,7 +373,7 @@ begin end if; end process; - + ------------------------------------------------- -- CBMNet Ready Modules ------------------------------------------------- @@ -433,9 +437,9 @@ begin end if; end process; - SERDES_ready <= rm_tx_ready_i and rm_rx_ready_i when rising_edge(clk_125_i); - led_ok_i <= SERDES_ready; - + serdes_ready_i <= rm_tx_ready_i and rm_rx_ready_i when rising_edge(clk_125_i); + led_ok_i <= serdes_ready_i; + SERDES_ready <= serdes_ready_i; ------------------------------------------------- -- SCI @@ -560,7 +564,56 @@ begin last_rx_serdes_rst_i := rx_serdes_rst_i; end process; + + PROC_SENSE_RX_DLM0: process is + variable detected_first_word_v : std_logic := '0'; + begin + wait until rising_edge(rclk_250_i); + low_level_rx_see_dlm0 <= '0'; + if detected_first_word_v = '0' then + if rx_data_from_serdes_i = "1" & x"fb" then + detected_first_word_v := '1'; + end if; + + else + detected_first_word_v := '0'; + if rx_data_from_serdes_i = "001101010" then + low_level_rx_see_dlm0 <= '1'; + end if; + + end if; + end process; + + PROC_SENSE_TX_DLM0: process is + variable detected_first_word_v : std_logic := '0'; + begin + wait until rising_edge(clk_tx_full_i); + low_level_tx_see_dlm0 <= '0'; + + if detected_first_word_v = '0' then + if tx_data_to_serdes_i = "1" & x"fb" then + detected_first_word_v := '1'; + end if; + + else + detected_first_word_v := '0'; + if tx_data_to_serdes_i = "001101010" then + low_level_tx_see_dlm0 <= '1'; + end if; + + end if; + end process; + + PROC_SENSE_TX_DLM125: process is + begin + wait until rising_edge(clk_125_i); + + low_level_tx_see_dlm0_125 <= '0'; + if tx_data_i = "10" & x"fb6a" then + low_level_tx_see_dlm0_125 <= '1'; + end if; + end process; DEBUG_OUT(19 downto 0) <= "00" & tx_data_i; DEBUG_OUT(23 downto 20) <= "0" & tx_pll_lol_i & rx_los_low_i & rx_cdr_lol_i; @@ -570,7 +623,7 @@ begin DEBUG_OUT(51 downto 32) <= "00" & rx_data_i; DEBUG_OUT(59 downto 52) <= rx_rst_fsm_state_i & tx_rst_fsm_state_i; - DEBUG_OUT(63 downto 60) <= SERDES_ready & rm_rx_ready_i & rm_tx_ready_i & rm_tx_almost_ready_i; + DEBUG_OUT(63 downto 60) <= serdes_ready_i & rm_rx_ready_i & rm_tx_ready_i & rm_tx_almost_ready_i; DEBUG_OUT(99 downto 96) <= rm_rx_almost_ready_i & rm_rx_see_ready0_i & rm_rx_saw_ready1_i & rm_rx_valid_char_i; DEBUG_OUT(103 downto 100) <= wa_position_i(3 downto 0); DEBUG_OUT(107 downto 104) <= "00" & rm_rx_to_gear_reset_i & gear_to_rm_rst_i; @@ -578,14 +631,16 @@ begin DEBUG_OUT(127 downto 108) <= "00" & tx_data_debug_i; --STD_LOGIC_VECTOR(stat_reconnect_counter_i); -- STAT_OP REGISTER - STAT_OP(8 downto 0) <= tx_data_to_serdes_i; + STAT_OP(6 downto 0) <= tx_data_to_serdes_i(6 downto 0); - STAT_OP(9) <= rclk_250_i; - STAT_OP(10) <= clk_125_i; + STAT_OP( 7) <= low_level_tx_see_dlm0_125; + STAT_OP( 8) <= clk_125_local; + STAT_OP( 9) <= rclk_250_i; + STAT_OP(10) <= rclk_125_i; STAT_OP(11) <= clk_tx_full_i; - STAT_OP(12) <= rx_los_low_i; - STAT_OP(13) <= lsm_status_i; - STAT_OP(14) <= rx_serdes_rst_i; - STAT_OP(15) <= rx_pcs_rst_i; + STAT_OP(12) <= clk_tx_half_i; + + STAT_OP(13) <= low_level_rx_see_dlm0; + STAT_OP(14) <= low_level_tx_see_dlm0; end generate; end architecture; diff --git a/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd b/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd index 68c5b9b..0e30bf8 100644 --- a/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd @@ -36,19 +36,14 @@ architecture rx_reset_fsm_arch of cbmnet_phy_ecp3_rx_reset_fsm is signal tx_pll_lol_qd_s_int: std_logic; signal rx_los_low_int: std_logic; - signal plol_los_int: std_logic; signal rx_lol_los : std_logic; signal rx_lol_los_int: std_logic; signal rx_lol_los_del: std_logic; signal rx_pcs_rst_ch_c_int: std_logic; signal rx_serdes_rst_ch_c_int: std_logic; - signal reset_timer1: std_logic; signal reset_timer2: std_logic; - signal counter1: unsigned(1 downto 0); - signal timer1: std_logic; - signal counter2: unsigned(19 downto 0); signal timer2 : std_logic; @@ -107,7 +102,7 @@ begin end process; - proc_fsm_trans: process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, timer1, rx_lol_los_int, timer2) + proc_fsm_trans: process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, rx_lol_los_int, timer2) begin -- reset_timer1 <= '0'; reset_timer2 <= '0'; diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index ec29757..855151a 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -138,7 +138,7 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +$c=qq'$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd" | grep -v -e "^WARNING.*has no load"'; execute($c); my $tpmap = $TOPNAME . "_map" ; diff --git a/cbmnet/trb3_periph_cbmnet.prj b/cbmnet/trb3_periph_cbmnet.prj index 9b061a9..f91a32e 100644 --- a/cbmnet/trb3_periph_cbmnet.prj +++ b/cbmnet/trb3_periph_cbmnet.prj @@ -19,11 +19,13 @@ add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_s add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_wo_spec.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si_all.v" + add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/async_input_sync.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_ready_module.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_rm_fsm.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_ready_module.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_rm_fsm.v" + add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_crc_generator.v" @@ -47,6 +49,11 @@ add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_fs add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v" add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v" +add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_send_fsm.v" +add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_random_stopper.v" +add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_be.v" +add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_fe.v" + add_file -vhdl -lib work "./version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" @@ -147,7 +154,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_ecp3_rx_reset_fsm.vhd" -add_file -vhdl -lib work "./code/cbmnet_phy_gear.vhd" +add_file -vhdl -lib work "./code/cbmnet_phy_rx_gear.vhd" +add_file -vhdl -lib work "./code/cbmnet_phy_tx_gear.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_ecp3.vhd" add_file -vhdl -lib work "./trb3_periph_cbmnet.vhd" diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd index 0e99fff..291d436 100644 --- a/cbmnet/trb3_periph_cbmnet.vhd +++ b/cbmnet/trb3_periph_cbmnet.vhd @@ -80,8 +80,7 @@ entity trb3_periph_cbmnet is SD_TXD_N_OUT : out std_logic; SD_TXD_P_OUT : out std_logic ); - - + attribute syn_useioff : boolean; --no IO-FF for LEDs relaxes timing constraints attribute syn_useioff of LED_GREEN : signal is false; @@ -108,20 +107,17 @@ entity trb3_periph_cbmnet is attribute nopad : string; attribute nopad of SD_RXD_N_IN, SD_RXD_P_IN, SD_TXD_N_OUT, SD_TXD_P_OUT : signal is "true"; + attribute syn_keep : boolean; + attribute syn_keep of CLK_GPLL_LEFT, CLK_GPLL_RIGHT, CLK_PCLK_LEFT, CLK_PCLK_RIGHT, TRIGGER_LEFT, TRIGGER_RIGHT : signal is true; attribute syn_keep : boolean; - attribute syn_keep of CLK_GPLL_LEFT, CLK_GPLL_RIGHT, CLK_PCLK_LEFT, - CLK_PCLK_RIGHT, TRIGGER_LEFT, TRIGGER_RIGHT : signal is true; - - + attribute syn_preserve : boolean; end entity; architecture trb3_periph_arch of trb3_periph_cbmnet is - --Constants +--Constants constant REGIO_NUM_STAT_REGS : integer := 2; constant REGIO_NUM_CTRL_REGS : integer := 2; - attribute syn_keep : boolean; - attribute syn_preserve : boolean; --Clock / Reset signal clk_125_i : std_logic; -- clock reference for CBMNet serdes @@ -282,12 +278,44 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0'); signal phy_debug_i : std_logic_vector (127 downto 0) := (others => '0'); + +-- Link Tester + signal link_tester_ctrl_en :std_logic; + signal link_tester_dlm_en :std_logic; + signal link_tester_data_en :std_logic; + + signal link_tester_data_stop :std_logic; + signal link_tester_ctrl_stop :std_logic; + + signal link_tester_data_valid:std_logic; + signal link_tester_ctrl_valid:std_logic; + signal link_tester_dlm_valid :std_logic; + + + + + + + + + + + + + + - signal dlm_counter : unsigned(31 downto 0); + + signal link_tester_ctrl : std_logic_vector(31 downto 0) := (others => '0'); + signal link_tester_stat : std_logic_vector(31 downto 0) := (others => '0'); + begin clk_125_i <= CLK_GPLL_LEFT; +--------------------------------------------------------------------------- +-- CBMNet and PHY +--------------------------------------------------------------------------- THE_CBM_PHY: cbmnet_phy_ecp3 generic map (IS_SYNC_SLAVE => CBM_FEE_MODE) port map ( @@ -331,6 +359,9 @@ begin ); SFP_RATESEL <= (others => '1'); + + TEST_LINE(14 downto 0) <= phy_stat_op(14 downto 0); + TEST_LINE(15) <= cbm_dlm2send_va when CBM_FEE_MODE = c_YES else cbm_dlm_rec_va; THE_CBM_ENDPOINT: lp_top @@ -356,18 +387,23 @@ begin ctrl2send_start => cbm_ctrl2send_start, ctrl2send_end => cbm_ctrl2send_end, ctrl2send => cbm_ctrl2send, + data2send_stop => cbm_data2send_stop, data2send_start => cbm_data2send_start, data2send_end => cbm_data2send_end, data2send => cbm_data2send, + dlm2send_va => cbm_dlm2send_va, dlm2send => cbm_dlm2send, + dlm_rec_type => cbm_dlm_rec_type, dlm_rec_va => cbm_dlm_rec_va, + data_rec => cbm_data_rec, data_rec_start => cbm_data_rec_start, data_rec_end => cbm_data_rec_end, data_rec_stop => cbm_data_rec_stop, + ctrl_rec => cbm_ctrl_rec, ctrl_rec_start => cbm_ctrl_rec_start, ctrl_rec_end => cbm_ctrl_rec_end, @@ -376,50 +412,130 @@ begin ); cbm_res_n <= not rreset_i; - -- TEST_LINE <= phy_stat_op; - - TEST_LINE(7 downto 0) <= phy_stat_debug(7 downto 0); - TEST_LINE(8) <= cbm_SERDES_ready; - TEST_LINE(9) <= cbm_link_active; - --TEST_LINE(10) see FEE/MST switch below - TEST_LINE(11) <= rreset_i; - TEST_LINE(15 downto 12) <= (others => '0'); - - GEN_MST_TEST_LOGIC: if CBM_FEE_MODE = c_NO generate - process is - constant counter_max : integer := 1250000; - variable counter : integer range 0 to counter_max := 0; - begin - wait until rising_edge(rclk_125_i); - - cbm_dlm2send_va <= '0'; - if rreset_i = '1' then - counter := 1; - else - if counter = counter_max then - counter := 0; - cbm_dlm2send_va <= '1'; - else - counter := counter + 1; - end if; - end if; - end process; +--------------------------------------------------------------------------- +-- CBMNet Link Tester +--------------------------------------------------------------------------- + GEN_LINK_TESTER_BE: if CBM_FEE_MODE = c_NO generate + THE_LINK_TESTER: link_tester_be + generic map ( + MIN_CTRL_PACKET_SIZE => 12, -- : integer := 12; + MAX_CTRL_PACKET_SIZE => 60, -- : integer := 60; + + DATAWIDTH => 16, -- : integer := 16; + SINGLE_DEST => 1, -- : integer := 1; + DATA_PADDING => 0, -- : integer := 0; + CTRL_PADDING => 16#A5A5#, -- : integer := 16#A5A5#; + + ROC_ADDR => "00000000XXXXXXXX", -- : std_logic_vector(15 downto 0) := "00000000xxxxxxxx"; + OWN_ADDR => "1000000000000000" -- : std_logic_vector(15 downto 0) := "1000000000000000"; + ) + port map ( + clk => rclk_125_i, -- in std_logic; + res_n => cbm_res_n, -- in std_logic; + link_active => cbm_link_active, -- in std_logic; + + ctrl_en => link_tester_ctrl_en, -- in std_logic; //enable ctrl packet generation + dlm_en => link_tester_dlm_en, -- in std_logic; //enable dlm generation + force_rec_data_stop => link_tester_data_stop, -- in std_logic; //force data flow to stop + force_rec_ctrl_stop => link_tester_ctrl_stop, -- in std_logic; //force ctrl flow to stop + + ctrl2send_stop => cbm_ctrl2send_stop, -- in std_logic; + ctrl2send_start => cbm_ctrl2send_start, -- out std_logic; + ctrl2send_end => cbm_ctrl2send_end, -- out std_logic; + ctrl2send => cbm_ctrl2send, -- out std_logic_vector(15 downto 0); + + dlm2send_valid => cbm_dlm2send_va, -- out std_logic; + dlm2send => cbm_dlm2send, -- out std_logic_vector(3 downto 0); + + dlm_rec => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0); + dlm_rec_valid => cbm_dlm_rec_va, -- in std_logic; + + data_rec_start => cbm_data_rec_start(0), -- in std_logic; + data_rec_end => cbm_data_rec_end(0), -- in std_logic; + data_rec => cbm_data_rec, -- in std_logic_vector(DATAWIDTH-1 downto 0); + data_rec_stop => cbm_data_rec_stop(0), -- out std_logic; + + ctrl_rec_start => cbm_ctrl_rec_start, -- in std_logic; + ctrl_rec_end => cbm_ctrl_rec_end, -- in std_logic; + ctrl_rec => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0); + ctrl_rec_stop => cbm_ctrl_rec_stop, -- out std_logic; + + data_valid => link_tester_data_valid, -- out std_logic; + ctrl_valid => link_tester_ctrl_valid, -- out std_logic; + dlm_valid => link_tester_dlm_valid -- out std_logic + ); + end generate; + + GEN_LINK_TESTER_FE: if CBM_FEE_MODE = c_YES generate + THE_LINK_TESTER: link_tester_fe + -- generic map ( + -- MIN_PACKET_SIZE => 8, -- : integer := 8; + -- MAX_PACKET_SIZE => 64, -- : integer := 64; + -- PACKET_GRAN => 2, -- : integer := 2; + -- + -- MIN_CTRL_PACKET_SIZE => 12, -- : integer := 12; + -- MAX_CTRL_PACKET_SIZE => 60, -- : integer := 60; + -- + -- DATAWIDTH => 16, -- : integer := 16; + -- SINGLE_DEST => 1, -- : integer := 1; + -- DATA_PADDING => 0, -- : integer := 0; + -- CTRL_PADDING => 16#A5A5#, -- : integer := 16#A5A5#; + -- + -- ROC_ADDR => "0000000000000000", -- : std_logic_vector(15 downto 0) := "0000000000000000"; + -- OWN_ADDR => "1000000000000000", -- : std_logic_vector(15 downto 0) := "1000000000000000"; + -- + -- PACKET_MODE : integer := 1 --if enabled generates another packet size order to test further corner cases + -- ) + port map ( + clk => rclk_125_i, -- in std_logic; + res_n => cbm_res_n, -- in std_logic; + link_active => cbm_link_active, -- in std_logic; + + data_en => link_tester_data_en, -- in std_logic; //enable data packet generation + ctrl_en => link_tester_ctrl_en, -- in std_logic; //enable ctrl packet generation + force_rec_ctrl_stop => link_tester_ctrl_stop, -- in std_logic; //force ctrl flow to stop + + ctrl2send_stop => cbm_ctrl2send_stop, -- in std_logic; + ctrl2send_start => cbm_ctrl2send_start, -- out std_logic; + ctrl2send_end => cbm_ctrl2send_end, -- out std_logic; + ctrl2send => cbm_ctrl2send, -- out std_logic_vector(15 downto 0); + + data2send_stop => cbm_data2send_stop(0), -- in std_logic; + data2send_start => cbm_data2send_start(0), -- out std_logic; + data2send_end => cbm_data2send_end(0), -- out std_logic; + data2send => cbm_data2send, -- out std_logic_vector(15 downto 0); + + dlm2send_valid => cbm_dlm2send_va, -- out std_logic; + dlm2send => cbm_dlm2send, -- out std_logic_vector(3 downto 0); + + dlm_rec => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0); + dlm_rec_valid => cbm_dlm_rec_va, -- in std_logic; + + data_rec_start => cbm_data_rec_start(0), -- in std_logic; + data_rec_end => cbm_data_rec_end(0), -- in std_logic; + data_rec => cbm_data_rec, -- in std_logic_vector(15 downto 0); + data_rec_stop => cbm_data_rec_stop(0), -- out std_logic; + + ctrl_rec_start => cbm_ctrl_rec_start, -- in std_logic; + ctrl_rec_end => cbm_ctrl_rec_end, -- in std_logic; + ctrl_rec => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0); + ctrl_rec_stop => cbm_ctrl_rec_stop -- std_logic + ); end generate; - - PROC_DLM_COUNTER: process is begin - wait until rising_edge(rclk_125_i); - - TEST_LINE(10) <= '0'; - if rreset_i = '1' then - dlm_counter <= TO_UNSIGNED(0,32); - - elsif cbm_dlm2send_va='1' or cbm_dlm_rec_va='1' then - TEST_LINE(10) <= '1'; - dlm_counter <= dlm_counter + TO_UNSIGNED(1, 32); - end if; - end process; - + link_tester_stat <= ( + 0 => link_tester_data_valid, + 1 => link_tester_ctrl_valid, + 2 => link_tester_dlm_valid, + others => '0' + ); + + link_tester_data_en <= link_tester_ctrl(0); + link_tester_ctrl_en <= link_tester_ctrl(1); + link_tester_dlm_en <= link_tester_ctrl(2); + + link_tester_data_stop <= link_tester_ctrl(4); + link_tester_ctrl_stop <= link_tester_ctrl(5); PROC_REGIO_DEBUG: process is variable address : integer range 0 to 255; @@ -431,34 +547,37 @@ begin debug_ack <= '0'; debug_ack <= debug_read_en or debug_write_en; - case (address) is - when 0 => debug_data_out <= x"0000" & phy_stat_op; - when 1 => debug_data_out <= x"0000" & phy_ctrl_op; - when 2 => debug_data_out <= phy_stat_debug(31 downto 0); - when 3 => debug_data_out <= phy_stat_debug(63 downto 32); - when 4 => debug_data_out <= phy_ctrl_debug(31 downto 0); - when 5 => debug_data_out <= phy_ctrl_debug(63 downto 32); - when 6 => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32)); - when 8 => debug_data_out <= phy_debug_i(31+32*0 downto 32*0); - when 9 => debug_data_out <= phy_debug_i(31+32*1 downto 32*1); - when 10 => debug_data_out <= phy_debug_i(31+32*2 downto 32*2); - when 11 => debug_data_out <= phy_debug_i(31+32*3 downto 32*3); - when 12 => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter); + case address is + when 16#0# => debug_data_out <= x"0000" & phy_stat_op; + when 16#1# => debug_data_out <= x"0000" & phy_ctrl_op; + when 16#2# => debug_data_out <= phy_stat_debug(31 downto 0); + when 16#3# => debug_data_out <= phy_stat_debug(63 downto 32); + when 16#4# => debug_data_out <= phy_ctrl_debug(31 downto 0); + when 16#5# => debug_data_out <= phy_ctrl_debug(63 downto 32); + when 16#6# => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32)); + when 16#8# => debug_data_out <= phy_debug_i(31+32*0 downto 32*0); + when 16#9# => debug_data_out <= phy_debug_i(31+32*1 downto 32*1); + when 16#a# => debug_data_out <= phy_debug_i(31+32*2 downto 32*2); + when 16#b# => debug_data_out <= phy_debug_i(31+32*3 downto 32*3); + + when 16#c# => debug_data_out <= link_tester_stat; + when 16#d# => debug_data_out <= link_tester_ctrl; + when others => debug_ack <= '0'; end case; if debug_write_en = '1' then case (address) is - when 1 => phy_ctrl_op <= debug_data_in(15 downto 0); - when 4 => phy_ctrl_debug(31 downto 0) <= debug_data_in; - when 5 => phy_ctrl_debug(63 downto 32) <= debug_data_in; + when 16#1# => phy_ctrl_op <= debug_data_in(15 downto 0); + when 16#4# => phy_ctrl_debug(31 downto 0) <= debug_data_in; + when 16#5# => phy_ctrl_debug(63 downto 32) <= debug_data_in; + + when 16#d# => link_tester_ctrl <= debug_data_in; when others => debug_ack <= '0'; end case; end if; end process; - --TEST_LINE <= phy_stat_op; - --------------------------------------------------------------------------- -- Reset Generation --------------------------------------------------------------------------- @@ -491,6 +610,7 @@ begin CLK => CLK_GPLL_RIGHT, CLKOP => clk_100_i, CLKOK => clk_200_i, + CLKOS => open, LOCK => pll_lock1 ); @@ -538,7 +658,11 @@ begin STAT_OP => med_stat_op, CTRL_OP => med_ctrl_op, STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') + CTRL_DEBUG => (others => '0'), + + sci_ack => open, + clk_rx_full_out => open, + clk_rx_half_out => open ); --------------------------------------------------------------------------- diff --git a/cbmnet/trb3_periph_cbmnet_constraints.lpf b/cbmnet/trb3_periph_cbmnet_constraints.lpf index 107c643..feee12b 100644 --- a/cbmnet/trb3_periph_cbmnet_constraints.lpf +++ b/cbmnet/trb3_periph_cbmnet_constraints.lpf @@ -13,14 +13,18 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - + FREQUENCY NET "THE_CBM_PHY/CLK_TX_FULL_I" 250 MHz; + FREQUENCY NET "THE_CBM_PHY/RCLK_250_I" 250 MHz; + #Change the next two lines to the clk_fast signal of the ADC USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0"; USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0"; - - USE PRIMARY NET "CLK_PCLK_LEFT"; USE PRIMARY NET "CLK_PCLK_LEFT_c"; + + USE PRIMARY NET "THE_CBM_PHY/RCLK_250_I"; + USE SECONDARY NET "THE_CBM_PHY/CLK_TX_FULL_I"; + ################################################################# # Reset Nets ################################################################# -- 2.43.0