From f3ec5d23ab58ac72d095a8cdab903c24baa71c8c Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 22 Jun 2018 11:13:12 +0200 Subject: [PATCH] modified test bench --- mupix/Mupix8/tb/DataMuxTest.vhd | 305 +++++++++++++++++--------------- 1 file changed, 158 insertions(+), 147 deletions(-) diff --git a/mupix/Mupix8/tb/DataMuxTest.vhd b/mupix/Mupix8/tb/DataMuxTest.vhd index b0f5f3a..cd1d2bc 100644 --- a/mupix/Mupix8/tb/DataMuxTest.vhd +++ b/mupix/Mupix8/tb/DataMuxTest.vhd @@ -6,153 +6,164 @@ use work.StdTypes.all; entity DataMuxTest is end entity DataMuxTest; - + architecture sim of DataMuxTest is - - component FiFoDataMux - generic( - g_datawidth : integer := 32; - g_inputs : integer := 4; - g_clockspeed : integer := 1e8 - ); - port( - clk : in std_logic; - rst : in std_logic; - fifo_empty : in std_logic_vector(g_inputs - 1 downto 0); - fifo_full : in std_logic_vector(g_inputs - 1 downto 0); - fifo_datain : in std_logic_vector(g_inputs*g_datawidth - 1 downto 0); - fifo_mask : in std_logic_vector(g_inputs - 1 downto 0); - fifo_rden : out std_logic_vector(g_inputs - 1 downto 0); - buff_wren : out std_logic; - dataout : out std_logic_vector(g_datawidth - 1 downto 0); - wordin_freq : out std_logic_vector(32*g_inputs - 1 downto 0); - fifo_full_o : out std_logic - ); - end component FiFoDataMux; - - component STD_FIFO - generic( - DATA_WIDTH : positive := 8; - FIFO_DEPTH : positive := 256 - ); - port( - CLK : in std_logic; - RST : in std_logic; - WriteEn : in std_logic; - DataIn : in std_logic_vector(DATA_WIDTH - 1 downto 0); - ReadEn : in std_logic; - DataOut : out std_logic_vector(DATA_WIDTH - 1 downto 0); - Empty : out std_logic; - Full : out std_logic - ); - end component STD_FIFO; - - constant c_datawidth : integer := 8; - constant c_inputs : integer := 2; - constant c_clockspeed : integer := 1e3; - constant c_fifo_depth : integer := 16; - - constant c_clk_period : time := 10 ns; - - signal clk : std_logic; - signal rst : std_logic := '0'; - signal WriteEn : std_logic_vector(c_inputs - 1 downto 0) := (others => '0'); - signal DataIn : std_logic_vector(c_inputs*c_datawidth - 1 downto 0) := (others => '0'); - signal ReadEn : std_logic_vector(c_inputs - 1 downto 0); - signal DataOut : std_logic_vector(c_inputs*c_datawidth - 1 downto 0); - signal Empty : std_logic_vector(c_inputs - 1 downto 0); - signal Full : std_logic_vector(c_inputs - 1 downto 0); - signal fifo_mask : std_logic_vector(c_inputs - 1 downto 0) := (others => '0'); - signal buff_wren : std_logic; - signal wordin_freq : std_logic_vector(32*c_inputs - 1 downto 0); - signal fifo_full_o : std_logic; - signal dataout_buf : std_logic_vector(c_datawidth - 1 downto 0); - + + component FiFoDataMux + generic( + g_datawidthfifo : integer := 40; + g_datawidthtrb : integer := 32; + g_inputs : integer := 4; + g_clockspeed : integer := 1e8 + ); + port( + clk : in std_logic; + rst : in std_logic; + fifo_empty : in std_logic_vector(g_inputs - 1 downto 0); + fifo_full : in std_logic_vector(g_inputs - 1 downto 0); + fifo_datain : in std_logic_vector(g_inputs*g_datawidthfifo - 1 downto 0); + fifo_mask : in std_logic_vector(g_inputs - 1 downto 0); + fifo_rden : out std_logic_vector(g_inputs - 1 downto 0); + buff_wren : out std_logic; + dataout : out std_logic_vector(g_datawidthtrb - 1 downto 0); + wordin_freq : out std_logic_vector(32*g_inputs - 1 downto 0); + fifo_full_o : out std_logic + ); + end component FiFoDataMux; + + component STD_FIFO + generic( + DATA_WIDTH : positive := 8; + FIFO_DEPTH : positive := 256 + ); + port( + CLK : in std_logic; + RST : in std_logic; + WriteEn : in std_logic; + DataIn : in std_logic_vector(DATA_WIDTH - 1 downto 0); + ReadEn : in std_logic; + DataOut : out std_logic_vector(DATA_WIDTH - 1 downto 0); + Empty : out std_logic; + Full : out std_logic + ); + end component STD_FIFO; + + constant c_datawidthfifo : integer := 40; + constant c_datawidthtrb : integer := 32; + constant c_inputs : integer := 2; + constant c_clockspeed : integer := 1e3; + constant c_fifo_depth : integer := 16; + + constant c_clk_period : time := 10 ns; + + signal clk : std_logic; + signal rst : std_logic := '0'; + signal WriteEn : std_logic_vector(c_inputs - 1 downto 0) := (others => '0'); + signal DataIn : std_logic_vector(c_inputs*c_datawidthfifo - 1 downto 0) := (others => '0'); + signal ReadEn : std_logic_vector(c_inputs - 1 downto 0); + signal DataOut : std_logic_vector(c_inputs*c_datawidthfifo - 1 downto 0); + signal Empty : std_logic_vector(c_inputs - 1 downto 0); + signal Full : std_logic_vector(c_inputs - 1 downto 0); + signal fifo_mask : std_logic_vector(c_inputs - 1 downto 0) := (others => '0'); + signal buff_wren : std_logic; + signal wordin_freq : std_logic_vector(32*c_inputs - 1 downto 0); + signal fifo_full_o : std_logic; + signal dataout_buf : std_logic_vector(c_datawidthtrb - 1 downto 0); + + type memory_type is array (0 to 15) of std_logic_vector(15 downto 0); + signal testdata : memory_type := (0 => x"AAAA", 1 => x"BBBB", 2 => x"CCCC", + 3 => x"DDDD", 4 => x"EEEE", 5 => x"FFFF", + 6 => x"AAAA", 7 => x"BBBB", 8 => x"CCCC", + 9 => x"DDDD", 10 => x"EEEE", 11 => x"FFFF", + 12 => x"AAAA", 13 => x"BBBB", 14 => x"CCCC", + 15 => x"DDDD"); + begin - - generate_fifo : for i in 0 to c_inputs - 1 generate - fifo :component STD_FIFO - generic map( - DATA_WIDTH => c_datawidth, - FIFO_DEPTH => c_fifo_depth - ) - port map( - CLK => clk, - RST => rst, - WriteEn => WriteEn(i), - DataIn => DataIn((i + 1)*c_datawidth - 1 downto i*c_datawidth), - ReadEn => ReadEn(i), - DataOut => DataOut((i + 1)*c_datawidth - 1 downto i*c_datawidth), - Empty => Empty(i), - Full => Full(i) - ); - end generate generate_fifo; - - dut : component FiFoDataMux - generic map( - g_datawidth => c_datawidth, - g_inputs => c_inputs, - g_clockspeed => c_clockspeed - ) - port map( - clk => clk, - rst => rst, - fifo_empty => Empty, - fifo_full => Full, - fifo_datain => dataout, - fifo_mask => fifo_mask, - fifo_rden => ReadEn, - buff_wren => buff_wren, - dataout => dataout_buf, - wordin_freq => wordin_freq, - fifo_full_o => fifo_full_o - ); - - clk_gen : process is - begin - clk <= '0'; - wait for c_clk_period/2; - clk <= '1'; - wait for c_clk_period/2; - end process clk_gen; - - stimulus : process is - begin - wait for 100 ns; - fifo_mask <= "11"; - --write to single fifo - for i in 0 to 10 loop - WriteEn(1) <= '1'; - DataIn(2*c_datawidth - 1 downto c_datawidth) <= x"A" & std_logic_vector(to_unsigned(i, 4)); - wait for c_clk_period; - end loop; - WriteEn(1) <= '0'; - DataIn(2*c_datawidth - 1 downto c_datawidth) <= (others => '0'); - wait for 100 ns; - --write to both fifos at same time, reading should start at last fifo - for i in 0 to 10 loop - WriteEn <= "11"; - DataIn <= x"A" & std_logic_vector(to_unsigned(i, 4)) & x"B" & std_logic_vector(to_unsigned(i, 4)); - wait for c_clk_period; - end loop; - WriteEn <= (others => '0'); - DataIn <= (others => '0'); - wait for 200 ns; - --start writing into first fifo then in second fifo, state machine should finish reading fifo 1 and then start reading other fifo - for i in 0 to 10 loop - if i < 5 then - WriteEn(0) <= '1'; - DataIn(c_datawidth - 1 downto 0) <= x"B" & std_logic_vector(to_unsigned(i, 4)); - else - WriteEn <= "11"; - DataIn <= x"A" & std_logic_vector(to_unsigned(i, 4)) & x"B" & std_logic_vector(to_unsigned(i, 4)); - end if; - wait for c_clk_period; - end loop; - WriteEn <= (others => '0'); - DataIn <= (others => '0'); - wait; - end process stimulus; - - + + generate_fifo : for i in 0 to c_inputs - 1 generate + fifo : component STD_FIFO + generic map( + DATA_WIDTH => c_datawidthfifo, + FIFO_DEPTH => c_fifo_depth + ) + port map( + CLK => clk, + RST => rst, + WriteEn => WriteEn(i), + DataIn => DataIn((i + 1)*c_datawidthfifo - 1 downto i*c_datawidthfifo), + ReadEn => ReadEn(i), + DataOut => DataOut((i + 1)*c_datawidthfifo - 1 downto i*c_datawidthfifo), + Empty => Empty(i), + Full => Full(i) + ); + end generate generate_fifo; + + dut : component FiFoDataMux + generic map( + g_datawidthfifo => c_datawidthfifo, + g_datawidthtrb => c_datawidthtrb, + g_inputs => c_inputs, + g_clockspeed => c_clockspeed + ) + port map( + clk => clk, + rst => rst, + fifo_empty => Empty, + fifo_full => Full, + fifo_datain => dataout, + fifo_mask => fifo_mask, + fifo_rden => ReadEn, + buff_wren => buff_wren, + dataout => dataout_buf, + wordin_freq => wordin_freq, + fifo_full_o => fifo_full_o + ); + + clk_gen : process is + begin + clk <= '0'; + wait for c_clk_period/2; + clk <= '1'; + wait for c_clk_period/2; + end process clk_gen; + + stimulus : process is + begin + wait for 100 ns; + fifo_mask <= "11"; + --write to single fifo and test data width conversion + for i in 0 to 14 loop + WriteEn(1) <= '1'; + DataIn(2*c_datawidthfifo - 1 downto c_datawidthfifo) <= testdata(i) & std_logic_vector(to_unsigned(i, 8)) & testdata(i); + wait for c_clk_period; + end loop; + WriteEn(1) <= '0'; + DataIn(2*c_datawidthfifo - 1 downto c_datawidthfifo) <= (others => '0'); + wait for 250 ns; + --write to both fifos at same time, reading should start at last fifo + for i in 0 to 10 loop + WriteEn <= "11"; + DataIn <= x"A" & std_logic_vector(to_unsigned(i, 36)) & x"B" & std_logic_vector(to_unsigned(i, 36)); + wait for c_clk_period; + end loop; + WriteEn <= (others => '0'); + DataIn <= (others => '0'); + wait for 200 ns; + --start writing into first fifo then in second fifo, state machine should finish reading fifo 1 and then start reading other fifo + for i in 0 to 10 loop + if i < 5 then + WriteEn(0) <= '1'; + DataIn(c_datawidthfifo - 1 downto 0) <= x"B" & std_logic_vector(to_unsigned(i, 36)); + else + WriteEn <= "11"; + DataIn <= x"A" & std_logic_vector(to_unsigned(i, 36)) & x"B" & std_logic_vector(to_unsigned(i, 36)); + end if; + wait for c_clk_period; + end loop; + WriteEn <= (others => '0'); + DataIn <= (others => '0'); + wait; + end process stimulus; + + end architecture sim; -- 2.43.0