From f43cfa2170dfe55547934ebdcbeb642891da29d9 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Sat, 17 Aug 2013 13:10:59 +0200 Subject: [PATCH] CBMNet: Work in progress --- base/trb3_periph_cbmnet.lpf | 213 ++++++++++++++++++ cbmnet/cbmnet | 1 + cbmnet/clean_workdir | 5 + cbmnet/code/cbmnet_phy_pkg.vhd | 59 +++++ cbmnet/code/cbmnet_pkg.vhd | 130 +++++++++++ cbmnet/compile_periph_frankfurt.pl | 2 +- cbmnet/trb3_periph_cbmnet.prj | 253 ++++++++++++++-------- cbmnet/trb3_periph_cbmnet.vhd | 248 ++++++++++++++++++--- cbmnet/trb3_periph_cbmnet_constraints.lpf | 25 +-- 9 files changed, 779 insertions(+), 157 deletions(-) create mode 100644 base/trb3_periph_cbmnet.lpf create mode 120000 cbmnet/cbmnet create mode 100755 cbmnet/clean_workdir create mode 100644 cbmnet/code/cbmnet_phy_pkg.vhd create mode 100644 cbmnet/code/cbmnet_pkg.vhd diff --git a/base/trb3_periph_cbmnet.lpf b/base/trb3_periph_cbmnet.lpf new file mode 100644 index 0000000..177c22b --- /dev/null +++ b/base/trb3_periph_cbmnet.lpf @@ -0,0 +1,213 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +# SYSCONFIG MCCLK_FREQ = 2.5; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; + + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; + + + + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; + +################################################################# +# Connection to AddOn +################################################################# + +LOCATE COMP "LED_LINKOK_1" SITE "P1"; #DQLL0_0 #1 +LOCATE COMP "LED_RX_1" SITE "P2"; #DQLL0_1 #3 +LOCATE COMP "LED_TX_1" SITE "T2"; #DQLL0_2 #5 +LOCATE COMP "SFP_MOD0_1" SITE "U3"; #DQLL0_3 #7 +LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 +LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 +LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 +LOCATE COMP "SFP_TXDIS_1" SITE "P3"; #DQSLL0_C #15 +LOCATE COMP "SFP_LOS_1" SITE "P5"; #DQLL0_6 #17 +LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 + +LOCATE COMP "LED_LINKOK_2" SITE "N5"; #DQLL0_8 #21 +LOCATE COMP "LED_RX_2" SITE "N6"; #DQLL0_9 #23 +LOCATE COMP "LED_TX_2" SITE "AC2"; #DQLL2_0 #25 +LOCATE COMP "SFP_MOD0_2" SITE "AC3"; #DQLL2_1 #27 +LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 +LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 +LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 +LOCATE COMP "SFP_TXDIS_2" SITE "AA2"; #DQLL2_5 #35 +LOCATE COMP "SFP_LOS_2" SITE "W7"; #DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 + +LOCATE COMP "LED_LINKOK_3" SITE "AD1"; #DQLL3_0 #2 +LOCATE COMP "LED_RX_3" SITE "AD2"; #DQLL3_1 #4 +LOCATE COMP "LED_TX_3" SITE "AB5"; #DQLL3_2 #6 +LOCATE COMP "SFP_MOD0_3" SITE "AB6"; #DQLL3_3 #8 +LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 +LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 +LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 +LOCATE COMP "SFP_TXDIS_3" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS_3" SITE "AA3"; #DQLL3_6 #18 +LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 + +LOCATE COMP "LED_LINKOK_4" SITE "W8"; #DQLL3_8 #22 +LOCATE COMP "LED_RX_4" SITE "W9"; #DQLL3_9 #24 +LOCATE COMP "LED_TX_4" SITE "V1"; #DQLL1_0 #26 +LOCATE COMP "SFP_MOD0_4" SITE "U2"; #DQLL1_1 #28 +LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 +LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 +LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "SFP_TXDIS_4" SITE "R3"; #DQLL1_5 #36 +LOCATE COMP "SFP_LOS_4" SITE "T3"; #DQSLL1_T #38 +LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 + + + +LOCATE COMP "LED_LINKOK_5" SITE "W23"; #DQLR1_0 #169 +LOCATE COMP "LED_RX_5" SITE "W22"; #DQLR1_1 #171 +LOCATE COMP "LED_TX_5" SITE "AA25"; #DQLR1_2 #173 +LOCATE COMP "SFP_MOD0_5" SITE "Y24"; #DQLR1_3 #175 +LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 +LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 +LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 +LOCATE COMP "SFP_TXDIS_5" SITE "W20"; #DQSLR1_C #183 +LOCATE COMP "SFP_LOS_5" SITE "AA24"; #DQLR1_6 #185 +LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 + +LOCATE COMP "LED_LINKOK_6" SITE "R25"; #DQLR2_0 #170 +LOCATE COMP "LED_RX_6" SITE "R26"; #DQLR2_1 #172 +LOCATE COMP "LED_TX_6" SITE "T25"; #DQLR2_2 #174 +LOCATE COMP "SFP_MOD0_6" SITE "T24"; #DQLR2_3 #176 +LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 +LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 +LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 +LOCATE COMP "SFP_TXDIS_6" SITE "V22"; #DQSLR2_C #184 +LOCATE COMP "SFP_LOS_6" SITE "U24"; #DQLR2_6 #186 +LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 + + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +################################################################# +# Additional Lines to AddOn +################################################################# + +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 + +################################################################# +# Flash ROM and Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; diff --git a/cbmnet/cbmnet b/cbmnet/cbmnet new file mode 120000 index 0000000..e775894 --- /dev/null +++ b/cbmnet/cbmnet @@ -0,0 +1 @@ +../../cbmnet \ No newline at end of file diff --git a/cbmnet/clean_workdir b/cbmnet/clean_workdir new file mode 100755 index 0000000..fa5b8d1 --- /dev/null +++ b/cbmnet/clean_workdir @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +rm -rf workdir +mkdir workdir +cd workdir +../../base/linkdesignfiles.sh \ No newline at end of file diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd new file mode 100644 index 0000000..5d29372 --- /dev/null +++ b/cbmnet/code/cbmnet_phy_pkg.vhd @@ -0,0 +1,59 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use work.trb_net_std.all; + +package cbmnet_phy_pkg is + component cbmnet_phy_ecp3 is + generic( + IS_SYNC_SLAVE : integer := c_NO --select slave mode + ); + port( + CLK : in std_logic; -- *internal* 125 MHz reference clock + RESET : in std_logic; -- synchronous reset + + --Internal Connection TX + MED_TXDATA_IN : in std_logic_vector(15 downto 0); + MED_TXDATA_K_IN : in std_logic_vector( 1 downto 0); + + --Internal Connection RX + MED_RXDATA_OUT : out std_logic_vector(15 downto 0) := (others => '0'); + MED_RXDATA_K_OUT : out std_logic_vector( 1 downto 0) := (others => '0'); + + CLK_RX_HALF_OUT : out std_logic := '0'; -- recovered 125 MHz + CLK_RX_FULL_OUT : out std_logic := '0'; -- recovered 250 MHz + CLK_RX_RESET_OUT : out std_logic := '1'; -- set to 0, ~1us after link is assumed to be stable + + LINK_ACTIVE_OUT : out std_logic; -- link is active and can send and receive data + SERDES_ready : out std_logic; + + --SFP Connection + SD_RXD_P_IN : in std_logic := '0'; + SD_RXD_N_IN : in std_logic := '0'; + SD_TXD_P_OUT : out std_logic := '0'; + SD_TXD_N_OUT : out std_logic := '0'; + + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable + + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); + end component; +end package cbmnet_phy_pkg; + +package body cbmnet_phy_pkg is +end package body; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_pkg.vhd b/cbmnet/code/cbmnet_pkg.vhd new file mode 100644 index 0000000..19206d0 --- /dev/null +++ b/cbmnet/code/cbmnet_pkg.vhd @@ -0,0 +1,130 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package cbmnet_interface_pkg is + constant K280 : std_logic_vector(7 downto 0) := "00011100"; + constant K281 : std_logic_vector(7 downto 0) := "00111100"; + constant K282 : std_logic_vector(7 downto 0) := "01011100"; + constant K283 : std_logic_vector(7 downto 0) := "01111100"; + constant K284 : std_logic_vector(7 downto 0) := "10011100"; + constant K285 : std_logic_vector(7 downto 0) := "10111100"; + constant K286 : std_logic_vector(7 downto 0) := "11011100"; + constant K287 : std_logic_vector(7 downto 0) := "11111100"; + constant K237 : std_logic_vector(7 downto 0) := "11111110"; + constant K277 : std_logic_vector(7 downto 0) := "11111011"; + constant K297 : std_logic_vector(7 downto 0) := "11111101"; + constant K307 : std_logic_vector(7 downto 0) := "11111110"; + + + component gtp_rx_ready_module is + generic ( + READY_CHAR0 : std_logic_vector(7 downto 0) := K284; + READY_CHAR1 : std_logic_vector(7 downto 0) := K287; + ALIGN_CHAR : std_logic_vector(7 downto 0) := K285; + DATAWIDTH : integer := 16; + WORDS : integer := DATAWIDTH/8; + + INCL_8B10B_DEC : integer range 0 to 1 := 1 + ); + port ( + clk : in std_logic; + res_n : in std_logic; + ready_MGT2RM : in std_logic; + rxdata_in : in std_logic_vector((WORDS*10)-1 downto 0); + + tx_ready : in std_logic; + tx_almost_ready : in std_logic; + + ready_RM2LP : out std_logic; + almost_ready_OUT : out std_logic; + rxdata_out : out std_logic_vector((DATAWIDTH-1) downto 0); + charisk_out : out std_logic_vector((WORDS-1) downto 0); + see_ready0 : out std_logic; + saw_ready1 : out std_logic; + valid_char : out std_logic; + reset_rx : out std_logic + ); + end component; + + component gtp_tx_ready_module is + generic ( + READY_CHAR0 : std_logic_vector(7 downto 0) := K284; + READY_CHAR1 : std_logic_vector(7 downto 0) := K287; + ALIGN_CHAR : std_logic_vector(7 downto 0) := K285; + DATAWIDTH : integer := 16; + WORDS :integer := DATAWIDTH/8 + ); + port ( + clk : in std_logic; + res_n : in std_logic; + restart_link : in std_logic; + ready_MGT2RM : in std_logic; + txdata_in : in std_logic_vector((DATAWIDTH-1) downto 0); + txcharisk_in : in std_logic_vector((WORDS-1) downto 0); + + see_ready0 : in std_logic; + saw_ready1 : in std_logic; + valid_char : in std_logic; + rx_rm_ready : in std_logic; + + ready_RM2LP : out std_logic; + txdata_out : out std_logic_vector((WORDS*9)-1 downto 0); + almost_ready : out std_logic; + gt11_reinit : out std_logic + ); + end component; + + component lp_top is + generic ( + NUM_LANES : integer := 1; -- Number of data lanes + TX_SLAVE : integer := 0 -- If set; module will act as TX slave; otherwise as RX slave + -- If only one lane is used; parameter does not matter + ); + port ( + clk : in std_logic; -- Main clock + res_n : in std_logic; -- Active low reset; can be changed by define + link_active : out std_logic; -- link is active and can send and receive data + + ctrl2send_stop : out std_logic; -- send control interface + ctrl2send_start : in std_logic; + ctrl2send_end : in std_logic; + ctrl2send : in std_logic_vector(15 downto 0); + + data2send_stop : out std_logic_vector(NUM_LANES-1 downto 0); -- send data interface + data2send_start : in std_logic_vector(NUM_LANES-1 downto 0); + data2send_end : in std_logic_vector(NUM_LANES-1 downto 0); + data2send : in std_logic_vector((16*NUM_LANES)-1 downto 0); + + dlm2send_va : in std_logic; -- send dlm interface + dlm2send : in std_logic_vector(3 downto 0); + + dlm_rec_type : out std_logic_vector(3 downto 0); -- receive dlm interface + dlm_rec_va : out std_logic; + + data_rec : out std_logic_vector((16*NUM_LANES)-1 downto 0); -- receive data interface + data_rec_start : out std_logic_vector(NUM_LANES-1 downto 0); + data_rec_end : out std_logic_vector(NUM_LANES-1 downto 0); + data_rec_stop : in std_logic_vector(NUM_LANES-1 downto 0); + + ctrl_rec : out std_logic_vector(15 downto 0); -- receive control interface + ctrl_rec_start : out std_logic; + ctrl_rec_end : out std_logic; + ctrl_rec_stop : in std_logic; + + data_from_link : in std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface from the PHY + data2link : out std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface to the PHY + + link_activeovr : in std_logic; -- Overrides; set 0 by default + link_readyovr : in std_logic; + + SERDES_ready : in std_logic -- signalize when PHY ready + ); + end component; + + + +end package cbmnet_interface_pkg; + +package body cbmnet_interface_pkg is +end package body; \ No newline at end of file diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index ab9d4e5..f9e0a5e 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -11,7 +11,7 @@ use strict; my $TOPNAME = "trb3_periph_cbmnet"; #Name of top-level entity my $BasePath = "../base/"; #path to "base" directory my $CbmNetPath = "../../cbmnet"; -my $lattice_path = '/d/jspc29/lattice/diamond/1.4'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; diff --git a/cbmnet/trb3_periph_cbmnet.prj b/cbmnet/trb3_periph_cbmnet.prj index b285bb3..c8d4d02 100644 --- a/cbmnet/trb3_periph_cbmnet.prj +++ b/cbmnet/trb3_periph_cbmnet.prj @@ -1,71 +1,99 @@ - -# implementation: "workdir" -impl -add workdir -type fpga - -# device options -set_option -technology LATTICE-ECP3 -set_option -part LFE3_150EA -set_option -package FN672C -set_option -speed_grade -8 -set_option -part_companion "" - -# compilation/mapping options -set_option -default_enum_encoding sequential -set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb3_periph_cbmnet" -set_option -resource_sharing true - -# map options -set_option -frequency 200 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 0 -#set_option -force_gsr -set_option -force_gsr false -set_option -fixgatedclocks false #3 -set_option -fixgeneratedclocks false #3 -set_option -compiler_compatible true - - -# simulation options -set_option -write_verilog 0 -set_option -write_vhdl 1 - -# automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -# set result format/file last -project -result_format "edif" -project -result_file "workdir/trb3_periph_cbmnet.edf" - -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 -impl -active "workdir" - -#################### - - - -#add_file options - -add_file -vhdl -lib work "version.vhd" +#-- Synopsys, Inc. +#-- Version F-2012.03-SP1 +#-- Project file /u/mpenschuck/Documents/trb3/cbmnet/trb3_periph_cbmnet.prj + +#project files +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_2c.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w2r_1c.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_1c.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_2c.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c_enable.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fast_fifo.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_ram.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_reg.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_fwft_fifo.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_standard_fifo.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_spec_so.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_wo_spec.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_wo_spec.v" +add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si_all.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/async_input_sync.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_ready_module.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_rm_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_ready_module.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_rm_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_crc_generator.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_in.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_out.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in_decode.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_out.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_packet_gen.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_buffer.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service_ctrl.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_slave_top.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_top.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v" + +add_file -vhdl -lib work "./version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd" +add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../base/cores/pll_in125_out20.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib "work" "../base/trb3_components.vhd" - +add_file -vhdl -lib work "../base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" @@ -73,6 +101,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" @@ -80,63 +109,95 @@ add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" - -add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" -add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" -add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" - -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" - -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" - add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" -add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" - -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" + +add_file -vhdl -lib work "./code/cbmnet_pkg.vhd" +add_file -vhdl -lib work "./code/cbmnet_phy_pkg.vhd" + +add_file -vhdl -lib work "./cores/cbmnet_sfp1.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "./code/cbmnet_phy_ecp3.vhd" + +add_file -vhdl -lib work "./trb3_periph_cbmnet.vhd" + +#implementation: "workdir" +impl -add workdir -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +set_option -include_path {cbmnet/cores/CBMnet/includes/} + +#device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" -add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +#compilation/mapping options +set_option -top_module "trb3_periph_cbmnet" -add_file -vhdl -lib "work" "trb3_periph_cbmnet.vhd" +# mapper_options +set_option -frequency 200 +set_option -default_enum_encoding sequential +set_option -write_verilog 0 +set_option -write_vhdl 1 +# Lattice XP +set_option -maxfan 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fixgatedclocks 0 +set_option -fixgeneratedclocks 0 +set_option -update_models_cp 0 + +# NFilter +set_option -popfeed 0 +set_option -constprop 0 +set_option -createhierarchy 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 1 +set_option -resource_sharing 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_file "./workdir/trb3_periph_cbmnet.edf" +impl -active "workdir" diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd index 89c47ca..fe1af45 100644 --- a/cbmnet/trb3_periph_cbmnet.vhd +++ b/cbmnet/trb3_periph_cbmnet.vhd @@ -8,16 +8,22 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.version.all; +use work.cbmnet_interface_pkg.all; +use work.cbmnet_phy_pkg.all; entity trb3_periph_cbmnet is + generic ( + CBM_FEE_MODE : integer := c_YES -- in FEE mode, logic will run on recovered clock and (for now) listen only to data received + -- in Master mode, logic will run on internal clock and regularly send dlms + ); port( --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - + --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out @@ -36,17 +42,17 @@ entity trb3_periph_cbmnet is --Bit 2/3 output, serial link TX active --others yet undefined --Connection to AddOn - SPARE_LINE : inout std_logic_vector(5 downto 0); --inputs only - DQUL : inout std_logic_vector(45 downto 0); - DQLL : inout std_logic_vector(47 downto 0); - DQUR : inout std_logic_vector(33 downto 0); - DQLR : inout std_logic_vector(35 downto 0); - --All DQ groups from one bank are grouped. - --All DQS are inserted in the DQ lines at position 6 and 7, DQ 6-9 are shifted to 8-11 - --Order per bank is kept, i.e. adjacent numbers have adjacent pins - --all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 is 6+2+2=10. - --even numbers are positive LVDS line, odd numbers are negative LVDS line - --DQUL can be switched to 1.8V + LED_LINKOK : out std_logic_vector(6 downto 1); + LED_RX : out std_logic_vector(6 downto 1); + LED_TX : out std_logic_vector(6 downto 1); + + SFP_MOD0 : in std_logic_vector(6 downto 1); + SFP_TXDIS : out std_logic_vector(6 downto 1); + SFP_LOS : in std_logic_vector(6 downto 1); + SFP_MOD1 : out std_logic_vector(6 downto 1); + SFP_MOD2 : inout std_logic_vector(6 downto 1); + + --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; @@ -64,7 +70,13 @@ entity trb3_periph_cbmnet is SUPPL : in std_logic; --terminated diff pair, PCLK, Pads --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : out std_logic_vector(15 downto 0); + +-- PCS Core TODO: Suppose this is necessary only for simulation + SD_RXD_N_IN : in std_logic; + SD_RXD_P_IN : in std_logic; + SD_TXD_N_OUT : out std_logic; + SD_TXD_P_OUT : out std_logic ); @@ -87,11 +99,14 @@ entity trb3_periph_cbmnet is attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of DQLL : signal is true; - attribute syn_useioff of DQUL : signal is true; - attribute syn_useioff of DQLR : signal is true; - attribute syn_useioff of DQUR : signal is true; - attribute syn_useioff of SPARE_LINE : signal is true; +-- attribute syn_useioff of DQLL : signal is true; +-- attribute syn_useioff of DQUL : signal is true; +-- attribute syn_useioff of DQLR : signal is true; +-- attribute syn_useioff of DQUR : signal is true; +-- attribute syn_useioff of SPARE_LINE : signal is true; + +attribute nopad : string; +attribute nopad of SD_RXD_N_IN, SD_RXD_P_IN, SD_TXD_N_OUT, SD_TXD_P_OUT : signal is "true"; end entity; @@ -105,6 +120,7 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is attribute syn_preserve : boolean; --Clock / Reset + signal clk_125_i : std_logic; -- clock reference for CBMNet serdes signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. @@ -114,6 +130,11 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; + + signal rclk_125_i : std_logic; -- recovered clock + signal rreset_i : std_logic; -- reset for recovered clock ~ 1us after clock becomes stable + + --Media Interface signal med_stat_op : std_logic_vector (1*16-1 downto 0); signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); @@ -202,14 +223,179 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; - --FPGA Test signal time_counter : unsigned(31 downto 0); + +-- CBMNet signals + constant NUM_LANES : integer := 1; + signal cbm_clk : std_logic; -- Main clock + signal cbm_res_n : std_logic; -- Active low reset; can be changed by define + signal cbm_link_active : std_logic; -- link is active and can send and receive data + + signal cbm_ctrl2send_stop : std_logic := '0'; -- send control interface + signal cbm_ctrl2send_start : std_logic := '0'; + signal cbm_ctrl2send_end : std_logic := '0'; + signal cbm_ctrl2send : std_logic_vector(15 downto 0) := (others => '0'); + + signal cbm_data2send_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); -- send data interface + signal cbm_data2send_start : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); + signal cbm_data2send_end : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); + signal cbm_data2send : std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0'); + + signal cbm_dlm2send_va : std_logic := '0'; -- send dlm interface + signal cbm_dlm2send : std_logic_vector(3 downto 0) := (others => '0'); + + signal cbm_dlm_rec_type : std_logic_vector(3 downto 0) := (others => '0'); -- receive dlm interface + signal cbm_dlm_rec_va : std_logic := '0'; + + signal cbm_data_rec : std_logic_vector((16*NUM_LANES)-1 downto 0); -- receive data interface + signal cbm_data_rec_start : std_logic_vector(NUM_LANES-1 downto 0); + signal cbm_data_rec_end : std_logic_vector(NUM_LANES-1 downto 0); + signal cbm_data_rec_stop : std_logic_vector(NUM_LANES-1 downto 0); + + signal cbm_ctrl_rec : std_logic_vector(15 downto 0); -- receive control interface + signal cbm_ctrl_rec_start : std_logic; + signal cbm_ctrl_rec_end : std_logic; + signal cbm_ctrl_rec_stop : std_logic; + + signal cbm_data_from_link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface from the PHY + signal cbm_data2link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface to the PHY + + signal cbm_link_activeovr : std_logic := '0'; -- Overrides; set 0 by default + signal cbm_link_readyovr : std_logic := '0'; + + signal cbm_SERDES_ready : std_logic; -- signalize when PHY ready + + signal phy_stat_op, phy_ctrl_op : std_logic_vector(15 downto 0) := (others => '0'); + signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0'); + begin + clk_125_i <= CLK_GPLL_LEFT; + + THE_CBM_PHY: cbmnet_phy_ecp3 + generic map (IS_SYNC_SLAVE => CBM_FEE_MODE) + port map ( + CLK => clk_125_i, + RESET => reset_i, + + --Internal Connection TX + MED_TXDATA_IN => cbm_data2link(15 downto 0), + MED_TXDATA_K_IN => cbm_data2link(17 downto 16), + + --Internal Connection RX + MED_RXDATA_OUT => cbm_data_from_link(15 downto 0), + MED_RXDATA_K_OUT => cbm_data_from_link(17 downto 16), + + CLK_RX_HALF_OUT => rclk_125_i, + CLK_RX_FULL_OUT => open, + CLK_RX_RESET_OUT => rreset_i, + + LINK_ACTIVE_OUT => cbm_link_active, + SERDES_ready => cbm_SERDES_ready, + + --SFP Connection + SD_RXD_P_IN => SD_RXD_P_IN, + SD_RXD_N_IN => SD_RXD_N_IN, + SD_TXD_P_OUT => SD_TXD_P_OUT, + SD_TXD_N_OUT => SD_TXD_N_OUT, + + SD_PRSNT_N_IN => SFP_MOD0(1), + SD_LOS_IN => SFP_LOS(1), + SD_TXDIS_OUT => SFP_TXDIS(1), + + --Control Interface (not used, default values set in component def) +-- SCI_DATA_IN => , +-- SCI_DATA_OUT => , +-- SCI_ADDR => , +-- SCI_READ => , +-- SCI_WRITE => , +-- SCI_ACK => , +-- SCI_NACK => , + + -- Status and control port + STAT_OP => phy_stat_op, + CTRL_OP => phy_ctrl_op, + STAT_DEBUG => phy_stat_debug, + CTRL_DEBUG => phy_ctrl_debug + ); + + LED_LINKOK(1) <= cbm_link_active; + LED_RX(1) <= phy_stat_op(10); + LED_TX(1) <= phy_stat_op(11); + + THE_CBM_ENDPOINT: lp_top + generic map ( + NUM_LANES => NUM_LANES, + TX_SLAVE => 1 + ) + port map ( + clk => cbm_clk, + res_n => cbm_res_n, + link_active => cbm_link_active, + ctrl2send_stop => cbm_ctrl2send_stop, + ctrl2send_start => cbm_ctrl2send_start, + ctrl2send_end => cbm_ctrl2send_end, + ctrl2send => cbm_ctrl2send, + data2send_stop => cbm_data2send_stop, + data2send_start => cbm_data2send_start, + data2send_end => cbm_data2send_end, + data2send => cbm_data2send, + dlm2send_va => cbm_dlm2send_va, + dlm2send => cbm_dlm2send, + dlm_rec_type => cbm_dlm_rec_type, + dlm_rec_va => cbm_dlm_rec_va, + data_rec => cbm_data_rec, + data_rec_start => cbm_data_rec_start, + data_rec_end => cbm_data_rec_end, + data_rec_stop => cbm_data_rec_stop, + ctrl_rec => cbm_ctrl_rec, + ctrl_rec_start => cbm_ctrl_rec_start, + ctrl_rec_end => cbm_ctrl_rec_end, + ctrl_rec_stop => cbm_ctrl_rec_stop, + data_from_link => cbm_data_from_link, + data2link => cbm_data2link, + link_activeovr => cbm_link_activeovr, + link_readyovr => cbm_link_readyovr, + SERDES_ready => cbm_SERDES_ready + ); + + TEST_LINE(7 downto 0) <= cbm_data_from_link(7 downto 0); + TEST_LINE(8) <= cbm_SERDES_ready; + TEST_LINE(9) <= cbm_link_active; +--TEST_LINE(10) see FEE/MST switch below + TEST_LINE(11) <= rreset_i; + TEST_LINE(15 downto 12) <= (others => '0'); + + GEN_FEE_TEST_LOGIC: if CBM_FEE_MODE generate + TEST_LINE(10) <= cbm_dlm_rec_va; + end generate; + + + GEN_MST_TEST_LOGIC: if not CBM_FEE_MODE generate + process(rclk_125_i) is + constant counter_max : integer := 1250000; + variable counter : integer range 0 to counter_max := 0; + begin + cbm_dlm2send_va <= '0'; + if rreset_i = '1' then + counter := 1; + else + if counter = counter_max then + counter := 0; + cbm_dlm2send_va <= '1'; + else + counter := counter + 1; + end if; + end if; + end process; + + TEST_LINE(10) <= cbm_dlm2send_va; + end generate; + + --------------------------------------------------------------------------- -- Reset Generation --------------------------------------------------------------------------- - GSR_N <= pll_lock; THE_RESET_HANDLER : trb_net_reset_handler @@ -400,10 +586,10 @@ begin --------------------------------------------------------------------------- -- AddOn --------------------------------------------------------------------------- - DQLL <= (others => '0'); - DQUL <= (others => '0'); - DQLR <= (others => '0'); - DQUR <= (others => '0'); +-- DQLL <= (others => '0'); +-- DQUL <= (others => '0'); +-- DQLR <= (others => '0'); +-- DQUR <= (others => '0'); --------------------------------------------------------------------------- -- Bus Handler @@ -441,6 +627,7 @@ begin BUS_WRITE_ACK_IN(0) => spictrl_ack, BUS_NO_MORE_DATA_IN(0) => spictrl_busy, BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) BUS_READ_ENABLE_OUT(1) => spimem_read_en, BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, @@ -529,17 +716,6 @@ begin LED_RED <= not time_counter(26); LED_YELLOW <= not med_stat_op(11); - ---------------------------------------------------------------------------- --- Test Connector ---------------------------------------------------------------------------- - TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); - TEST_LINE(8) <= med_dataready_in; - TEST_LINE(9) <= med_dataready_out; - TEST_LINE(10) <= stat_reg_strobe(0); - TEST_LINE(15 downto 11) <= (others => '0'); - - --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- diff --git a/cbmnet/trb3_periph_cbmnet_constraints.lpf b/cbmnet/trb3_periph_cbmnet_constraints.lpf index 7f13282..107c643 100644 --- a/cbmnet/trb3_periph_cbmnet_constraints.lpf +++ b/cbmnet/trb3_periph_cbmnet_constraints.lpf @@ -13,14 +13,6 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - FREQUENCY PORT NX1_CLK256A_OUT 256 MHz; - FREQUENCY PORT NX2_CLK256A_OUT 256 MHz; - -#Put the names of your nxyter inputs here: - FREQUENCY PORT NX1_CLK128_IN 128 MHz; - FREQUENCY PORT NX2_CLK128_IN 128 MHz; - FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz; - FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz; #Change the next two lines to the clk_fast signal of the ADC USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0"; @@ -29,19 +21,6 @@ USE PRIMARY NET "CLK_PCLK_LEFT"; USE PRIMARY NET "CLK_PCLK_LEFT_c"; - - USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT_c"; - - USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT_c"; - - USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - - #USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - #USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - ################################################################# # Reset Nets ################################################################# @@ -60,6 +39,4 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; # Relax some of the timing constraints ################################################################# MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; - - +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; \ No newline at end of file -- 2.43.0